board/inka4x0/inka4x0.c

   1 /*
   2  * (C) Copyright 2008-2009
   3  * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
   4  *
   5  * (C) Copyright 2009
   6  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   7  *
   8  * (C) Copyright 2004
   9  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  10  *
  11  * (C) Copyright 2004
  12  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  13  *
  14  * (C) Copyright 2003-2004
  15  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19
  20 #include <asm/io.h>
  21 #include <common.h>
  22 #include <mpc5xxx.h>
  23 #include <pci.h>
  24
  25 #if defined(CONFIG_DDR_MT46V16M16)
  26 #include "mt46v16m16-75.h"
  27 #elif defined(CONFIG_SDR_MT48LC16M16A2)
  28 #include "mt48lc16m16a2-75.h"
  29 #elif defined(CONFIG_DDR_MT46V32M16)
  30 #include "mt46v32m16.h"
  31 #elif defined(CONFIG_DDR_HYB25D512160BF)
  32 #include "hyb25d512160bf.h"
  33 #elif defined(CONFIG_DDR_K4H511638C)
  34 #include "k4h511638c.h"
  35 #else
  36 #error "INKA4x0 SDRAM: invalid chip type specified!"
  37 #endif
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #ifndef CONFIG_SYS_RAMBOOT
  42 static void sdram_start (int hi_addr)
  43 {
  44         volatile struct mpc5xxx_sdram *sdram =
  45                 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  46         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  47
  48         /* unlock mode register */
  49         out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
  50
  51         /* precharge all banks */
  52         out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
  53
  54 #if SDRAM_DDR
  55         /* set mode register: extended mode */
  56         out_be32(&sdram->mode, SDRAM_EMODE);
  57
  58         /* set mode register: reset DLL */
  59         out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
  60 #endif
  61
  62         /* precharge all banks */
  63         out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
  64
  65         /* auto refresh */
  66         out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
  67
  68         /* set mode register */
  69         out_be32(&sdram->mode, SDRAM_MODE);
  70
  71         /* normal operation */
  72         out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
  73 }
  74 #endif
  75
  76 /*
  77  * ATTENTION: Although partially referenced initdram does NOT make real use
  78  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  79  *            is something else than 0x00000000.
  80  */
  81
  82 int initdram(void)
  83 {
  84         volatile struct mpc5xxx_mmap_ctl *mm =
  85                 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
  86         volatile struct mpc5xxx_cdm     *cdm =
  87                 (struct mpc5xxx_cdm *)      MPC5XXX_CDM;
  88         volatile struct mpc5xxx_sdram *sdram =
  89                 (struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
  90         ulong dramsize = 0;
  91 #ifndef CONFIG_SYS_RAMBOOT
  92         long test1, test2;
  93
  94         /* setup SDRAM chip selects */
  95         out_be32(&mm->sdram0, 0x0000001c);      /* 512MB at 0x0 */
  96         out_be32(&mm->sdram1, 0x40000000);      /* disabled */
  97
  98         /* setup config registers */
  99         out_be32(&sdram->config1, SDRAM_CONFIG1);
 100         out_be32(&sdram->config2, SDRAM_CONFIG2);
 101
 102 #if SDRAM_DDR
 103         /* set tap delay */
 104         out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
 105 #endif
 106
 107         /* find RAM size using SDRAM CS0 only */
 108         sdram_start(0);
 109         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 110         sdram_start(1);
 111         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 112         if (test1 > test2) {
 113                 sdram_start(0);
 114                 dramsize = test1;
 115         } else {
 116                 dramsize = test2;
 117         }
 118
 119         /* memory smaller than 1MB is impossible */
 120         if (dramsize < (1 << 20)) {
 121                 dramsize = 0;
 122         }
 123
 124         /* set SDRAM CS0 size according to the amount of RAM found */
 125         if (dramsize > 0) {
 126                 out_be32(&mm->sdram0, 0x13 +
 127                          __builtin_ffs(dramsize >> 20) - 1);
 128         } else {
 129                 out_be32(&mm->sdram0, 0); /* disabled */
 130         }
 131
 132         out_be32(&mm->sdram1, dramsize); /* disabled */
 133 #else /* CONFIG_SYS_RAMBOOT */
 134
 135         /* retrieve size of memory connected to SDRAM CS0 */
 136         dramsize = in_be32(&mm->sdram0) & 0xFF;
 137         if (dramsize >= 0x13) {
 138                 dramsize = (1 << (dramsize - 0x13)) << 20;
 139         } else {
 140                 dramsize = 0;
 141         }
 142 #endif /* CONFIG_SYS_RAMBOOT */
 143
 144         gd->ram_size = dramsize;
 145
 146         return 0;
 147 }
 148
 149 int checkboard (void)
 150 {
 151         puts ("Board: INKA 4X0\n");
 152         return 0;
 153 }
 154
 155 void flash_preinit(void)
 156 {
 157         volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
 158
 159         /*
 160          * Now, when we are in RAM, enable flash write
 161          * access for detection process.
 162          * Note that CS_BOOT (CS0) cannot be cleared when
 163          * executing in flash.
 164          */
 165         clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
 166 }
 167
 168 int misc_init_f (void)
 169 {
 170         volatile struct mpc5xxx_gpio    *gpio    =
 171                 (struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
 172         volatile struct mpc5xxx_wu_gpio *wu_gpio =
 173                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 174         volatile struct mpc5xxx_gpt     *gpt;
 175         char tmp[10];
 176         int i, br;
 177
 178         i = getenv_f("brightness", tmp, sizeof(tmp));
 179         br = (i > 0)
 180                 ? (int) simple_strtoul (tmp, NULL, 10)
 181                 : CONFIG_SYS_BRIGHTNESS;
 182         if (br > 255)
 183                 br = 255;
 184
 185         /* Initialize GPIO output pins.
 186          */
 187         /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
 188         for (i = 0; i <= 5; i++) {
 189                 gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
 190                 out_be32(&gpt->emsr, 0x34);
 191         }
 192
 193         /* Configure GPT7 as PWM timer, 1kHz, no ints. */
 194         gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
 195         out_be32(&gpt->emsr,  0);               /* Disable */
 196         out_be32(&gpt->cir,   0x020000fe);
 197         out_be32(&gpt->pwmcr, (br << 16));
 198         out_be32(&gpt->emsr,  0x3);             /* Enable PWM mode and start */
 199
 200         /* Configure PSC3_6,7 as GPIO output */
 201         setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
 202                                           MPC5XXX_GPIO_SIMPLE_PSC3_7);
 203         setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
 204                                           MPC5XXX_GPIO_SIMPLE_PSC3_7);
 205
 206         /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
 207         setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
 208                                      MPC5XXX_GPIO_WKUP_7 |
 209                                      MPC5XXX_GPIO_WKUP_PSC3_9);
 210         setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
 211                                      MPC5XXX_GPIO_WKUP_7 |
 212                                      MPC5XXX_GPIO_WKUP_PSC3_9);
 213
 214         /* Set LR mirror bit because it is low-active */
 215         setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);
 216
 217         /* Reset Coral-P graphics controller */
 218         setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);
 219
 220         /* Enable display backlight */
 221         clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
 222         setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
 223         setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
 224         setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);
 225
 226         /*
 227          * Configure three wire serial interface to RTC (PSC1_4,
 228          * PSC2_4, PSC3_4, PSC3_5)
 229          */
 230         setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
 231                                      MPC5XXX_GPIO_WKUP_PSC2_4);
 232         setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
 233                                      MPC5XXX_GPIO_WKUP_PSC2_4);
 234         clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
 235         clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
 236                                      MPC5XXX_GPIO_SINT_PSC3_5);
 237         setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
 238                                      MPC5XXX_GPIO_SINT_PSC3_5);
 239         setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
 240         clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);
 241
 242         return 0;
 243 }
 244
 245 #ifdef  CONFIG_PCI
 246 static struct pci_controller hose;
 247
 248 extern void pci_mpc5xxx_init(struct pci_controller *);
 249
 250 void pci_init_board(void)
 251 {
 252         pci_mpc5xxx_init(&hose);
 253 }
 254 #endif