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Commit | Line | Data |
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ac9db066 | 1 | /* |
0809ea2f | 2 | * (C) Copyright 2007 - 2008 |
ac9db066 HS |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
ac9db066 HS |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <mpc8260.h> | |
10 | #include <ioports.h> | |
9661bf9d | 11 | #include <malloc.h> |
9e299192 | 12 | #include <asm/io.h> |
ac9db066 | 13 | |
ac9db066 | 14 | #include <libfdt.h> |
9661bf9d | 15 | #include <i2c.h> |
210c8c00 HS |
16 | #include "../common/common.h" |
17 | ||
2973b098 VL |
18 | static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; |
19 | ||
ac9db066 HS |
20 | /* |
21 | * I/O Port configuration table | |
22 | * | |
23 | * if conf is 1, then that port pin will be configured at boot time | |
24 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
25 | */ | |
26 | const iop_conf_t iop_conf_tab[4][32] = { | |
27 | ||
2220e6ca HB |
28 | /* Port A */ |
29 | { /* conf ppar psor pdir podr pdat */ | |
30 | { 0, 0, 0, 0, 0, 0 }, /* PA31 */ | |
31 | { 0, 0, 0, 0, 0, 0 }, /* PA30 */ | |
32 | { 0, 0, 0, 0, 0, 0 }, /* PA29 */ | |
33 | { 0, 0, 0, 0, 0, 0 }, /* PA28 */ | |
34 | { 0, 0, 0, 0, 0, 0 }, /* PA27 */ | |
35 | { 0, 0, 0, 0, 0, 0 }, /* PA26 */ | |
36 | { 0, 0, 0, 0, 0, 0 }, /* PA25 */ | |
37 | { 0, 0, 0, 0, 0, 0 }, /* PA24 */ | |
38 | { 0, 0, 0, 0, 0, 0 }, /* PA23 */ | |
39 | { 0, 0, 0, 0, 0, 0 }, /* PA22 */ | |
40 | { 0, 0, 0, 0, 0, 0 }, /* PA21 */ | |
41 | { 0, 0, 0, 0, 0, 0 }, /* PA20 */ | |
42 | { 0, 0, 0, 0, 0, 0 }, /* PA19 */ | |
43 | { 0, 0, 0, 0, 0, 0 }, /* PA18 */ | |
44 | { 0, 0, 0, 0, 0, 0 }, /* PA17 */ | |
45 | { 0, 0, 0, 0, 0, 0 }, /* PA16 */ | |
46 | { 0, 0, 0, 0, 0, 0 }, /* PA15 */ | |
47 | { 0, 0, 0, 0, 0, 0 }, /* PA14 */ | |
48 | { 0, 0, 0, 0, 0, 0 }, /* PA13 */ | |
49 | { 0, 0, 0, 0, 0, 0 }, /* PA12 */ | |
50 | { 0, 0, 0, 0, 0, 0 }, /* PA11 */ | |
51 | { 0, 0, 0, 0, 0, 0 }, /* PA10 */ | |
52 | { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */ | |
53 | { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */ | |
54 | { 0, 0, 0, 0, 0, 0 }, /* PA7 */ | |
55 | { 0, 0, 0, 0, 0, 0 }, /* PA6 */ | |
56 | { 0, 0, 0, 0, 0, 0 }, /* PA5 */ | |
57 | { 0, 0, 0, 0, 0, 0 }, /* PA4 */ | |
58 | { 0, 0, 0, 0, 0, 0 }, /* PA3 */ | |
59 | { 0, 0, 0, 0, 0, 0 }, /* PA2 */ | |
60 | { 0, 0, 0, 0, 0, 0 }, /* PA1 */ | |
61 | { 0, 0, 0, 0, 0, 0 } /* PA0 */ | |
62 | }, | |
ac9db066 | 63 | |
2220e6ca HB |
64 | /* Port B */ |
65 | { /* conf ppar psor pdir podr pdat */ | |
66 | { 0, 0, 0, 0, 0, 0 }, /* PB31 */ | |
67 | { 0, 0, 0, 0, 0, 0 }, /* PB30 */ | |
68 | { 0, 0, 0, 0, 0, 0 }, /* PB29 */ | |
69 | { 0, 0, 0, 0, 0, 0 }, /* PB28 */ | |
70 | { 0, 0, 0, 0, 0, 0 }, /* PB27 */ | |
71 | { 0, 0, 0, 0, 0, 0 }, /* PB26 */ | |
72 | { 0, 0, 0, 0, 0, 0 }, /* PB25 */ | |
73 | { 0, 0, 0, 0, 0, 0 }, /* PB24 */ | |
74 | { 0, 0, 0, 0, 0, 0 }, /* PB23 */ | |
75 | { 0, 0, 0, 0, 0, 0 }, /* PB22 */ | |
76 | { 0, 0, 0, 0, 0, 0 }, /* PB21 */ | |
77 | { 0, 0, 0, 0, 0, 0 }, /* PB20 */ | |
78 | { 0, 0, 0, 0, 0, 0 }, /* PB19 */ | |
79 | { 0, 0, 0, 0, 0, 0 }, /* PB18 */ | |
80 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
81 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
82 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
83 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
84 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
85 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
86 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
87 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
88 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
89 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
90 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
91 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
92 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
93 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
94 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
95 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
96 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
97 | { 0, 0, 0, 0, 0, 0 } /* non-existent */ | |
98 | }, | |
ac9db066 | 99 | |
2220e6ca HB |
100 | /* Port C */ |
101 | { /* conf ppar psor pdir podr pdat */ | |
102 | { 0, 0, 0, 0, 0, 0 }, /* PC31 */ | |
103 | { 0, 0, 0, 0, 0, 0 }, /* PC30 */ | |
104 | { 0, 0, 0, 0, 0, 0 }, /* PC29 */ | |
105 | { 0, 0, 0, 0, 0, 0 }, /* PC28 */ | |
106 | { 0, 0, 0, 0, 0, 0 }, /* PC27 */ | |
107 | { 0, 0, 0, 0, 0, 0 }, /* PC26 */ | |
108 | { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */ | |
109 | { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */ | |
110 | { 0, 0, 0, 0, 0, 0 }, /* PC23 */ | |
111 | { 0, 0, 0, 0, 0, 0 }, /* PC22 */ | |
112 | { 0, 0, 0, 0, 0, 0 }, /* PC21 */ | |
113 | { 0, 0, 0, 0, 0, 0 }, /* PC20 */ | |
114 | { 0, 0, 0, 0, 0, 0 }, /* PC19 */ | |
115 | { 0, 0, 0, 0, 0, 0 }, /* PC18 */ | |
116 | { 0, 0, 0, 0, 0, 0 }, /* PC17 */ | |
117 | { 0, 0, 0, 0, 0, 0 }, /* PC16 */ | |
118 | { 0, 0, 0, 0, 0, 0 }, /* PC15 */ | |
119 | { 0, 0, 0, 0, 0, 0 }, /* PC14 */ | |
120 | { 0, 0, 0, 0, 0, 0 }, /* PC13 */ | |
121 | { 0, 0, 0, 0, 0, 0 }, /* PC12 */ | |
122 | { 0, 0, 0, 0, 0, 0 }, /* PC11 */ | |
123 | { 0, 0, 0, 0, 0, 0 }, /* PC10 */ | |
124 | { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */ | |
125 | { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */ | |
126 | { 0, 0, 0, 0, 0, 0 }, /* PC7 */ | |
127 | { 0, 0, 0, 0, 0, 0 }, /* PC6 */ | |
128 | { 0, 0, 0, 0, 0, 0 }, /* PC5 */ | |
129 | { 0, 0, 0, 0, 0, 0 }, /* PC4 */ | |
130 | { 0, 0, 0, 0, 0, 0 }, /* PC3 */ | |
131 | { 0, 0, 0, 0, 0, 0 }, /* PC2 */ | |
132 | { 0, 0, 0, 0, 0, 0 }, /* PC1 */ | |
133 | { 0, 0, 0, 0, 0, 0 }, /* PC0 */ | |
134 | }, | |
ac9db066 | 135 | |
2220e6ca HB |
136 | /* Port D */ |
137 | { /* conf ppar psor pdir podr pdat */ | |
138 | { 0, 0, 0, 0, 0, 0 }, /* PD31 */ | |
139 | { 0, 0, 0, 0, 0, 0 }, /* PD30 */ | |
140 | { 0, 0, 0, 0, 0, 0 }, /* PD29 */ | |
141 | { 0, 0, 0, 0, 0, 0 }, /* PD28 */ | |
142 | { 0, 0, 0, 0, 0, 0 }, /* PD27 */ | |
143 | { 0, 0, 0, 0, 0, 0 }, /* PD26 */ | |
144 | { 0, 0, 0, 0, 0, 0 }, /* PD25 */ | |
145 | { 0, 0, 0, 0, 0, 0 }, /* PD24 */ | |
146 | { 0, 0, 0, 0, 0, 0 }, /* PD23 */ | |
147 | { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */ | |
148 | { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */ | |
149 | { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */ | |
150 | { 0, 0, 0, 0, 0, 0 }, /* PD19 */ | |
151 | { 0, 0, 0, 0, 0, 0 }, /* PD18 */ | |
152 | { 0, 0, 0, 0, 0, 0 }, /* PD17 */ | |
153 | { 0, 0, 0, 0, 0, 0 }, /* PD16 */ | |
9661bf9d | 154 | #if defined(CONFIG_HARD_I2C) |
2220e6ca HB |
155 | { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */ |
156 | { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */ | |
9661bf9d | 157 | #else |
2220e6ca HB |
158 | { 1, 0, 0, 0, 1, 1 }, /* PD15 */ |
159 | { 1, 0, 0, 1, 1, 1 }, /* PD14 */ | |
9661bf9d | 160 | #endif |
2220e6ca HB |
161 | { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
162 | { 0, 0, 0, 0, 0, 0 }, /* PD12 */ | |
163 | { 0, 0, 0, 0, 0, 0 }, /* PD11 */ | |
164 | { 0, 0, 0, 0, 0, 0 }, /* PD10 */ | |
165 | { 0, 0, 0, 0, 0, 0 }, /* PD9 */ | |
166 | { 0, 0, 0, 0, 0, 0 }, /* PD8 */ | |
167 | { 0, 0, 0, 0, 0, 0 }, /* PD7 */ | |
168 | { 0, 0, 0, 0, 0, 0 }, /* PD6 */ | |
169 | { 0, 0, 0, 0, 0, 0 }, /* PD5 */ | |
170 | { 0, 0, 0, 0, 0, 0 }, /* PD4 */ | |
171 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
172 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
173 | { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
174 | { 0, 0, 0, 0, 0, 0 } /* non-existent */ | |
175 | } | |
ac9db066 HS |
176 | }; |
177 | ||
b11f53f3 HS |
178 | /* |
179 | * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx | |
ac9db066 HS |
180 | * |
181 | * This routine performs standard 8260 initialization sequence | |
182 | * and calculates the available memory size. It may be called | |
183 | * several times to try different SDRAM configurations on both | |
184 | * 60x and local buses. | |
185 | */ | |
b11f53f3 HS |
186 | static long int try_init(memctl8260_t *memctl, ulong sdmr, |
187 | ulong orx, uchar *base) | |
ac9db066 | 188 | { |
b11f53f3 | 189 | uchar c = 0xff; |
ac9db066 HS |
190 | ulong maxsize, size; |
191 | int i; | |
192 | ||
b11f53f3 HS |
193 | /* |
194 | * We must be able to test a location outsize the maximum legal size | |
ac9db066 HS |
195 | * to find out THAT we are outside; but this address still has to be |
196 | * mapped by the controller. That means, that the initial mapping has | |
197 | * to be (at least) twice as large as the maximum expected size. | |
198 | */ | |
199 | maxsize = (1 + (~orx | 0x7fff))/* / 2*/; | |
200 | ||
b11f53f3 | 201 | out_be32(&memctl->memc_or1, orx); |
ac9db066 HS |
202 | |
203 | /* | |
204 | * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): | |
205 | * | |
206 | * "At system reset, initialization software must set up the | |
207 | * programmable parameters in the memory controller banks registers | |
208 | * (ORx, BRx, P/LSDMR). After all memory parameters are configured, | |
209 | * system software should execute the following initialization sequence | |
210 | * for each SDRAM device. | |
211 | * | |
212 | * 1. Issue a PRECHARGE-ALL-BANKS command | |
213 | * 2. Issue eight CBR REFRESH commands | |
214 | * 3. Issue a MODE-SET command to initialize the mode register | |
215 | * | |
216 | * The initial commands are executed by setting P/LSDMR[OP] and | |
217 | * accessing the SDRAM with a single-byte transaction." | |
218 | * | |
219 | * The appropriate BRx/ORx registers have already been set when we | |
2220e6ca HB |
220 | * get here. The SDRAM can be accessed at the address |
221 | * CONFIG_SYS_SDRAM_BASE. | |
ac9db066 HS |
222 | */ |
223 | ||
b11f53f3 HS |
224 | out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA); |
225 | out_8(base, c); | |
ac9db066 | 226 | |
b11f53f3 | 227 | out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR); |
ac9db066 | 228 | for (i = 0; i < 8; i++) |
b11f53f3 | 229 | out_8(base, c); |
ac9db066 | 230 | |
b11f53f3 HS |
231 | out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW); |
232 | /* setting MR on address lines */ | |
233 | out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c); | |
ac9db066 | 234 | |
b11f53f3 HS |
235 | out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN); |
236 | out_8(base, c); | |
ac9db066 | 237 | |
b11f53f3 HS |
238 | size = get_ram_size((long *)base, maxsize); |
239 | out_be32(&memctl->memc_or1, orx | ~(size - 1)); | |
ac9db066 | 240 | |
2220e6ca | 241 | return size; |
ac9db066 HS |
242 | } |
243 | ||
3a532346 GF |
244 | #ifdef CONFIG_SYS_SDRAM_LIST |
245 | ||
246 | /* | |
247 | * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM | |
248 | * configurations therein (should be from high to lower) to find the | |
249 | * one actually matching the current configuration. | |
250 | * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are | |
251 | * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST | |
252 | * (defined as the initialization value for the array of struct sdram_conf_s) | |
253 | * will then be ORed with such base values. | |
254 | */ | |
255 | ||
256 | struct sdram_conf_s { | |
257 | ulong size; | |
258 | int or1; | |
259 | int psdmr; | |
260 | }; | |
261 | ||
262 | static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST; | |
263 | ||
264 | static long probe_sdram(memctl8260_t *memctl) | |
265 | { | |
266 | int n = 0; | |
267 | long psize = 0; | |
268 | ||
269 | for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) { | |
270 | psize = try_init(memctl, | |
271 | CONFIG_SYS_PSDMR | sdram_conf[n].psdmr, | |
272 | CONFIG_SYS_OR1 | sdram_conf[n].or1, | |
273 | (uchar *) CONFIG_SYS_SDRAM_BASE); | |
274 | debug("Probing %ld bytes returned %ld\n", | |
275 | sdram_conf[n].size, psize); | |
276 | if (psize == sdram_conf[n].size) | |
277 | break; | |
278 | } | |
279 | return psize; | |
280 | } | |
281 | ||
282 | #else /* CONFIG_SYS_SDRAM_LIST */ | |
283 | ||
284 | static long probe_sdram(memctl8260_t *memctl) | |
285 | { | |
286 | return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1, | |
287 | (uchar *) CONFIG_SYS_SDRAM_BASE); | |
288 | } | |
289 | #endif /* CONFIG_SYS_SDRAM_LIST */ | |
290 | ||
291 | ||
b11f53f3 | 292 | phys_size_t initdram(int board_type) |
ac9db066 | 293 | { |
b11f53f3 HS |
294 | immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
295 | memctl8260_t *memctl = &immap->im_memctl; | |
ac9db066 HS |
296 | |
297 | long psize; | |
298 | ||
b11f53f3 HS |
299 | out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT); |
300 | out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); | |
ac9db066 | 301 | |
ac9db066 HS |
302 | /* 60x SDRAM setup: |
303 | */ | |
3a532346 | 304 | psize = probe_sdram(memctl); |
ac9db066 | 305 | |
b11f53f3 | 306 | icache_enable(); |
ac9db066 | 307 | |
2220e6ca | 308 | return psize; |
ac9db066 HS |
309 | } |
310 | ||
311 | int checkboard(void) | |
312 | { | |
af895e45 | 313 | #if defined(CONFIG_MGCOGE) |
b11f53f3 | 314 | puts("Board: Keymile mgcoge"); |
af895e45 | 315 | #else |
489337f5 | 316 | puts("Board: Keymile mgcoge3ne"); |
af895e45 | 317 | #endif |
b11f53f3 HS |
318 | if (ethernet_present()) |
319 | puts(" with PIGGY."); | |
320 | puts("\n"); | |
ac9db066 HS |
321 | return 0; |
322 | } | |
323 | ||
91a3c14c AH |
324 | int last_stage_init(void) |
325 | { | |
f30c62bb HA |
326 | struct bfticu_iomap *base = |
327 | (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE; | |
91a3c14c | 328 | u8 dip_switch; |
f30c62bb HA |
329 | |
330 | dip_switch = in_8(&base->mswitch); | |
331 | dip_switch &= BFTICU_DIPSWITCH_MASK; | |
91a3c14c AH |
332 | /* dip switch 'full reset' or 'db erase' */ |
333 | if (dip_switch & 0x1 || dip_switch & 0x2) { | |
334 | /* start bootloader */ | |
335 | puts("DIP: Enabled\n"); | |
336 | setenv("actual_bank", "0"); | |
337 | } | |
f1fef1d8 | 338 | set_km_env(); |
91a3c14c AH |
339 | return 0; |
340 | } | |
341 | ||
489337f5 | 342 | #ifdef CONFIG_MGCOGE3NE |
74edc607 | 343 | static void set_pin(int state, unsigned long mask, int port); |
1adfd9dd | 344 | |
489337f5 HB |
345 | /* |
346 | * For mgcoge3ne boards, the mgcoge3un control is controlled from | |
347 | * a GPIO line on the PPC CPU. If bobcatreset is set the line | |
348 | * will toggle once what forces the mgocge3un part to restart | |
349 | * immediately. | |
350 | */ | |
47ce50e8 | 351 | static void handle_mgcoge3un_reset(void) |
489337f5 HB |
352 | { |
353 | char *bobcatreset = getenv("bobcatreset"); | |
354 | if (bobcatreset) { | |
355 | if (strcmp(bobcatreset, "true") == 0) { | |
356 | puts("Forcing bobcat reset\n"); | |
74edc607 | 357 | set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */ |
489337f5 | 358 | udelay(1000); |
74edc607 | 359 | set_pin(1, 0x00000004, 3); |
489337f5 | 360 | } else |
74edc607 | 361 | set_pin(1, 0x00000004, 3); /* don't reset arm */ |
489337f5 HB |
362 | } |
363 | } | |
364 | #endif | |
365 | ||
1eb95ebe KJ |
366 | int ethernet_present(void) |
367 | { | |
368 | struct km_bec_fpga *base = | |
369 | (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; | |
370 | ||
371 | return in_8(&base->bprth) & PIGGY_PRESENT; | |
372 | } | |
373 | ||
e492c90c HS |
374 | /* |
375 | * Early board initalization. | |
376 | */ | |
b11f53f3 | 377 | int board_early_init_r(void) |
e492c90c | 378 | { |
8ed74341 HS |
379 | struct km_bec_fpga *base = |
380 | (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; | |
b11f53f3 | 381 | |
e492c90c | 382 | /* setup the UPIOx */ |
4897ee33 | 383 | /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */ |
b11f53f3 | 384 | out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED)); |
4897ee33 | 385 | /* SCC4 enable, halfduplex, FCC1 powerdown */ |
b11f53f3 HS |
386 | out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA | |
387 | H_OPORTS_FCC1_PW_DWN)); | |
388 | ||
489337f5 HB |
389 | #ifdef CONFIG_MGCOGE3NE |
390 | handle_mgcoge3un_reset(); | |
391 | #endif | |
e492c90c HS |
392 | return 0; |
393 | } | |
394 | ||
2973b098 VL |
395 | int misc_init_r(void) |
396 | { | |
60c4ae00 | 397 | ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); |
2973b098 VL |
398 | return 0; |
399 | } | |
400 | ||
b11f53f3 | 401 | int hush_init_var(void) |
8f64da7f | 402 | { |
2973b098 | 403 | ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); |
8f64da7f HS |
404 | return 0; |
405 | } | |
406 | ||
1adfd9dd HB |
407 | #define SDA_MASK 0x00010000 |
408 | #define SCL_MASK 0x00020000 | |
409 | ||
74edc607 | 410 | static void set_pin(int state, unsigned long mask, int port) |
1adfd9dd | 411 | { |
74edc607 | 412 | ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); |
1adfd9dd HB |
413 | |
414 | if (state) | |
415 | setbits_be32(&iop->pdat, mask); | |
416 | else | |
417 | clrbits_be32(&iop->pdat, mask); | |
418 | ||
419 | setbits_be32(&iop->pdir, mask); | |
420 | } | |
421 | ||
74edc607 | 422 | static int get_pin(unsigned long mask, int port) |
1adfd9dd | 423 | { |
74edc607 | 424 | ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); |
1adfd9dd HB |
425 | |
426 | clrbits_be32(&iop->pdir, mask); | |
427 | return 0 != (in_be32(&iop->pdat) & mask); | |
428 | } | |
429 | ||
430 | void set_sda(int state) | |
431 | { | |
74edc607 | 432 | set_pin(state, SDA_MASK, 3); |
1adfd9dd HB |
433 | } |
434 | ||
435 | void set_scl(int state) | |
436 | { | |
74edc607 | 437 | set_pin(state, SCL_MASK, 3); |
1adfd9dd HB |
438 | } |
439 | ||
440 | int get_sda(void) | |
441 | { | |
74edc607 | 442 | return get_pin(SDA_MASK, 3); |
1adfd9dd HB |
443 | } |
444 | ||
445 | int get_scl(void) | |
446 | { | |
74edc607 | 447 | return get_pin(SCL_MASK, 3); |
1adfd9dd HB |
448 | } |
449 | ||
fc882a31 | 450 | void ft_board_setup(void *blob, bd_t *bd) |
ac9db066 | 451 | { |
b11f53f3 | 452 | ft_cpu_setup(blob, bd); |
e895a4b0 SG |
453 | |
454 | return 0; | |
ac9db066 | 455 | } |
d3f1d6f4 HB |
456 | |
457 | #if defined(CONFIG_MGCOGE3NE) | |
458 | int get_testpin(void) | |
459 | { | |
460 | /* Testpin is Port C pin 29 - enable = low */ | |
461 | int testpin = !get_pin(0x00000004, 2); | |
462 | return testpin; | |
463 | } | |
464 | #endif |