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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
a4d88920 SDPP |
3 | config IDENT_STRING |
4 | default " Allwinner Technology" | |
5 | ||
8f925584 SG |
6 | config PRE_CONSOLE_BUFFER |
7 | default y | |
8 | ||
53b5bf3c SG |
9 | config SPL_GPIO_SUPPORT |
10 | default y | |
11 | ||
77d2f7f5 SG |
12 | config SPL_LIBCOMMON_SUPPORT |
13 | default y | |
14 | ||
1646eba8 SG |
15 | config SPL_LIBDISK_SUPPORT |
16 | default y | |
17 | ||
cc4288ef SG |
18 | config SPL_LIBGENERIC_SUPPORT |
19 | default y | |
20 | ||
1fdf7c64 SG |
21 | config SPL_MMC_SUPPORT |
22 | default y | |
23 | ||
2253797d SG |
24 | config SPL_POWER_SUPPORT |
25 | default y | |
26 | ||
e00f76ce SG |
27 | config SPL_SERIAL_SUPPORT |
28 | default y | |
29 | ||
44d8ae5b HG |
30 | # Note only one of these may be selected at a time! But hidden choices are |
31 | # not supported by Kconfig | |
32 | config SUNXI_GEN_SUN4I | |
33 | bool | |
34 | ---help--- | |
35 | Select this for sunxi SoCs which have resets and clocks set up | |
36 | as the original A10 (mach-sun4i). | |
37 | ||
38 | config SUNXI_GEN_SUN6I | |
39 | bool | |
40 | ---help--- | |
41 | Select this for sunxi SoCs which have sun6i like periphery, like | |
42 | separate ahb reset control registers, custom pmic bus, new style | |
43 | watchdog, etc. | |
44 | ||
45 | ||
2c7e3b90 IC |
46 | choice |
47 | prompt "Sunxi SoC Variant" | |
3da9536e | 48 | optional |
2c7e3b90 | 49 | |
c3be2793 | 50 | config MACH_SUN4I |
2c7e3b90 IC |
51 | bool "sun4i (Allwinner A10)" |
52 | select CPU_V7 | |
44d8ae5b | 53 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
54 | select SUPPORT_SPL |
55 | ||
c3be2793 | 56 | config MACH_SUN5I |
2c7e3b90 IC |
57 | bool "sun5i (Allwinner A13)" |
58 | select CPU_V7 | |
44d8ae5b | 59 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
60 | select SUPPORT_SPL |
61 | ||
c3be2793 | 62 | config MACH_SUN6I |
2c7e3b90 IC |
63 | bool "sun6i (Allwinner A31)" |
64 | select CPU_V7 | |
cc08ea4c CYT |
65 | select CPU_V7_HAS_NONSEC |
66 | select CPU_V7_HAS_VIRT | |
217f92bb | 67 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 68 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 69 | select SUPPORT_SPL |
cc08ea4c | 70 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 71 | |
c3be2793 | 72 | config MACH_SUN7I |
2c7e3b90 IC |
73 | bool "sun7i (Allwinner A20)" |
74 | select CPU_V7 | |
ea624e19 HG |
75 | select CPU_V7_HAS_NONSEC |
76 | select CPU_V7_HAS_VIRT | |
217f92bb | 77 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 78 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 79 | select SUPPORT_SPL |
b366fb92 | 80 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 81 | |
5e6bacdb | 82 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
83 | bool "sun8i (Allwinner A23)" |
84 | select CPU_V7 | |
014414f5 CYT |
85 | select CPU_V7_HAS_NONSEC |
86 | select CPU_V7_HAS_VIRT | |
217f92bb | 87 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 88 | select SUNXI_GEN_SUN6I |
08fd1479 | 89 | select SUPPORT_SPL |
014414f5 | 90 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 91 | |
8c3dacff VP |
92 | config MACH_SUN8I_A33 |
93 | bool "sun8i (Allwinner A33)" | |
94 | select CPU_V7 | |
014414f5 CYT |
95 | select CPU_V7_HAS_NONSEC |
96 | select CPU_V7_HAS_VIRT | |
217f92bb | 97 | select ARCH_SUPPORT_PSCI |
8c3dacff VP |
98 | select SUNXI_GEN_SUN6I |
99 | select SUPPORT_SPL | |
014414f5 | 100 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
8c3dacff | 101 | |
a81b7995 CYT |
102 | config MACH_SUN8I_A83T |
103 | bool "sun8i (Allwinner A83T)" | |
104 | select CPU_V7 | |
105 | select SUNXI_GEN_SUN6I | |
106 | select SUPPORT_SPL | |
107 | ||
1c27b7dc JK |
108 | config MACH_SUN8I_H3 |
109 | bool "sun8i (Allwinner H3)" | |
110 | select CPU_V7 | |
853f6d1e CYT |
111 | select CPU_V7_HAS_NONSEC |
112 | select CPU_V7_HAS_VIRT | |
217f92bb | 113 | select ARCH_SUPPORT_PSCI |
1c27b7dc | 114 | select SUNXI_GEN_SUN6I |
0404d53f | 115 | select SUPPORT_SPL |
853f6d1e | 116 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
1c27b7dc | 117 | |
1871a8ca HG |
118 | config MACH_SUN9I |
119 | bool "sun9i (Allwinner A80)" | |
120 | select CPU_V7 | |
121 | select SUNXI_GEN_SUN6I | |
a98c296a | 122 | select SUPPORT_SPL |
1871a8ca | 123 | |
a81b7995 CYT |
124 | config MACH_SUN50I |
125 | bool "sun50i (Allwinner A64)" | |
126 | select ARM64 | |
127 | select SUNXI_GEN_SUN6I | |
128 | ||
2c7e3b90 | 129 | endchoice |
8a6564da | 130 | |
5e6bacdb HG |
131 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
132 | config MACH_SUN8I | |
133 | bool | |
762e24a0 | 134 | default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T |
5e6bacdb | 135 | |
f5fd8caf VP |
136 | config DRAM_TYPE |
137 | int "sunxi dram type" | |
138 | depends on MACH_SUN8I_A83T | |
139 | default 3 | |
140 | ---help--- | |
141 | Set the dram type, 3: DDR3, 7: LPDDR3 | |
5e6bacdb | 142 | |
37781a1a | 143 | config DRAM_CLK |
8ffc487c | 144 | int "sunxi dram clock speed" |
297bb9e0 | 145 | default 792 if MACH_SUN9I |
8ffc487c HG |
146 | default 312 if MACH_SUN6I || MACH_SUN8I |
147 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
37781a1a | 148 | ---help--- |
297bb9e0 PT |
149 | Set the dram clock speed, valid range 240 - 480 (prior to sun9i), |
150 | must be a multiple of 24. For the sun9i (A80), the tested values | |
151 | (for DDR3-1600) are 312 to 792. | |
37781a1a | 152 | |
47e3501a SS |
153 | if MACH_SUN5I || MACH_SUN7I |
154 | config DRAM_MBUS_CLK | |
155 | int "sunxi mbus clock speed" | |
156 | default 300 | |
157 | ---help--- | |
158 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
159 | ||
160 | endif | |
161 | ||
37781a1a | 162 | config DRAM_ZQ |
8ffc487c HG |
163 | int "sunxi dram zq value" |
164 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
165 | default 127 if MACH_SUN7I | |
58b628ed | 166 | default 4145117 if MACH_SUN9I |
37781a1a | 167 | ---help--- |
e1a0888e | 168 | Set the dram zq value. |
8ffc487c | 169 | |
8975cdf4 HG |
170 | config DRAM_ODT_EN |
171 | bool "sunxi dram odt enable" | |
172 | default n if !MACH_SUN8I_A23 | |
173 | default y if MACH_SUN8I_A23 | |
174 | ---help--- | |
175 | Select this to enable dram odt (on die termination). | |
176 | ||
8ffc487c HG |
177 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
178 | config DRAM_EMR1 | |
179 | int "sunxi dram emr1 value" | |
180 | default 0 if MACH_SUN4I | |
181 | default 4 if MACH_SUN5I || MACH_SUN7I | |
182 | ---help--- | |
e1a0888e | 183 | Set the dram controller emr1 value. |
d133647a | 184 | |
47e3501a SS |
185 | config DRAM_TPR3 |
186 | hex "sunxi dram tpr3 value" | |
187 | default 0 | |
188 | ---help--- | |
189 | Set the dram controller tpr3 parameter. This parameter configures | |
190 | the delay on the command lane and also phase shifts, which are | |
191 | applied for sampling incoming read data. The default value 0 | |
192 | means that no phase/delay adjustments are necessary. Properly | |
193 | configuring this parameter increases reliability at high DRAM | |
194 | clock speeds. | |
195 | ||
196 | config DRAM_DQS_GATING_DELAY | |
197 | hex "sunxi dram dqs_gating_delay value" | |
198 | default 0 | |
199 | ---help--- | |
200 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
201 | encodes the DQS gating delay for each byte lane. The delay | |
202 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
203 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
204 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
205 | The default value 0 means autodetection. The results of hardware | |
206 | autodetection are not very reliable and depend on the chip | |
207 | temperature (sometimes producing different results on cold start | |
208 | and warm reboot). But the accuracy of hardware autodetection | |
209 | is usually good enough, unless running at really high DRAM | |
210 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
211 | ||
d133647a SS |
212 | choice |
213 | prompt "sunxi dram timings" | |
214 | default DRAM_TIMINGS_VENDOR_MAGIC | |
215 | ---help--- | |
216 | Select the timings of the DDR3 chips. | |
217 | ||
218 | config DRAM_TIMINGS_VENDOR_MAGIC | |
219 | bool "Magic vendor timings from Android" | |
220 | ---help--- | |
221 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
222 | ||
223 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
224 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
225 | ---help--- | |
226 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
227 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
228 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
229 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
230 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
231 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
232 | uses a bit faster timings than DDR3-1333H). | |
233 | ||
234 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
235 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
236 | ---help--- | |
237 | Use the timings of the slowest possible JEDEC speed bin for the | |
238 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
239 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
240 | ||
241 | endchoice | |
242 | ||
37781a1a HG |
243 | endif |
244 | ||
8975cdf4 HG |
245 | if MACH_SUN8I_A23 |
246 | config DRAM_ODT_CORRECTION | |
247 | int "sunxi dram odt correction value" | |
248 | default 0 | |
249 | ---help--- | |
250 | Set the dram odt correction value (range -255 - 255). In allwinner | |
251 | fex files, this option is found in bits 8-15 of the u32 odt_en variable | |
252 | in the [dram] section. When bit 31 of the odt_en variable is set | |
253 | then the correction is negative. Usually the value for this is 0. | |
254 | endif | |
255 | ||
e71b422b | 256 | config SYS_CLK_FREQ |
d96ebc46 | 257 | default 816000000 if MACH_SUN50I |
e71b422b | 258 | default 912000000 if MACH_SUN7I |
c53344ad | 259 | default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I |
e71b422b | 260 | |
8a6564da | 261 | config SYS_CONFIG_NAME |
c3be2793 IC |
262 | default "sun4i" if MACH_SUN4I |
263 | default "sun5i" if MACH_SUN5I | |
264 | default "sun6i" if MACH_SUN6I | |
265 | default "sun7i" if MACH_SUN7I | |
266 | default "sun8i" if MACH_SUN8I | |
1871a8ca | 267 | default "sun9i" if MACH_SUN9I |
d96ebc46 | 268 | default "sun50i" if MACH_SUN50I |
dd84058d | 269 | |
dd84058d | 270 | config SYS_BOARD |
dd84058d MY |
271 | default "sunxi" |
272 | ||
273 | config SYS_SOC | |
dd84058d MY |
274 | default "sunxi" |
275 | ||
f0ce28e9 SS |
276 | config UART0_PORT_F |
277 | bool "UART0 on MicroSD breakout board" | |
f0ce28e9 SS |
278 | default n |
279 | ---help--- | |
280 | Repurpose the SD card slot for getting access to the UART0 serial | |
281 | console. Primarily useful only for low level u-boot debugging on | |
282 | tablets, where normal UART0 is difficult to access and requires | |
283 | device disassembly and/or soldering. As the SD card can't be used | |
284 | at the same time, the system can be only booted in the FEL mode. | |
285 | Only enable this if you really know what you are doing. | |
286 | ||
accc9e44 | 287 | config OLD_SUNXI_KERNEL_COMPAT |
ab65006b | 288 | bool "Enable workarounds for booting old kernels" |
accc9e44 HG |
289 | default n |
290 | ---help--- | |
291 | Set this to enable various workarounds for old kernels, this results in | |
292 | sub-optimal settings for newer kernels, only enable if needed. | |
293 | ||
44c79879 MR |
294 | config MMC |
295 | depends on !UART0_PORT_F | |
296 | default y if ARCH_SUNXI | |
297 | ||
cd82113a HG |
298 | config MMC0_CD_PIN |
299 | string "Card detect pin for mmc0" | |
acdab175 | 300 | default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I |
cd82113a HG |
301 | default "" |
302 | ---help--- | |
303 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
304 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
305 | PH1 for pin 1 of port H. | |
306 | ||
307 | config MMC1_CD_PIN | |
308 | string "Card detect pin for mmc1" | |
309 | default "" | |
310 | ---help--- | |
311 | See MMC0_CD_PIN help text. | |
312 | ||
313 | config MMC2_CD_PIN | |
314 | string "Card detect pin for mmc2" | |
315 | default "" | |
316 | ---help--- | |
317 | See MMC0_CD_PIN help text. | |
318 | ||
319 | config MMC3_CD_PIN | |
320 | string "Card detect pin for mmc3" | |
321 | default "" | |
322 | ---help--- | |
323 | See MMC0_CD_PIN help text. | |
324 | ||
8deacca9 PK |
325 | config MMC1_PINS |
326 | string "Pins for mmc1" | |
327 | default "" | |
328 | ---help--- | |
329 | Set the pins used for mmc1, when applicable. This takes a string in the | |
330 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
331 | ||
332 | config MMC2_PINS | |
333 | string "Pins for mmc2" | |
334 | default "" | |
335 | ---help--- | |
336 | See MMC1_PINS help text. | |
337 | ||
338 | config MMC3_PINS | |
339 | string "Pins for mmc3" | |
340 | default "" | |
341 | ---help--- | |
342 | See MMC1_PINS help text. | |
343 | ||
2ccfac01 HG |
344 | config MMC_SUNXI_SLOT_EXTRA |
345 | int "mmc extra slot number" | |
346 | default -1 | |
347 | ---help--- | |
348 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
349 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
350 | support for this. | |
351 | ||
2c3c3ecb HG |
352 | config INITIAL_USB_SCAN_DELAY |
353 | int "delay initial usb scan by x ms to allow builtin devices to init" | |
354 | default 0 | |
355 | ---help--- | |
356 | Some boards have on board usb devices which need longer than the | |
357 | USB spec's 1 second to connect from board powerup. Set this config | |
358 | option to a non 0 value to add an extra delay before the first usb | |
359 | bus scan. | |
360 | ||
4458b7a6 HG |
361 | config USB0_VBUS_PIN |
362 | string "Vbus enable pin for usb0 (otg)" | |
363 | default "" | |
364 | ---help--- | |
365 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
366 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
367 | ||
52defe8f HG |
368 | config USB0_VBUS_DET |
369 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
370 | default "" |
371 | ---help--- | |
372 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
373 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
374 | ||
48c06c98 HG |
375 | config USB0_ID_DET |
376 | string "ID detect pin for usb0 (otg)" | |
377 | default "" | |
378 | ---help--- | |
379 | Set the ID detect pin for usb0 (otg). This takes a string in the | |
380 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
381 | ||
115200ce HG |
382 | config USB1_VBUS_PIN |
383 | string "Vbus enable pin for usb1 (ehci0)" | |
384 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 385 | default "PH27" if MACH_SUN6I |
115200ce HG |
386 | ---help--- |
387 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
388 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
389 | PH1 for pin 1 of port H. | |
390 | ||
391 | config USB2_VBUS_PIN | |
392 | string "Vbus enable pin for usb2 (ehci1)" | |
393 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 394 | default "PH24" if MACH_SUN6I |
115200ce HG |
395 | ---help--- |
396 | See USB1_VBUS_PIN help text. | |
397 | ||
60fa6301 HG |
398 | config USB3_VBUS_PIN |
399 | string "Vbus enable pin for usb3 (ehci2)" | |
400 | default "" | |
401 | ---help--- | |
402 | See USB1_VBUS_PIN help text. | |
403 | ||
6c739c5d PK |
404 | config I2C0_ENABLE |
405 | bool "Enable I2C/TWI controller 0" | |
406 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
407 | default n if MACH_SUN6I || MACH_SUN8I | |
0878a8a7 | 408 | select CMD_I2C |
6c739c5d PK |
409 | ---help--- |
410 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
411 | its clock and setting up the bus. This is especially useful on devices | |
412 | with slaves connected to the bus or with pins exposed through e.g. an | |
413 | expansion port/header. | |
414 | ||
415 | config I2C1_ENABLE | |
416 | bool "Enable I2C/TWI controller 1" | |
417 | default n | |
0878a8a7 | 418 | select CMD_I2C |
6c739c5d PK |
419 | ---help--- |
420 | See I2C0_ENABLE help text. | |
421 | ||
422 | config I2C2_ENABLE | |
423 | bool "Enable I2C/TWI controller 2" | |
424 | default n | |
0878a8a7 | 425 | select CMD_I2C |
6c739c5d PK |
426 | ---help--- |
427 | See I2C0_ENABLE help text. | |
428 | ||
429 | if MACH_SUN6I || MACH_SUN7I | |
430 | config I2C3_ENABLE | |
431 | bool "Enable I2C/TWI controller 3" | |
432 | default n | |
0878a8a7 | 433 | select CMD_I2C |
6c739c5d PK |
434 | ---help--- |
435 | See I2C0_ENABLE help text. | |
436 | endif | |
437 | ||
0d8382ae | 438 | if SUNXI_GEN_SUN6I |
9d082687 JW |
439 | config R_I2C_ENABLE |
440 | bool "Enable the PRCM I2C/TWI controller" | |
0d8382ae JW |
441 | # This is used for the pmic on H3 |
442 | default y if SY8106A_POWER | |
0878a8a7 | 443 | select CMD_I2C |
9d082687 JW |
444 | ---help--- |
445 | Set this to y to enable the I2C controller which is part of the PRCM. | |
0d8382ae | 446 | endif |
9d082687 | 447 | |
6c739c5d PK |
448 | if MACH_SUN7I |
449 | config I2C4_ENABLE | |
450 | bool "Enable I2C/TWI controller 4" | |
451 | default n | |
0878a8a7 | 452 | select CMD_I2C |
6c739c5d PK |
453 | ---help--- |
454 | See I2C0_ENABLE help text. | |
455 | endif | |
456 | ||
2fcf033d | 457 | config AXP_GPIO |
ab65006b | 458 | bool "Enable support for gpio-s on axp PMICs" |
2fcf033d HG |
459 | default n |
460 | ---help--- | |
461 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
462 | ||
7f2c521f | 463 | config VIDEO |
ab65006b | 464 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
fa855d3d | 465 | depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I |
7f2c521f LV |
466 | default y |
467 | ---help--- | |
2dae800f HG |
468 | Say Y here to add support for using a cfb console on the HDMI, LCD |
469 | or VGA output found on most sunxi devices. See doc/README.video for | |
470 | info on how to select the video output and mode. | |
471 | ||
2fbf091a | 472 | config VIDEO_HDMI |
ab65006b | 473 | bool "HDMI output support" |
2fbf091a HG |
474 | depends on VIDEO && !MACH_SUN8I |
475 | default y | |
476 | ---help--- | |
477 | Say Y here to add support for outputting video over HDMI. | |
478 | ||
d9786d23 | 479 | config VIDEO_VGA |
ab65006b | 480 | bool "VGA output support" |
d9786d23 HG |
481 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
482 | default n | |
483 | ---help--- | |
484 | Say Y here to add support for outputting video over VGA. | |
485 | ||
e2bbdfb1 | 486 | config VIDEO_VGA_VIA_LCD |
ab65006b | 487 | bool "VGA via LCD controller support" |
2583d5b1 | 488 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
489 | default n |
490 | ---help--- | |
491 | Say Y here to add support for external DACs connected to the parallel | |
492 | LCD interface driving a VGA connector, such as found on the | |
493 | Olimex A13 boards. | |
494 | ||
fb75d972 | 495 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
ab65006b | 496 | bool "Force sync active high for VGA via LCD controller support" |
fb75d972 HG |
497 | depends on VIDEO_VGA_VIA_LCD |
498 | default n | |
499 | ---help--- | |
500 | Say Y here if you've a board which uses opendrain drivers for the vga | |
501 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
502 | positive edges for a stable video output, so on boards with opendrain | |
503 | drivers the sync signals must always be active high. | |
504 | ||
507e27df CYT |
505 | config VIDEO_VGA_EXTERNAL_DAC_EN |
506 | string "LCD panel power enable pin" | |
507 | depends on VIDEO_VGA_VIA_LCD | |
508 | default "" | |
509 | ---help--- | |
510 | Set the enable pin for the external VGA DAC. This takes a string in the | |
511 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
512 | ||
39920c81 | 513 | config VIDEO_COMPOSITE |
ab65006b | 514 | bool "Composite video output support" |
39920c81 HG |
515 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
516 | default n | |
517 | ---help--- | |
518 | Say Y here to add support for outputting composite video. | |
519 | ||
2dae800f HG |
520 | config VIDEO_LCD_MODE |
521 | string "LCD panel timing details" | |
522 | depends on VIDEO | |
523 | default "" | |
524 | ---help--- | |
525 | LCD panel timing details string, leave empty if there is no LCD panel. | |
526 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
527 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
8addd3ed | 528 | Also see: http://linux-sunxi.org/LCD |
2dae800f | 529 | |
6515032e HG |
530 | config VIDEO_LCD_DCLK_PHASE |
531 | int "LCD panel display clock phase" | |
532 | depends on VIDEO | |
533 | default 1 | |
534 | ---help--- | |
535 | Select LCD panel display clock phase shift, range 0-3. | |
536 | ||
2dae800f HG |
537 | config VIDEO_LCD_POWER |
538 | string "LCD panel power enable pin" | |
539 | depends on VIDEO | |
540 | default "" | |
541 | ---help--- | |
542 | Set the power enable pin for the LCD panel. This takes a string in the | |
543 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
544 | ||
242e3d89 HG |
545 | config VIDEO_LCD_RESET |
546 | string "LCD panel reset pin" | |
547 | depends on VIDEO | |
548 | default "" | |
549 | ---help--- | |
550 | Set the reset pin for the LCD panel. This takes a string in the format | |
551 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
552 | ||
2dae800f HG |
553 | config VIDEO_LCD_BL_EN |
554 | string "LCD panel backlight enable pin" | |
555 | depends on VIDEO | |
556 | default "" | |
557 | ---help--- | |
558 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
559 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
560 | port H. | |
561 | ||
562 | config VIDEO_LCD_BL_PWM | |
563 | string "LCD panel backlight pwm pin" | |
564 | depends on VIDEO | |
565 | default "" | |
566 | ---help--- | |
567 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
568 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 569 | |
a7403ae8 HG |
570 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
571 | bool "LCD panel backlight pwm is inverted" | |
572 | depends on VIDEO | |
573 | default y | |
574 | ---help--- | |
575 | Set this if the backlight pwm output is active low. | |
576 | ||
55410089 HG |
577 | config VIDEO_LCD_PANEL_I2C |
578 | bool "LCD panel needs to be configured via i2c" | |
579 | depends on VIDEO | |
1fc42018 | 580 | default n |
0878a8a7 | 581 | select CMD_I2C |
55410089 HG |
582 | ---help--- |
583 | Say y here if the LCD panel needs to be configured via i2c. This | |
584 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
585 | ||
586 | config VIDEO_LCD_PANEL_I2C_SDA | |
587 | string "LCD panel i2c interface SDA pin" | |
588 | depends on VIDEO_LCD_PANEL_I2C | |
589 | default "PG12" | |
590 | ---help--- | |
591 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
592 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
593 | ||
594 | config VIDEO_LCD_PANEL_I2C_SCL | |
595 | string "LCD panel i2c interface SCL pin" | |
596 | depends on VIDEO_LCD_PANEL_I2C | |
597 | default "PG10" | |
598 | ---help--- | |
599 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
600 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
601 | ||
213480e1 HG |
602 | |
603 | # Note only one of these may be selected at a time! But hidden choices are | |
604 | # not supported by Kconfig | |
605 | config VIDEO_LCD_IF_PARALLEL | |
606 | bool | |
607 | ||
608 | config VIDEO_LCD_IF_LVDS | |
609 | bool | |
610 | ||
611 | ||
612 | choice | |
613 | prompt "LCD panel support" | |
614 | depends on VIDEO | |
615 | ---help--- | |
616 | Select which type of LCD panel to support. | |
617 | ||
618 | config VIDEO_LCD_PANEL_PARALLEL | |
619 | bool "Generic parallel interface LCD panel" | |
620 | select VIDEO_LCD_IF_PARALLEL | |
621 | ||
622 | config VIDEO_LCD_PANEL_LVDS | |
623 | bool "Generic lvds interface LCD panel" | |
624 | select VIDEO_LCD_IF_LVDS | |
625 | ||
97ece830 SS |
626 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
627 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
628 | select VIDEO_LCD_SSD2828 | |
629 | select VIDEO_LCD_IF_PARALLEL | |
630 | ---help--- | |
c1cfd519 HG |
631 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
632 | ||
633 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 | |
634 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" | |
635 | select VIDEO_LCD_ANX9804 | |
636 | select VIDEO_LCD_IF_PARALLEL | |
637 | select VIDEO_LCD_PANEL_I2C | |
638 | ---help--- | |
639 | Select this for eDP LCD panels with 4 lanes running at 1.62G, | |
640 | connected via an ANX9804 bridge chip. | |
97ece830 | 641 | |
27515b20 HG |
642 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
643 | bool "Hitachi tx18d42vm LCD panel" | |
644 | select VIDEO_LCD_HITACHI_TX18D42VM | |
645 | select VIDEO_LCD_IF_LVDS | |
646 | ---help--- | |
647 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
648 | ||
aad2ac24 HG |
649 | config VIDEO_LCD_TL059WV5C0 |
650 | bool "tl059wv5c0 LCD panel" | |
651 | select VIDEO_LCD_PANEL_I2C | |
652 | select VIDEO_LCD_IF_PARALLEL | |
653 | ---help--- | |
654 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
655 | Aigo M60/M608/M606 tablets. | |
656 | ||
213480e1 HG |
657 | endchoice |
658 | ||
659 | ||
c13f60d9 HG |
660 | config GMAC_TX_DELAY |
661 | int "GMAC Transmit Clock Delay Chain" | |
662 | default 0 | |
663 | ---help--- | |
664 | Set the GMAC Transmit Clock Delay Chain value. | |
665 | ||
ff42d107 | 666 | config SPL_STACK_R_ADDR |
d96ebc46 | 667 | default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I |
ff42d107 HG |
668 | default 0x2fe00000 if MACH_SUN9I |
669 | ||
dd84058d | 670 | endif |