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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
a4d88920 SDPP |
3 | config IDENT_STRING |
4 | default " Allwinner Technology" | |
5 | ||
0dcf18c6 | 6 | # FIXME: Should not redefine these Kconfig symbols |
8f925584 SG |
7 | config PRE_CONSOLE_BUFFER |
8 | default y | |
9 | ||
53b5bf3c SG |
10 | config SPL_GPIO_SUPPORT |
11 | default y | |
12 | ||
77d2f7f5 SG |
13 | config SPL_LIBCOMMON_SUPPORT |
14 | default y | |
15 | ||
1646eba8 SG |
16 | config SPL_LIBDISK_SUPPORT |
17 | default y | |
18 | ||
cc4288ef SG |
19 | config SPL_LIBGENERIC_SUPPORT |
20 | default y | |
21 | ||
1fdf7c64 | 22 | config SPL_MMC_SUPPORT |
0dcf18c6 | 23 | depends on SPL && GENERIC_MMC |
1fdf7c64 SG |
24 | default y |
25 | ||
2253797d SG |
26 | config SPL_POWER_SUPPORT |
27 | default y | |
28 | ||
e00f76ce SG |
29 | config SPL_SERIAL_SUPPORT |
30 | default y | |
31 | ||
bc613d85 AP |
32 | config SUNXI_HIGH_SRAM |
33 | bool | |
34 | default n | |
35 | ---help--- | |
36 | Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, | |
37 | with the first SRAM region being located at address 0. | |
38 | Some newer SoCs map the boot ROM at address 0 instead and move the | |
39 | SRAM to 64KB, just behind the mask ROM. | |
40 | Chips using the latter setup are supposed to select this option to | |
41 | adjust the addresses accordingly. | |
42 | ||
44d8ae5b HG |
43 | # Note only one of these may be selected at a time! But hidden choices are |
44 | # not supported by Kconfig | |
45 | config SUNXI_GEN_SUN4I | |
46 | bool | |
47 | ---help--- | |
48 | Select this for sunxi SoCs which have resets and clocks set up | |
49 | as the original A10 (mach-sun4i). | |
50 | ||
51 | config SUNXI_GEN_SUN6I | |
52 | bool | |
53 | ---help--- | |
54 | Select this for sunxi SoCs which have sun6i like periphery, like | |
55 | separate ahb reset control registers, custom pmic bus, new style | |
56 | watchdog, etc. | |
57 | ||
58 | ||
7b82a229 AP |
59 | config MACH_SUNXI_H3_H5 |
60 | bool | |
61 | select SUNXI_GEN_SUN6I | |
62 | select SUPPORT_SPL | |
63 | ||
2c7e3b90 IC |
64 | choice |
65 | prompt "Sunxi SoC Variant" | |
3da9536e | 66 | optional |
2c7e3b90 | 67 | |
c3be2793 | 68 | config MACH_SUN4I |
2c7e3b90 IC |
69 | bool "sun4i (Allwinner A10)" |
70 | select CPU_V7 | |
85db5831 | 71 | select ARM_CORTEX_CPU_IS_UP |
44d8ae5b | 72 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
73 | select SUPPORT_SPL |
74 | ||
c3be2793 | 75 | config MACH_SUN5I |
2c7e3b90 IC |
76 | bool "sun5i (Allwinner A13)" |
77 | select CPU_V7 | |
85db5831 | 78 | select ARM_CORTEX_CPU_IS_UP |
44d8ae5b | 79 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
80 | select SUPPORT_SPL |
81 | ||
c3be2793 | 82 | config MACH_SUN6I |
2c7e3b90 IC |
83 | bool "sun6i (Allwinner A31)" |
84 | select CPU_V7 | |
cc08ea4c CYT |
85 | select CPU_V7_HAS_NONSEC |
86 | select CPU_V7_HAS_VIRT | |
217f92bb | 87 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 88 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 89 | select SUPPORT_SPL |
cc08ea4c | 90 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 91 | |
c3be2793 | 92 | config MACH_SUN7I |
2c7e3b90 IC |
93 | bool "sun7i (Allwinner A20)" |
94 | select CPU_V7 | |
ea624e19 HG |
95 | select CPU_V7_HAS_NONSEC |
96 | select CPU_V7_HAS_VIRT | |
217f92bb | 97 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 98 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 99 | select SUPPORT_SPL |
b366fb92 | 100 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 101 | |
5e6bacdb | 102 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
103 | bool "sun8i (Allwinner A23)" |
104 | select CPU_V7 | |
014414f5 CYT |
105 | select CPU_V7_HAS_NONSEC |
106 | select CPU_V7_HAS_VIRT | |
217f92bb | 107 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 108 | select SUNXI_GEN_SUN6I |
08fd1479 | 109 | select SUPPORT_SPL |
014414f5 | 110 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 111 | |
8c3dacff VP |
112 | config MACH_SUN8I_A33 |
113 | bool "sun8i (Allwinner A33)" | |
114 | select CPU_V7 | |
014414f5 CYT |
115 | select CPU_V7_HAS_NONSEC |
116 | select CPU_V7_HAS_VIRT | |
217f92bb | 117 | select ARCH_SUPPORT_PSCI |
8c3dacff VP |
118 | select SUNXI_GEN_SUN6I |
119 | select SUPPORT_SPL | |
014414f5 | 120 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
8c3dacff | 121 | |
a81b7995 CYT |
122 | config MACH_SUN8I_A83T |
123 | bool "sun8i (Allwinner A83T)" | |
124 | select CPU_V7 | |
125 | select SUNXI_GEN_SUN6I | |
126 | select SUPPORT_SPL | |
127 | ||
1c27b7dc JK |
128 | config MACH_SUN8I_H3 |
129 | bool "sun8i (Allwinner H3)" | |
130 | select CPU_V7 | |
853f6d1e CYT |
131 | select CPU_V7_HAS_NONSEC |
132 | select CPU_V7_HAS_VIRT | |
217f92bb | 133 | select ARCH_SUPPORT_PSCI |
7b82a229 | 134 | select MACH_SUNXI_H3_H5 |
853f6d1e | 135 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
1c27b7dc | 136 | |
379febac CYT |
137 | config MACH_SUN8I_R40 |
138 | bool "sun8i (Allwinner R40)" | |
139 | select CPU_V7 | |
140 | select SUNXI_GEN_SUN6I | |
141 | ||
1871a8ca HG |
142 | config MACH_SUN9I |
143 | bool "sun9i (Allwinner A80)" | |
144 | select CPU_V7 | |
bc613d85 | 145 | select SUNXI_HIGH_SRAM |
1871a8ca | 146 | select SUNXI_GEN_SUN6I |
a98c296a | 147 | select SUPPORT_SPL |
1871a8ca | 148 | |
a81b7995 CYT |
149 | config MACH_SUN50I |
150 | bool "sun50i (Allwinner A64)" | |
151 | select ARM64 | |
152 | select SUNXI_GEN_SUN6I | |
bc613d85 | 153 | select SUNXI_HIGH_SRAM |
eb77f5c9 | 154 | select SUPPORT_SPL |
a81b7995 | 155 | |
997bde60 AP |
156 | config MACH_SUN50I_H5 |
157 | bool "sun50i (Allwinner H5)" | |
158 | select ARM64 | |
159 | select MACH_SUNXI_H3_H5 | |
160 | select SUNXI_HIGH_SRAM | |
161 | ||
2c7e3b90 | 162 | endchoice |
8a6564da | 163 | |
5e6bacdb HG |
164 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
165 | config MACH_SUN8I | |
166 | bool | |
301791c9 CYT |
167 | default y if MACH_SUN8I_A23 |
168 | default y if MACH_SUN8I_A33 | |
169 | default y if MACH_SUN8I_A83T | |
170 | default y if MACH_SUNXI_H3_H5 | |
379febac | 171 | default y if MACH_SUN8I_R40 |
5e6bacdb | 172 | |
b5402d13 AP |
173 | config RESERVE_ALLWINNER_BOOT0_HEADER |
174 | bool "reserve space for Allwinner boot0 header" | |
175 | select ENABLE_ARM_SOC_BOOT0_HOOK | |
176 | ---help--- | |
177 | Prepend a 1536 byte (empty) header to the U-Boot image file, to be | |
178 | filled with magic values post build. The Allwinner provided boot0 | |
179 | blob relies on this information to load and execute U-Boot. | |
180 | Only needed on 64-bit Allwinner boards so far when using boot0. | |
181 | ||
83843c9b AP |
182 | config ARM_BOOT_HOOK_RMR |
183 | bool | |
184 | depends on ARM64 | |
185 | default y | |
186 | select ENABLE_ARM_SOC_BOOT0_HOOK | |
187 | ---help--- | |
188 | Insert some ARM32 code at the very beginning of the U-Boot binary | |
189 | which uses an RMR register write to bring the core into AArch64 mode. | |
190 | The very first instruction acts as a switch, since it's carefully | |
191 | chosen to be a NOP in one mode and a branch in the other, so the | |
192 | code would only be executed if not already in AArch64. | |
193 | This allows both the SPL and the U-Boot proper to be entered in | |
194 | either mode and switch to AArch64 if needed. | |
195 | ||
f5fd8caf VP |
196 | config DRAM_TYPE |
197 | int "sunxi dram type" | |
198 | depends on MACH_SUN8I_A83T | |
199 | default 3 | |
200 | ---help--- | |
201 | Set the dram type, 3: DDR3, 7: LPDDR3 | |
5e6bacdb | 202 | |
37781a1a | 203 | config DRAM_CLK |
8ffc487c | 204 | int "sunxi dram clock speed" |
297bb9e0 | 205 | default 792 if MACH_SUN9I |
8ffc487c HG |
206 | default 312 if MACH_SUN6I || MACH_SUN8I |
207 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
52e3182b | 208 | default 672 if MACH_SUN50I |
37781a1a | 209 | ---help--- |
297bb9e0 PT |
210 | Set the dram clock speed, valid range 240 - 480 (prior to sun9i), |
211 | must be a multiple of 24. For the sun9i (A80), the tested values | |
212 | (for DDR3-1600) are 312 to 792. | |
37781a1a | 213 | |
47e3501a SS |
214 | if MACH_SUN5I || MACH_SUN7I |
215 | config DRAM_MBUS_CLK | |
216 | int "sunxi mbus clock speed" | |
217 | default 300 | |
218 | ---help--- | |
219 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
220 | ||
221 | endif | |
222 | ||
37781a1a | 223 | config DRAM_ZQ |
8ffc487c HG |
224 | int "sunxi dram zq value" |
225 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
226 | default 127 if MACH_SUN7I | |
58b628ed | 227 | default 4145117 if MACH_SUN9I |
52e3182b | 228 | default 3881915 if MACH_SUN50I |
37781a1a | 229 | ---help--- |
e1a0888e | 230 | Set the dram zq value. |
8ffc487c | 231 | |
8975cdf4 HG |
232 | config DRAM_ODT_EN |
233 | bool "sunxi dram odt enable" | |
234 | default n if !MACH_SUN8I_A23 | |
235 | default y if MACH_SUN8I_A23 | |
eb77f5c9 | 236 | default y if MACH_SUN50I |
8975cdf4 HG |
237 | ---help--- |
238 | Select this to enable dram odt (on die termination). | |
239 | ||
8ffc487c HG |
240 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
241 | config DRAM_EMR1 | |
242 | int "sunxi dram emr1 value" | |
243 | default 0 if MACH_SUN4I | |
244 | default 4 if MACH_SUN5I || MACH_SUN7I | |
245 | ---help--- | |
e1a0888e | 246 | Set the dram controller emr1 value. |
d133647a | 247 | |
47e3501a SS |
248 | config DRAM_TPR3 |
249 | hex "sunxi dram tpr3 value" | |
250 | default 0 | |
251 | ---help--- | |
252 | Set the dram controller tpr3 parameter. This parameter configures | |
253 | the delay on the command lane and also phase shifts, which are | |
254 | applied for sampling incoming read data. The default value 0 | |
255 | means that no phase/delay adjustments are necessary. Properly | |
256 | configuring this parameter increases reliability at high DRAM | |
257 | clock speeds. | |
258 | ||
259 | config DRAM_DQS_GATING_DELAY | |
260 | hex "sunxi dram dqs_gating_delay value" | |
261 | default 0 | |
262 | ---help--- | |
263 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
264 | encodes the DQS gating delay for each byte lane. The delay | |
265 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
266 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
267 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
268 | The default value 0 means autodetection. The results of hardware | |
269 | autodetection are not very reliable and depend on the chip | |
270 | temperature (sometimes producing different results on cold start | |
271 | and warm reboot). But the accuracy of hardware autodetection | |
272 | is usually good enough, unless running at really high DRAM | |
273 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
274 | ||
d133647a SS |
275 | choice |
276 | prompt "sunxi dram timings" | |
277 | default DRAM_TIMINGS_VENDOR_MAGIC | |
278 | ---help--- | |
279 | Select the timings of the DDR3 chips. | |
280 | ||
281 | config DRAM_TIMINGS_VENDOR_MAGIC | |
282 | bool "Magic vendor timings from Android" | |
283 | ---help--- | |
284 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
285 | ||
286 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
287 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
288 | ---help--- | |
289 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
290 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
291 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
292 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
293 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
294 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
295 | uses a bit faster timings than DDR3-1333H). | |
296 | ||
297 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
298 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
299 | ---help--- | |
300 | Use the timings of the slowest possible JEDEC speed bin for the | |
301 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
302 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
303 | ||
304 | endchoice | |
305 | ||
37781a1a HG |
306 | endif |
307 | ||
8975cdf4 HG |
308 | if MACH_SUN8I_A23 |
309 | config DRAM_ODT_CORRECTION | |
310 | int "sunxi dram odt correction value" | |
311 | default 0 | |
312 | ---help--- | |
313 | Set the dram odt correction value (range -255 - 255). In allwinner | |
314 | fex files, this option is found in bits 8-15 of the u32 odt_en variable | |
315 | in the [dram] section. When bit 31 of the odt_en variable is set | |
316 | then the correction is negative. Usually the value for this is 0. | |
317 | endif | |
318 | ||
e71b422b | 319 | config SYS_CLK_FREQ |
301791c9 CYT |
320 | default 1008000000 if MACH_SUN4I |
321 | default 1008000000 if MACH_SUN5I | |
322 | default 1008000000 if MACH_SUN6I | |
e71b422b | 323 | default 912000000 if MACH_SUN7I |
301791c9 CYT |
324 | default 1008000000 if MACH_SUN8I |
325 | default 1008000000 if MACH_SUN9I | |
326 | default 816000000 if MACH_SUN50I | |
e71b422b | 327 | |
8a6564da | 328 | config SYS_CONFIG_NAME |
c3be2793 IC |
329 | default "sun4i" if MACH_SUN4I |
330 | default "sun5i" if MACH_SUN5I | |
331 | default "sun6i" if MACH_SUN6I | |
332 | default "sun7i" if MACH_SUN7I | |
333 | default "sun8i" if MACH_SUN8I | |
1871a8ca | 334 | default "sun9i" if MACH_SUN9I |
d96ebc46 | 335 | default "sun50i" if MACH_SUN50I |
dd84058d | 336 | |
dd84058d | 337 | config SYS_BOARD |
dd84058d MY |
338 | default "sunxi" |
339 | ||
340 | config SYS_SOC | |
dd84058d MY |
341 | default "sunxi" |
342 | ||
f0ce28e9 SS |
343 | config UART0_PORT_F |
344 | bool "UART0 on MicroSD breakout board" | |
f0ce28e9 SS |
345 | default n |
346 | ---help--- | |
347 | Repurpose the SD card slot for getting access to the UART0 serial | |
348 | console. Primarily useful only for low level u-boot debugging on | |
349 | tablets, where normal UART0 is difficult to access and requires | |
350 | device disassembly and/or soldering. As the SD card can't be used | |
351 | at the same time, the system can be only booted in the FEL mode. | |
352 | Only enable this if you really know what you are doing. | |
353 | ||
accc9e44 | 354 | config OLD_SUNXI_KERNEL_COMPAT |
ab65006b | 355 | bool "Enable workarounds for booting old kernels" |
accc9e44 HG |
356 | default n |
357 | ---help--- | |
358 | Set this to enable various workarounds for old kernels, this results in | |
359 | sub-optimal settings for newer kernels, only enable if needed. | |
360 | ||
f5fd7886 MJ |
361 | config MACPWR |
362 | string "MAC power pin" | |
363 | default "" | |
364 | help | |
365 | Set the pin used to power the MAC. This takes a string in the format | |
366 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
367 | ||
cd82113a HG |
368 | config MMC0_CD_PIN |
369 | string "Card detect pin for mmc0" | |
7b82a229 | 370 | default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I |
cd82113a HG |
371 | default "" |
372 | ---help--- | |
373 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
374 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
375 | PH1 for pin 1 of port H. | |
376 | ||
377 | config MMC1_CD_PIN | |
378 | string "Card detect pin for mmc1" | |
379 | default "" | |
380 | ---help--- | |
381 | See MMC0_CD_PIN help text. | |
382 | ||
383 | config MMC2_CD_PIN | |
384 | string "Card detect pin for mmc2" | |
385 | default "" | |
386 | ---help--- | |
387 | See MMC0_CD_PIN help text. | |
388 | ||
389 | config MMC3_CD_PIN | |
390 | string "Card detect pin for mmc3" | |
391 | default "" | |
392 | ---help--- | |
393 | See MMC0_CD_PIN help text. | |
394 | ||
8deacca9 PK |
395 | config MMC1_PINS |
396 | string "Pins for mmc1" | |
397 | default "" | |
398 | ---help--- | |
399 | Set the pins used for mmc1, when applicable. This takes a string in the | |
400 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
401 | ||
402 | config MMC2_PINS | |
403 | string "Pins for mmc2" | |
404 | default "" | |
405 | ---help--- | |
406 | See MMC1_PINS help text. | |
407 | ||
408 | config MMC3_PINS | |
409 | string "Pins for mmc3" | |
410 | default "" | |
411 | ---help--- | |
412 | See MMC1_PINS help text. | |
413 | ||
2ccfac01 HG |
414 | config MMC_SUNXI_SLOT_EXTRA |
415 | int "mmc extra slot number" | |
416 | default -1 | |
417 | ---help--- | |
418 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
419 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
420 | support for this. | |
421 | ||
2c3c3ecb HG |
422 | config INITIAL_USB_SCAN_DELAY |
423 | int "delay initial usb scan by x ms to allow builtin devices to init" | |
424 | default 0 | |
425 | ---help--- | |
426 | Some boards have on board usb devices which need longer than the | |
427 | USB spec's 1 second to connect from board powerup. Set this config | |
428 | option to a non 0 value to add an extra delay before the first usb | |
429 | bus scan. | |
430 | ||
4458b7a6 HG |
431 | config USB0_VBUS_PIN |
432 | string "Vbus enable pin for usb0 (otg)" | |
433 | default "" | |
434 | ---help--- | |
435 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
436 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
437 | ||
52defe8f HG |
438 | config USB0_VBUS_DET |
439 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
440 | default "" |
441 | ---help--- | |
442 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
443 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
444 | ||
48c06c98 HG |
445 | config USB0_ID_DET |
446 | string "ID detect pin for usb0 (otg)" | |
447 | default "" | |
448 | ---help--- | |
449 | Set the ID detect pin for usb0 (otg). This takes a string in the | |
450 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
451 | ||
115200ce HG |
452 | config USB1_VBUS_PIN |
453 | string "Vbus enable pin for usb1 (ehci0)" | |
454 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 455 | default "PH27" if MACH_SUN6I |
115200ce HG |
456 | ---help--- |
457 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
458 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
459 | PH1 for pin 1 of port H. | |
460 | ||
461 | config USB2_VBUS_PIN | |
462 | string "Vbus enable pin for usb2 (ehci1)" | |
463 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 464 | default "PH24" if MACH_SUN6I |
115200ce HG |
465 | ---help--- |
466 | See USB1_VBUS_PIN help text. | |
467 | ||
60fa6301 HG |
468 | config USB3_VBUS_PIN |
469 | string "Vbus enable pin for usb3 (ehci2)" | |
470 | default "" | |
471 | ---help--- | |
472 | See USB1_VBUS_PIN help text. | |
473 | ||
6c739c5d PK |
474 | config I2C0_ENABLE |
475 | bool "Enable I2C/TWI controller 0" | |
476 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
477 | default n if MACH_SUN6I || MACH_SUN8I | |
0878a8a7 | 478 | select CMD_I2C |
6c739c5d PK |
479 | ---help--- |
480 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
481 | its clock and setting up the bus. This is especially useful on devices | |
482 | with slaves connected to the bus or with pins exposed through e.g. an | |
483 | expansion port/header. | |
484 | ||
485 | config I2C1_ENABLE | |
486 | bool "Enable I2C/TWI controller 1" | |
487 | default n | |
0878a8a7 | 488 | select CMD_I2C |
6c739c5d PK |
489 | ---help--- |
490 | See I2C0_ENABLE help text. | |
491 | ||
492 | config I2C2_ENABLE | |
493 | bool "Enable I2C/TWI controller 2" | |
494 | default n | |
0878a8a7 | 495 | select CMD_I2C |
6c739c5d PK |
496 | ---help--- |
497 | See I2C0_ENABLE help text. | |
498 | ||
499 | if MACH_SUN6I || MACH_SUN7I | |
500 | config I2C3_ENABLE | |
501 | bool "Enable I2C/TWI controller 3" | |
502 | default n | |
0878a8a7 | 503 | select CMD_I2C |
6c739c5d PK |
504 | ---help--- |
505 | See I2C0_ENABLE help text. | |
506 | endif | |
507 | ||
0d8382ae | 508 | if SUNXI_GEN_SUN6I |
9d082687 JW |
509 | config R_I2C_ENABLE |
510 | bool "Enable the PRCM I2C/TWI controller" | |
0d8382ae JW |
511 | # This is used for the pmic on H3 |
512 | default y if SY8106A_POWER | |
0878a8a7 | 513 | select CMD_I2C |
9d082687 JW |
514 | ---help--- |
515 | Set this to y to enable the I2C controller which is part of the PRCM. | |
0d8382ae | 516 | endif |
9d082687 | 517 | |
6c739c5d PK |
518 | if MACH_SUN7I |
519 | config I2C4_ENABLE | |
520 | bool "Enable I2C/TWI controller 4" | |
521 | default n | |
0878a8a7 | 522 | select CMD_I2C |
6c739c5d PK |
523 | ---help--- |
524 | See I2C0_ENABLE help text. | |
525 | endif | |
526 | ||
2fcf033d | 527 | config AXP_GPIO |
ab65006b | 528 | bool "Enable support for gpio-s on axp PMICs" |
2fcf033d HG |
529 | default n |
530 | ---help--- | |
531 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
532 | ||
7f2c521f | 533 | config VIDEO |
ab65006b | 534 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
301791c9 CYT |
535 | depends on !MACH_SUN8I_A83T |
536 | depends on !MACH_SUNXI_H3_H5 | |
379febac | 537 | depends on !MACH_SUN8I_R40 |
301791c9 CYT |
538 | depends on !MACH_SUN9I |
539 | depends on !MACH_SUN50I | |
7f2c521f LV |
540 | default y |
541 | ---help--- | |
2dae800f HG |
542 | Say Y here to add support for using a cfb console on the HDMI, LCD |
543 | or VGA output found on most sunxi devices. See doc/README.video for | |
544 | info on how to select the video output and mode. | |
545 | ||
2fbf091a | 546 | config VIDEO_HDMI |
ab65006b | 547 | bool "HDMI output support" |
2fbf091a HG |
548 | depends on VIDEO && !MACH_SUN8I |
549 | default y | |
550 | ---help--- | |
551 | Say Y here to add support for outputting video over HDMI. | |
552 | ||
d9786d23 | 553 | config VIDEO_VGA |
ab65006b | 554 | bool "VGA output support" |
d9786d23 HG |
555 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
556 | default n | |
557 | ---help--- | |
558 | Say Y here to add support for outputting video over VGA. | |
559 | ||
e2bbdfb1 | 560 | config VIDEO_VGA_VIA_LCD |
ab65006b | 561 | bool "VGA via LCD controller support" |
2583d5b1 | 562 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
563 | default n |
564 | ---help--- | |
565 | Say Y here to add support for external DACs connected to the parallel | |
566 | LCD interface driving a VGA connector, such as found on the | |
567 | Olimex A13 boards. | |
568 | ||
fb75d972 | 569 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
ab65006b | 570 | bool "Force sync active high for VGA via LCD controller support" |
fb75d972 HG |
571 | depends on VIDEO_VGA_VIA_LCD |
572 | default n | |
573 | ---help--- | |
574 | Say Y here if you've a board which uses opendrain drivers for the vga | |
575 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
576 | positive edges for a stable video output, so on boards with opendrain | |
577 | drivers the sync signals must always be active high. | |
578 | ||
507e27df CYT |
579 | config VIDEO_VGA_EXTERNAL_DAC_EN |
580 | string "LCD panel power enable pin" | |
581 | depends on VIDEO_VGA_VIA_LCD | |
582 | default "" | |
583 | ---help--- | |
584 | Set the enable pin for the external VGA DAC. This takes a string in the | |
585 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
586 | ||
39920c81 | 587 | config VIDEO_COMPOSITE |
ab65006b | 588 | bool "Composite video output support" |
39920c81 HG |
589 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
590 | default n | |
591 | ---help--- | |
592 | Say Y here to add support for outputting composite video. | |
593 | ||
2dae800f HG |
594 | config VIDEO_LCD_MODE |
595 | string "LCD panel timing details" | |
596 | depends on VIDEO | |
597 | default "" | |
598 | ---help--- | |
599 | LCD panel timing details string, leave empty if there is no LCD panel. | |
600 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
601 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
8addd3ed | 602 | Also see: http://linux-sunxi.org/LCD |
2dae800f | 603 | |
6515032e HG |
604 | config VIDEO_LCD_DCLK_PHASE |
605 | int "LCD panel display clock phase" | |
606 | depends on VIDEO | |
607 | default 1 | |
608 | ---help--- | |
609 | Select LCD panel display clock phase shift, range 0-3. | |
610 | ||
2dae800f HG |
611 | config VIDEO_LCD_POWER |
612 | string "LCD panel power enable pin" | |
613 | depends on VIDEO | |
614 | default "" | |
615 | ---help--- | |
616 | Set the power enable pin for the LCD panel. This takes a string in the | |
617 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
618 | ||
242e3d89 HG |
619 | config VIDEO_LCD_RESET |
620 | string "LCD panel reset pin" | |
621 | depends on VIDEO | |
622 | default "" | |
623 | ---help--- | |
624 | Set the reset pin for the LCD panel. This takes a string in the format | |
625 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
626 | ||
2dae800f HG |
627 | config VIDEO_LCD_BL_EN |
628 | string "LCD panel backlight enable pin" | |
629 | depends on VIDEO | |
630 | default "" | |
631 | ---help--- | |
632 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
633 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
634 | port H. | |
635 | ||
636 | config VIDEO_LCD_BL_PWM | |
637 | string "LCD panel backlight pwm pin" | |
638 | depends on VIDEO | |
639 | default "" | |
640 | ---help--- | |
641 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
642 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 643 | |
a7403ae8 HG |
644 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
645 | bool "LCD panel backlight pwm is inverted" | |
646 | depends on VIDEO | |
647 | default y | |
648 | ---help--- | |
649 | Set this if the backlight pwm output is active low. | |
650 | ||
55410089 HG |
651 | config VIDEO_LCD_PANEL_I2C |
652 | bool "LCD panel needs to be configured via i2c" | |
653 | depends on VIDEO | |
1fc42018 | 654 | default n |
0878a8a7 | 655 | select CMD_I2C |
55410089 HG |
656 | ---help--- |
657 | Say y here if the LCD panel needs to be configured via i2c. This | |
658 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
659 | ||
660 | config VIDEO_LCD_PANEL_I2C_SDA | |
661 | string "LCD panel i2c interface SDA pin" | |
662 | depends on VIDEO_LCD_PANEL_I2C | |
663 | default "PG12" | |
664 | ---help--- | |
665 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
666 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
667 | ||
668 | config VIDEO_LCD_PANEL_I2C_SCL | |
669 | string "LCD panel i2c interface SCL pin" | |
670 | depends on VIDEO_LCD_PANEL_I2C | |
671 | default "PG10" | |
672 | ---help--- | |
673 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
674 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
675 | ||
213480e1 HG |
676 | |
677 | # Note only one of these may be selected at a time! But hidden choices are | |
678 | # not supported by Kconfig | |
679 | config VIDEO_LCD_IF_PARALLEL | |
680 | bool | |
681 | ||
682 | config VIDEO_LCD_IF_LVDS | |
683 | bool | |
684 | ||
685 | ||
686 | choice | |
687 | prompt "LCD panel support" | |
688 | depends on VIDEO | |
689 | ---help--- | |
690 | Select which type of LCD panel to support. | |
691 | ||
692 | config VIDEO_LCD_PANEL_PARALLEL | |
693 | bool "Generic parallel interface LCD panel" | |
694 | select VIDEO_LCD_IF_PARALLEL | |
695 | ||
696 | config VIDEO_LCD_PANEL_LVDS | |
697 | bool "Generic lvds interface LCD panel" | |
698 | select VIDEO_LCD_IF_LVDS | |
699 | ||
97ece830 SS |
700 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
701 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
702 | select VIDEO_LCD_SSD2828 | |
703 | select VIDEO_LCD_IF_PARALLEL | |
704 | ---help--- | |
c1cfd519 HG |
705 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
706 | ||
707 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 | |
708 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" | |
709 | select VIDEO_LCD_ANX9804 | |
710 | select VIDEO_LCD_IF_PARALLEL | |
711 | select VIDEO_LCD_PANEL_I2C | |
712 | ---help--- | |
713 | Select this for eDP LCD panels with 4 lanes running at 1.62G, | |
714 | connected via an ANX9804 bridge chip. | |
97ece830 | 715 | |
27515b20 HG |
716 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
717 | bool "Hitachi tx18d42vm LCD panel" | |
718 | select VIDEO_LCD_HITACHI_TX18D42VM | |
719 | select VIDEO_LCD_IF_LVDS | |
720 | ---help--- | |
721 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
722 | ||
aad2ac24 HG |
723 | config VIDEO_LCD_TL059WV5C0 |
724 | bool "tl059wv5c0 LCD panel" | |
725 | select VIDEO_LCD_PANEL_I2C | |
726 | select VIDEO_LCD_IF_PARALLEL | |
727 | ---help--- | |
728 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
729 | Aigo M60/M608/M606 tablets. | |
730 | ||
213480e1 HG |
731 | endchoice |
732 | ||
d7b560e6 MJ |
733 | config SATAPWR |
734 | string "SATA power pin" | |
735 | default "" | |
736 | help | |
737 | Set the pins used to power the SATA. This takes a string in the | |
738 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
739 | port H. | |
213480e1 | 740 | |
c13f60d9 HG |
741 | config GMAC_TX_DELAY |
742 | int "GMAC Transmit Clock Delay Chain" | |
743 | default 0 | |
744 | ---help--- | |
745 | Set the GMAC Transmit Clock Delay Chain value. | |
746 | ||
ff42d107 | 747 | config SPL_STACK_R_ADDR |
301791c9 CYT |
748 | default 0x4fe00000 if MACH_SUN4I |
749 | default 0x4fe00000 if MACH_SUN5I | |
750 | default 0x4fe00000 if MACH_SUN6I | |
751 | default 0x4fe00000 if MACH_SUN7I | |
752 | default 0x4fe00000 if MACH_SUN8I | |
ff42d107 | 753 | default 0x2fe00000 if MACH_SUN9I |
301791c9 | 754 | default 0x4fe00000 if MACH_SUN50I |
ff42d107 | 755 | |
dd84058d | 756 | endif |