[thirdparty/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <malloc.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/psu_init_gpl.h>
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <zynqmppl.h>
#include <i2c.h>
#include <g_dnl.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;

static const struct {
	u32 id;
	u32 ver;
	char *name;
	bool evexists;
} zynqmp_devices[] = {
	{
		.id = 0x10,
		.name = "3eg",
	},
	{
		.id = 0x10,
		.ver = 0x2c,
		.name = "3cg",
	},
	{
		.id = 0x11,
		.name = "2eg",
	},
	{
		.id = 0x11,
		.ver = 0x2c,
		.name = "2cg",
	},
	{
		.id = 0x20,
		.name = "5ev",
		.evexists = 1,
	},
	{
		.id = 0x20,
		.ver = 0x100,
		.name = "5eg",
		.evexists = 1,
	},
	{
		.id = 0x20,
		.ver = 0x12c,
		.name = "5cg",
	},
	{
		.id = 0x21,
		.name = "4ev",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.ver = 0x100,
		.name = "4eg",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.ver = 0x12c,
		.name = "4cg",
	},
	{
		.id = 0x30,
		.name = "7ev",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.ver = 0x100,
		.name = "7eg",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.ver = 0x12c,
		.name = "7cg",
	},
	{
		.id = 0x38,
		.name = "9eg",
	},
	{
		.id = 0x38,
		.ver = 0x2c,
		.name = "9cg",
	},
	{
		.id = 0x39,
		.name = "6eg",
	},
	{
		.id = 0x39,
		.ver = 0x2c,
		.name = "6cg",
	},
	{
		.id = 0x40,
		.name = "11eg",
	},
	{ /* For testing purpose only */
		.id = 0x50,
		.ver = 0x2c,
		.name = "15cg",
	},
	{
		.id = 0x50,
		.name = "15eg",
	},
	{
		.id = 0x58,
		.name = "19eg",
	},
	{
		.id = 0x59,
		.name = "17eg",
	},
	{
		.id = 0x61,
		.name = "21dr",
	},
	{
		.id = 0x63,
		.name = "23dr",
	},
	{
		.id = 0x65,
		.name = "25dr",
	},
	{
		.id = 0x64,
		.name = "27dr",
	},
	{
		.id = 0x60,
		.name = "28dr",
	},
	{
		.id = 0x62,
		.name = "29dr",
	},
};
#endif

int chip_id(unsigned char id)
{
	struct pt_regs regs;
	int val = -EINVAL;

	if (current_el() != 3) {
		regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
		regs.regs[1] = 0;
		regs.regs[2] = 0;
		regs.regs[3] = 0;

		smc_call(&regs);

		/*
		 * SMC returns:
		 * regs[0][31:0]  = status of the operation
		 * regs[0][63:32] = CSU.IDCODE register
		 * regs[1][31:0]  = CSU.version register
		 * regs[1][63:32] = CSU.IDCODE2 register
		 */
		switch (id) {
		case IDCODE:
			regs.regs[0] = upper_32_bits(regs.regs[0]);
			regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
					ZYNQMP_CSU_IDCODE_SVD_MASK;
			regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			val = regs.regs[0];
			break;
		case VERSION:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
			val = regs.regs[1];
			break;
		case IDCODE2:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
			val = regs.regs[1];
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	} else {
		switch (id) {
		case IDCODE:
			val = readl(ZYNQMP_CSU_IDCODE_ADDR);
			val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
			       ZYNQMP_CSU_IDCODE_SVD_MASK;
			val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			break;
		case VERSION:
			val = readl(ZYNQMP_CSU_VER_ADDR);
			val &= ZYNQMP_CSU_SILICON_VER_MASK;
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	}

	return val;
}

#define ZYNQMP_VERSION_SIZE		9
#define ZYNQMP_PL_STATUS_BIT		9
#define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	!defined(CONFIG_SPL_BUILD)
static char *zynqmp_get_silicon_idcode_name(void)
{
	u32 i, id, ver;
	char *buf;
	static char name[ZYNQMP_VERSION_SIZE];

	id = chip_id(IDCODE);
	ver = chip_id(IDCODE2);

	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
		if ((zynqmp_devices[i].id == id) &&
		    (zynqmp_devices[i].ver == (ver &
		    ZYNQMP_CSU_VERSION_MASK))) {
			strncat(name, "zu", 2);
			strncat(name, zynqmp_devices[i].name,
				ZYNQMP_VERSION_SIZE - 3);
			break;
		}
	}

	if (i >= ARRAY_SIZE(zynqmp_devices))
		return "unknown";

	if (!zynqmp_devices[i].evexists)
		return name;

	if (ver & ZYNQMP_PL_STATUS_MASK)
		return name;

	if (strstr(name, "eg") || strstr(name, "ev")) {
		buf = strstr(name, "e");
		*buf = '\0';
	}

	return name;
}
#endif

int board_early_init_f(void)
{
	int ret = 0;
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	zynqmp_pmufw_version();
#endif

#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
	ret = psu_init();
#endif

	return ret;
}

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
    defined(CONFIG_SPL_BUILD))
	if (current_el() != 3) {
		zynqmppl.name = zynqmp_get_silicon_idcode_name();
		printf("Chip ID:\t%s\n", zynqmppl.name);
		fpga_init();
		fpga_add(fpga_xilinx, &zynqmppl);
	}
#endif

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;

	if (!val) {
		val = readl(&crlapb_base->timestamp_ref_ctrl);
		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
		writel(val, &crlapb_base->timestamp_ref_ctrl);

		/* Program freq register in System counter */
		writel(zynqmp_get_system_timer_freq(),
		       &iou_scntr_secure->base_frequency_id_register);
		/* And enable system counter */
		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
		       &iou_scntr_secure->counter_control_register);
	}
	return 0;
}

int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
    defined(CONFIG_ZYNQ_EEPROM_BUS)
	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);

	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
			ethaddr, 6))
		printf("I2C EEPROM MAC address read failed\n");
#endif

	return 0;
}

unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
			 char * const argv[])
{
	int ret = 0;

	if (current_el() > 1) {
		smp_kick_all_cpus();
		dcache_disable();
		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
				    ES_TO_AARCH64);
	} else {
		printf("FAIL: current EL is not above EL1\n");
		ret = EINVAL;
	}
	return ret;
}

#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
	return fdtdec_setup_memory_banksize();
}

int dram_init(void)
{
	if (fdtdec_setup_memory_size() != 0)
		return -EINVAL;

	return 0;
}
#else
int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);

	return 0;
}
#endif

void reset_cpu(ulong addr)
{
}

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;
	const char *mode;
	char *new_targets;
	char *env_targets;
	int ret;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
	if (ret)
		return -EINVAL;

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "usb";
		env_set("modeboot", "usb_dfu_spl");
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "pxe dhcp";
		env_set("modeboot", "jtagboot");
		break;
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		mode = "qspi0";
		puts("QSPI_MODE\n");
		env_set("modeboot", "qspiboot");
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		mode = "mmc0";
		env_set("modeboot", "emmcboot");
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		mode = "mmc0";
		env_set("modeboot", "sdboot");
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
		mode = "mmc1";
		env_set("sdbootdev", "1");
#else
		mode = "mmc0";
#endif
		env_set("modeboot", "sdboot");
		break;
	case NAND_MODE:
		puts("NAND_MODE\n");
		mode = "nand0";
		env_set("modeboot", "nandboot");
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	env_targets = env_get("boot_targets");
	if (env_targets) {
		new_targets = calloc(1, strlen(mode) +
				     strlen(env_targets) + 2);
		sprintf(new_targets, "%s %s", mode, env_targets);
	} else {
		new_targets = calloc(1, strlen(mode) + 2);
		sprintf(new_targets, "%s", mode);
	}

	env_set("boot_targets", new_targets);

	return 0;
}

int checkboard(void)
{
	puts("Board: Xilinx ZynqMP\n");
	return 0;
}

#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data0 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 0,
};

static struct dwc3_device dwc3_device_data1 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 1,
};

int usb_gadget_handle_interrupts(int index)
{
	dwc3_uboot_handle_interrupt(index);
	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	debug("%s: index %x\n", __func__, index);

#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
#endif

	switch (index) {
	case 0:
		return dwc3_uboot_init(&dwc3_device_data0);
	case 1:
		return dwc3_uboot_init(&dwc3_device_data1);
	};

	return -1;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	dwc3_uboot_exit(index);
	return 0;
}
#endif
Commit	Line	Data
84c7204b MS	1	/*
	2	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	3	* Michal Simek <michal.simek@xilinx.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
679b994a	9	#include <sata.h>
6fe6f135 MS	10	#include <ahci.h>
6fe6f135 MS	11	#include <scsi.h>
b72894f1	12	#include <malloc.h>
0785dfd8	13	#include <asm/arch/clk.h>
84c7204b MS	14	#include <asm/arch/hardware.h>
84c7204b MS	15	#include <asm/arch/sys_proto.h>
2ad341ed	16	#include <asm/arch/psu_init_gpl.h>
84c7204b	17	#include <asm/io.h>
16fa00a7 SDPP	18	#include <usb.h>
16fa00a7 SDPP	19	#include <dwc3-uboot.h>
47e60cbd	20	#include <zynqmppl.h>
6919b4bf	21	#include <i2c.h>
9feff385	22	#include <g_dnl.h>
84c7204b MS	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
47e60cbd MS	26	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	27	!defined(CONFIG_SPL_BUILD)
	28	static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
	29
	30	static const struct {
8ebdf9ef	31	u32 id;
494fffe7	32	u32 ver;
47e60cbd	33	char *name;
83bf2ff0	34	bool evexists;
47e60cbd MS	35	} zynqmp_devices[] = {
	36	{
	37	.id = 0x10,
	38	.name = "3eg",
	39	},
494fffe7 MS	40	{
	41	.id = 0x10,
	42	.ver = 0x2c,
	43	.name = "3cg",
	44	},
47e60cbd MS	45	{
	46	.id = 0x11,
	47	.name = "2eg",
	48	},
494fffe7 MS	49	{
	50	.id = 0x11,
	51	.ver = 0x2c,
	52	.name = "2cg",
	53	},
47e60cbd MS	54	{
	55	.id = 0x20,
	56	.name = "5ev",
83bf2ff0	57	.evexists = 1,
47e60cbd	58	},
494fffe7 MS	59	{
	60	.id = 0x20,
	61	.ver = 0x100,
	62	.name = "5eg",
83bf2ff0	63	.evexists = 1,
494fffe7 MS	64	},
	65	{
	66	.id = 0x20,
	67	.ver = 0x12c,
	68	.name = "5cg",
	69	},
47e60cbd MS	70	{
	71	.id = 0x21,
	72	.name = "4ev",
83bf2ff0	73	.evexists = 1,
47e60cbd	74	},
494fffe7 MS	75	{
	76	.id = 0x21,
	77	.ver = 0x100,
	78	.name = "4eg",
83bf2ff0	79	.evexists = 1,
494fffe7 MS	80	},
	81	{
	82	.id = 0x21,
	83	.ver = 0x12c,
	84	.name = "4cg",
	85	},
47e60cbd MS	86	{
	87	.id = 0x30,
	88	.name = "7ev",
83bf2ff0	89	.evexists = 1,
47e60cbd	90	},
494fffe7 MS	91	{
	92	.id = 0x30,
	93	.ver = 0x100,
	94	.name = "7eg",
83bf2ff0	95	.evexists = 1,
494fffe7 MS	96	},
	97	{
	98	.id = 0x30,
	99	.ver = 0x12c,
	100	.name = "7cg",
	101	},
47e60cbd MS	102	{
	103	.id = 0x38,
	104	.name = "9eg",
	105	},
494fffe7 MS	106	{
	107	.id = 0x38,
	108	.ver = 0x2c,
	109	.name = "9cg",
	110	},
47e60cbd MS	111	{
	112	.id = 0x39,
	113	.name = "6eg",
	114	},
494fffe7 MS	115	{
	116	.id = 0x39,
	117	.ver = 0x2c,
	118	.name = "6cg",
	119	},
47e60cbd MS	120	{
	121	.id = 0x40,
	122	.name = "11eg",
	123	},
494fffe7 MS	124	{ /* For testing purpose only */
	125	.id = 0x50,
	126	.ver = 0x2c,
	127	.name = "15cg",
	128	},
47e60cbd MS	129	{
	130	.id = 0x50,
	131	.name = "15eg",
	132	},
	133	{
	134	.id = 0x58,
	135	.name = "19eg",
	136	},
	137	{
	138	.id = 0x59,
	139	.name = "17eg",
	140	},
b030fedf MS	141	{
	142	.id = 0x61,
	143	.name = "21dr",
	144	},
	145	{
	146	.id = 0x63,
	147	.name = "23dr",
	148	},
	149	{
	150	.id = 0x65,
	151	.name = "25dr",
	152	},
	153	{
	154	.id = 0x64,
	155	.name = "27dr",
	156	},
	157	{
	158	.id = 0x60,
	159	.name = "28dr",
	160	},
	161	{
	162	.id = 0x62,
	163	.name = "29dr",
	164	},
47e60cbd	165	};
74ba69db	166	#endif
47e60cbd	167
f52bf5a3	168	int chip_id(unsigned char id)
47e60cbd MS	169	{
47e60cbd MS	170	struct pt_regs regs;
db3123b4	171	int val = -EINVAL;
47e60cbd	172
74ba69db SDPP	173	if (current_el() != 3) {
	174	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
	175	regs.regs[1] = 0;
	176	regs.regs[2] = 0;
	177	regs.regs[3] = 0;
	178
	179	smc_call(&regs);
	180
	181	/*
	182	* SMC returns:
	183	* regs[0][31:0] = status of the operation
	184	* regs[0][63:32] = CSU.IDCODE register
	185	* regs[1][31:0] = CSU.version register
494fffe7	186	* regs[1][63:32] = CSU.IDCODE2 register
74ba69db SDPP	187	*/
	188	switch (id) {
	189	case IDCODE:
	190	regs.regs[0] = upper_32_bits(regs.regs[0]);
	191	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	192	ZYNQMP_CSU_IDCODE_SVD_MASK;
	193	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	194	val = regs.regs[0];
	195	break;
	196	case VERSION:
	197	regs.regs[1] = lower_32_bits(regs.regs[1]);
	198	regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
	199	val = regs.regs[1];
	200	break;
494fffe7 MS	201	case IDCODE2:
	202	regs.regs[1] = lower_32_bits(regs.regs[1]);
	203	regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
	204	val = regs.regs[1];
	205	break;
74ba69db SDPP	206	default:
	207	printf("%s, Invalid Req:0x%x\n", __func__, id);
	208	}
	209	} else {
	210	switch (id) {
	211	case IDCODE:
	212	val = readl(ZYNQMP_CSU_IDCODE_ADDR);
	213	val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	214	ZYNQMP_CSU_IDCODE_SVD_MASK;
	215	val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	216	break;
	217	case VERSION:
	218	val = readl(ZYNQMP_CSU_VER_ADDR);
	219	val &= ZYNQMP_CSU_SILICON_VER_MASK;
	220	break;
	221	default:
	222	printf("%s, Invalid Req:0x%x\n", __func__, id);
	223	}
db3123b4	224	}
0cba6abb	225
db3123b4	226	return val;
47e60cbd MS	227	}
47e60cbd MS	228
83bf2ff0 SDPP	229	#define ZYNQMP_VERSION_SIZE 9
	230	#define ZYNQMP_PL_STATUS_BIT 9
	231	#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
	232	#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
	233
74ba69db SDPP	234	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
74ba69db SDPP	235	!defined(CONFIG_SPL_BUILD)
47e60cbd MS	236	static char *zynqmp_get_silicon_idcode_name(void)
47e60cbd MS	237	{
494fffe7	238	u32 i, id, ver;
83bf2ff0 SDPP	239	char *buf;
83bf2ff0 SDPP	240	static char name[ZYNQMP_VERSION_SIZE];
47e60cbd	241
db3123b4	242	id = chip_id(IDCODE);
494fffe7 MS	243	ver = chip_id(IDCODE2);
494fffe7 MS	244
47e60cbd	245	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
83bf2ff0 SDPP	246	if ((zynqmp_devices[i].id == id) &&
	247	(zynqmp_devices[i].ver == (ver &
	248	ZYNQMP_CSU_VERSION_MASK))) {
	249	strncat(name, "zu", 2);
	250	strncat(name, zynqmp_devices[i].name,
	251	ZYNQMP_VERSION_SIZE - 3);
	252	break;
	253	}
47e60cbd	254	}
83bf2ff0 SDPP	255
	256	if (i >= ARRAY_SIZE(zynqmp_devices))
	257	return "unknown";
	258
	259	if (!zynqmp_devices[i].evexists)
	260	return name;
	261
	262	if (ver & ZYNQMP_PL_STATUS_MASK)
	263	return name;
	264
	265	if (strstr(name, "eg") \|\| strstr(name, "ev")) {
	266	buf = strstr(name, "e");
	267	*buf = '\0';
	268	}
	269
	270	return name;
47e60cbd MS	271	}
	272	#endif
	273
fb4000e8 MS	274	int board_early_init_f(void)
fb4000e8 MS	275	{
f32e79f1	276	int ret = 0;
fb4000e8 MS	277	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	278	zynqmp_pmufw_version();
	279	#endif
55de0929	280
88f05a92	281	#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
f32e79f1	282	ret = psu_init();
55de0929 MS	283	#endif
55de0929 MS	284
f32e79f1	285	return ret;
fb4000e8 MS	286	}
fb4000e8 MS	287
84c7204b MS	288	int board_init(void)
84c7204b MS	289	{
a0736efb MS	290	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	291
47e60cbd MS	292	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	293	!defined(CONFIG_SPL_BUILD) \|\| (defined(CONFIG_SPL_FPGA_SUPPORT) && \
	294	defined(CONFIG_SPL_BUILD))
	295	if (current_el() != 3) {
83bf2ff0	296	zynqmppl.name = zynqmp_get_silicon_idcode_name();
47e60cbd MS	297	printf("Chip ID:\t%s\n", zynqmppl.name);
	298	fpga_init();
	299	fpga_add(fpga_xilinx, &zynqmppl);
	300	}
	301	#endif
	302
84c7204b MS	303	return 0;
	304	}
	305
	306	int board_early_init_r(void)
	307	{
	308	u32 val;
	309
ec60a279 SDPP	310	if (current_el() != 3)
	311	return 0;
	312
90a35db4 MS	313	val = readl(&crlapb_base->timestamp_ref_ctrl);
	314	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	315
ec60a279	316	if (!val) {
0785dfd8 MS	317	val = readl(&crlapb_base->timestamp_ref_ctrl);
	318	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	319	writel(val, &crlapb_base->timestamp_ref_ctrl);
84c7204b	320
0785dfd8 MS	321	/* Program freq register in System counter */
	322	writel(zynqmp_get_system_timer_freq(),
	323	&iou_scntr_secure->base_frequency_id_register);
	324	/* And enable system counter */
	325	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	326	&iou_scntr_secure->counter_control_register);
	327	}
84c7204b MS	328	return 0;
	329	}
	330
6919b4bf MS	331	int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
	332	{
	333	#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
	334	defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
	335	defined(CONFIG_ZYNQ_EEPROM_BUS)
	336	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
	337
	338	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
	339	CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
	340	ethaddr, 6))
	341	printf("I2C EEPROM MAC address read failed\n");
	342	#endif
	343
	344	return 0;
	345	}
	346
51916864 NJ	347	unsigned long do_go_exec(ulong (entry)(int, char const []), int argc,
	348	char * const argv[])
	349	{
	350	int ret = 0;
	351
	352	if (current_el() > 1) {
	353	smp_kick_all_cpus();
	354	dcache_disable();
	355	armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
	356	ES_TO_AARCH64);
	357	} else {
	358	printf("FAIL: current EL is not above EL1\n");
	359	ret = EINVAL;
	360	}
	361	return ret;
	362	}
	363
8d59d7f6	364	#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
76b00aca	365	int dram_init_banksize(void)
361a8799	366	{
da3f003b	367	return fdtdec_setup_memory_banksize();
8a5db0ab	368	}
8d59d7f6	369
361a8799	370	int dram_init(void)
8a5db0ab	371	{
950f86ca NR	372	if (fdtdec_setup_memory_size() != 0)
950f86ca NR	373	return -EINVAL;
8a5db0ab	374
361a8799	375	return 0;
8d59d7f6 MS	376	}
8d59d7f6 MS	377	#else
84c7204b MS	378	int dram_init(void)
84c7204b MS	379	{
61dc92a2 MS	380	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
61dc92a2 MS	381	CONFIG_SYS_SDRAM_SIZE);
84c7204b MS	382
	383	return 0;
	384	}
8d59d7f6	385	#endif
84c7204b	386
84c7204b MS	387	void reset_cpu(ulong addr)
	388	{
	389	}
	390
84c7204b MS	391	int board_late_init(void)
	392	{
	393	u32 reg = 0;
	394	u8 bootmode;
b72894f1 MS	395	const char *mode;
b72894f1 MS	396	char *new_targets;
01c42d3d	397	char *env_targets;
d1db89f4	398	int ret;
b72894f1 MS	399
	400	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	401	debug("Saved variables - Skipping\n");
	402	return 0;
	403	}
84c7204b	404
d1db89f4 SDPP	405	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
	406	if (ret)
	407	return -EINVAL;
	408
47359a03 MS	409	if (reg >> BOOT_MODE_ALT_SHIFT)
	410	reg >>= BOOT_MODE_ALT_SHIFT;
	411
84c7204b MS	412	bootmode = reg & BOOT_MODES_MASK;
84c7204b MS	413
fb90917c	414	puts("Bootmode: ");
84c7204b	415	switch (bootmode) {
d58fc12e MS	416	case USB_MODE:
	417	puts("USB_MODE\n");
	418	mode = "usb";
07656ba5	419	env_set("modeboot", "usb_dfu_spl");
d58fc12e	420	break;
0a5bcc8c	421	case JTAG_MODE:
fb90917c	422	puts("JTAG_MODE\n");
b72894f1	423	mode = "pxe dhcp";
07656ba5	424	env_set("modeboot", "jtagboot");
0a5bcc8c SDPP	425	break;
	426	case QSPI_MODE_24BIT:
	427	case QSPI_MODE_32BIT:
b72894f1	428	mode = "qspi0";
fb90917c	429	puts("QSPI_MODE\n");
07656ba5	430	env_set("modeboot", "qspiboot");
0a5bcc8c	431	break;
39c56f55	432	case EMMC_MODE:
78678fee	433	puts("EMMC_MODE\n");
b72894f1	434	mode = "mmc0";
07656ba5	435	env_set("modeboot", "emmcboot");
78678fee MS	436	break;
78678fee MS	437	case SD_MODE:
fb90917c	438	puts("SD_MODE\n");
b72894f1	439	mode = "mmc0";
07656ba5	440	env_set("modeboot", "sdboot");
84c7204b	441	break;
e1992276 SDPP	442	case SD1_LSHFT_MODE:
	443	puts("LVL_SHFT_");
	444	/* fall through */
af813acd	445	case SD_MODE1:
fb90917c	446	puts("SD_MODE1\n");
2d9925bc	447	#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
b72894f1	448	mode = "mmc1";
07656ba5	449	env_set("sdbootdev", "1");
b72894f1 MS	450	#else
b72894f1 MS	451	mode = "mmc0";
2d9925bc	452	#endif
07656ba5	453	env_set("modeboot", "sdboot");
af813acd MS	454	break;
af813acd MS	455	case NAND_MODE:
fb90917c	456	puts("NAND_MODE\n");
b72894f1	457	mode = "nand0";
07656ba5	458	env_set("modeboot", "nandboot");
af813acd	459	break;
84c7204b	460	default:
b72894f1	461	mode = "";
84c7204b MS	462	printf("Invalid Boot Mode:0x%x\n", bootmode);
	463	break;
	464	}
	465
b72894f1 MS	466	/*
	467	* One terminating char + one byte for space between mode
	468	* and default boot_targets
	469	*/
01c42d3d SDPP	470	env_targets = env_get("boot_targets");
	471	if (env_targets) {
	472	new_targets = calloc(1, strlen(mode) +
	473	strlen(env_targets) + 2);
	474	sprintf(new_targets, "%s %s", mode, env_targets);
	475	} else {
	476	new_targets = calloc(1, strlen(mode) + 2);
	477	sprintf(new_targets, "%s", mode);
	478	}
b72894f1	479
382bee57	480	env_set("boot_targets", new_targets);
b72894f1	481
84c7204b MS	482	return 0;
84c7204b MS	483	}
84696ff5 SDPP	484
	485	int checkboard(void)
	486	{
5af08556	487	puts("Board: Xilinx ZynqMP\n");
84696ff5 SDPP	488	return 0;
84696ff5 SDPP	489	}
16fa00a7 SDPP	490
16fa00a7 SDPP	491	#ifdef CONFIG_USB_DWC3
275bd6d1	492	static struct dwc3_device dwc3_device_data0 = {
16fa00a7 SDPP	493	.maximum_speed = USB_SPEED_HIGH,
	494	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	495	.dr_mode = USB_DR_MODE_PERIPHERAL,
	496	.index = 0,
	497	};
	498
275bd6d1 MS	499	static struct dwc3_device dwc3_device_data1 = {
	500	.maximum_speed = USB_SPEED_HIGH,
	501	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	502	.dr_mode = USB_DR_MODE_PERIPHERAL,
	503	.index = 1,
	504	};
	505
9feff385	506	int usb_gadget_handle_interrupts(int index)
16fa00a7	507	{
9feff385	508	dwc3_uboot_handle_interrupt(index);
16fa00a7 SDPP	509	return 0;
	510	}
	511
	512	int board_usb_init(int index, enum usb_init_type init)
	513	{
275bd6d1 MS	514	debug("%s: index %x\n", __func__, index);
275bd6d1 MS	515
8ecd50c8 MS	516	#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	517	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
	518	#endif
	519
275bd6d1 MS	520	switch (index) {
	521	case 0:
	522	return dwc3_uboot_init(&dwc3_device_data0);
	523	case 1:
	524	return dwc3_uboot_init(&dwc3_device_data1);
	525	};
	526
	527	return -1;
16fa00a7 SDPP	528	}
	529
	530	int board_usb_cleanup(int index, enum usb_init_type init)
	531	{
	532	dwc3_uboot_exit(index);
	533	return 0;
	534	}
	535	#endif