[people/ms/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <malloc.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <zynqmppl.h>
#include <i2c.h>
#include <g_dnl.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;

static const struct {
	uint32_t id;
	char *name;
} zynqmp_devices[] = {
	{
		.id = 0x10,
		.name = "3eg",
	},
	{
		.id = 0x11,
		.name = "2eg",
	},
	{
		.id = 0x20,
		.name = "5ev",
	},
	{
		.id = 0x21,
		.name = "4ev",
	},
	{
		.id = 0x30,
		.name = "7ev",
	},
	{
		.id = 0x38,
		.name = "9eg",
	},
	{
		.id = 0x39,
		.name = "6eg",
	},
	{
		.id = 0x40,
		.name = "11eg",
	},
	{
		.id = 0x50,
		.name = "15eg",
	},
	{
		.id = 0x58,
		.name = "19eg",
	},
	{
		.id = 0x59,
		.name = "17eg",
	},
};

static int chip_id(void)
{
	struct pt_regs regs;
	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
	regs.regs[1] = 0;
	regs.regs[2] = 0;
	regs.regs[3] = 0;

	smc_call(&regs);

	/*
	 * SMC returns:
	 * regs[0][31:0]  = status of the operation
	 * regs[0][63:32] = CSU.IDCODE register
	 * regs[1][31:0]  = CSU.version register
	 */
	regs.regs[0] = upper_32_bits(regs.regs[0]);
	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
			ZYNQMP_CSU_IDCODE_SVD_MASK;
	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;

	return regs.regs[0];
}

static char *zynqmp_get_silicon_idcode_name(void)
{
	uint32_t i, id;

	id = chip_id();
	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
		if (zynqmp_devices[i].id == id)
			return zynqmp_devices[i].name;
	}
	return "unknown";
}
#endif

#define ZYNQMP_VERSION_SIZE	9

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
    defined(CONFIG_SPL_BUILD))
	if (current_el() != 3) {
		static char version[ZYNQMP_VERSION_SIZE];

		strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
		zynqmppl.name = strncat(version,
					zynqmp_get_silicon_idcode_name(),
					ZYNQMP_VERSION_SIZE);
		printf("Chip ID:\t%s\n", zynqmppl.name);
		fpga_init();
		fpga_add(fpga_xilinx, &zynqmppl);
	}
#endif

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	if (current_el() == 3) {
		val = readl(&crlapb_base->timestamp_ref_ctrl);
		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
		writel(val, &crlapb_base->timestamp_ref_ctrl);

		/* Program freq register in System counter */
		writel(zynqmp_get_system_timer_freq(),
		       &iou_scntr_secure->base_frequency_id_register);
		/* And enable system counter */
		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
		       &iou_scntr_secure->counter_control_register);
	}
	/* Program freq register in System counter and enable system counter */
	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
	       ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	       &iou_scntr->counter_control_register);

	return 0;
}

int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
    defined(CONFIG_ZYNQ_EEPROM_BUS)
	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);

	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
			ethaddr, 6))
		printf("I2C EEPROM MAC address read failed\n");
#endif

	return 0;
}

#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
/*
 * fdt_get_reg - Fill buffer by information from DT
 */
static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
			       const u32 *cell, int n)
{
	int i = 0, b, banks;
	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
	int address_cells = fdt_address_cells(fdt, parent_offset);
	int size_cells = fdt_size_cells(fdt, parent_offset);
	char *p = buf;
	u64 val;
	u64 vals;

	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
	      __func__, address_cells, size_cells, buf, cell);

	/* Check memory bank setup */
	banks = n % (address_cells + size_cells);
	if (banks)
		panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
		      n, address_cells, size_cells);

	banks = n / (address_cells + size_cells);

	for (b = 0; b < banks; b++) {
		debug("%s: Bank #%d:\n", __func__, b);
		if (address_cells == 2) {
			val = cell[i + 1];
			val <<= 32;
			val |= cell[i];
			val = fdt64_to_cpu(val);
			debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
			      __func__, val, p, &cell[i]);
			*(phys_addr_t *)p = val;
		} else {
			debug("%s: addr32=%x, ptr=%p\n",
			      __func__, fdt32_to_cpu(cell[i]), p);
			*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
		}
		p += sizeof(phys_addr_t);
		i += address_cells;

		debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
		      sizeof(phys_addr_t));

		if (size_cells == 2) {
			vals = cell[i + 1];
			vals <<= 32;
			vals |= cell[i];
			vals = fdt64_to_cpu(vals);

			debug("%s: size64=%llx, ptr=%p, cell=%p\n",
			      __func__, vals, p, &cell[i]);
			*(phys_size_t *)p = vals;
		} else {
			debug("%s: size32=%x, ptr=%p\n",
			      __func__, fdt32_to_cpu(cell[i]), p);
			*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
		}
		p += sizeof(phys_size_t);
		i += size_cells;

		debug("%s: ps=%p, i=%x, size=%zu\n",
		      __func__, p, i, sizeof(phys_size_t));
	}

	/* Return the first address size */
	return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
}

#define FDT_REG_SIZE  sizeof(u32)
/* Temp location for sharing data for storing */
/* Up to 64-bit address + 64-bit size */
static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];

void dram_init_banksize(void)
{
	int bank;

	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));

	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
		debug("Bank #%d: start %llx\n", bank,
		      (unsigned long long)gd->bd->bi_dram[bank].start);
		debug("Bank #%d: size %llx\n", bank,
		      (unsigned long long)gd->bd->bi_dram[bank].size);
	}
}

int dram_init(void)
{
	int node, len;
	const void *blob = gd->fdt_blob;
	const u32 *cell;

	memset(&tmp, 0, sizeof(tmp));

	/* find or create "/memory" node. */
	node = fdt_subnode_offset(blob, 0, "memory");
	if (node < 0) {
		printf("%s: Can't get memory node\n", __func__);
		return node;
	}

	/* Get pointer to cells and lenght of it */
	cell = fdt_getprop(blob, node, "reg", &len);
	if (!cell) {
		printf("%s: Can't get reg property\n", __func__);
		return -1;
	}

	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);

	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);

	return 0;
}
#else
int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}
#endif

void reset_cpu(ulong addr)
{
}

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;
	const char *mode;
	char *new_targets;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	reg = readl(&crlapb_base->boot_mode);
	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "usb";
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "pxe dhcp";
		break;
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		mode = "qspi0";
		puts("QSPI_MODE\n");
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		mode = "mmc0";
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		mode = "mmc0";
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
		mode = "mmc1";
#else
		mode = "mmc0";
#endif
		break;
	case NAND_MODE:
		puts("NAND_MODE\n");
		mode = "nand0";
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	new_targets = calloc(1, strlen(mode) +
				strlen(getenv("boot_targets")) + 2);

	sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
	setenv("boot_targets", new_targets);

	return 0;
}

int checkboard(void)
{
	puts("Board: Xilinx ZynqMP\n");
	return 0;
}

#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data0 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 0,
};

static struct dwc3_device dwc3_device_data1 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 1,
};

int usb_gadget_handle_interrupts(int index)
{
	dwc3_uboot_handle_interrupt(index);
	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	debug("%s: index %x\n", __func__, index);

#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
#endif

	switch (index) {
	case 0:
		return dwc3_uboot_init(&dwc3_device_data0);
	case 1:
		return dwc3_uboot_init(&dwc3_device_data1);
	};

	return -1;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	dwc3_uboot_exit(index);
	return 0;
}
#endif
Commit	Line	Data
84c7204b MS	1	/*
	2	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	3	* Michal Simek <michal.simek@xilinx.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
679b994a	9	#include <sata.h>
6fe6f135 MS	10	#include <ahci.h>
6fe6f135 MS	11	#include <scsi.h>
b72894f1	12	#include <malloc.h>
0785dfd8	13	#include <asm/arch/clk.h>
84c7204b MS	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/io.h>
16fa00a7 SDPP	17	#include <usb.h>
16fa00a7 SDPP	18	#include <dwc3-uboot.h>
47e60cbd	19	#include <zynqmppl.h>
6919b4bf	20	#include <i2c.h>
9feff385	21	#include <g_dnl.h>
84c7204b MS	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
47e60cbd MS	25	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	26	!defined(CONFIG_SPL_BUILD)
	27	static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
	28
	29	static const struct {
	30	uint32_t id;
	31	char *name;
	32	} zynqmp_devices[] = {
	33	{
	34	.id = 0x10,
	35	.name = "3eg",
	36	},
	37	{
	38	.id = 0x11,
	39	.name = "2eg",
	40	},
	41	{
	42	.id = 0x20,
	43	.name = "5ev",
	44	},
	45	{
	46	.id = 0x21,
	47	.name = "4ev",
	48	},
	49	{
	50	.id = 0x30,
	51	.name = "7ev",
	52	},
	53	{
	54	.id = 0x38,
	55	.name = "9eg",
	56	},
	57	{
	58	.id = 0x39,
	59	.name = "6eg",
	60	},
	61	{
	62	.id = 0x40,
	63	.name = "11eg",
	64	},
	65	{
	66	.id = 0x50,
	67	.name = "15eg",
	68	},
	69	{
	70	.id = 0x58,
	71	.name = "19eg",
	72	},
	73	{
	74	.id = 0x59,
	75	.name = "17eg",
	76	},
	77	};
	78
	79	static int chip_id(void)
	80	{
	81	struct pt_regs regs;
	82	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
	83	regs.regs[1] = 0;
	84	regs.regs[2] = 0;
	85	regs.regs[3] = 0;
	86
	87	smc_call(&regs);
	88
0cba6abb SB	89	/*
	90	* SMC returns:
	91	* regs[0][31:0] = status of the operation
	92	* regs[0][63:32] = CSU.IDCODE register
	93	* regs[1][31:0] = CSU.version register
	94	*/
	95	regs.regs[0] = upper_32_bits(regs.regs[0]);
	96	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	97	ZYNQMP_CSU_IDCODE_SVD_MASK;
	98	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	99
47e60cbd MS	100	return regs.regs[0];
	101	}
	102
	103	static char *zynqmp_get_silicon_idcode_name(void)
	104	{
	105	uint32_t i, id;
	106
	107	id = chip_id();
	108	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
	109	if (zynqmp_devices[i].id == id)
	110	return zynqmp_devices[i].name;
	111	}
	112	return "unknown";
	113	}
	114	#endif
	115
	116	#define ZYNQMP_VERSION_SIZE 9
	117
84c7204b MS	118	int board_init(void)
84c7204b MS	119	{
a0736efb MS	120	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	121
47e60cbd MS	122	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	123	!defined(CONFIG_SPL_BUILD) \|\| (defined(CONFIG_SPL_FPGA_SUPPORT) && \
	124	defined(CONFIG_SPL_BUILD))
	125	if (current_el() != 3) {
	126	static char version[ZYNQMP_VERSION_SIZE];
	127
	128	strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
	129	zynqmppl.name = strncat(version,
	130	zynqmp_get_silicon_idcode_name(),
	131	ZYNQMP_VERSION_SIZE);
	132	printf("Chip ID:\t%s\n", zynqmppl.name);
	133	fpga_init();
	134	fpga_add(fpga_xilinx, &zynqmppl);
	135	}
	136	#endif
	137
84c7204b MS	138	return 0;
	139	}
	140
	141	int board_early_init_r(void)
	142	{
	143	u32 val;
	144
0785dfd8 MS	145	if (current_el() == 3) {
	146	val = readl(&crlapb_base->timestamp_ref_ctrl);
	147	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	148	writel(val, &crlapb_base->timestamp_ref_ctrl);
84c7204b	149
0785dfd8 MS	150	/* Program freq register in System counter */
	151	writel(zynqmp_get_system_timer_freq(),
	152	&iou_scntr_secure->base_frequency_id_register);
	153	/* And enable system counter */
	154	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	155	&iou_scntr_secure->counter_control_register);
	156	}
84c7204b MS	157	/* Program freq register in System counter and enable system counter */
	158	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
	159	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG \|
	160	ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	161	&iou_scntr->counter_control_register);
	162
	163	return 0;
	164	}
	165
6919b4bf MS	166	int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
	167	{
	168	#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
	169	defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
	170	defined(CONFIG_ZYNQ_EEPROM_BUS)
	171	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
	172
	173	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
	174	CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
	175	ethaddr, 6))
	176	printf("I2C EEPROM MAC address read failed\n");
	177	#endif
	178
	179	return 0;
	180	}
	181
8d59d7f6 MS	182	#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
	183	/*
	184	* fdt_get_reg - Fill buffer by information from DT
	185	*/
	186	static phys_size_t fdt_get_reg(const void fdt, int nodeoffset, void buf,
	187	const u32 *cell, int n)
	188	{
	189	int i = 0, b, banks;
	190	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
	191	int address_cells = fdt_address_cells(fdt, parent_offset);
	192	int size_cells = fdt_size_cells(fdt, parent_offset);
	193	char *p = buf;
658b3a56 MS	194	u64 val;
658b3a56 MS	195	u64 vals;
8d59d7f6 MS	196
	197	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
	198	__func__, address_cells, size_cells, buf, cell);
	199
	200	/* Check memory bank setup */
	201	banks = n % (address_cells + size_cells);
	202	if (banks)
	203	panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
	204	n, address_cells, size_cells);
	205
	206	banks = n / (address_cells + size_cells);
	207
	208	for (b = 0; b < banks; b++) {
	209	debug("%s: Bank #%d:\n", __func__, b);
	210	if (address_cells == 2) {
	211	val = cell[i + 1];
	212	val <<= 32;
	213	val \|= cell[i];
	214	val = fdt64_to_cpu(val);
	215	debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
	216	__func__, val, p, &cell[i]);
	217	(phys_addr_t )p = val;
	218	} else {
	219	debug("%s: addr32=%x, ptr=%p\n",
	220	__func__, fdt32_to_cpu(cell[i]), p);
	221	(phys_addr_t )p = fdt32_to_cpu(cell[i]);
	222	}
	223	p += sizeof(phys_addr_t);
	224	i += address_cells;
	225
	226	debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
	227	sizeof(phys_addr_t));
	228
	229	if (size_cells == 2) {
	230	vals = cell[i + 1];
	231	vals <<= 32;
	232	vals \|= cell[i];
	233	vals = fdt64_to_cpu(vals);
	234
	235	debug("%s: size64=%llx, ptr=%p, cell=%p\n",
	236	__func__, vals, p, &cell[i]);
	237	(phys_size_t )p = vals;
	238	} else {
	239	debug("%s: size32=%x, ptr=%p\n",
	240	__func__, fdt32_to_cpu(cell[i]), p);
	241	(phys_size_t )p = fdt32_to_cpu(cell[i]);
	242	}
	243	p += sizeof(phys_size_t);
	244	i += size_cells;
	245
	246	debug("%s: ps=%p, i=%x, size=%zu\n",
	247	__func__, p, i, sizeof(phys_size_t));
	248	}
	249
	250	/* Return the first address size */
	251	return (phys_size_t )((char *)buf + sizeof(phys_addr_t));
	252	}
	253
	254	#define FDT_REG_SIZE sizeof(u32)
	255	/* Temp location for sharing data for storing */
	256	/* Up to 64-bit address + 64-bit size */
	257	static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
	258
	259	void dram_init_banksize(void)
260	{
261	int bank;
262
263	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
264
265	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
266	debug("Bank #%d: start %llx\n", bank,
267	(unsigned long long)gd->bd->bi_dram[bank].start);
268	debug("Bank #%d: size %llx\n", bank,
269	(unsigned long long)gd->bd->bi_dram[bank].size);
270	}
271	}
272
273	int dram_init(void)
274	{
275	int node, len;
276	const void *blob = gd->fdt_blob;
277	const u32 *cell;
278
279	memset(&tmp, 0, sizeof(tmp));
280
281	/* find or create "/memory" node. */
282	node = fdt_subnode_offset(blob, 0, "memory");
283	if (node < 0) {
284	printf("%s: Can't get memory node\n", __func__);
285	return node;
286	}
287
288	/* Get pointer to cells and lenght of it */
289	cell = fdt_getprop(blob, node, "reg", &len);
290	if (!cell) {
291	printf("%s: Can't get reg property\n", __func__);
292	return -1;
293	}
294
295	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
296
658b3a56	297	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
8d59d7f6 MS	298
	299	return 0;
	300	}
	301	#else
84c7204b MS	302	int dram_init(void)
	303	{
	304	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	305
	306	return 0;
	307	}
8d59d7f6	308	#endif
84c7204b	309
84c7204b MS	310	void reset_cpu(ulong addr)
	311	{
	312	}
	313
84c7204b MS	314	int board_late_init(void)
	315	{
	316	u32 reg = 0;
	317	u8 bootmode;
b72894f1 MS	318	const char *mode;
	319	char *new_targets;
	320
	321	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	322	debug("Saved variables - Skipping\n");
	323	return 0;
	324	}
84c7204b MS	325
84c7204b MS	326	reg = readl(&crlapb_base->boot_mode);
47359a03 MS	327	if (reg >> BOOT_MODE_ALT_SHIFT)
	328	reg >>= BOOT_MODE_ALT_SHIFT;
	329
84c7204b MS	330	bootmode = reg & BOOT_MODES_MASK;
84c7204b MS	331
fb90917c	332	puts("Bootmode: ");
84c7204b	333	switch (bootmode) {
d58fc12e MS	334	case USB_MODE:
	335	puts("USB_MODE\n");
	336	mode = "usb";
	337	break;
0a5bcc8c	338	case JTAG_MODE:
fb90917c	339	puts("JTAG_MODE\n");
b72894f1	340	mode = "pxe dhcp";
0a5bcc8c SDPP	341	break;
	342	case QSPI_MODE_24BIT:
	343	case QSPI_MODE_32BIT:
b72894f1	344	mode = "qspi0";
fb90917c	345	puts("QSPI_MODE\n");
0a5bcc8c	346	break;
39c56f55	347	case EMMC_MODE:
78678fee	348	puts("EMMC_MODE\n");
b72894f1	349	mode = "mmc0";
78678fee MS	350	break;
78678fee MS	351	case SD_MODE:
fb90917c	352	puts("SD_MODE\n");
b72894f1	353	mode = "mmc0";
84c7204b	354	break;
e1992276 SDPP	355	case SD1_LSHFT_MODE:
	356	puts("LVL_SHFT_");
	357	/* fall through */
af813acd	358	case SD_MODE1:
fb90917c	359	puts("SD_MODE1\n");
2d9925bc	360	#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
b72894f1 MS	361	mode = "mmc1";
	362	#else
	363	mode = "mmc0";
2d9925bc	364	#endif
af813acd MS	365	break;
af813acd MS	366	case NAND_MODE:
fb90917c	367	puts("NAND_MODE\n");
b72894f1	368	mode = "nand0";
af813acd	369	break;
84c7204b	370	default:
b72894f1	371	mode = "";
84c7204b MS	372	printf("Invalid Boot Mode:0x%x\n", bootmode);
	373	break;
	374	}
	375
b72894f1 MS	376	/*
	377	* One terminating char + one byte for space between mode
	378	* and default boot_targets
	379	*/
	380	new_targets = calloc(1, strlen(mode) +
	381	strlen(getenv("boot_targets")) + 2);
	382
	383	sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
	384	setenv("boot_targets", new_targets);
	385
84c7204b MS	386	return 0;
84c7204b MS	387	}
84696ff5 SDPP	388
	389	int checkboard(void)
	390	{
5af08556	391	puts("Board: Xilinx ZynqMP\n");
84696ff5 SDPP	392	return 0;
84696ff5 SDPP	393	}
16fa00a7 SDPP	394
16fa00a7 SDPP	395	#ifdef CONFIG_USB_DWC3
275bd6d1	396	static struct dwc3_device dwc3_device_data0 = {
16fa00a7 SDPP	397	.maximum_speed = USB_SPEED_HIGH,
	398	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	399	.dr_mode = USB_DR_MODE_PERIPHERAL,
	400	.index = 0,
	401	};
	402
275bd6d1 MS	403	static struct dwc3_device dwc3_device_data1 = {
	404	.maximum_speed = USB_SPEED_HIGH,
	405	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	406	.dr_mode = USB_DR_MODE_PERIPHERAL,
	407	.index = 1,
	408	};
	409
9feff385	410	int usb_gadget_handle_interrupts(int index)
16fa00a7	411	{
9feff385	412	dwc3_uboot_handle_interrupt(index);
16fa00a7 SDPP	413	return 0;
	414	}
	415
	416	int board_usb_init(int index, enum usb_init_type init)
	417	{
275bd6d1 MS	418	debug("%s: index %x\n", __func__, index);
275bd6d1 MS	419
8ecd50c8 MS	420	#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	421	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
	422	#endif
	423
275bd6d1 MS	424	switch (index) {
	425	case 0:
	426	return dwc3_uboot_init(&dwc3_device_data0);
	427	case 1:
	428	return dwc3_uboot_init(&dwc3_device_data1);
	429	};
	430
	431	return -1;
16fa00a7 SDPP	432	}
	433
	434	int board_usb_cleanup(int index, enum usb_init_type init)
	435	{
	436	dwc3_uboot_exit(index);
	437	return 0;
	438	}
	439	#endif