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CommitLineData
8bde7f77
WD
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Boot support
26 */
27#include <common.h>
28#include <command.h>
d88af4da 29#include <linux/compiler.h>
8bde7f77 30
d87080b7 31DECLARE_GLOBAL_DATA_PTR;
8bde7f77 32
d88af4da
MF
33__maybe_unused
34static void print_num(const char *name, ulong value)
35{
36 printf("%-12s= 0x%08lX\n", name, value);
37}
8bde7f77 38
5f3dfadc 39__maybe_unused
d88af4da
MF
40static void print_eth(int idx)
41{
42 char name[10], *val;
43 if (idx)
44 sprintf(name, "eth%iaddr", idx);
45 else
46 strcpy(name, "ethaddr");
47 val = getenv(name);
48 if (!val)
49 val = "(not set)";
50 printf("%-12s= %s\n", name, val);
51}
de2dff6f 52
d88af4da
MF
53__maybe_unused
54static void print_lnum(const char *name, u64 value)
55{
56 printf("%-12s= 0x%.8llX\n", name, value);
57}
58
59__maybe_unused
60static void print_mhz(const char *name, unsigned long hz)
61{
62 char buf[32];
63
64 printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
65}
8bde7f77 66
c99ea790 67#if defined(CONFIG_PPC)
8bde7f77 68
5902e8f7 69int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 70{
8bde7f77 71 bd_t *bd = gd->bd;
8bde7f77
WD
72
73#ifdef DEBUG
5902e8f7
ML
74 print_num("bd address", (ulong)bd);
75#endif
76 print_num("memstart", bd->bi_memstart);
77 print_lnum("memsize", bd->bi_memsize);
78 print_num("flashstart", bd->bi_flashstart);
79 print_num("flashsize", bd->bi_flashsize);
80 print_num("flashoffset", bd->bi_flashoffset);
81 print_num("sramstart", bd->bi_sramstart);
82 print_num("sramsize", bd->bi_sramsize);
83#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
84 defined(CONFIG_8260) || defined(CONFIG_E500)
85 print_num("immr_base", bd->bi_immr_base);
86#endif
87 print_num("bootflags", bd->bi_bootflags);
88#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
89 defined(CONFIG_405GP) || \
90 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
91 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
92 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
93 defined(CONFIG_XILINX_405)
0c277ef9
TT
94 print_mhz("procfreq", bd->bi_procfreq);
95 print_mhz("plb_busfreq", bd->bi_plb_busfreq);
5902e8f7
ML
96#if defined(CONFIG_405EP) || defined(CONFIG_405GP) || \
97 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
98 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
99 defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
0c277ef9 100 print_mhz("pci_busfreq", bd->bi_pci_busfreq);
8bde7f77 101#endif
9fea65a6 102#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
9c4c5ae3 103#if defined(CONFIG_CPM2)
0c277ef9
TT
104 print_mhz("vco", bd->bi_vco);
105 print_mhz("sccfreq", bd->bi_sccfreq);
106 print_mhz("brgfreq", bd->bi_brgfreq);
8bde7f77 107#endif
0c277ef9 108 print_mhz("intfreq", bd->bi_intfreq);
9c4c5ae3 109#if defined(CONFIG_CPM2)
0c277ef9 110 print_mhz("cpmfreq", bd->bi_cpmfreq);
8bde7f77 111#endif
0c277ef9 112 print_mhz("busfreq", bd->bi_busfreq);
9fea65a6 113#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
983fda83 114#if defined(CONFIG_MPC8220)
0c277ef9
TT
115 print_mhz("inpfreq", bd->bi_inpfreq);
116 print_mhz("flbfreq", bd->bi_flbfreq);
117 print_mhz("pcifreq", bd->bi_pcifreq);
118 print_mhz("vcofreq", bd->bi_vcofreq);
119 print_mhz("pevfreq", bd->bi_pevfreq);
983fda83 120#endif
03f5c550 121
de2dff6f 122 print_eth(0);
e2ffd59b 123#if defined(CONFIG_HAS_ETH1)
de2dff6f 124 print_eth(1);
03f5c550 125#endif
e2ffd59b 126#if defined(CONFIG_HAS_ETH2)
de2dff6f 127 print_eth(2);
42d1f039 128#endif
e2ffd59b 129#if defined(CONFIG_HAS_ETH3)
de2dff6f 130 print_eth(3);
03f5c550 131#endif
c68a05fe 132#if defined(CONFIG_HAS_ETH4)
de2dff6f 133 print_eth(4);
c68a05fe 134#endif
c68a05fe 135#if defined(CONFIG_HAS_ETH5)
de2dff6f 136 print_eth(5);
c68a05fe 137#endif
138
8bde7f77 139#ifdef CONFIG_HERMES
0c277ef9 140 print_mhz("ethspeed", bd->bi_ethspeed);
8bde7f77 141#endif
5902e8f7
ML
142 printf("IP addr = %pI4\n", &bd->bi_ip_addr);
143 printf("baudrate = %6ld bps\n", bd->bi_baudrate);
144 print_num("relocaddr", gd->relocaddr);
8bde7f77
WD
145 return 0;
146}
147
c99ea790 148#elif defined(CONFIG_NIOS2)
5c952cf0 149
5902e8f7 150int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
5c952cf0 151{
5c952cf0
WD
152 bd_t *bd = gd->bd;
153
5902e8f7
ML
154 print_num("mem start", (ulong)bd->bi_memstart);
155 print_lnum("mem size", (u64)bd->bi_memsize);
156 print_num("flash start", (ulong)bd->bi_flashstart);
157 print_num("flash size", (ulong)bd->bi_flashsize);
158 print_num("flash offset", (ulong)bd->bi_flashoffset);
5c952cf0 159
6d0f6bcf 160#if defined(CONFIG_SYS_SRAM_BASE)
5c952cf0
WD
161 print_num ("sram start", (ulong)bd->bi_sramstart);
162 print_num ("sram size", (ulong)bd->bi_sramsize);
163#endif
164
90253178 165#if defined(CONFIG_CMD_NET)
de2dff6f 166 print_eth(0);
5902e8f7 167 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
5c952cf0
WD
168#endif
169
5902e8f7 170 printf("baudrate = %ld bps\n", bd->bi_baudrate);
5c952cf0
WD
171
172 return 0;
173}
c99ea790
RM
174
175#elif defined(CONFIG_MICROBLAZE)
cfc67116 176
5902e8f7 177int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cfc67116 178{
cfc67116 179 bd_t *bd = gd->bd;
5902e8f7
ML
180 print_num("mem start ", (ulong)bd->bi_memstart);
181 print_lnum("mem size ", (u64)bd->bi_memsize);
182 print_num("flash start ", (ulong)bd->bi_flashstart);
183 print_num("flash size ", (ulong)bd->bi_flashsize);
184 print_num("flash offset ", (ulong)bd->bi_flashoffset);
6d0f6bcf 185#if defined(CONFIG_SYS_SRAM_BASE)
5902e8f7
ML
186 print_num("sram start ", (ulong)bd->bi_sramstart);
187 print_num("sram size ", (ulong)bd->bi_sramsize);
cfc67116 188#endif
90253178 189#if defined(CONFIG_CMD_NET)
de2dff6f 190 print_eth(0);
5902e8f7 191 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
cfc67116 192#endif
5902e8f7 193 printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate);
cfc67116
MS
194 return 0;
195}
4a551709 196
c99ea790
RM
197#elif defined(CONFIG_SPARC)
198
54841ab5 199int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
00ab32c8
DH
200{
201 bd_t *bd = gd->bd;
00ab32c8
DH
202
203#ifdef DEBUG
204 print_num("bd address ", (ulong) bd);
205#endif
206 print_num("memstart ", bd->bi_memstart);
b57ca3e1 207 print_lnum("memsize ", bd->bi_memsize);
00ab32c8 208 print_num("flashstart ", bd->bi_flashstart);
6d0f6bcf 209 print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE);
0e8d1586 210 print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR);
6d0f6bcf
JCPV
211 printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%lx (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
212 CONFIG_SYS_MONITOR_LEN);
213 printf("CONFIG_SYS_MALLOC_BASE = 0x%lx (%d)\n", CONFIG_SYS_MALLOC_BASE,
214 CONFIG_SYS_MALLOC_LEN);
215 printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
216 CONFIG_SYS_STACK_SIZE);
217 printf("CONFIG_SYS_PROM_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
218 CONFIG_SYS_PROM_SIZE);
219 printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
25ddd1fb 220 GENERATED_GBL_DATA_SIZE);
00ab32c8
DH
221
222#if defined(CONFIG_CMD_NET)
de2dff6f 223 print_eth(0);
b6446b67 224 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
00ab32c8 225#endif
b6446b67 226 printf("baudrate = %6ld bps\n", bd->bi_baudrate);
00ab32c8
DH
227 return 0;
228}
229
c99ea790
RM
230#elif defined(CONFIG_M68K)
231
5902e8f7 232int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8e585f02 233{
8e585f02 234 bd_t *bd = gd->bd;
8ae158cd 235
5902e8f7
ML
236 print_num("memstart", (ulong)bd->bi_memstart);
237 print_lnum("memsize", (u64)bd->bi_memsize);
238 print_num("flashstart", (ulong)bd->bi_flashstart);
239 print_num("flashsize", (ulong)bd->bi_flashsize);
240 print_num("flashoffset", (ulong)bd->bi_flashoffset);
6d0f6bcf 241#if defined(CONFIG_SYS_INIT_RAM_ADDR)
5902e8f7
ML
242 print_num("sramstart", (ulong)bd->bi_sramstart);
243 print_num("sramsize", (ulong)bd->bi_sramsize);
8e585f02 244#endif
6d0f6bcf 245#if defined(CONFIG_SYS_MBAR)
5902e8f7 246 print_num("mbar", bd->bi_mbar_base);
8e585f02 247#endif
0c277ef9
TT
248 print_mhz("cpufreq", bd->bi_intfreq);
249 print_mhz("busfreq", bd->bi_busfreq);
8ae158cd 250#ifdef CONFIG_PCI
0c277ef9 251 print_mhz("pcifreq", bd->bi_pcifreq);
8ae158cd
TL
252#endif
253#ifdef CONFIG_EXTRA_CLOCK
0c277ef9
TT
254 print_mhz("flbfreq", bd->bi_flbfreq);
255 print_mhz("inpfreq", bd->bi_inpfreq);
256 print_mhz("vcofreq", bd->bi_vcofreq);
8ae158cd 257#endif
26667b7f 258#if defined(CONFIG_CMD_NET)
de2dff6f 259 print_eth(0);
8e585f02 260#if defined(CONFIG_HAS_ETH1)
de2dff6f 261 print_eth(1);
8e585f02 262#endif
8e585f02 263#if defined(CONFIG_HAS_ETH2)
de2dff6f 264 print_eth(2);
8e585f02 265#endif
8e585f02 266#if defined(CONFIG_HAS_ETH3)
de2dff6f 267 print_eth(3);
8e585f02
TL
268#endif
269
5902e8f7 270 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
26667b7f 271#endif
5902e8f7 272 printf("baudrate = %ld bps\n", bd->bi_baudrate);
8e585f02
TL
273
274 return 0;
275}
276
8dc48d71 277#elif defined(CONFIG_BLACKFIN)
c99ea790 278
54841ab5 279int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8dc48d71 280{
8dc48d71
MF
281 bd_t *bd = gd->bd;
282
283 printf("U-Boot = %s\n", bd->bi_r_version);
284 printf("CPU = %s\n", bd->bi_cpu);
285 printf("Board = %s\n", bd->bi_board_name);
0c277ef9
TT
286 print_mhz("VCO", bd->bi_vco);
287 print_mhz("CCLK", bd->bi_cclk);
288 print_mhz("SCLK", bd->bi_sclk);
8dc48d71 289
5902e8f7
ML
290 print_num("boot_params", (ulong)bd->bi_boot_params);
291 print_num("memstart", (ulong)bd->bi_memstart);
292 print_lnum("memsize", (u64)bd->bi_memsize);
293 print_num("flashstart", (ulong)bd->bi_flashstart);
294 print_num("flashsize", (ulong)bd->bi_flashsize);
295 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8dc48d71 296
de2dff6f 297 print_eth(0);
b6446b67
MF
298 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
299 printf("baudrate = %d bps\n", bd->bi_baudrate);
8dc48d71
MF
300
301 return 0;
302}
303
c99ea790 304#elif defined(CONFIG_MIPS)
8bde7f77 305
5902e8f7 306int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 307{
8bde7f77
WD
308 bd_t *bd = gd->bd;
309
5902e8f7
ML
310 print_num("boot_params", (ulong)bd->bi_boot_params);
311 print_num("memstart", (ulong)bd->bi_memstart);
312 print_lnum("memsize", (u64)bd->bi_memsize);
313 print_num("flashstart", (ulong)bd->bi_flashstart);
314 print_num("flashsize", (ulong)bd->bi_flashsize);
315 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8bde7f77 316
de2dff6f 317 print_eth(0);
5902e8f7
ML
318 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
319 printf("baudrate = %d bps\n", bd->bi_baudrate);
8bde7f77
WD
320
321 return 0;
322}
8bde7f77 323
c99ea790
RM
324#elif defined(CONFIG_AVR32)
325
5902e8f7 326int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
c99ea790
RM
327{
328 bd_t *bd = gd->bd;
329
5902e8f7
ML
330 print_num("boot_params", (ulong)bd->bi_boot_params);
331 print_num("memstart", (ulong)bd->bi_memstart);
332 print_lnum("memsize", (u64)bd->bi_memsize);
333 print_num("flashstart", (ulong)bd->bi_flashstart);
334 print_num("flashsize", (ulong)bd->bi_flashsize);
335 print_num("flashoffset", (ulong)bd->bi_flashoffset);
c99ea790
RM
336
337 print_eth(0);
5902e8f7
ML
338 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
339 printf("baudrate = %lu bps\n", bd->bi_baudrate);
c99ea790
RM
340
341 return 0;
342}
343
344#elif defined(CONFIG_ARM)
8bde7f77 345
5902e8f7 346int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 347{
8bde7f77
WD
348 int i;
349 bd_t *bd = gd->bd;
350
5902e8f7
ML
351 print_num("arch_number", bd->bi_arch_number);
352 print_num("boot_params", (ulong)bd->bi_boot_params);
8bde7f77 353
5902e8f7 354 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
8bde7f77
WD
355 print_num("DRAM bank", i);
356 print_num("-> start", bd->bi_dram[i].start);
357 print_num("-> size", bd->bi_dram[i].size);
358 }
359
a41dbbd9 360#if defined(CONFIG_CMD_NET)
de2dff6f 361 print_eth(0);
5902e8f7 362 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
a41dbbd9 363#endif
5902e8f7 364 printf("baudrate = %d bps\n", bd->bi_baudrate);
e47f2db5 365#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
5902e8f7 366 print_num("TLB addr", gd->tlb_addr);
f1d2b313 367#endif
5902e8f7
ML
368 print_num("relocaddr", gd->relocaddr);
369 print_num("reloc off", gd->reloc_off);
370 print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
371 print_num("sp start ", gd->start_addr_sp);
372 print_num("FB base ", gd->fb_base);
8f5d4687
HM
373 /*
374 * TODO: Currently only support for davinci SOC's is added.
375 * Remove this check once all the board implement this.
376 */
377#ifdef CONFIG_CLOCKS
378 printf("ARM frequency = %ld MHz\n", gd->bd->bi_arm_freq);
379 printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq);
380 printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq);
381#endif
8bde7f77
WD
382 return 0;
383}
384
ebd0d062
NI
385#elif defined(CONFIG_SH)
386
5902e8f7 387int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
ebd0d062
NI
388{
389 bd_t *bd = gd->bd;
5902e8f7
ML
390 print_num("mem start ", (ulong)bd->bi_memstart);
391 print_lnum("mem size ", (u64)bd->bi_memsize);
392 print_num("flash start ", (ulong)bd->bi_flashstart);
393 print_num("flash size ", (ulong)bd->bi_flashsize);
394 print_num("flash offset ", (ulong)bd->bi_flashoffset);
ebd0d062
NI
395
396#if defined(CONFIG_CMD_NET)
397 print_eth(0);
5902e8f7 398 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
ebd0d062 399#endif
5902e8f7 400 printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate);
ebd0d062
NI
401 return 0;
402}
403
a806ee6f
GR
404#elif defined(CONFIG_X86)
405
5902e8f7 406int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
a806ee6f
GR
407{
408 int i;
409 bd_t *bd = gd->bd;
a806ee6f 410
5902e8f7
ML
411 print_num("boot_params", (ulong)bd->bi_boot_params);
412 print_num("bi_memstart", bd->bi_memstart);
413 print_num("bi_memsize", bd->bi_memsize);
414 print_num("bi_flashstart", bd->bi_flashstart);
415 print_num("bi_flashsize", bd->bi_flashsize);
416 print_num("bi_flashoffset", bd->bi_flashoffset);
417 print_num("bi_sramstart", bd->bi_sramstart);
418 print_num("bi_sramsize", bd->bi_sramsize);
419 print_num("bi_bootflags", bd->bi_bootflags);
0c277ef9
TT
420 print_mhz("cpufreq", bd->bi_intfreq);
421 print_mhz("busfreq", bd->bi_busfreq);
5902e8f7
ML
422
423 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
a806ee6f
GR
424 print_num("DRAM bank", i);
425 print_num("-> start", bd->bi_dram[i].start);
426 print_num("-> size", bd->bi_dram[i].size);
427 }
428
429#if defined(CONFIG_CMD_NET)
430 print_eth(0);
5902e8f7 431 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
0c277ef9 432 print_mhz("ethspeed", bd->bi_ethspeed);
a806ee6f 433#endif
5902e8f7 434 printf("baudrate = %d bps\n", bd->bi_baudrate);
a806ee6f
GR
435
436 return 0;
437}
438
6fcc3be4
SG
439#elif defined(CONFIG_SANDBOX)
440
441int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
442{
443 int i;
444 bd_t *bd = gd->bd;
445
446 print_num("boot_params", (ulong)bd->bi_boot_params);
447
448 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
449 print_num("DRAM bank", i);
450 print_num("-> start", bd->bi_dram[i].start);
451 print_num("-> size", bd->bi_dram[i].size);
452 }
453
454#if defined(CONFIG_CMD_NET)
455 print_eth(0);
456 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
457#endif
458 print_num("FB base ", gd->fb_base);
459 return 0;
460}
461
64d61461
ML
462#elif defined(CONFIG_NDS32)
463
464int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
465{
466 int i;
467 bd_t *bd = gd->bd;
468
469 print_num("arch_number", bd->bi_arch_number);
470 print_num("boot_params", (ulong)bd->bi_boot_params);
471
472 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
473 print_num("DRAM bank", i);
474 print_num("-> start", bd->bi_dram[i].start);
475 print_num("-> size", bd->bi_dram[i].size);
476 }
477
478#if defined(CONFIG_CMD_NET)
479 print_eth(0);
480 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
481#endif
482 printf("baudrate = %d bps\n", bd->bi_baudrate);
483
484 return 0;
485}
486
2be9fdbf
SK
487#elif defined(CONFIG_OPENRISC)
488
489int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
490{
491 bd_t *bd = gd->bd;
492
493 print_num("mem start", (ulong)bd->bi_memstart);
494 print_lnum("mem size", (u64)bd->bi_memsize);
495 print_num("flash start", (ulong)bd->bi_flashstart);
496 print_num("flash size", (ulong)bd->bi_flashsize);
497 print_num("flash offset", (ulong)bd->bi_flashoffset);
498
499#if defined(CONFIG_CMD_NET)
500 print_eth(0);
501 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
502#endif
503
504 printf("baudrate = %ld bps\n", bd->bi_baudrate);
505
506 return 0;
507}
508
c99ea790
RM
509#else
510 #error "a case for this architecture does not exist!"
511#endif
8bde7f77 512
8bde7f77
WD
513/* -------------------------------------------------------------------- */
514
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WD
515U_BOOT_CMD(
516 bdinfo, 1, 1, do_bdinfo,
2fb2604d 517 "print Board Info structure",
a89c33db 518 ""
8bde7f77 519);