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c609719b 1/*
34c202c7 2 * (C) Copyright 2000-2011
c609719b
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * IDE support
27 */
113bfe48 28
c609719b
WD
29#include <common.h>
30#include <config.h>
31#include <watchdog.h>
32#include <command.h>
33#include <image.h>
34#include <asm/byteorder.h>
f98984cb 35#include <asm/io.h>
735dd97b 36
c609719b
WD
37#if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA)
38# include <pcmcia.h>
39#endif
735dd97b 40
c609719b
WD
41#include <ide.h>
42#include <ata.h>
735dd97b 43
c609719b
WD
44#ifdef CONFIG_STATUS_LED
45# include <status_led.h>
46#endif
735dd97b 47
5cf91d6b
WD
48#ifdef __PPC__
49# define EIEIO __asm__ volatile ("eieio")
1a344f29 50# define SYNC __asm__ volatile ("sync")
5cf91d6b
WD
51#else
52# define EIEIO /* nothing */
1a344f29 53# define SYNC /* nothing */
c609719b
WD
54#endif
55
c609719b
WD
56/* ------------------------------------------------------------------------- */
57
58/* Current I/O Device */
59static int curr_device = -1;
60
61/* Current offset for IDE0 / IDE1 bus access */
6d0f6bcf
JCPV
62ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
63#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
64 CONFIG_SYS_ATA_IDE0_OFFSET,
c609719b 65#endif
6d0f6bcf
JCPV
66#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
67 CONFIG_SYS_ATA_IDE1_OFFSET,
c609719b
WD
68#endif
69};
70
6d0f6bcf 71static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
c609719b 72
6d0f6bcf 73block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
c609719b
WD
74/* ------------------------------------------------------------------------- */
75
c609719b
WD
76#ifdef CONFIG_IDE_RESET
77static void ide_reset (void);
78#else
79#define ide_reset() /* dummy */
80#endif
81
82static void ide_ident (block_dev_desc_t *dev_desc);
83static uchar ide_wait (int dev, ulong t);
84
85#define IDE_TIME_OUT 2000 /* 2 sec timeout */
86
87#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */
88
89#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
90
c609719b
WD
91static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
92
6d0f6bcf
JCPV
93#ifndef CONFIG_SYS_ATA_PORT_ADDR
94#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
566a494f 95#endif
c609719b
WD
96
97#ifdef CONFIG_ATAPI
98static void atapi_inquiry(block_dev_desc_t *dev_desc);
b6458d38
SG
99static ulong atapi_read(int device, ulong blknr, lbaint_t blkcnt,
100 void *buffer);
c609719b
WD
101#endif
102
103
c609719b
WD
104/* ------------------------------------------------------------------------- */
105
34c202c7 106int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
c609719b 107{
34c202c7
WD
108 int rcode = 0;
109
110 switch (argc) {
111 case 0:
112 case 1:
4c12eeb8 113 return CMD_RET_USAGE;
34c202c7
WD
114 case 2:
115 if (strncmp(argv[1], "res", 3) == 0) {
116 puts("\nReset IDE"
c609719b 117#ifdef CONFIG_IDE_8xx_DIRECT
34c202c7 118 " on PCMCIA " PCMCIA_SLOT_MSG
c609719b 119#endif
34c202c7 120 ": ");
c609719b 121
34c202c7
WD
122 ide_init();
123 return 0;
124 } else if (strncmp(argv[1], "inf", 3) == 0) {
125 int i;
c609719b 126
34c202c7 127 putc('\n');
c609719b 128
34c202c7
WD
129 for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
130 if (ide_dev_desc[i].type == DEV_TYPE_UNKNOWN)
131 continue; /* list only known devices */
132 printf("IDE device %d: ", i);
133 dev_print(&ide_dev_desc[i]);
134 }
135 return 0;
c609719b 136
34c202c7
WD
137 } else if (strncmp(argv[1], "dev", 3) == 0) {
138 if ((curr_device < 0)
139 || (curr_device >= CONFIG_SYS_IDE_MAXDEVICE)) {
140 puts("\nno IDE devices available\n");
141 return 1;
c609719b 142 }
34c202c7
WD
143 printf("\nIDE device %d: ", curr_device);
144 dev_print(&ide_dev_desc[curr_device]);
145 return 0;
146 } else if (strncmp(argv[1], "part", 4) == 0) {
147 int dev, ok;
148
149 for (ok = 0, dev = 0;
150 dev < CONFIG_SYS_IDE_MAXDEVICE;
151 ++dev) {
152 if (ide_dev_desc[dev].part_type !=
153 PART_TYPE_UNKNOWN) {
154 ++ok;
155 if (dev)
156 putc('\n');
157 print_part(&ide_dev_desc[dev]);
158 }
159 }
160 if (!ok) {
161 puts("\nno IDE devices available\n");
162 rcode++;
163 }
164 return rcode;
c609719b 165 }
4c12eeb8 166 return CMD_RET_USAGE;
34c202c7
WD
167 case 3:
168 if (strncmp(argv[1], "dev", 3) == 0) {
169 int dev = (int) simple_strtoul(argv[2], NULL, 10);
c609719b 170
34c202c7
WD
171 printf("\nIDE device %d: ", dev);
172 if (dev >= CONFIG_SYS_IDE_MAXDEVICE) {
173 puts("unknown device\n");
174 return 1;
175 }
176 dev_print(&ide_dev_desc[dev]);
177 /*ide_print (dev); */
c609719b 178
34c202c7
WD
179 if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
180 return 1;
c609719b 181
34c202c7 182 curr_device = dev;
c609719b 183
34c202c7
WD
184 puts("... is now current device\n");
185
186 return 0;
187 } else if (strncmp(argv[1], "part", 4) == 0) {
188 int dev = (int) simple_strtoul(argv[2], NULL, 10);
c609719b 189
34c202c7 190 if (ide_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
c609719b 191 print_part(&ide_dev_desc[dev]);
34c202c7
WD
192 } else {
193 printf("\nIDE device %d not available\n",
194 dev);
195 rcode = 1;
196 }
197 return rcode;
c609719b 198 }
c609719b 199
4c12eeb8 200 return CMD_RET_USAGE;
34c202c7
WD
201 default:
202 /* at least 4 args */
c609719b 203
34c202c7
WD
204 if (strcmp(argv[1], "read") == 0) {
205 ulong addr = simple_strtoul(argv[2], NULL, 16);
206 ulong cnt = simple_strtoul(argv[4], NULL, 16);
207 ulong n;
c609719b 208
6d0f6bcf 209#ifdef CONFIG_SYS_64BIT_LBA
34c202c7 210 lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
c609719b 211
34c202c7
WD
212 printf("\nIDE read: device %d block # %lld, count %ld ... ",
213 curr_device, blk, cnt);
42dfe7a1 214#else
34c202c7
WD
215 lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
216
217 printf("\nIDE read: device %d block # %ld, count %ld ... ",
218 curr_device, blk, cnt);
219#endif
220
221 n = ide_dev_desc[curr_device].block_read(curr_device,
222 blk, cnt,
223 (ulong *)addr);
224 /* flush cache after read */
225 flush_cache(addr,
226 cnt * ide_dev_desc[curr_device].blksz);
227
228 printf("%ld blocks read: %s\n",
229 n, (n == cnt) ? "OK" : "ERROR");
230 if (n == cnt)
231 return 0;
232 else
233 return 1;
234 } else if (strcmp(argv[1], "write") == 0) {
235 ulong addr = simple_strtoul(argv[2], NULL, 16);
236 ulong cnt = simple_strtoul(argv[4], NULL, 16);
237 ulong n;
c609719b 238
6d0f6bcf 239#ifdef CONFIG_SYS_64BIT_LBA
34c202c7 240 lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
c609719b 241
34c202c7
WD
242 printf("\nIDE write: device %d block # %lld, count %ld ... ",
243 curr_device, blk, cnt);
42dfe7a1 244#else
34c202c7 245 lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
42dfe7a1 246
34c202c7
WD
247 printf("\nIDE write: device %d block # %ld, count %ld ... ",
248 curr_device, blk, cnt);
42dfe7a1 249#endif
34c202c7 250 n = ide_write(curr_device, blk, cnt, (ulong *) addr);
c609719b 251
34c202c7
WD
252 printf("%ld blocks written: %s\n",
253 n, (n == cnt) ? "OK" : "ERROR");
254 if (n == cnt)
255 return 0;
256 else
257 return 1;
258 } else {
4c12eeb8 259 return CMD_RET_USAGE;
34c202c7 260 }
c609719b 261
34c202c7 262 return rcode;
c609719b 263 }
c609719b
WD
264}
265
34c202c7 266int do_diskboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
c609719b 267{
7405a133 268 return common_diskboot(cmdtp, "ide", argc, argv);
c609719b
WD
269}
270
271/* ------------------------------------------------------------------------- */
272
19be2ea2
PH
273void __ide_led(uchar led, uchar status)
274{
275#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
276 static uchar led_buffer; /* Buffer for current LED status */
277
278 uchar *led_port = LED_PORT;
279
280 if (status) /* switch LED on */
281 led_buffer |= led;
282 else /* switch LED off */
283 led_buffer &= ~led;
284
285 *led_port = led_buffer;
286#endif
287}
288
289void ide_led(uchar led, uchar status)
290 __attribute__ ((weak, alias("__ide_led")));
291
292#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
293# define DEVICE_LED(x) 0
294# define LED_IDE1 1
295# define LED_IDE2 2
296#endif
297
298/* ------------------------------------------------------------------------- */
299
34c202c7 300inline void __ide_outb(int dev, int port, unsigned char val)
f2302d44 301{
34c202c7
WD
302 debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
303 dev, port, val,
304 (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
0abddf82
ML
305
306#if defined(CONFIG_IDE_AHB)
307 if (port) {
308 /* write command */
309 ide_write_register(dev, port, val);
310 } else {
311 /* write data */
312 outb(val, (ATA_CURR_BASE(dev)));
313 }
314#else
34c202c7 315 outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
0abddf82 316#endif
f2302d44 317}
0abddf82 318
34c202c7
WD
319void ide_outb(int dev, int port, unsigned char val)
320 __attribute__ ((weak, alias("__ide_outb")));
f2302d44 321
34c202c7 322inline unsigned char __ide_inb(int dev, int port)
f2302d44
SR
323{
324 uchar val;
0abddf82
ML
325
326#if defined(CONFIG_IDE_AHB)
327 val = ide_read_register(dev, port);
328#else
34c202c7 329 val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
0abddf82
ML
330#endif
331
34c202c7
WD
332 debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
333 dev, port,
334 (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
f2302d44
SR
335 return val;
336}
34c202c7 337
2df72b82 338unsigned char ide_inb(int dev, int port)
34c202c7 339 __attribute__ ((weak, alias("__ide_inb")));
f2302d44 340
36c2d306 341#ifdef CONFIG_TUNE_PIO
34c202c7 342inline int __ide_set_piomode(int pio_mode)
36c2d306
SF
343{
344 return 0;
345}
34c202c7
WD
346
347inline int ide_set_piomode(int pio_mode)
348 __attribute__ ((weak, alias("__ide_set_piomode")));
36c2d306
SF
349#endif
350
34c202c7 351void ide_init(void)
c609719b 352{
c609719b
WD
353 unsigned char c;
354 int i, bus;
34c202c7 355
9fd5e31f 356#ifdef CONFIG_IDE_8xx_PCCARD
34c202c7
WD
357 extern int ide_devices_found; /* Initialized in check_ide_device() */
358#endif /* CONFIG_IDE_8xx_PCCARD */
9fd5e31f
WD
359
360#ifdef CONFIG_IDE_PREINIT
361 WATCHDOG_RESET();
362
34c202c7
WD
363 if (ide_preinit()) {
364 puts("ide_preinit failed\n");
9fd5e31f
WD
365 return;
366 }
34c202c7 367#endif /* CONFIG_IDE_PREINIT */
c609719b 368
c609719b
WD
369 WATCHDOG_RESET();
370
34c202c7
WD
371 /*
372 * Reset the IDE just to be sure.
c609719b
WD
373 * Light LED's to show
374 */
34c202c7
WD
375 ide_led((LED_IDE1 | LED_IDE2), 1); /* LED's on */
376
377 /* ATAPI Drives seems to need a proper IDE Reset */
378 ide_reset();
c609719b 379
8d1165e1
PH
380#ifdef CONFIG_IDE_INIT_POSTRESET
381 WATCHDOG_RESET();
c609719b 382
8d1165e1
PH
383 if (ide_init_postreset()) {
384 puts("ide_preinit_postreset failed\n");
385 return;
386 }
387#endif /* CONFIG_IDE_INIT_POSTRESET */
c609719b
WD
388
389 /*
390 * Wait for IDE to get ready.
391 * According to spec, this can take up to 31 seconds!
392 */
34c202c7
WD
393 for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
394 int dev =
395 bus * (CONFIG_SYS_IDE_MAXDEVICE /
396 CONFIG_SYS_IDE_MAXBUS);
c609719b 397
6069ff26
WD
398#ifdef CONFIG_IDE_8xx_PCCARD
399 /* Skip non-ide devices from probing */
400 if ((ide_devices_found & (1 << bus)) == 0) {
34c202c7 401 ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
6069ff26
WD
402 continue;
403 }
404#endif
34c202c7 405 printf("Bus %d: ", bus);
c609719b
WD
406
407 ide_bus_ok[bus] = 0;
408
409 /* Select device
410 */
34c202c7
WD
411 udelay(100000); /* 100 ms */
412 ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
413 udelay(100000); /* 100 ms */
c609719b
WD
414 i = 0;
415 do {
34c202c7 416 udelay(10000); /* 10 ms */
c609719b 417
34c202c7 418 c = ide_inb(dev, ATA_STATUS);
c609719b
WD
419 i++;
420 if (i > (ATA_RESET_TIME * 100)) {
34c202c7
WD
421 puts("** Timeout **\n");
422 /* LED's off */
423 ide_led((LED_IDE1 | LED_IDE2), 0);
c609719b
WD
424 return;
425 }
34c202c7
WD
426 if ((i >= 100) && ((i % 100) == 0))
427 putc('.');
428
c609719b
WD
429 } while (c & ATA_STAT_BUSY);
430
431 if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
34c202c7
WD
432 puts("not available ");
433 debug("Status = 0x%02X ", c);
434#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
435 } else if ((c & ATA_STAT_READY) == 0) {
436 puts("not available ");
437 debug("Status = 0x%02X ", c);
c609719b
WD
438#endif
439 } else {
34c202c7 440 puts("OK ");
c609719b
WD
441 ide_bus_ok[bus] = 1;
442 }
443 WATCHDOG_RESET();
444 }
c7de829c 445
34c202c7 446 putc('\n');
c609719b 447
34c202c7 448 ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
c609719b
WD
449
450 curr_device = -1;
34c202c7 451 for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
c609719b 452 int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
34c202c7
WD
453 ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
454 ide_dev_desc[i].if_type = IF_TYPE_IDE;
455 ide_dev_desc[i].dev = i;
456 ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
457 ide_dev_desc[i].blksz = 0;
0472fbfd
EE
458 ide_dev_desc[i].log2blksz =
459 LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
34c202c7
WD
460 ide_dev_desc[i].lba = 0;
461 ide_dev_desc[i].block_read = ide_read;
0abddf82 462 ide_dev_desc[i].block_write = ide_write;
c609719b
WD
463 if (!ide_bus_ok[IDE_BUS(i)])
464 continue;
34c202c7 465 ide_led(led, 1); /* LED on */
c609719b 466 ide_ident(&ide_dev_desc[i]);
34c202c7 467 ide_led(led, 0); /* LED off */
c609719b 468 dev_print(&ide_dev_desc[i]);
34c202c7 469
c609719b 470 if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
34c202c7
WD
471 /* initialize partition type */
472 init_part(&ide_dev_desc[i]);
c609719b
WD
473 if (curr_device < 0)
474 curr_device = i;
475 }
476 }
477 WATCHDOG_RESET();
478}
479
480/* ------------------------------------------------------------------------- */
481
df3fc526 482#ifdef CONFIG_PARTITIONS
34c202c7 483block_dev_desc_t *ide_get_dev(int dev)
c609719b 484{
6d0f6bcf 485 return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
c609719b 486}
df3fc526 487#endif
c609719b 488
c609719b
WD
489/* ------------------------------------------------------------------------- */
490
f5b82c0f
PH
491void ide_input_swap_data(int dev, ulong *sect_buf, int words)
492 __attribute__ ((weak, alias("__ide_input_swap_data")));
493
494void ide_input_data(int dev, ulong *sect_buf, int words)
495 __attribute__ ((weak, alias("__ide_input_data")));
496
497void ide_output_data(int dev, const ulong *sect_buf, int words)
498 __attribute__ ((weak, alias("__ide_output_data")));
499
5da627a4 500/* We only need to swap data if we are running on a big endian cpu. */
4d1361d8 501#if defined(__LITTLE_ENDIAN)
f5b82c0f
PH
502void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
503{
504 ide_input_data(dev, sect_buf, words);
505}
5da627a4 506#else
f5b82c0f 507void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
c609719b 508{
34c202c7
WD
509 volatile ushort *pbuf =
510 (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
511 ushort *dbuf = (ushort *) sect_buf;
1a344f29 512
34c202c7
WD
513 debug("in input swap data base for read is %lx\n",
514 (unsigned long) pbuf);
1a344f29
WD
515
516 while (words--) {
0c32d96d 517#ifdef __MIPS__
34c202c7
WD
518 *dbuf++ = swab16p((u16 *) pbuf);
519 *dbuf++ = swab16p((u16 *) pbuf);
0c32d96d 520#else
1a344f29
WD
521 *dbuf++ = ld_le16(pbuf);
522 *dbuf++ = ld_le16(pbuf);
0c32d96d 523#endif /* !MIPS */
1a344f29 524 }
c609719b 525}
4d1361d8 526#endif /* __LITTLE_ENDIAN */
2262cfee
WD
527
528
f2a37fcd 529#if defined(CONFIG_IDE_SWAP_IO)
f5b82c0f 530void __ide_output_data(int dev, const ulong *sect_buf, int words)
c609719b 531{
34c202c7
WD
532 ushort *dbuf;
533 volatile ushort *pbuf;
1a344f29 534
34c202c7
WD
535 pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
536 dbuf = (ushort *) sect_buf;
1a344f29
WD
537 while (words--) {
538 EIEIO;
539 *pbuf = *dbuf++;
540 EIEIO;
541 *pbuf = *dbuf++;
542 }
c609719b 543}
34c202c7 544#else /* ! CONFIG_IDE_SWAP_IO */
f5b82c0f 545void __ide_output_data(int dev, const ulong *sect_buf, int words)
2262cfee 546{
0abddf82
ML
547#if defined(CONFIG_IDE_AHB)
548 ide_write_data(dev, sect_buf, words);
549#else
34c202c7 550 outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
0abddf82 551#endif
2262cfee 552}
34c202c7 553#endif /* CONFIG_IDE_SWAP_IO */
c609719b 554
f2a37fcd 555#if defined(CONFIG_IDE_SWAP_IO)
f5b82c0f 556void __ide_input_data(int dev, ulong *sect_buf, int words)
c609719b 557{
34c202c7
WD
558 ushort *dbuf;
559 volatile ushort *pbuf;
1a344f29 560
34c202c7
WD
561 pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
562 dbuf = (ushort *) sect_buf;
1a344f29
WD
563
564 debug("in input data base for read is %lx\n", (unsigned long) pbuf);
565
566 while (words--) {
cd172b71 567 EIEIO;
1a344f29 568 *dbuf++ = *pbuf;
cd172b71 569 EIEIO;
1a344f29 570 *dbuf++ = *pbuf;
a522fa0e 571 }
c609719b 572}
34c202c7 573#else /* ! CONFIG_IDE_SWAP_IO */
f5b82c0f 574void __ide_input_data(int dev, ulong *sect_buf, int words)
2262cfee 575{
0abddf82
ML
576#if defined(CONFIG_IDE_AHB)
577 ide_read_data(dev, sect_buf, words);
578#else
34c202c7 579 insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
0abddf82 580#endif
2262cfee
WD
581}
582
34c202c7 583#endif /* CONFIG_IDE_SWAP_IO */
c609719b
WD
584
585/* -------------------------------------------------------------------------
586 */
34c202c7 587static void ide_ident(block_dev_desc_t *dev_desc)
c609719b 588{
c609719b 589 unsigned char c;
b18eabfa 590 hd_driveid_t iop;
c609719b 591
64f70bed
WD
592#ifdef CONFIG_ATAPI
593 int retries = 0;
c7de829c
WD
594#endif
595
36c2d306
SF
596#ifdef CONFIG_TUNE_PIO
597 int pio_mode;
598#endif
599
c609719b
WD
600#if 0
601 int mode, cycle_time;
602#endif
603 int device;
c609719b 604
34c202c7
WD
605 device = dev_desc->dev;
606 printf(" Device %d: ", device);
607
608 ide_led(DEVICE_LED(device), 1); /* LED on */
c609719b
WD
609 /* Select device
610 */
34c202c7
WD
611 ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
612 dev_desc->if_type = IF_TYPE_IDE;
c609719b 613#ifdef CONFIG_ATAPI
c7de829c 614
34c202c7
WD
615 retries = 0;
616
617 /* Warning: This will be tricky to read */
618 while (retries <= 1) {
619 /* check signature */
620 if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
621 (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
622 (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
623 (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
624 /* ATAPI Signature found */
625 dev_desc->if_type = IF_TYPE_ATAPI;
626 /*
627 * Start Ident Command
628 */
629 ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
630 /*
631 * Wait for completion - ATAPI devices need more time
632 * to become ready
633 */
634 c = ide_wait(device, ATAPI_TIME_OUT);
635 } else
c609719b 636#endif
1a344f29 637 {
34c202c7
WD
638 /*
639 * Start Ident Command
640 */
641 ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
642
643 /*
644 * Wait for completion
645 */
646 c = ide_wait(device, IDE_TIME_OUT);
1a344f29 647 }
34c202c7
WD
648 ide_led(DEVICE_LED(device), 0); /* LED off */
649
650 if (((c & ATA_STAT_DRQ) == 0) ||
651 ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
652#ifdef CONFIG_ATAPI
653 {
654 /*
655 * Need to soft reset the device
656 * in case it's an ATAPI...
657 */
658 debug("Retrying...\n");
659 ide_outb(device, ATA_DEV_HD,
660 ATA_LBA | ATA_DEVICE(device));
661 udelay(100000);
662 ide_outb(device, ATA_COMMAND, 0x08);
663 udelay(500000); /* 500 ms */
664 }
665 /*
666 * Select device
667 */
668 ide_outb(device, ATA_DEV_HD,
669 ATA_LBA | ATA_DEVICE(device));
670 retries++;
64f70bed 671#else
34c202c7 672 return;
64f70bed 673#endif
34c202c7 674 }
64f70bed 675#ifdef CONFIG_ATAPI
34c202c7
WD
676 else
677 break;
678 } /* see above - ugly to read */
64f70bed 679
34c202c7 680 if (retries == 2) /* Not found */
64f70bed
WD
681 return;
682#endif
c609719b 683
f5b82c0f 684 ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
c609719b 685
34c202c7
WD
686 ident_cpy((unsigned char *) dev_desc->revision, iop.fw_rev,
687 sizeof(dev_desc->revision));
688 ident_cpy((unsigned char *) dev_desc->vendor, iop.model,
689 sizeof(dev_desc->vendor));
690 ident_cpy((unsigned char *) dev_desc->product, iop.serial_no,
691 sizeof(dev_desc->product));
c3f9d493
WD
692#ifdef __LITTLE_ENDIAN
693 /*
bcdf1d2c
RR
694 * firmware revision, model, and serial number have Big Endian Byte
695 * order in Word. Convert all three to little endian.
c3f9d493
WD
696 *
697 * See CF+ and CompactFlash Specification Revision 2.0:
bcdf1d2c 698 * 6.2.1.6: Identify Drive, Table 39 for more details
c3f9d493
WD
699 */
700
34c202c7
WD
701 strswab(dev_desc->revision);
702 strswab(dev_desc->vendor);
703 strswab(dev_desc->product);
c3f9d493 704#endif /* __LITTLE_ENDIAN */
c609719b 705
b18eabfa 706 if ((iop.config & 0x0080) == 0x0080)
c609719b
WD
707 dev_desc->removable = 1;
708 else
709 dev_desc->removable = 0;
710
36c2d306
SF
711#ifdef CONFIG_TUNE_PIO
712 /* Mode 0 - 2 only, are directly determined by word 51. */
b18eabfa 713 pio_mode = iop.tPIO;
36c2d306
SF
714 if (pio_mode > 2) {
715 printf("WARNING: Invalid PIO (word 51 = %d).\n", pio_mode);
34c202c7
WD
716 /* Force it to dead slow, and hope for the best... */
717 pio_mode = 0;
36c2d306
SF
718 }
719
720 /* Any CompactFlash Storage Card that supports PIO mode 3 or above
721 * shall set bit 1 of word 53 to one and support the fields contained
722 * in words 64 through 70.
723 */
b18eabfa 724 if (iop.field_valid & 0x02) {
34c202c7
WD
725 /*
726 * Mode 3 and above are possible. Check in order from slow
36c2d306
SF
727 * to fast, so we wind up with the highest mode allowed.
728 */
b18eabfa 729 if (iop.eide_pio_modes & 0x01)
36c2d306 730 pio_mode = 3;
b18eabfa 731 if (iop.eide_pio_modes & 0x02)
36c2d306 732 pio_mode = 4;
b18eabfa
MV
733 if (ata_id_is_cfa((u16 *)&iop)) {
734 if ((iop.cf_advanced_caps & 0x07) == 0x01)
36c2d306 735 pio_mode = 5;
b18eabfa 736 if ((iop.cf_advanced_caps & 0x07) == 0x02)
36c2d306
SF
737 pio_mode = 6;
738 }
739 }
740
741 /* System-specific, depends on bus speeds, etc. */
742 ide_set_piomode(pio_mode);
743#endif /* CONFIG_TUNE_PIO */
744
c609719b
WD
745#if 0
746 /*
747 * Drive PIO mode autoselection
748 */
b18eabfa 749 mode = iop.tPIO;
c609719b 750
34c202c7 751 printf("tPIO = 0x%02x = %d\n", mode, mode);
c609719b
WD
752 if (mode > 2) { /* 2 is maximum allowed tPIO value */
753 mode = 2;
34c202c7 754 debug("Override tPIO -> 2\n");
c609719b 755 }
b18eabfa 756 if (iop.field_valid & 2) { /* drive implements ATA2? */
34c202c7 757 debug("Drive implements ATA2\n");
b18eabfa
MV
758 if (iop.capability & 8) { /* drive supports use_iordy? */
759 cycle_time = iop.eide_pio_iordy;
c609719b 760 } else {
b18eabfa 761 cycle_time = iop.eide_pio;
c609719b 762 }
34c202c7 763 debug("cycle time = %d\n", cycle_time);
c609719b 764 mode = 4;
34c202c7
WD
765 if (cycle_time > 120)
766 mode = 3; /* 120 ns for PIO mode 4 */
767 if (cycle_time > 180)
768 mode = 2; /* 180 ns for PIO mode 3 */
769 if (cycle_time > 240)
770 mode = 1; /* 240 ns for PIO mode 4 */
771 if (cycle_time > 383)
772 mode = 0; /* 383 ns for PIO mode 4 */
c609719b 773 }
34c202c7 774 printf("PIO mode to use: PIO %d\n", mode);
c609719b
WD
775#endif /* 0 */
776
777#ifdef CONFIG_ATAPI
34c202c7 778 if (dev_desc->if_type == IF_TYPE_ATAPI) {
c609719b
WD
779 atapi_inquiry(dev_desc);
780 return;
781 }
782#endif /* CONFIG_ATAPI */
783
c3f9d493 784#ifdef __BIG_ENDIAN
c609719b 785 /* swap shorts */
b18eabfa 786 dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
34c202c7 787#else /* ! __BIG_ENDIAN */
c3f9d493
WD
788 /*
789 * do not swap shorts on little endian
790 *
791 * See CF+ and CompactFlash Specification Revision 2.0:
792 * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
793 */
b18eabfa 794 dev_desc->lba = iop.lba_capacity;
34c202c7 795#endif /* __BIG_ENDIAN */
c40b2956 796
42dfe7a1 797#ifdef CONFIG_LBA48
34c202c7 798 if (iop.command_set_2 & 0x0400) { /* LBA 48 support */
6e592385 799 dev_desc->lba48 = 1;
34c202c7
WD
800 dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
801 ((unsigned long long) iop.lba48_capacity[1] << 16) |
802 ((unsigned long long) iop.lba48_capacity[2] << 32) |
803 ((unsigned long long) iop.lba48_capacity[3] << 48);
c40b2956 804 } else {
c40b2956
WD
805 dev_desc->lba48 = 0;
806 }
807#endif /* CONFIG_LBA48 */
c609719b 808 /* assuming HD */
34c202c7
WD
809 dev_desc->type = DEV_TYPE_HARDDISK;
810 dev_desc->blksz = ATA_BLOCKSIZE;
0472fbfd 811 dev_desc->log2blksz = LOG2(dev_desc->blksz);
34c202c7
WD
812 dev_desc->lun = 0; /* just to fill something in... */
813
814#if 0 /* only used to test the powersaving mode,
815 * if enabled, the drive goes after 5 sec
816 * in standby mode */
817 ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
818 c = ide_wait(device, IDE_TIME_OUT);
819 ide_outb(device, ATA_SECT_CNT, 1);
820 ide_outb(device, ATA_LBA_LOW, 0);
821 ide_outb(device, ATA_LBA_MID, 0);
822 ide_outb(device, ATA_LBA_HIGH, 0);
823 ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
824 ide_outb(device, ATA_COMMAND, 0xe3);
825 udelay(50);
826 c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
c609719b
WD
827#endif
828}
829
830
831/* ------------------------------------------------------------------------- */
832
b6458d38 833ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
c609719b
WD
834{
835 ulong n = 0;
836 unsigned char c;
34c202c7
WD
837 unsigned char pwrsave = 0; /* power save */
838
42dfe7a1 839#ifdef CONFIG_LBA48
c40b2956 840 unsigned char lba48 = 0;
c609719b 841
413bf586 842 if (blknr & 0x0000fffff0000000ULL) {
c40b2956
WD
843 /* more than 28 bits used, use 48bit mode */
844 lba48 = 1;
845 }
846#endif
b6458d38 847 debug("ide_read dev %d start %lX, blocks " LBAF " buffer at %lX\n",
34c202c7 848 device, blknr, blkcnt, (ulong) buffer);
c609719b 849
34c202c7 850 ide_led(DEVICE_LED(device), 1); /* LED on */
c609719b
WD
851
852 /* Select device
853 */
34c202c7
WD
854 ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
855 c = ide_wait(device, IDE_TIME_OUT);
c609719b
WD
856
857 if (c & ATA_STAT_BUSY) {
34c202c7 858 printf("IDE read: device %d not ready\n", device);
c609719b
WD
859 goto IDE_READ_E;
860 }
861
862 /* first check if the drive is in Powersaving mode, if yes,
863 * increase the timeout value */
34c202c7
WD
864 ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
865 udelay(50);
c609719b 866
34c202c7 867 c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
c609719b
WD
868
869 if (c & ATA_STAT_BUSY) {
34c202c7 870 printf("IDE read: device %d not ready\n", device);
c609719b
WD
871 goto IDE_READ_E;
872 }
873 if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
34c202c7 874 printf("No Powersaving mode %X\n", c);
c609719b 875 } else {
34c202c7
WD
876 c = ide_inb(device, ATA_SECT_CNT);
877 debug("Powersaving %02X\n", c);
878 if (c == 0)
879 pwrsave = 1;
c609719b
WD
880 }
881
882
883 while (blkcnt-- > 0) {
884
34c202c7 885 c = ide_wait(device, IDE_TIME_OUT);
c609719b
WD
886
887 if (c & ATA_STAT_BUSY) {
34c202c7 888 printf("IDE read: device %d not ready\n", device);
c609719b
WD
889 break;
890 }
42dfe7a1 891#ifdef CONFIG_LBA48
c40b2956
WD
892 if (lba48) {
893 /* write high bits */
34c202c7
WD
894 ide_outb(device, ATA_SECT_CNT, 0);
895 ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
6d0f6bcf 896#ifdef CONFIG_SYS_64BIT_LBA
34c202c7
WD
897 ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
898 ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
413bf586 899#else
34c202c7
WD
900 ide_outb(device, ATA_LBA_MID, 0);
901 ide_outb(device, ATA_LBA_HIGH, 0);
413bf586 902#endif
c40b2956
WD
903 }
904#endif
34c202c7
WD
905 ide_outb(device, ATA_SECT_CNT, 1);
906 ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
907 ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
908 ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
c40b2956 909
42dfe7a1 910#ifdef CONFIG_LBA48
c40b2956 911 if (lba48) {
34c202c7
WD
912 ide_outb(device, ATA_DEV_HD,
913 ATA_LBA | ATA_DEVICE(device));
914 ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
c40b2956
WD
915
916 } else
917#endif
918 {
34c202c7
WD
919 ide_outb(device, ATA_DEV_HD, ATA_LBA |
920 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
921 ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
c40b2956 922 }
c609719b 923
34c202c7 924 udelay(50);
c609719b 925
34c202c7
WD
926 if (pwrsave) {
927 /* may take up to 4 sec */
928 c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
929 pwrsave = 0;
c609719b 930 } else {
34c202c7
WD
931 /* can't take over 500 ms */
932 c = ide_wait(device, IDE_TIME_OUT);
c609719b
WD
933 }
934
34c202c7
WD
935 if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
936 ATA_STAT_DRQ) {
b6458d38 937 printf("Error (no IRQ) dev %d blk %ld: status %#02x\n",
c609719b
WD
938 device, blknr, c);
939 break;
940 }
941
f5b82c0f 942 ide_input_data(device, buffer, ATA_SECTORWORDS);
34c202c7 943 (void) ide_inb(device, ATA_STATUS); /* clear IRQ */
c609719b
WD
944
945 ++n;
946 ++blknr;
0b94504d 947 buffer += ATA_BLOCKSIZE;
c609719b
WD
948 }
949IDE_READ_E:
34c202c7 950 ide_led(DEVICE_LED(device), 0); /* LED off */
c609719b
WD
951 return (n);
952}
953
954/* ------------------------------------------------------------------------- */
955
956
b6458d38 957ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
c609719b
WD
958{
959 ulong n = 0;
960 unsigned char c;
34c202c7 961
42dfe7a1 962#ifdef CONFIG_LBA48
c40b2956
WD
963 unsigned char lba48 = 0;
964
413bf586 965 if (blknr & 0x0000fffff0000000ULL) {
c40b2956
WD
966 /* more than 28 bits used, use 48bit mode */
967 lba48 = 1;
968 }
969#endif
c609719b 970
34c202c7 971 ide_led(DEVICE_LED(device), 1); /* LED on */
c609719b
WD
972
973 /* Select device
974 */
34c202c7 975 ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
c609719b
WD
976
977 while (blkcnt-- > 0) {
978
34c202c7 979 c = ide_wait(device, IDE_TIME_OUT);
c609719b
WD
980
981 if (c & ATA_STAT_BUSY) {
34c202c7 982 printf("IDE read: device %d not ready\n", device);
c609719b
WD
983 goto WR_OUT;
984 }
42dfe7a1 985#ifdef CONFIG_LBA48
c40b2956
WD
986 if (lba48) {
987 /* write high bits */
34c202c7
WD
988 ide_outb(device, ATA_SECT_CNT, 0);
989 ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
6d0f6bcf 990#ifdef CONFIG_SYS_64BIT_LBA
34c202c7
WD
991 ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
992 ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
413bf586 993#else
34c202c7
WD
994 ide_outb(device, ATA_LBA_MID, 0);
995 ide_outb(device, ATA_LBA_HIGH, 0);
413bf586 996#endif
c40b2956
WD
997 }
998#endif
34c202c7
WD
999 ide_outb(device, ATA_SECT_CNT, 1);
1000 ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
1001 ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
1002 ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
c40b2956 1003
42dfe7a1 1004#ifdef CONFIG_LBA48
c40b2956 1005 if (lba48) {
34c202c7
WD
1006 ide_outb(device, ATA_DEV_HD,
1007 ATA_LBA | ATA_DEVICE(device));
1008 ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
c40b2956
WD
1009
1010 } else
1011#endif
1012 {
34c202c7
WD
1013 ide_outb(device, ATA_DEV_HD, ATA_LBA |
1014 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
1015 ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
c40b2956 1016 }
c609719b 1017
34c202c7 1018 udelay(50);
c609719b 1019
34c202c7
WD
1020 /* can't take over 500 ms */
1021 c = ide_wait(device, IDE_TIME_OUT);
c609719b 1022
34c202c7
WD
1023 if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
1024 ATA_STAT_DRQ) {
b6458d38 1025 printf("Error (no IRQ) dev %d blk %ld: status %#02x\n",
c609719b
WD
1026 device, blknr, c);
1027 goto WR_OUT;
1028 }
1029
f5b82c0f 1030 ide_output_data(device, buffer, ATA_SECTORWORDS);
34c202c7 1031 c = ide_inb(device, ATA_STATUS); /* clear IRQ */
c609719b
WD
1032 ++n;
1033 ++blknr;
0b94504d 1034 buffer += ATA_BLOCKSIZE;
c609719b
WD
1035 }
1036WR_OUT:
34c202c7 1037 ide_led(DEVICE_LED(device), 0); /* LED off */
c609719b
WD
1038 return (n);
1039}
1040
1041/* ------------------------------------------------------------------------- */
1042
1043/*
1044 * copy src to dest, skipping leading and trailing blanks and null
1045 * terminate the string
7d7ce412 1046 * "len" is the size of available memory including the terminating '\0'
c609719b 1047 */
34c202c7
WD
1048static void ident_cpy(unsigned char *dst, unsigned char *src,
1049 unsigned int len)
c609719b 1050{
7d7ce412
WD
1051 unsigned char *end, *last;
1052
1053 last = dst;
34c202c7 1054 end = src + len - 1;
7d7ce412
WD
1055
1056 /* reserve space for '\0' */
1057 if (len < 2)
1058 goto OUT;
efa329cb 1059
7d7ce412 1060 /* skip leading white space */
34c202c7 1061 while ((*src) && (src < end) && (*src == ' '))
7d7ce412
WD
1062 ++src;
1063
1064 /* copy string, omitting trailing white space */
34c202c7 1065 while ((*src) && (src < end)) {
7d7ce412
WD
1066 *dst++ = *src;
1067 if (*src++ != ' ')
1068 last = dst;
c609719b 1069 }
7d7ce412
WD
1070OUT:
1071 *last = '\0';
c609719b
WD
1072}
1073
1074/* ------------------------------------------------------------------------- */
1075
1076/*
1077 * Wait until Busy bit is off, or timeout (in ms)
1078 * Return last status
1079 */
34c202c7 1080static uchar ide_wait(int dev, ulong t)
c609719b 1081{
34c202c7 1082 ulong delay = 10 * t; /* poll every 100 us */
c609719b
WD
1083 uchar c;
1084
2262cfee 1085 while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
34c202c7
WD
1086 udelay(100);
1087 if (delay-- == 0)
c609719b 1088 break;
c609719b
WD
1089 }
1090 return (c);
1091}
1092
1093/* ------------------------------------------------------------------------- */
1094
1095#ifdef CONFIG_IDE_RESET
1096extern void ide_set_reset(int idereset);
1097
34c202c7 1098static void ide_reset(void)
c609719b 1099{
c609719b
WD
1100 int i;
1101
1102 curr_device = -1;
34c202c7 1103 for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
c609719b 1104 ide_bus_ok[i] = 0;
34c202c7 1105 for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
c609719b
WD
1106 ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
1107
34c202c7 1108 ide_set_reset(1); /* assert reset */
c609719b 1109
e175eacc
MK
1110 /* the reset signal shall be asserted for et least 25 us */
1111 udelay(25);
1112
c609719b
WD
1113 WATCHDOG_RESET();
1114
c609719b
WD
1115 /* de-assert RESET signal */
1116 ide_set_reset(0);
1117
1118 /* wait 250 ms */
34c202c7
WD
1119 for (i = 0; i < 250; ++i)
1120 udelay(1000);
c609719b
WD
1121}
1122
34c202c7 1123#endif /* CONFIG_IDE_RESET */
c609719b
WD
1124
1125/* ------------------------------------------------------------------------- */
1126
3887c3fb
HS
1127#if defined(CONFIG_OF_IDE_FIXUP)
1128int ide_device_present(int dev)
1129{
1130 if (dev >= CONFIG_SYS_IDE_MAXBUS)
1131 return 0;
1132 return (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1);
1133}
1134#endif
c609719b
WD
1135/* ------------------------------------------------------------------------- */
1136
1137#ifdef CONFIG_ATAPI
1138/****************************************************************************
1139 * ATAPI Support
1140 */
1141
f5b82c0f
PH
1142void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
1143 __attribute__ ((weak, alias("__ide_input_data_shorts")));
1144
1145void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
1146 __attribute__ ((weak, alias("__ide_output_data_shorts")));
1147
1148
f2a37fcd 1149#if defined(CONFIG_IDE_SWAP_IO)
c609719b
WD
1150/* since ATAPI may use commands with not 4 bytes alligned length
1151 * we have our own transfer functions, 2 bytes alligned */
f5b82c0f 1152void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
c609719b 1153{
34c202c7
WD
1154 ushort *dbuf;
1155 volatile ushort *pbuf;
c609719b 1156
34c202c7
WD
1157 pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
1158 dbuf = (ushort *) sect_buf;
db01a2ea 1159
34c202c7
WD
1160 debug("in output data shorts base for read is %lx\n",
1161 (unsigned long) pbuf);
db01a2ea 1162
c609719b 1163 while (shorts--) {
5cf91d6b 1164 EIEIO;
1a344f29 1165 *pbuf = *dbuf++;
c609719b 1166 }
1a344f29
WD
1167}
1168
f5b82c0f 1169void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
1a344f29 1170{
34c202c7
WD
1171 ushort *dbuf;
1172 volatile ushort *pbuf;
1a344f29 1173
34c202c7
WD
1174 pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
1175 dbuf = (ushort *) sect_buf;
1a344f29 1176
34c202c7
WD
1177 debug("in input data shorts base for read is %lx\n",
1178 (unsigned long) pbuf);
1a344f29
WD
1179
1180 while (shorts--) {
1181 EIEIO;
1182 *dbuf++ = *pbuf;
1183 }
c609719b
WD
1184}
1185
34c202c7 1186#else /* ! CONFIG_IDE_SWAP_IO */
f5b82c0f 1187void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
2262cfee 1188{
34c202c7 1189 outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
2262cfee
WD
1190}
1191
f5b82c0f 1192void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
2262cfee 1193{
34c202c7 1194 insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
2262cfee
WD
1195}
1196
34c202c7 1197#endif /* CONFIG_IDE_SWAP_IO */
2262cfee 1198
c609719b
WD
1199/*
1200 * Wait until (Status & mask) == res, or timeout (in ms)
1201 * Return last status
1202 * This is used since some ATAPI CD ROMs clears their Busy Bit first
1203 * and then they set their DRQ Bit
1204 */
34c202c7 1205static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
c609719b 1206{
34c202c7 1207 ulong delay = 10 * t; /* poll every 100 us */
c609719b
WD
1208 uchar c;
1209
34c202c7
WD
1210 /* prevents to read the status before valid */
1211 c = ide_inb(dev, ATA_DEV_CTL);
1212
2262cfee 1213 while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
c609719b 1214 /* break if error occurs (doesn't make sense to wait more) */
34c202c7 1215 if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
c609719b 1216 break;
34c202c7
WD
1217 udelay(100);
1218 if (delay-- == 0)
c609719b 1219 break;
c609719b
WD
1220 }
1221 return (c);
1222}
1223
1224/*
1225 * issue an atapi command
1226 */
34c202c7
WD
1227unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
1228 unsigned char *buffer, int buflen)
c609719b 1229{
34c202c7 1230 unsigned char c, err, mask, res;
c609719b 1231 int n;
34c202c7
WD
1232
1233 ide_led(DEVICE_LED(device), 1); /* LED on */
c609719b
WD
1234
1235 /* Select device
1236 */
34c202c7 1237 mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
c609719b 1238 res = 0;
34c202c7
WD
1239 ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
1240 c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
c609719b 1241 if ((c & mask) != res) {
34c202c7
WD
1242 printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
1243 c);
1244 err = 0xFF;
c609719b
WD
1245 goto AI_OUT;
1246 }
1247 /* write taskfile */
34c202c7
WD
1248 ide_outb(device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */
1249 ide_outb(device, ATA_SECT_CNT, 0);
1250 ide_outb(device, ATA_SECT_NUM, 0);
1251 ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
1252 ide_outb(device, ATA_CYL_HIGH,
1253 (unsigned char) ((buflen >> 8) & 0xFF));
1254 ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
1255
1256 ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
1257 udelay(50);
1258
1259 mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
c609719b 1260 res = ATA_STAT_DRQ;
34c202c7 1261 c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
c609719b 1262
34c202c7
WD
1263 if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */
1264 printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
1265 device, c);
1266 err = 0xFF;
c609719b
WD
1267 goto AI_OUT;
1268 }
1269
34c202c7 1270 /* write command block */
f5b82c0f 1271 ide_output_data_shorts(device, (unsigned short *) ccb, ccblen / 2);
34c202c7 1272
53677ef1 1273 /* ATAPI Command written wait for completition */
34c202c7 1274 udelay(5000); /* device must set bsy */
c609719b 1275
34c202c7
WD
1276 mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
1277 /*
1278 * if no data wait for DRQ = 0 BSY = 0
1279 * if data wait for DRQ = 1 BSY = 0
1280 */
1281 res = 0;
1282 if (buflen)
c609719b 1283 res = ATA_STAT_DRQ;
34c202c7
WD
1284 c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
1285 if ((c & mask) != res) {
c609719b 1286 if (c & ATA_STAT_ERR) {
34c202c7
WD
1287 err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
1288 debug("atapi_issue 1 returned sense key %X status %02X\n",
1289 err, c);
c609719b 1290 } else {
34c202c7
WD
1291 printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n",
1292 ccb[0], c);
1293 err = 0xFF;
c609719b
WD
1294 }
1295 goto AI_OUT;
1296 }
34c202c7
WD
1297 n = ide_inb(device, ATA_CYL_HIGH);
1298 n <<= 8;
1299 n += ide_inb(device, ATA_CYL_LOW);
1300 if (n > buflen) {
1301 printf("ERROR, transfer bytes %d requested only %d\n", n,
1302 buflen);
1303 err = 0xff;
c609719b
WD
1304 goto AI_OUT;
1305 }
34c202c7
WD
1306 if ((n == 0) && (buflen < 0)) {
1307 printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
1308 err = 0xff;
c609719b
WD
1309 goto AI_OUT;
1310 }
34c202c7
WD
1311 if (n != buflen) {
1312 debug("WARNING, transfer bytes %d not equal with requested %d\n",
1313 n, buflen);
c609719b 1314 }
34c202c7
WD
1315 if (n != 0) { /* data transfer */
1316 debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
1317 /* we transfer shorts */
1318 n >>= 1;
c609719b 1319 /* ok now decide if it is an in or output */
34c202c7
WD
1320 if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
1321 debug("Write to device\n");
f5b82c0f
PH
1322 ide_output_data_shorts(device,
1323 (unsigned short *) buffer, n);
c609719b 1324 } else {
34c202c7 1325 debug("Read from device @ %p shorts %d\n", buffer, n);
f5b82c0f
PH
1326 ide_input_data_shorts(device,
1327 (unsigned short *) buffer, n);
c609719b
WD
1328 }
1329 }
34c202c7
WD
1330 udelay(5000); /* seems that some CD ROMs need this... */
1331 mask = ATA_STAT_BUSY | ATA_STAT_ERR;
1332 res = 0;
1333 c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
c609719b 1334 if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
34c202c7
WD
1335 err = (ide_inb(device, ATA_ERROR_REG) >> 4);
1336 debug("atapi_issue 2 returned sense key %X status %X\n", err,
1337 c);
c609719b
WD
1338 } else {
1339 err = 0;
1340 }
1341AI_OUT:
34c202c7 1342 ide_led(DEVICE_LED(device), 0); /* LED off */
c609719b
WD
1343 return (err);
1344}
1345
1346/*
1347 * sending the command to atapi_issue. If an status other than good
1348 * returns, an request_sense will be issued
1349 */
1350
53677ef1 1351#define ATAPI_DRIVE_NOT_READY 100
c609719b
WD
1352#define ATAPI_UNIT_ATTN 10
1353
34c202c7
WD
1354unsigned char atapi_issue_autoreq(int device,
1355 unsigned char *ccb,
1356 int ccblen,
1357 unsigned char *buffer, int buflen)
c609719b 1358{
34c202c7
WD
1359 unsigned char sense_data[18], sense_ccb[12];
1360 unsigned char res, key, asc, ascq;
1361 int notready, unitattn;
c609719b 1362
34c202c7
WD
1363 unitattn = ATAPI_UNIT_ATTN;
1364 notready = ATAPI_DRIVE_NOT_READY;
c609719b
WD
1365
1366retry:
34c202c7
WD
1367 res = atapi_issue(device, ccb, ccblen, buffer, buflen);
1368 if (res == 0)
1369 return 0; /* Ok */
1370
1371 if (res == 0xFF)
1372 return 0xFF; /* error */
1373
1374 debug("(auto_req)atapi_issue returned sense key %X\n", res);
1375
1376 memset(sense_ccb, 0, sizeof(sense_ccb));
1377 memset(sense_data, 0, sizeof(sense_data));
1378 sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
1379 sense_ccb[4] = 18; /* allocation Length */
1380
1381 res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
1382 key = (sense_data[2] & 0xF);
1383 asc = (sense_data[12]);
1384 ascq = (sense_data[13]);
1385
1386 debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
1387 debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
1388 sense_data[0], key, asc, ascq);
1389
1390 if ((key == 0))
1391 return 0; /* ok device ready */
1392
1393 if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
1394 if (unitattn-- > 0) {
1395 udelay(200 * 1000);
c609719b
WD
1396 goto retry;
1397 }
34c202c7 1398 printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
c609719b
WD
1399 goto error;
1400 }
34c202c7
WD
1401 if ((asc == 0x4) && (ascq == 0x1)) {
1402 /* not ready, but will be ready soon */
1403 if (notready-- > 0) {
1404 udelay(200 * 1000);
c609719b
WD
1405 goto retry;
1406 }
34c202c7
WD
1407 printf("Drive not ready, tried %d times\n",
1408 ATAPI_DRIVE_NOT_READY);
c609719b
WD
1409 goto error;
1410 }
34c202c7
WD
1411 if (asc == 0x3a) {
1412 debug("Media not present\n");
c609719b
WD
1413 goto error;
1414 }
c7de829c 1415
34c202c7
WD
1416 printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
1417 ascq);
c609719b 1418error:
34c202c7 1419 debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
c609719b
WD
1420 return (0xFF);
1421}
1422
1423
34c202c7 1424static void atapi_inquiry(block_dev_desc_t *dev_desc)
c609719b 1425{
34c202c7
WD
1426 unsigned char ccb[12]; /* Command descriptor block */
1427 unsigned char iobuf[64]; /* temp buf */
c609719b
WD
1428 unsigned char c;
1429 int device;
1430
34c202c7
WD
1431 device = dev_desc->dev;
1432 dev_desc->type = DEV_TYPE_UNKNOWN; /* not yet valid */
1433 dev_desc->block_read = atapi_read;
c609719b 1434
34c202c7
WD
1435 memset(ccb, 0, sizeof(ccb));
1436 memset(iobuf, 0, sizeof(iobuf));
c609719b 1437
34c202c7
WD
1438 ccb[0] = ATAPI_CMD_INQUIRY;
1439 ccb[4] = 40; /* allocation Legnth */
1440 c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 40);
c609719b 1441
34c202c7
WD
1442 debug("ATAPI_CMD_INQUIRY returned %x\n", c);
1443 if (c != 0)
c609719b
WD
1444 return;
1445
1446 /* copy device ident strings */
34c202c7
WD
1447 ident_cpy((unsigned char *) dev_desc->vendor, &iobuf[8], 8);
1448 ident_cpy((unsigned char *) dev_desc->product, &iobuf[16], 16);
1449 ident_cpy((unsigned char *) dev_desc->revision, &iobuf[32], 5);
c609719b 1450
34c202c7
WD
1451 dev_desc->lun = 0;
1452 dev_desc->lba = 0;
1453 dev_desc->blksz = 0;
0472fbfd 1454 dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
34c202c7 1455 dev_desc->type = iobuf[0] & 0x1f;
c609719b 1456
34c202c7 1457 if ((iobuf[1] & 0x80) == 0x80)
c609719b
WD
1458 dev_desc->removable = 1;
1459 else
1460 dev_desc->removable = 0;
1461
34c202c7
WD
1462 memset(ccb, 0, sizeof(ccb));
1463 memset(iobuf, 0, sizeof(iobuf));
1464 ccb[0] = ATAPI_CMD_START_STOP;
1465 ccb[4] = 0x03; /* start */
c609719b 1466
34c202c7 1467 c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 0);
c609719b 1468
34c202c7
WD
1469 debug("ATAPI_CMD_START_STOP returned %x\n", c);
1470 if (c != 0)
c609719b
WD
1471 return;
1472
34c202c7
WD
1473 memset(ccb, 0, sizeof(ccb));
1474 memset(iobuf, 0, sizeof(iobuf));
1475 c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 0);
c609719b 1476
34c202c7
WD
1477 debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
1478 if (c != 0)
c609719b
WD
1479 return;
1480
34c202c7
WD
1481 memset(ccb, 0, sizeof(ccb));
1482 memset(iobuf, 0, sizeof(iobuf));
1483 ccb[0] = ATAPI_CMD_READ_CAP;
1484 c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 8);
1485 debug("ATAPI_CMD_READ_CAP returned %x\n", c);
1486 if (c != 0)
c609719b
WD
1487 return;
1488
34c202c7
WD
1489 debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
1490 iobuf[0], iobuf[1], iobuf[2], iobuf[3],
1491 iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
1492
1493 dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
1494 ((unsigned long) iobuf[1] << 16) +
1495 ((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
1496 dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
1497 ((unsigned long) iobuf[5] << 16) +
1498 ((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
0472fbfd 1499 dev_desc->log2blksz = LOG2(dev_desc->blksz);
42dfe7a1 1500#ifdef CONFIG_LBA48
34c202c7
WD
1501 /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
1502 dev_desc->lba48 = 0;
42dfe7a1 1503#endif
c609719b
WD
1504 return;
1505}
1506
1507
1508/*
1509 * atapi_read:
1510 * we transfer only one block per command, since the multiple DRQ per
1511 * command is not yet implemented
1512 */
1513#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */
1514#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
34c202c7 1515#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
c609719b 1516
b6458d38 1517ulong atapi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
c609719b
WD
1518{
1519 ulong n = 0;
34c202c7 1520 unsigned char ccb[12]; /* Command descriptor block */
c609719b
WD
1521 ulong cnt;
1522
b6458d38 1523 debug("atapi_read dev %d start %lX, blocks " LBAF " buffer at %lX\n",
34c202c7 1524 device, blknr, blkcnt, (ulong) buffer);
c609719b
WD
1525
1526 do {
34c202c7
WD
1527 if (blkcnt > ATAPI_READ_MAX_BLOCK)
1528 cnt = ATAPI_READ_MAX_BLOCK;
1529 else
1530 cnt = blkcnt;
1531
1532 ccb[0] = ATAPI_CMD_READ_12;
1533 ccb[1] = 0; /* reserved */
1534 ccb[2] = (unsigned char) (blknr >> 24) & 0xFF; /* MSB Block */
1535 ccb[3] = (unsigned char) (blknr >> 16) & 0xFF; /* */
1536 ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
1537 ccb[5] = (unsigned char) blknr & 0xFF; /* LSB Block */
1538 ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
1539 ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
1540 ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
1541 ccb[9] = (unsigned char) cnt & 0xFF; /* LSB Block */
1542 ccb[10] = 0; /* reserved */
1543 ccb[11] = 0; /* reserved */
1544
1545 if (atapi_issue_autoreq(device, ccb, 12,
1546 (unsigned char *) buffer,
1547 cnt * ATAPI_READ_BLOCK_SIZE)
1548 == 0xFF) {
c609719b
WD
1549 return (n);
1550 }
34c202c7
WD
1551 n += cnt;
1552 blkcnt -= cnt;
1553 blknr += cnt;
1554 buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
c609719b
WD
1555 } while (blkcnt > 0);
1556 return (n);
1557}
1558
1559/* ------------------------------------------------------------------------- */
1560
1561#endif /* CONFIG_ATAPI */
1562
34c202c7
WD
1563U_BOOT_CMD(ide, 5, 1, do_ide,
1564 "IDE sub-system",
1565 "reset - reset IDE controller\n"
1566 "ide info - show available IDE devices\n"
1567 "ide device [dev] - show or set current device\n"
1568 "ide part [dev] - print partition table of one or all IDE devices\n"
1569 "ide read addr blk# cnt\n"
1570 "ide write addr blk# cnt - read/write `cnt'"
1571 " blocks starting at block `blk#'\n"
1572 " to/from memory address `addr'");
1573
1574U_BOOT_CMD(diskboot, 3, 1, do_diskboot,
1575 "boot from IDE device", "loadAddr dev:part");