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Add support for AMCC 440SPe CPU based eval board (Yucca).
[people/ms/u-boot.git] / cpu / ppc4xx / serial.c
CommitLineData
fe8c2806
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23/*------------------------------------------------------------------------------+ */
24/*
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
31 *
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
35 *
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
39 *
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
42 */
43/*------------------------------------------------------------------------------- */
ff36fd85
WD		 44/*
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
47 */
fe8c2806
WD		 48#include <common.h>
49#include <commproc.h>
50#include <asm/processor.h>
51#include <watchdog.h>
52#include "vecnum.h"
53
ff36fd85
WD		 54#ifdef CONFIG_SERIAL_MULTI
55#include <serial.h>
56#endif
57
42dfe7a1 58#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 59#include <malloc.h>
60#endif
61
62/*****************************************************************************/
63#ifdef CONFIG_IOP480
64
65#define SPU_BASE 0x40000000
66
67#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
68#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
69#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
70#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
71#define spu_BRateDivh 0x10 /* Baud rate divisor high */
72#define spu_BRateDivl 0x14 /* Baud rate divisor low */
73#define spu_CtlReg 0x18 /* Control Register */
74#define spu_RxCmd 0x1c /* Rx Command Register */
75#define spu_TxCmd 0x20 /* Tx Command Register */
76#define spu_RxBuff 0x24 /* Rx data buffer */
77#define spu_TxBuff 0x24 /* Tx data buffer */
78
79/*-----------------------------------------------------------------------------+
80 | Line Status Register.
81 +-----------------------------------------------------------------------------*/
82#define asyncLSRport1 0x40000000
83#define asyncLSRport1set 0x40000004
84#define asyncLSRDataReady 0x80
85#define asyncLSRFramingError 0x40
86#define asyncLSROverrunError 0x20
87#define asyncLSRParityError 0x10
88#define asyncLSRBreakInterrupt 0x08
89#define asyncLSRTxHoldEmpty 0x04
90#define asyncLSRTxShiftEmpty 0x02
91
92/*-----------------------------------------------------------------------------+
93 | Handshake Status Register.
94 +-----------------------------------------------------------------------------*/
95#define asyncHSRport1 0x40000008
96#define asyncHSRport1set 0x4000000c
97#define asyncHSRDsr 0x80
98#define asyncLSRCts 0x40
99
100/*-----------------------------------------------------------------------------+
101 | Control Register.
102 +-----------------------------------------------------------------------------*/
103#define asyncCRport1 0x40000018
104#define asyncCRNormal 0x00
105#define asyncCRLoopback 0x40
106#define asyncCRAutoEcho 0x80
107#define asyncCRDtr 0x20
108#define asyncCRRts 0x10
109#define asyncCRWordLength7 0x00
110#define asyncCRWordLength8 0x08
111#define asyncCRParityDisable 0x00
112#define asyncCRParityEnable 0x04
113#define asyncCREvenParity 0x00
114#define asyncCROddParity 0x02
115#define asyncCRStopBitsOne 0x00
116#define asyncCRStopBitsTwo 0x01
117#define asyncCRDisableDtrRts 0x00
118
119/*-----------------------------------------------------------------------------+
120 | Receiver Command Register.
121 +-----------------------------------------------------------------------------*/
122#define asyncRCRport1 0x4000001c
123#define asyncRCRDisable 0x00
124#define asyncRCREnable 0x80
125#define asyncRCRIntDisable 0x00
126#define asyncRCRIntEnabled 0x20
127#define asyncRCRDMACh2 0x40
128#define asyncRCRDMACh3 0x60
129#define asyncRCRErrorInt 0x10
130#define asyncRCRPauseEnable 0x08
131
132/*-----------------------------------------------------------------------------+
133 | Transmitter Command Register.
134 +-----------------------------------------------------------------------------*/
135#define asyncTCRport1 0x40000020
136#define asyncTCRDisable 0x00
137#define asyncTCREnable 0x80
138#define asyncTCRIntDisable 0x00
139#define asyncTCRIntEnabled 0x20
140#define asyncTCRDMACh2 0x40
141#define asyncTCRDMACh3 0x60
142#define asyncTCRTxEmpty 0x10
143#define asyncTCRErrorInt 0x08
144#define asyncTCRStopPause 0x04
145#define asyncTCRBreakGen 0x02
146
147/*-----------------------------------------------------------------------------+
148 | Miscellanies defines.
149 +-----------------------------------------------------------------------------*/
150#define asyncTxBufferport1 0x40000024
151#define asyncRxBufferport1 0x40000024
152#define asyncDLABLsbport1 0x40000014
153#define asyncDLABMsbport1 0x40000010
154#define asyncXOFFchar 0x13
155#define asyncXONchar 0x11
156
fe8c2806
WD		 157/*
158 * Minimal serial functions needed to use one of the SMC ports
159 * as serial console interface.
160 */
161
162int serial_init (void)
163{
164 DECLARE_GLOBAL_DATA_PTR;
165
166 volatile char val;
167 unsigned short br_reg;
168
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
170
171 /*
172 * Init onboard UART
173 */
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
182
183 return (0);
184}
185
fe8c2806
WD		 186void serial_setbrg (void)
187{
188 DECLARE_GLOBAL_DATA_PTR;
189
190 unsigned short br_reg;
191
192 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
193
194 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
195 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
196}
197
fe8c2806
WD		 198void serial_putc (const char c)
199{
200 if (c == '\n')
201 serial_putc ('\r');
202
203 /* load status from handshake register */
204 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
205 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
206
207 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
208
209 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
210 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
211 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
212 }
213}
214
fe8c2806
WD		 215void serial_puts (const char *s)
216{
217 while (*s) {
218 serial_putc (*s++);
219 }
220}
221
fe8c2806
WD		 222int serial_getc ()
223{
224 unsigned char status = 0;
225
226 while (1) {
227 status = in8 (asyncLSRport1);
228 if ((status & asyncLSRDataReady) != 0x0) {
229 break;
230 }
231 if ((status & ( asyncLSRFramingError |
232 asyncLSROverrunError |
233 asyncLSRParityError |
234 asyncLSRBreakInterrupt )) != 0) {
235 (void) out8 (asyncLSRport1,
236 asyncLSRFramingError |
237 asyncLSROverrunError |
238 asyncLSRParityError |
239 asyncLSRBreakInterrupt );
240 }
241 }
242 return (0x000000ff & (int) in8 (asyncRxBufferport1));
243}
244
fe8c2806
WD		 245int serial_tstc ()
246{
247 unsigned char status;
248
249 status = in8 (asyncLSRport1);
250 if ((status & asyncLSRDataReady) != 0x0) {
251 return (1);
252 }
253 if ((status & ( asyncLSRFramingError |
254 asyncLSROverrunError |
255 asyncLSRParityError |
256 asyncLSRBreakInterrupt )) != 0) {
257 (void) out8 (asyncLSRport1,
258 asyncLSRFramingError |
259 asyncLSROverrunError |
260 asyncLSRParityError |
261 asyncLSRBreakInterrupt);
262 }
263 return 0;
264}
265
266#endif /* CONFIG_IOP480 */
267
fe8c2806 268/*****************************************************************************/
8749cfb4 269#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
fe8c2806
WD		 270
271#if defined(CONFIG_440)
846b0dd2 272#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
c157d8e2
SR		 273#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
274#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
275#else
fe8c2806
WD		 276#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
277#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
c157d8e2 278#endif
6e7fb6ea 279
6c5879f3 280#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
6e7fb6ea
SR		 281#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
282#endif
283
6c5879f3 284#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
ba56f625
WD		 285#define CR0_MASK 0xdfffffff
286#define CR0_EXTCLK_ENA 0x00800000
287#define CR0_UDIV_POS 0
288#else
fe8c2806
WD		 289#define CR0_MASK 0x3fff0000
290#define CR0_EXTCLK_ENA 0x00600000
291#define CR0_UDIV_POS 16
846b0dd2 292#endif /* CONFIG_440GX */
8749cfb4
SR		 293#elif defined(CONFIG_405EP)
294#define UART0_BASE 0xef600300
295#define UART1_BASE 0xef600400
296#define UCR0_MASK 0x0000007f
297#define UCR1_MASK 0x00007f00
298#define UCR0_UDIV_POS 0
299#define UCR1_UDIV_POS 8
300#define UDIV_MAX 127
301#else /* CONFIG_405GP || CONFIG_405CR */
fe8c2806
WD		 302#define UART0_BASE 0xef600300
303#define UART1_BASE 0xef600400
304#define CR0_MASK 0x00001fff
d7787c6e 305#define CR0_EXTCLK_ENA 0x000000c0
fe8c2806 306#define CR0_UDIV_POS 1
8749cfb4
SR		 307#define UDIV_MAX 32
308#endif
309
310/* using serial port 0 or 1 as U-Boot console ? */
311#if defined(CONFIG_UART1_CONSOLE)
312#define ACTING_UART0_BASE UART1_BASE
313#define ACTING_UART1_BASE UART0_BASE
6c5879f3
MB		 314#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
315 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
316 defined(CONFIG_440SPE)
ba56f625
WD		 317#define UART0_SDR sdr_uart1
318#define UART1_SDR sdr_uart0
846b0dd2 319#endif /* CONFIG_440GX */
8749cfb4
SR		 320#else
321#define ACTING_UART0_BASE UART0_BASE
322#define ACTING_UART1_BASE UART1_BASE
6c5879f3
MB		 323#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
324 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
325 defined(CONFIG_440SPE)
ba56f625
WD		 326#define UART0_SDR sdr_uart0
327#define UART1_SDR sdr_uart1
846b0dd2 328#endif /* CONFIG_440GX */
8749cfb4
SR		 329#endif
330
331#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
0c8721a4 332#error "External serial clock not supported on AMCC PPC405EP!"
fe8c2806
WD		 333#endif
334
335#define UART_RBR 0x00
336#define UART_THR 0x00
337#define UART_IER 0x01
338#define UART_IIR 0x02
339#define UART_FCR 0x02
340#define UART_LCR 0x03
341#define UART_MCR 0x04
342#define UART_LSR 0x05
343#define UART_MSR 0x06
344#define UART_SCR 0x07
345#define UART_DLL 0x00
346#define UART_DLM 0x01
347
348/*-----------------------------------------------------------------------------+
349 | Line Status Register.
350 +-----------------------------------------------------------------------------*/
8749cfb4 351/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
fe8c2806
WD		 352#define asyncLSRDataReady1 0x01
353#define asyncLSROverrunError1 0x02
354#define asyncLSRParityError1 0x04
355#define asyncLSRFramingError1 0x08
356#define asyncLSRBreakInterrupt1 0x10
357#define asyncLSRTxHoldEmpty1 0x20
358#define asyncLSRTxShiftEmpty1 0x40
359#define asyncLSRRxFifoError1 0x80
360
361/*-----------------------------------------------------------------------------+
362 | Miscellanies defines.
363 +-----------------------------------------------------------------------------*/
8749cfb4
SR		 364/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
365/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
fe8c2806 366
42dfe7a1 367#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 368/*-----------------------------------------------------------------------------+
369 | Fifo
370 +-----------------------------------------------------------------------------*/
371typedef struct {
372 char *rx_buffer;
373 ulong rx_put;
374 ulong rx_get;
375} serial_buffer_t;
376
377volatile static serial_buffer_t buf_info;
378#endif
379
fe8c2806
WD		 380#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
381static void serial_divs (int baudrate, unsigned long *pudiv,
382 unsigned short *pbdiv )
383{
384 sys_info_t sysinfo;
385 unsigned long div; /* total divisor udiv * bdiv */
386 unsigned long umin; /* minimum udiv */
387 unsigned short diff; /* smallest diff */
388 unsigned long udiv; /* best udiv */
389
390 unsigned short idiff; /* current diff */
391 unsigned short ibdiv; /* current bdiv */
392 unsigned long i;
393 unsigned long est; /* current estimate */
394
395 get_sys_info( &sysinfo );
396
397 udiv = 32; /* Assume lowest possible serial clk */
398 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
399 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
400 diff = 32; /* highest possible */
401
402 /* i is the test udiv value -- start with the largest
403 * possible (32) to minimize serial clock and constrain
404 * search to umin.
405 */
406 for( i = 32; i > umin; i-- ){
407 ibdiv = div/i;
408 est = i * ibdiv;
409 idiff = (est > div) ? (est-div) : (div-est);
410 if( idiff == 0 ){
411 udiv = i;
412 break; /* can't do better */
413 }
414 else if( idiff < diff ){
415 udiv = i; /* best so far */
416 diff = idiff; /* update lowest diff*/
417 }
418 }
419
420 *pudiv = udiv;
421 *pbdiv = div/udiv;
422
423}
424#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
425
fe8c2806
WD		 426/*
427 * Minimal serial functions needed to use one of the SMC ports
428 * as serial console interface.
429 */
430
431#if defined(CONFIG_440)
ff36fd85
WD		 432#if defined(CONFIG_SERIAL_MULTI)
433int serial_init_dev (unsigned long dev_base)
434#else
435int serial_init(void)
436#endif
fe8c2806
WD		 437{
438 DECLARE_GLOBAL_DATA_PTR;
439
440 unsigned long reg;
441 unsigned long udiv;
442 unsigned short bdiv;
443 volatile char val;
444#ifdef CFG_EXT_SERIAL_CLOCK
445 unsigned long tmp;
446#endif
447
6c5879f3
MB		 448#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
449 defined(CONFIG_440SPE)
ff36fd85
WD		 450#if defined(CONFIG_SERIAL_MULTI)
451 if (UART0_BASE == dev_base) {
452 mfsdr(UART0_SDR,reg);
453 reg &= ~CR0_MASK;
454 } else {
455 mfsdr(UART1_SDR,reg);
456 reg &= ~CR0_MASK;
457 }
458#else
ba56f625
WD		 459 mfsdr(UART0_SDR,reg);
460 reg &= ~CR0_MASK;
ff36fd85 461#endif
ba56f625 462#else
fe8c2806 463 reg = mfdcr(cntrl0) & ~CR0_MASK;
846b0dd2 464#endif /* CONFIG_440GX */
fe8c2806
WD		 465#ifdef CFG_EXT_SERIAL_CLOCK
466 reg |= CR0_EXTCLK_ENA;
467 udiv = 1;
468 tmp = gd->baudrate * 16;
469 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
470#else
471 /* For 440, the cpu clock is on divider chain A, UART on divider
472 * chain B ... so cpu clock is irrelevant. Get the "optimized"
473 * values that are subject to the 1/2 opb clock constraint
474 */
475 serial_divs (gd->baudrate, &udiv, &bdiv);
476#endif
477
6c5879f3
MB		 478#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
479 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
480 defined(CONFIG_440SPE)
ba56f625 481 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
ff36fd85
WD		 482#if defined(CONFIG_SERIAL_MULTI)
483 if (UART0_BASE == dev_base) {
484 mtsdr (UART0_SDR,reg);
485 } else {
486 mtsdr (UART1_SDR,reg);
487 }
488#else
ba56f625 489 mtsdr (UART0_SDR,reg);
ff36fd85 490#endif
ba56f625 491#else
fe8c2806
WD		 492 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
493 mtdcr (cntrl0, reg);
ba56f625 494#endif
ff36fd85
WD		 495
496#if defined(CONFIG_SERIAL_MULTI)
497 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
498 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
499 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
500 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
501 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
502 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
503 val = in8 (dev_base + UART_LSR); /* clear line status */
504 val = in8 (dev_base + UART_RBR); /* read receive buffer */
505 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
506 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
507#else
8749cfb4
SR		 508 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
509 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
510 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
511 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
512 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
513 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
514 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
515 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
516 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
517 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
ff36fd85 518#endif
fe8c2806
WD		 519 return (0);
520}
521
522#else /* !defined(CONFIG_440) */
523
ff36fd85
WD		 524#if defined(CONFIG_SERIAL_MULTI)
525int serial_init_dev (unsigned long dev_base)
526#else
fe8c2806 527int serial_init (void)
ff36fd85 528#endif
fe8c2806
WD		 529{
530 DECLARE_GLOBAL_DATA_PTR;
531
532 unsigned long reg;
533 unsigned long tmp;
534 unsigned long clk;
535 unsigned long udiv;
536 unsigned short bdiv;
537 volatile char val;
538
8749cfb4
SR		 539#ifdef CONFIG_405EP
540 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
541 clk = gd->cpu_clk;
542 tmp = CFG_BASE_BAUD * 16;
543 udiv = (clk + tmp / 2) / tmp;
544 if (udiv > UDIV_MAX) /* max. n bits for udiv */
545 udiv = UDIV_MAX;
546 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
547 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
548 mtdcr (cpc0_ucr, reg);
549#else /* CONFIG_405EP */
fe8c2806
WD		 550 reg = mfdcr(cntrl0) & ~CR0_MASK;
551#ifdef CFG_EXT_SERIAL_CLOCK
552 clk = CFG_EXT_SERIAL_CLOCK;
553 udiv = 1;
554 reg |= CR0_EXTCLK_ENA;
555#else
556 clk = gd->cpu_clk;
557#ifdef CFG_405_UART_ERRATA_59
558 udiv = 31; /* Errata 59: stuck at 31 */
559#else
560 tmp = CFG_BASE_BAUD * 16;
561 udiv = (clk + tmp / 2) / tmp;
8749cfb4
SR		 562 if (udiv > UDIV_MAX) /* max. n bits for udiv */
563 udiv = UDIV_MAX;
fe8c2806
WD		 564#endif
565#endif
fe8c2806
WD		 566 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
567 mtdcr (cntrl0, reg);
8749cfb4 568#endif /* CONFIG_405EP */
fe8c2806
WD		 569
570 tmp = gd->baudrate * udiv * 16;
571 bdiv = (clk + tmp / 2) / tmp;
572
ff36fd85
WD		 573#if defined(CONFIG_SERIAL_MULTI)
574 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
575 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
576 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
577 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
578 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
579 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
580 val = in8 (dev_base + UART_LSR); /* clear line status */
581 val = in8 (dev_base + UART_RBR); /* read receive buffer */
582 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
583 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
584#else
8749cfb4
SR		 585 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
586 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
587 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
588 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
589 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
590 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
591 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
592 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
593 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
594 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
ff36fd85 595#endif
fe8c2806
WD		 596 return (0);
597}
598
599#endif /* if defined(CONFIG_440) */
600
ff36fd85
WD		 601#if defined(CONFIG_SERIAL_MULTI)
602void serial_setbrg_dev (unsigned long dev_base)
603#else
fe8c2806 604void serial_setbrg (void)
ff36fd85 605#endif
fe8c2806
WD		 606{
607 DECLARE_GLOBAL_DATA_PTR;
608
609 unsigned long tmp;
610 unsigned long clk;
611 unsigned long udiv;
612 unsigned short bdiv;
613
614#ifdef CFG_EXT_SERIAL_CLOCK
615 clk = CFG_EXT_SERIAL_CLOCK;
616#else
617 clk = gd->cpu_clk;
618#endif
8749cfb4
SR		 619
620#ifdef CONFIG_405EP
621 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
622#else
fe8c2806 623 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
8749cfb4 624#endif /* CONFIG_405EP */
6c5879f3
MB		 625
626#if !defined(CFG_EXT_SERIAL_CLOCK) && \
627 ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
628 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
629 defined(CONFIG_440SPE) )
630 serial_divs (gd->baudrate, &udiv, &bdiv);
631 tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */
632#if defined(CONFIG_SERIAL_MULTI)
633 if (UART0_BASE == dev_base) {
634 mtsdr (UART0_SDR, tmp);
635 } else {
636 mtsdr (UART1_SDR, tmp);
637 }
638#else
639 mtsdr (UART0_SDR, tmp);
640#endif
641
642#else
643
fe8c2806
WD		 644 tmp = gd->baudrate * udiv * 16;
645 bdiv = (clk + tmp / 2) / tmp;
6c5879f3 646#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
fe8c2806 647
ff36fd85
WD		 648#if defined(CONFIG_SERIAL_MULTI)
649 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
650 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
651 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
652 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
653#else
8749cfb4
SR		 654 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
655 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
656 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
657 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
ff36fd85 658#endif
fe8c2806
WD		 659}
660
ff36fd85
WD		 661#if defined(CONFIG_SERIAL_MULTI)
662void serial_putc_dev (unsigned long dev_base, const char c)
663#else
fe8c2806 664void serial_putc (const char c)
ff36fd85 665#endif
fe8c2806
WD		 666{
667 int i;
668
669 if (c == '\n')
ff36fd85
WD		 670#if defined(CONFIG_SERIAL_MULTI)
671 serial_putc_dev (dev_base, '\r');
672#else
fe8c2806 673 serial_putc ('\r');
ff36fd85 674#endif
fe8c2806
WD		 675
676 /* check THRE bit, wait for transmiter available */
677 for (i = 1; i < 3500; i++) {
ff36fd85
WD		 678#if defined(CONFIG_SERIAL_MULTI)
679 if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
680#else
8749cfb4 681 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
ff36fd85 682#endif
fe8c2806
WD		 683 break;
684 udelay (100);
685 }
ff36fd85
WD		 686#if defined(CONFIG_SERIAL_MULTI)
687 out8 (dev_base + UART_THR, c); /* put character out */
688#else
8749cfb4 689 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
ff36fd85 690#endif
fe8c2806
WD		 691}
692
ff36fd85
WD		 693#if defined(CONFIG_SERIAL_MULTI)
694void serial_puts_dev (unsigned long dev_base, const char *s)
695#else
fe8c2806 696void serial_puts (const char *s)
ff36fd85 697#endif
fe8c2806
WD		 698{
699 while (*s) {
ff36fd85
WD		 700#if defined(CONFIG_SERIAL_MULTI)
701 serial_putc_dev (dev_base, *s++);
702#else
fe8c2806 703 serial_putc (*s++);
ff36fd85 704#endif
fe8c2806
WD		 705 }
706}
707
ff36fd85
WD		 708#if defined(CONFIG_SERIAL_MULTI)
709int serial_getc_dev (unsigned long dev_base)
710#else
711int serial_getc (void)
712#endif
fe8c2806
WD		 713{
714 unsigned char status = 0;
715
716 while (1) {
717#if defined(CONFIG_HW_WATCHDOG)
718 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
719#endif /* CONFIG_HW_WATCHDOG */
ff36fd85
WD		 720#if defined(CONFIG_SERIAL_MULTI)
721 status = in8 (dev_base + UART_LSR);
722#else
8749cfb4 723 status = in8 (ACTING_UART0_BASE + UART_LSR);
ff36fd85 724#endif
fe8c2806
WD		 725 if ((status & asyncLSRDataReady1) != 0x0) {
726 break;
727 }
728 if ((status & ( asyncLSRFramingError1 |
729 asyncLSROverrunError1 |
730 asyncLSRParityError1 |
731 asyncLSRBreakInterrupt1 )) != 0) {
ff36fd85
WD		 732#if defined(CONFIG_SERIAL_MULTI)
733 out8 (dev_base + UART_LSR,
734#else
8749cfb4 735 out8 (ACTING_UART0_BASE + UART_LSR,
ff36fd85 736#endif
fe8c2806
WD		 737 asyncLSRFramingError1 |
738 asyncLSROverrunError1 |
739 asyncLSRParityError1 |
740 asyncLSRBreakInterrupt1);
741 }
742 }
ff36fd85
WD		 743#if defined(CONFIG_SERIAL_MULTI)
744 return (0x000000ff & (int) in8 (dev_base));
745#else
8749cfb4 746 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
ff36fd85 747#endif
fe8c2806
WD		 748}
749
ff36fd85
WD		 750#if defined(CONFIG_SERIAL_MULTI)
751int serial_tstc_dev (unsigned long dev_base)
752#else
753int serial_tstc (void)
754#endif
fe8c2806
WD		 755{
756 unsigned char status;
757
ff36fd85
WD		 758#if defined(CONFIG_SERIAL_MULTI)
759 status = in8 (dev_base + UART_LSR);
760#else
8749cfb4 761 status = in8 (ACTING_UART0_BASE + UART_LSR);
ff36fd85 762#endif
fe8c2806
WD		 763 if ((status & asyncLSRDataReady1) != 0x0) {
764 return (1);
765 }
766 if ((status & ( asyncLSRFramingError1 |
767 asyncLSROverrunError1 |
768 asyncLSRParityError1 |
769 asyncLSRBreakInterrupt1 )) != 0) {
ff36fd85
WD		 770#if defined(CONFIG_SERIAL_MULTI)
771 out8 (dev_base + UART_LSR,
772#else
8749cfb4 773 out8 (ACTING_UART0_BASE + UART_LSR,
ff36fd85 774#endif
fe8c2806
WD		 775 asyncLSRFramingError1 |
776 asyncLSROverrunError1 |
777 asyncLSRParityError1 |
778 asyncLSRBreakInterrupt1);
779 }
780 return 0;
781}
782
42dfe7a1 783#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 784
785void serial_isr (void *arg)
786{
787 int space;
788 int c;
789 const int rx_get = buf_info.rx_get;
790 int rx_put = buf_info.rx_put;
791
792 if (rx_get <= rx_put) {
793 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
794 } else {
795 space = rx_get - rx_put;
796 }
ff36fd85
WD		 797 while (serial_tstc_dev (ACTING_UART0_BASE)) {
798 c = serial_getc_dev (ACTING_UART0_BASE);
fe8c2806
WD		 799 if (space) {
800 buf_info.rx_buffer[rx_put++] = c;
801 space--;
802 }
803 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
804 rx_put = 0;
805 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
806 /* Stop flow by setting RTS inactive */
8749cfb4
SR		 807 out8 (ACTING_UART0_BASE + UART_MCR,
808 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
fe8c2806
WD		 809 }
810 }
811 buf_info.rx_put = rx_put;
812}
813
814void serial_buffered_init (void)
815{
816 serial_puts ("Switching to interrupt driven serial input mode.\n");
817 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
818 buf_info.rx_put = 0;
819 buf_info.rx_get = 0;
820
8749cfb4 821 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
fe8c2806
WD		 822 serial_puts ("Check CTS signal present on serial port: OK.\n");
823 } else {
824 serial_puts ("WARNING: CTS signal not present on serial port.\n");
825 }
826
827 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
828 serial_isr /*interrupt_handler_t *handler */ ,
829 (void *) &buf_info /*void *arg */ );
830
831 /* Enable "RX Data Available" Interrupt on UART */
8749cfb4
SR		 832 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
833 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
fe8c2806 834 /* Set DTR active */
8749cfb4 835 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
fe8c2806 836 /* Start flow by setting RTS active */
8749cfb4 837 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806 838 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
8749cfb4 839 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
fe8c2806
WD		 840}
841
842void serial_buffered_putc (const char c)
843{
844 /* Wait for CTS */
845#if defined(CONFIG_HW_WATCHDOG)
8749cfb4 846 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
fe8c2806
WD		 847 WATCHDOG_RESET ();
848#else
8749cfb4 849 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
fe8c2806
WD		 850#endif
851 serial_putc (c);
852}
853
854void serial_buffered_puts (const char *s)
855{
856 serial_puts (s);
857}
858
859int serial_buffered_getc (void)
860{
861 int space;
862 int c;
863 int rx_get = buf_info.rx_get;
864 int rx_put;
865
866#if defined(CONFIG_HW_WATCHDOG)
867 while (rx_get == buf_info.rx_put)
868 WATCHDOG_RESET ();
869#else
870 while (rx_get == buf_info.rx_put);
871#endif
872 c = buf_info.rx_buffer[rx_get++];
873 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
874 rx_get = 0;
875 buf_info.rx_get = rx_get;
876
877 rx_put = buf_info.rx_put;
878 if (rx_get <= rx_put) {
879 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
880 } else {
881 space = rx_get - rx_put;
882 }
883 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
884 /* Start flow by setting RTS active */
8749cfb4 885 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806
WD		 886 }
887
888 return c;
889}
890
891int serial_buffered_tstc (void)
892{
893 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
894}
895
896#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
897
fe8c2806
WD		 898#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
899/*
900 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
901 number 0 or number 1
902 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
903 configuration has been already done
904 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
905 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
906*/
907#if (CONFIG_KGDB_SER_INDEX & 2)
908void kgdb_serial_init (void)
909{
910 DECLARE_GLOBAL_DATA_PTR;
911
912 volatile char val;
913 unsigned short br_reg;
914
915 get_clocks ();
916 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
917 5) / 10;
918 /*
919 * Init onboard 16550 UART
920 */
8749cfb4
SR		 921 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
922 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
923 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
924 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
925 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
926 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
927 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
928 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
929 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
930 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
fe8c2806
WD		 931}
932
fe8c2806
WD		 933void putDebugChar (const char c)
934{
935 if (c == '\n')
936 serial_putc ('\r');
937
8749cfb4 938 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
fe8c2806
WD		 939
940 /* check THRE bit, wait for transfer done */
8749cfb4 941 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
fe8c2806
WD		 942}
943
fe8c2806
WD		 944void putDebugStr (const char *s)
945{
946 while (*s) {
947 serial_putc (*s++);
948 }
949}
950
fe8c2806
WD		 951int getDebugChar (void)
952{
953 unsigned char status = 0;
954
955 while (1) {
8749cfb4 956 status = in8 (ACTING_UART1_BASE + UART_LSR);
fe8c2806
WD		 957 if ((status & asyncLSRDataReady1) != 0x0) {
958 break;
959 }
960 if ((status & ( asyncLSRFramingError1 |
961 asyncLSROverrunError1 |
962 asyncLSRParityError1 |
963 asyncLSRBreakInterrupt1 )) != 0) {
8749cfb4 964 out8 (ACTING_UART1_BASE + UART_LSR,
fe8c2806
WD		 965 asyncLSRFramingError1 |
966 asyncLSROverrunError1 |
967 asyncLSRParityError1 |
968 asyncLSRBreakInterrupt1);
969 }
970 }
8749cfb4 971 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
fe8c2806
WD		 972}
973
fe8c2806
WD		 974void kgdb_interruptible (int yes)
975{
976 return;
977}
978
979#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
980
981void kgdb_serial_init (void)
982{
983 serial_printf ("[on serial] ");
984}
985
986void putDebugChar (int c)
987{
988 serial_putc (c);
989}
990
991void putDebugStr (const char *str)
992{
993 serial_puts (str);
994}
995
996int getDebugChar (void)
997{
998 return serial_getc ();
999}
1000
1001void kgdb_interruptible (int yes)
1002{
1003 return;
1004}
1005#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
1006#endif /* CFG_CMD_KGDB */
1007
ff36fd85
WD		 1008
1009#if defined(CONFIG_SERIAL_MULTI)
1010int serial0_init(void)
1011{
1012 return (serial_init_dev(UART0_BASE));
1013}
1014
1015int serial1_init(void)
1016{
1017 return (serial_init_dev(UART1_BASE));
1018}
1019void serial0_setbrg (void)
1020{
1021 serial_setbrg_dev(UART0_BASE);
1022}
1023void serial1_setbrg (void)
1024{
1025 serial_setbrg_dev(UART1_BASE);
1026}
1027
1028void serial0_putc(const char c)
1029{
1030 serial_putc_dev(UART0_BASE,c);
1031}
1032
1033void serial1_putc(const char c)
1034{
1035 serial_putc_dev(UART1_BASE, c);
1036}
1037void serial0_puts(const char *s)
1038{
1039 serial_puts_dev(UART0_BASE, s);
1040}
1041
1042void serial1_puts(const char *s)
1043{
1044 serial_puts_dev(UART1_BASE, s);
1045}
1046
1047int serial0_getc(void)
1048{
1049 return(serial_getc_dev(UART0_BASE));
1050}
1051
1052int serial1_getc(void)
1053{
1054 return(serial_getc_dev(UART1_BASE));
1055}
1056int serial0_tstc(void)
1057{
1058 return (serial_tstc_dev(UART0_BASE));
1059}
1060
1061int serial1_tstc(void)
1062{
1063 return (serial_tstc_dev(UART1_BASE));
1064}
1065
1066struct serial_device serial0_device =
1067{
1068 "serial0",
1069 "UART0",
1070 serial0_init,
1071 serial0_setbrg,
1072 serial0_getc,
1073 serial0_tstc,
1074 serial0_putc,
1075 serial0_puts,
1076};
1077
1078struct serial_device serial1_device =
1079{
1080 "serial1",
1081 "UART1",
1082 serial1_init,
1083 serial1_setbrg,
1084 serial1_getc,
1085 serial1_tstc,
1086 serial1_putc,
1087 serial1_puts,
1088};
1089#endif /* CONFIG_SERIAL_MULTI */
1090
fe8c2806 1091#endif /* CONFIG_405GP || CONFIG_405CR */
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