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Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
[people/ms/u-boot.git] / cpu / ppc4xx / serial.c
CommitLineData
fe8c2806
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23/*------------------------------------------------------------------------------+ */
24/*
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
31 *
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
35 *
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
39 *
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
42 */
43/*------------------------------------------------------------------------------- */
ff36fd85
WD		 44/*
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
47 */
fe8c2806
WD		 48#include <common.h>
49#include <commproc.h>
50#include <asm/processor.h>
51#include <watchdog.h>
52#include "vecnum.h"
53
ff36fd85
WD		 54#ifdef CONFIG_SERIAL_MULTI
55#include <serial.h>
56#endif
57
42dfe7a1 58#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 59#include <malloc.h>
60#endif
61
62/*****************************************************************************/
63#ifdef CONFIG_IOP480
64
65#define SPU_BASE 0x40000000
66
67#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
68#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
69#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
70#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
71#define spu_BRateDivh 0x10 /* Baud rate divisor high */
72#define spu_BRateDivl 0x14 /* Baud rate divisor low */
73#define spu_CtlReg 0x18 /* Control Register */
74#define spu_RxCmd 0x1c /* Rx Command Register */
75#define spu_TxCmd 0x20 /* Tx Command Register */
76#define spu_RxBuff 0x24 /* Rx data buffer */
77#define spu_TxBuff 0x24 /* Tx data buffer */
78
79/*-----------------------------------------------------------------------------+
80 | Line Status Register.
81 +-----------------------------------------------------------------------------*/
82#define asyncLSRport1 0x40000000
83#define asyncLSRport1set 0x40000004
84#define asyncLSRDataReady 0x80
85#define asyncLSRFramingError 0x40
86#define asyncLSROverrunError 0x20
87#define asyncLSRParityError 0x10
88#define asyncLSRBreakInterrupt 0x08
89#define asyncLSRTxHoldEmpty 0x04
90#define asyncLSRTxShiftEmpty 0x02
91
92/*-----------------------------------------------------------------------------+
93 | Handshake Status Register.
94 +-----------------------------------------------------------------------------*/
95#define asyncHSRport1 0x40000008
96#define asyncHSRport1set 0x4000000c
97#define asyncHSRDsr 0x80
98#define asyncLSRCts 0x40
99
100/*-----------------------------------------------------------------------------+
101 | Control Register.
102 +-----------------------------------------------------------------------------*/
103#define asyncCRport1 0x40000018
104#define asyncCRNormal 0x00
105#define asyncCRLoopback 0x40
106#define asyncCRAutoEcho 0x80
107#define asyncCRDtr 0x20
108#define asyncCRRts 0x10
109#define asyncCRWordLength7 0x00
110#define asyncCRWordLength8 0x08
111#define asyncCRParityDisable 0x00
112#define asyncCRParityEnable 0x04
113#define asyncCREvenParity 0x00
114#define asyncCROddParity 0x02
115#define asyncCRStopBitsOne 0x00
116#define asyncCRStopBitsTwo 0x01
117#define asyncCRDisableDtrRts 0x00
118
119/*-----------------------------------------------------------------------------+
120 | Receiver Command Register.
121 +-----------------------------------------------------------------------------*/
122#define asyncRCRport1 0x4000001c
123#define asyncRCRDisable 0x00
124#define asyncRCREnable 0x80
125#define asyncRCRIntDisable 0x00
126#define asyncRCRIntEnabled 0x20
127#define asyncRCRDMACh2 0x40
128#define asyncRCRDMACh3 0x60
129#define asyncRCRErrorInt 0x10
130#define asyncRCRPauseEnable 0x08
131
132/*-----------------------------------------------------------------------------+
133 | Transmitter Command Register.
134 +-----------------------------------------------------------------------------*/
135#define asyncTCRport1 0x40000020
136#define asyncTCRDisable 0x00
137#define asyncTCREnable 0x80
138#define asyncTCRIntDisable 0x00
139#define asyncTCRIntEnabled 0x20
140#define asyncTCRDMACh2 0x40
141#define asyncTCRDMACh3 0x60
142#define asyncTCRTxEmpty 0x10
143#define asyncTCRErrorInt 0x08
144#define asyncTCRStopPause 0x04
145#define asyncTCRBreakGen 0x02
146
147/*-----------------------------------------------------------------------------+
148 | Miscellanies defines.
149 +-----------------------------------------------------------------------------*/
150#define asyncTxBufferport1 0x40000024
151#define asyncRxBufferport1 0x40000024
152#define asyncDLABLsbport1 0x40000014
153#define asyncDLABMsbport1 0x40000010
154#define asyncXOFFchar 0x13
155#define asyncXONchar 0x11
156
fe8c2806
WD		 157/*
158 * Minimal serial functions needed to use one of the SMC ports
159 * as serial console interface.
160 */
161
162int serial_init (void)
163{
164 DECLARE_GLOBAL_DATA_PTR;
165
166 volatile char val;
167 unsigned short br_reg;
168
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
170
171 /*
172 * Init onboard UART
173 */
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
182
183 return (0);
184}
185
fe8c2806
WD		 186void serial_setbrg (void)
187{
188 DECLARE_GLOBAL_DATA_PTR;
189
190 unsigned short br_reg;
191
192 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
193
194 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
195 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
196}
197
fe8c2806
WD		 198void serial_putc (const char c)
199{
200 if (c == '\n')
201 serial_putc ('\r');
202
203 /* load status from handshake register */
204 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
205 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
206
207 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
208
209 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
210 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
211 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
212 }
213}
214
fe8c2806
WD		 215void serial_puts (const char *s)
216{
217 while (*s) {
218 serial_putc (*s++);
219 }
220}
221
fe8c2806
WD		 222int serial_getc ()
223{
224 unsigned char status = 0;
225
226 while (1) {
227 status = in8 (asyncLSRport1);
228 if ((status & asyncLSRDataReady) != 0x0) {
229 break;
230 }
231 if ((status & ( asyncLSRFramingError |
232 asyncLSROverrunError |
233 asyncLSRParityError |
234 asyncLSRBreakInterrupt )) != 0) {
235 (void) out8 (asyncLSRport1,
236 asyncLSRFramingError |
237 asyncLSROverrunError |
238 asyncLSRParityError |
239 asyncLSRBreakInterrupt );
240 }
241 }
242 return (0x000000ff & (int) in8 (asyncRxBufferport1));
243}
244
fe8c2806
WD		 245int serial_tstc ()
246{
247 unsigned char status;
248
249 status = in8 (asyncLSRport1);
250 if ((status & asyncLSRDataReady) != 0x0) {
251 return (1);
252 }
253 if ((status & ( asyncLSRFramingError |
254 asyncLSROverrunError |
255 asyncLSRParityError |
256 asyncLSRBreakInterrupt )) != 0) {
257 (void) out8 (asyncLSRport1,
258 asyncLSRFramingError |
259 asyncLSROverrunError |
260 asyncLSRParityError |
261 asyncLSRBreakInterrupt);
262 }
263 return 0;
264}
265
266#endif /* CONFIG_IOP480 */
267
fe8c2806 268/*****************************************************************************/
8749cfb4 269#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
fe8c2806
WD		 270
271#if defined(CONFIG_440)
846b0dd2 272#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
c157d8e2
SR		 273#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
274#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
275#else
fe8c2806
WD		 276#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
277#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
c157d8e2 278#endif
6e7fb6ea
SR		 279
280#if defined(CONFIG_440SP)
281#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
282#endif
283
284#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
ba56f625
WD		 285#define CR0_MASK 0xdfffffff
286#define CR0_EXTCLK_ENA 0x00800000
287#define CR0_UDIV_POS 0
288#else
fe8c2806
WD		 289#define CR0_MASK 0x3fff0000
290#define CR0_EXTCLK_ENA 0x00600000
291#define CR0_UDIV_POS 16
846b0dd2 292#endif /* CONFIG_440GX */
8749cfb4
SR		 293#elif defined(CONFIG_405EP)
294#define UART0_BASE 0xef600300
295#define UART1_BASE 0xef600400
296#define UCR0_MASK 0x0000007f
297#define UCR1_MASK 0x00007f00
298#define UCR0_UDIV_POS 0
299#define UCR1_UDIV_POS 8
300#define UDIV_MAX 127
301#else /* CONFIG_405GP || CONFIG_405CR */
fe8c2806
WD		 302#define UART0_BASE 0xef600300
303#define UART1_BASE 0xef600400
304#define CR0_MASK 0x00001fff
d7787c6e 305#define CR0_EXTCLK_ENA 0x000000c0
fe8c2806 306#define CR0_UDIV_POS 1
8749cfb4
SR		 307#define UDIV_MAX 32
308#endif
309
310/* using serial port 0 or 1 as U-Boot console ? */
311#if defined(CONFIG_UART1_CONSOLE)
312#define ACTING_UART0_BASE UART1_BASE
313#define ACTING_UART1_BASE UART0_BASE
6e7fb6ea 314#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
ba56f625
WD		 315#define UART0_SDR sdr_uart1
316#define UART1_SDR sdr_uart0
846b0dd2 317#endif /* CONFIG_440GX */
8749cfb4
SR		 318#else
319#define ACTING_UART0_BASE UART0_BASE
320#define ACTING_UART1_BASE UART1_BASE
6e7fb6ea 321#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
ba56f625
WD		 322#define UART0_SDR sdr_uart0
323#define UART1_SDR sdr_uart1
846b0dd2 324#endif /* CONFIG_440GX */
8749cfb4
SR		 325#endif
326
327#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
0c8721a4 328#error "External serial clock not supported on AMCC PPC405EP!"
fe8c2806
WD		 329#endif
330
331#define UART_RBR 0x00
332#define UART_THR 0x00
333#define UART_IER 0x01
334#define UART_IIR 0x02
335#define UART_FCR 0x02
336#define UART_LCR 0x03
337#define UART_MCR 0x04
338#define UART_LSR 0x05
339#define UART_MSR 0x06
340#define UART_SCR 0x07
341#define UART_DLL 0x00
342#define UART_DLM 0x01
343
344/*-----------------------------------------------------------------------------+
345 | Line Status Register.
346 +-----------------------------------------------------------------------------*/
8749cfb4 347/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
fe8c2806
WD		 348#define asyncLSRDataReady1 0x01
349#define asyncLSROverrunError1 0x02
350#define asyncLSRParityError1 0x04
351#define asyncLSRFramingError1 0x08
352#define asyncLSRBreakInterrupt1 0x10
353#define asyncLSRTxHoldEmpty1 0x20
354#define asyncLSRTxShiftEmpty1 0x40
355#define asyncLSRRxFifoError1 0x80
356
357/*-----------------------------------------------------------------------------+
358 | Miscellanies defines.
359 +-----------------------------------------------------------------------------*/
8749cfb4
SR		 360/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
361/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
fe8c2806 362
42dfe7a1 363#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 364/*-----------------------------------------------------------------------------+
365 | Fifo
366 +-----------------------------------------------------------------------------*/
367typedef struct {
368 char *rx_buffer;
369 ulong rx_put;
370 ulong rx_get;
371} serial_buffer_t;
372
373volatile static serial_buffer_t buf_info;
374#endif
375
fe8c2806
WD		 376#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
377static void serial_divs (int baudrate, unsigned long *pudiv,
378 unsigned short *pbdiv )
379{
380 sys_info_t sysinfo;
381 unsigned long div; /* total divisor udiv * bdiv */
382 unsigned long umin; /* minimum udiv */
383 unsigned short diff; /* smallest diff */
384 unsigned long udiv; /* best udiv */
385
386 unsigned short idiff; /* current diff */
387 unsigned short ibdiv; /* current bdiv */
388 unsigned long i;
389 unsigned long est; /* current estimate */
390
391 get_sys_info( &sysinfo );
392
393 udiv = 32; /* Assume lowest possible serial clk */
394 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
395 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
396 diff = 32; /* highest possible */
397
398 /* i is the test udiv value -- start with the largest
399 * possible (32) to minimize serial clock and constrain
400 * search to umin.
401 */
402 for( i = 32; i > umin; i-- ){
403 ibdiv = div/i;
404 est = i * ibdiv;
405 idiff = (est > div) ? (est-div) : (div-est);
406 if( idiff == 0 ){
407 udiv = i;
408 break; /* can't do better */
409 }
410 else if( idiff < diff ){
411 udiv = i; /* best so far */
412 diff = idiff; /* update lowest diff*/
413 }
414 }
415
416 *pudiv = udiv;
417 *pbdiv = div/udiv;
418
419}
420#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
421
fe8c2806
WD		 422/*
423 * Minimal serial functions needed to use one of the SMC ports
424 * as serial console interface.
425 */
426
427#if defined(CONFIG_440)
ff36fd85
WD		 428#if defined(CONFIG_SERIAL_MULTI)
429int serial_init_dev (unsigned long dev_base)
430#else
431int serial_init(void)
432#endif
fe8c2806
WD		 433{
434 DECLARE_GLOBAL_DATA_PTR;
435
436 unsigned long reg;
437 unsigned long udiv;
438 unsigned short bdiv;
439 volatile char val;
440#ifdef CFG_EXT_SERIAL_CLOCK
441 unsigned long tmp;
442#endif
443
6e7fb6ea 444#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
ff36fd85
WD		 445#if defined(CONFIG_SERIAL_MULTI)
446 if (UART0_BASE == dev_base) {
447 mfsdr(UART0_SDR,reg);
448 reg &= ~CR0_MASK;
449 } else {
450 mfsdr(UART1_SDR,reg);
451 reg &= ~CR0_MASK;
452 }
453#else
ba56f625
WD		 454 mfsdr(UART0_SDR,reg);
455 reg &= ~CR0_MASK;
ff36fd85 456#endif
ba56f625 457#else
fe8c2806 458 reg = mfdcr(cntrl0) & ~CR0_MASK;
846b0dd2 459#endif /* CONFIG_440GX */
fe8c2806
WD		 460#ifdef CFG_EXT_SERIAL_CLOCK
461 reg |= CR0_EXTCLK_ENA;
462 udiv = 1;
463 tmp = gd->baudrate * 16;
464 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
465#else
466 /* For 440, the cpu clock is on divider chain A, UART on divider
467 * chain B ... so cpu clock is irrelevant. Get the "optimized"
468 * values that are subject to the 1/2 opb clock constraint
469 */
470 serial_divs (gd->baudrate, &udiv, &bdiv);
471#endif
472
6e7fb6ea 473#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
ba56f625 474 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
ff36fd85
WD		 475#if defined(CONFIG_SERIAL_MULTI)
476 if (UART0_BASE == dev_base) {
477 mtsdr (UART0_SDR,reg);
478 } else {
479 mtsdr (UART1_SDR,reg);
480 }
481#else
ba56f625 482 mtsdr (UART0_SDR,reg);
ff36fd85 483#endif
ba56f625 484#else
fe8c2806
WD		 485 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
486 mtdcr (cntrl0, reg);
ba56f625 487#endif
ff36fd85
WD		 488
489#if defined(CONFIG_SERIAL_MULTI)
490 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
491 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
492 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
493 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
494 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
495 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
496 val = in8 (dev_base + UART_LSR); /* clear line status */
497 val = in8 (dev_base + UART_RBR); /* read receive buffer */
498 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
499 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
500#else
8749cfb4
SR		 501 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
502 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
503 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
504 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
505 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
506 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
507 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
508 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
509 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
510 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
ff36fd85 511#endif
fe8c2806
WD		 512 return (0);
513}
514
515#else /* !defined(CONFIG_440) */
516
ff36fd85
WD		 517#if defined(CONFIG_SERIAL_MULTI)
518int serial_init_dev (unsigned long dev_base)
519#else
fe8c2806 520int serial_init (void)
ff36fd85 521#endif
fe8c2806
WD		 522{
523 DECLARE_GLOBAL_DATA_PTR;
524
525 unsigned long reg;
526 unsigned long tmp;
527 unsigned long clk;
528 unsigned long udiv;
529 unsigned short bdiv;
530 volatile char val;
531
8749cfb4
SR		 532#ifdef CONFIG_405EP
533 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
534 clk = gd->cpu_clk;
535 tmp = CFG_BASE_BAUD * 16;
536 udiv = (clk + tmp / 2) / tmp;
537 if (udiv > UDIV_MAX) /* max. n bits for udiv */
538 udiv = UDIV_MAX;
539 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
540 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
541 mtdcr (cpc0_ucr, reg);
542#else /* CONFIG_405EP */
fe8c2806
WD		 543 reg = mfdcr(cntrl0) & ~CR0_MASK;
544#ifdef CFG_EXT_SERIAL_CLOCK
545 clk = CFG_EXT_SERIAL_CLOCK;
546 udiv = 1;
547 reg |= CR0_EXTCLK_ENA;
548#else
549 clk = gd->cpu_clk;
550#ifdef CFG_405_UART_ERRATA_59
551 udiv = 31; /* Errata 59: stuck at 31 */
552#else
553 tmp = CFG_BASE_BAUD * 16;
554 udiv = (clk + tmp / 2) / tmp;
8749cfb4
SR		 555 if (udiv > UDIV_MAX) /* max. n bits for udiv */
556 udiv = UDIV_MAX;
fe8c2806
WD		 557#endif
558#endif
fe8c2806
WD		 559 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
560 mtdcr (cntrl0, reg);
8749cfb4 561#endif /* CONFIG_405EP */
fe8c2806
WD		 562
563 tmp = gd->baudrate * udiv * 16;
564 bdiv = (clk + tmp / 2) / tmp;
565
ff36fd85
WD		 566#if defined(CONFIG_SERIAL_MULTI)
567 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
568 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
569 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
570 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
571 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
572 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
573 val = in8 (dev_base + UART_LSR); /* clear line status */
574 val = in8 (dev_base + UART_RBR); /* read receive buffer */
575 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
576 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
577#else
8749cfb4
SR		 578 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
579 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
580 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
581 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
582 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
583 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
584 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
585 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
586 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
587 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
ff36fd85 588#endif
fe8c2806
WD		 589 return (0);
590}
591
592#endif /* if defined(CONFIG_440) */
593
ff36fd85
WD		 594#if defined(CONFIG_SERIAL_MULTI)
595void serial_setbrg_dev (unsigned long dev_base)
596#else
fe8c2806 597void serial_setbrg (void)
ff36fd85 598#endif
fe8c2806
WD		 599{
600 DECLARE_GLOBAL_DATA_PTR;
601
602 unsigned long tmp;
603 unsigned long clk;
604 unsigned long udiv;
605 unsigned short bdiv;
606
607#ifdef CFG_EXT_SERIAL_CLOCK
608 clk = CFG_EXT_SERIAL_CLOCK;
609#else
610 clk = gd->cpu_clk;
611#endif
8749cfb4
SR		 612
613#ifdef CONFIG_405EP
614 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
615#else
fe8c2806 616 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
8749cfb4 617#endif /* CONFIG_405EP */
fe8c2806
WD		 618 tmp = gd->baudrate * udiv * 16;
619 bdiv = (clk + tmp / 2) / tmp;
620
ff36fd85
WD		 621#if defined(CONFIG_SERIAL_MULTI)
622 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
623 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
624 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
625 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
626#else
8749cfb4
SR		 627 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
628 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
629 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
630 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
ff36fd85 631#endif
fe8c2806
WD		 632}
633
ff36fd85
WD		 634#if defined(CONFIG_SERIAL_MULTI)
635void serial_putc_dev (unsigned long dev_base, const char c)
636#else
fe8c2806 637void serial_putc (const char c)
ff36fd85 638#endif
fe8c2806
WD		 639{
640 int i;
641
642 if (c == '\n')
ff36fd85
WD		 643#if defined(CONFIG_SERIAL_MULTI)
644 serial_putc_dev (dev_base, '\r');
645#else
fe8c2806 646 serial_putc ('\r');
ff36fd85 647#endif
fe8c2806
WD		 648
649 /* check THRE bit, wait for transmiter available */
650 for (i = 1; i < 3500; i++) {
ff36fd85
WD		 651#if defined(CONFIG_SERIAL_MULTI)
652 if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
653#else
8749cfb4 654 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
ff36fd85 655#endif
fe8c2806
WD		 656 break;
657 udelay (100);
658 }
ff36fd85
WD		 659#if defined(CONFIG_SERIAL_MULTI)
660 out8 (dev_base + UART_THR, c); /* put character out */
661#else
8749cfb4 662 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
ff36fd85 663#endif
fe8c2806
WD		 664}
665
ff36fd85
WD		 666#if defined(CONFIG_SERIAL_MULTI)
667void serial_puts_dev (unsigned long dev_base, const char *s)
668#else
fe8c2806 669void serial_puts (const char *s)
ff36fd85 670#endif
fe8c2806
WD		 671{
672 while (*s) {
ff36fd85
WD		 673#if defined(CONFIG_SERIAL_MULTI)
674 serial_putc_dev (dev_base, *s++);
675#else
fe8c2806 676 serial_putc (*s++);
ff36fd85 677#endif
fe8c2806
WD		 678 }
679}
680
ff36fd85
WD		 681#if defined(CONFIG_SERIAL_MULTI)
682int serial_getc_dev (unsigned long dev_base)
683#else
684int serial_getc (void)
685#endif
fe8c2806
WD		 686{
687 unsigned char status = 0;
688
689 while (1) {
690#if defined(CONFIG_HW_WATCHDOG)
691 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
692#endif /* CONFIG_HW_WATCHDOG */
ff36fd85
WD		 693#if defined(CONFIG_SERIAL_MULTI)
694 status = in8 (dev_base + UART_LSR);
695#else
8749cfb4 696 status = in8 (ACTING_UART0_BASE + UART_LSR);
ff36fd85 697#endif
fe8c2806
WD		 698 if ((status & asyncLSRDataReady1) != 0x0) {
699 break;
700 }
701 if ((status & ( asyncLSRFramingError1 |
702 asyncLSROverrunError1 |
703 asyncLSRParityError1 |
704 asyncLSRBreakInterrupt1 )) != 0) {
ff36fd85
WD		 705#if defined(CONFIG_SERIAL_MULTI)
706 out8 (dev_base + UART_LSR,
707#else
8749cfb4 708 out8 (ACTING_UART0_BASE + UART_LSR,
ff36fd85 709#endif
fe8c2806
WD		 710 asyncLSRFramingError1 |
711 asyncLSROverrunError1 |
712 asyncLSRParityError1 |
713 asyncLSRBreakInterrupt1);
714 }
715 }
ff36fd85
WD		 716#if defined(CONFIG_SERIAL_MULTI)
717 return (0x000000ff & (int) in8 (dev_base));
718#else
8749cfb4 719 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
ff36fd85 720#endif
fe8c2806
WD		 721}
722
ff36fd85
WD		 723#if defined(CONFIG_SERIAL_MULTI)
724int serial_tstc_dev (unsigned long dev_base)
725#else
726int serial_tstc (void)
727#endif
fe8c2806
WD		 728{
729 unsigned char status;
730
ff36fd85
WD		 731#if defined(CONFIG_SERIAL_MULTI)
732 status = in8 (dev_base + UART_LSR);
733#else
8749cfb4 734 status = in8 (ACTING_UART0_BASE + UART_LSR);
ff36fd85 735#endif
fe8c2806
WD		 736 if ((status & asyncLSRDataReady1) != 0x0) {
737 return (1);
738 }
739 if ((status & ( asyncLSRFramingError1 |
740 asyncLSROverrunError1 |
741 asyncLSRParityError1 |
742 asyncLSRBreakInterrupt1 )) != 0) {
ff36fd85
WD		 743#if defined(CONFIG_SERIAL_MULTI)
744 out8 (dev_base + UART_LSR,
745#else
8749cfb4 746 out8 (ACTING_UART0_BASE + UART_LSR,
ff36fd85 747#endif
fe8c2806
WD		 748 asyncLSRFramingError1 |
749 asyncLSROverrunError1 |
750 asyncLSRParityError1 |
751 asyncLSRBreakInterrupt1);
752 }
753 return 0;
754}
755
42dfe7a1 756#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 757
758void serial_isr (void *arg)
759{
760 int space;
761 int c;
762 const int rx_get = buf_info.rx_get;
763 int rx_put = buf_info.rx_put;
764
765 if (rx_get <= rx_put) {
766 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
767 } else {
768 space = rx_get - rx_put;
769 }
ff36fd85
WD		 770 while (serial_tstc_dev (ACTING_UART0_BASE)) {
771 c = serial_getc_dev (ACTING_UART0_BASE);
fe8c2806
WD		 772 if (space) {
773 buf_info.rx_buffer[rx_put++] = c;
774 space--;
775 }
776 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
777 rx_put = 0;
778 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
779 /* Stop flow by setting RTS inactive */
8749cfb4
SR		 780 out8 (ACTING_UART0_BASE + UART_MCR,
781 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
fe8c2806
WD		 782 }
783 }
784 buf_info.rx_put = rx_put;
785}
786
787void serial_buffered_init (void)
788{
789 serial_puts ("Switching to interrupt driven serial input mode.\n");
790 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
791 buf_info.rx_put = 0;
792 buf_info.rx_get = 0;
793
8749cfb4 794 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
fe8c2806
WD		 795 serial_puts ("Check CTS signal present on serial port: OK.\n");
796 } else {
797 serial_puts ("WARNING: CTS signal not present on serial port.\n");
798 }
799
800 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
801 serial_isr /*interrupt_handler_t *handler */ ,
802 (void *) &buf_info /*void *arg */ );
803
804 /* Enable "RX Data Available" Interrupt on UART */
8749cfb4
SR		 805 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
806 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
fe8c2806 807 /* Set DTR active */
8749cfb4 808 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
fe8c2806 809 /* Start flow by setting RTS active */
8749cfb4 810 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806 811 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
8749cfb4 812 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
fe8c2806
WD		 813}
814
815void serial_buffered_putc (const char c)
816{
817 /* Wait for CTS */
818#if defined(CONFIG_HW_WATCHDOG)
8749cfb4 819 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
fe8c2806
WD		 820 WATCHDOG_RESET ();
821#else
8749cfb4 822 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
fe8c2806
WD		 823#endif
824 serial_putc (c);
825}
826
827void serial_buffered_puts (const char *s)
828{
829 serial_puts (s);
830}
831
832int serial_buffered_getc (void)
833{
834 int space;
835 int c;
836 int rx_get = buf_info.rx_get;
837 int rx_put;
838
839#if defined(CONFIG_HW_WATCHDOG)
840 while (rx_get == buf_info.rx_put)
841 WATCHDOG_RESET ();
842#else
843 while (rx_get == buf_info.rx_put);
844#endif
845 c = buf_info.rx_buffer[rx_get++];
846 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
847 rx_get = 0;
848 buf_info.rx_get = rx_get;
849
850 rx_put = buf_info.rx_put;
851 if (rx_get <= rx_put) {
852 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
853 } else {
854 space = rx_get - rx_put;
855 }
856 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
857 /* Start flow by setting RTS active */
8749cfb4 858 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806
WD		 859 }
860
861 return c;
862}
863
864int serial_buffered_tstc (void)
865{
866 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
867}
868
869#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
870
fe8c2806
WD		 871#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
872/*
873 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
874 number 0 or number 1
875 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
876 configuration has been already done
877 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
878 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
879*/
880#if (CONFIG_KGDB_SER_INDEX & 2)
881void kgdb_serial_init (void)
882{
883 DECLARE_GLOBAL_DATA_PTR;
884
885 volatile char val;
886 unsigned short br_reg;
887
888 get_clocks ();
889 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
890 5) / 10;
891 /*
892 * Init onboard 16550 UART
893 */
8749cfb4
SR		 894 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
895 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
896 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
897 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
898 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
899 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
900 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
901 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
902 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
903 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
fe8c2806
WD		 904}
905
fe8c2806
WD		 906void putDebugChar (const char c)
907{
908 if (c == '\n')
909 serial_putc ('\r');
910
8749cfb4 911 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
fe8c2806
WD		 912
913 /* check THRE bit, wait for transfer done */
8749cfb4 914 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
fe8c2806
WD		 915}
916
fe8c2806
WD		 917void putDebugStr (const char *s)
918{
919 while (*s) {
920 serial_putc (*s++);
921 }
922}
923
fe8c2806
WD		 924int getDebugChar (void)
925{
926 unsigned char status = 0;
927
928 while (1) {
8749cfb4 929 status = in8 (ACTING_UART1_BASE + UART_LSR);
fe8c2806
WD		 930 if ((status & asyncLSRDataReady1) != 0x0) {
931 break;
932 }
933 if ((status & ( asyncLSRFramingError1 |
934 asyncLSROverrunError1 |
935 asyncLSRParityError1 |
936 asyncLSRBreakInterrupt1 )) != 0) {
8749cfb4 937 out8 (ACTING_UART1_BASE + UART_LSR,
fe8c2806
WD		 938 asyncLSRFramingError1 |
939 asyncLSROverrunError1 |
940 asyncLSRParityError1 |
941 asyncLSRBreakInterrupt1);
942 }
943 }
8749cfb4 944 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
fe8c2806
WD		 945}
946
fe8c2806
WD		 947void kgdb_interruptible (int yes)
948{
949 return;
950}
951
952#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
953
954void kgdb_serial_init (void)
955{
956 serial_printf ("[on serial] ");
957}
958
959void putDebugChar (int c)
960{
961 serial_putc (c);
962}
963
964void putDebugStr (const char *str)
965{
966 serial_puts (str);
967}
968
969int getDebugChar (void)
970{
971 return serial_getc ();
972}
973
974void kgdb_interruptible (int yes)
975{
976 return;
977}
978#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
979#endif /* CFG_CMD_KGDB */
980
ff36fd85
WD		 981
982#if defined(CONFIG_SERIAL_MULTI)
983int serial0_init(void)
984{
985 return (serial_init_dev(UART0_BASE));
986}
987
988int serial1_init(void)
989{
990 return (serial_init_dev(UART1_BASE));
991}
992void serial0_setbrg (void)
993{
994 serial_setbrg_dev(UART0_BASE);
995}
996void serial1_setbrg (void)
997{
998 serial_setbrg_dev(UART1_BASE);
999}
1000
1001void serial0_putc(const char c)
1002{
1003 serial_putc_dev(UART0_BASE,c);
1004}
1005
1006void serial1_putc(const char c)
1007{
1008 serial_putc_dev(UART1_BASE, c);
1009}
1010void serial0_puts(const char *s)
1011{
1012 serial_puts_dev(UART0_BASE, s);
1013}
1014
1015void serial1_puts(const char *s)
1016{
1017 serial_puts_dev(UART1_BASE, s);
1018}
1019
1020int serial0_getc(void)
1021{
1022 return(serial_getc_dev(UART0_BASE));
1023}
1024
1025int serial1_getc(void)
1026{
1027 return(serial_getc_dev(UART1_BASE));
1028}
1029int serial0_tstc(void)
1030{
1031 return (serial_tstc_dev(UART0_BASE));
1032}
1033
1034int serial1_tstc(void)
1035{
1036 return (serial_tstc_dev(UART1_BASE));
1037}
1038
1039struct serial_device serial0_device =
1040{
1041 "serial0",
1042 "UART0",
1043 serial0_init,
1044 serial0_setbrg,
1045 serial0_getc,
1046 serial0_tstc,
1047 serial0_putc,
1048 serial0_puts,
1049};
1050
1051struct serial_device serial1_device =
1052{
1053 "serial1",
1054 "UART1",
1055 serial1_init,
1056 serial1_setbrg,
1057 serial1_getc,
1058 serial1_tstc,
1059 serial1_putc,
1060 serial1_puts,
1061};
1062#endif /* CONFIG_SERIAL_MULTI */
1063
fe8c2806 1064#endif /* CONFIG_405GP || CONFIG_405CR */
"Das U-Boot" Source Tree