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Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone.
[people/ms/u-boot.git] / cpu / ppc4xx / serial.c
CommitLineData
fe8c2806
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23/*------------------------------------------------------------------------------+ */
24/*
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
31 *
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
35 *
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
39 *
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
42 */
43/*------------------------------------------------------------------------------- */
ff36fd85
WD		 44/*
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
47 */
fe8c2806
WD		 48#include <common.h>
49#include <commproc.h>
50#include <asm/processor.h>
51#include <watchdog.h>
52#include "vecnum.h"
53
ff36fd85
WD		 54#ifdef CONFIG_SERIAL_MULTI
55#include <serial.h>
56#endif
57
42dfe7a1 58#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 59#include <malloc.h>
60#endif
61
62/*****************************************************************************/
63#ifdef CONFIG_IOP480
64
65#define SPU_BASE 0x40000000
66
67#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
68#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
69#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
70#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
71#define spu_BRateDivh 0x10 /* Baud rate divisor high */
72#define spu_BRateDivl 0x14 /* Baud rate divisor low */
73#define spu_CtlReg 0x18 /* Control Register */
74#define spu_RxCmd 0x1c /* Rx Command Register */
75#define spu_TxCmd 0x20 /* Tx Command Register */
76#define spu_RxBuff 0x24 /* Rx data buffer */
77#define spu_TxBuff 0x24 /* Tx data buffer */
78
79/*-----------------------------------------------------------------------------+
80 | Line Status Register.
81 +-----------------------------------------------------------------------------*/
82#define asyncLSRport1 0x40000000
83#define asyncLSRport1set 0x40000004
84#define asyncLSRDataReady 0x80
85#define asyncLSRFramingError 0x40
86#define asyncLSROverrunError 0x20
87#define asyncLSRParityError 0x10
88#define asyncLSRBreakInterrupt 0x08
89#define asyncLSRTxHoldEmpty 0x04
90#define asyncLSRTxShiftEmpty 0x02
91
92/*-----------------------------------------------------------------------------+
93 | Handshake Status Register.
94 +-----------------------------------------------------------------------------*/
95#define asyncHSRport1 0x40000008
96#define asyncHSRport1set 0x4000000c
97#define asyncHSRDsr 0x80
98#define asyncLSRCts 0x40
99
100/*-----------------------------------------------------------------------------+
101 | Control Register.
102 +-----------------------------------------------------------------------------*/
103#define asyncCRport1 0x40000018
104#define asyncCRNormal 0x00
105#define asyncCRLoopback 0x40
106#define asyncCRAutoEcho 0x80
107#define asyncCRDtr 0x20
108#define asyncCRRts 0x10
109#define asyncCRWordLength7 0x00
110#define asyncCRWordLength8 0x08
111#define asyncCRParityDisable 0x00
112#define asyncCRParityEnable 0x04
113#define asyncCREvenParity 0x00
114#define asyncCROddParity 0x02
115#define asyncCRStopBitsOne 0x00
116#define asyncCRStopBitsTwo 0x01
117#define asyncCRDisableDtrRts 0x00
118
119/*-----------------------------------------------------------------------------+
120 | Receiver Command Register.
121 +-----------------------------------------------------------------------------*/
122#define asyncRCRport1 0x4000001c
123#define asyncRCRDisable 0x00
124#define asyncRCREnable 0x80
125#define asyncRCRIntDisable 0x00
126#define asyncRCRIntEnabled 0x20
127#define asyncRCRDMACh2 0x40
128#define asyncRCRDMACh3 0x60
129#define asyncRCRErrorInt 0x10
130#define asyncRCRPauseEnable 0x08
131
132/*-----------------------------------------------------------------------------+
133 | Transmitter Command Register.
134 +-----------------------------------------------------------------------------*/
135#define asyncTCRport1 0x40000020
136#define asyncTCRDisable 0x00
137#define asyncTCREnable 0x80
138#define asyncTCRIntDisable 0x00
139#define asyncTCRIntEnabled 0x20
140#define asyncTCRDMACh2 0x40
141#define asyncTCRDMACh3 0x60
142#define asyncTCRTxEmpty 0x10
143#define asyncTCRErrorInt 0x08
144#define asyncTCRStopPause 0x04
145#define asyncTCRBreakGen 0x02
146
147/*-----------------------------------------------------------------------------+
148 | Miscellanies defines.
149 +-----------------------------------------------------------------------------*/
150#define asyncTxBufferport1 0x40000024
151#define asyncRxBufferport1 0x40000024
152#define asyncDLABLsbport1 0x40000014
153#define asyncDLABMsbport1 0x40000010
154#define asyncXOFFchar 0x13
155#define asyncXONchar 0x11
156
fe8c2806
WD		 157/*
158 * Minimal serial functions needed to use one of the SMC ports
159 * as serial console interface.
160 */
161
162int serial_init (void)
163{
164 DECLARE_GLOBAL_DATA_PTR;
165
166 volatile char val;
167 unsigned short br_reg;
168
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
170
171 /*
172 * Init onboard UART
173 */
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
182
183 return (0);
184}
185
fe8c2806
WD		 186void serial_setbrg (void)
187{
188 DECLARE_GLOBAL_DATA_PTR;
189
190 unsigned short br_reg;
191
192 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
193
194 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
195 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
196}
197
fe8c2806
WD		 198void serial_putc (const char c)
199{
200 if (c == '\n')
201 serial_putc ('\r');
202
203 /* load status from handshake register */
204 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
205 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
206
207 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
208
209 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
210 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
211 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
212 }
213}
214
fe8c2806
WD		 215void serial_puts (const char *s)
216{
217 while (*s) {
218 serial_putc (*s++);
219 }
220}
221
fe8c2806
WD		 222int serial_getc ()
223{
224 unsigned char status = 0;
225
226 while (1) {
227 status = in8 (asyncLSRport1);
228 if ((status & asyncLSRDataReady) != 0x0) {
229 break;
230 }
231 if ((status & ( asyncLSRFramingError |
232 asyncLSROverrunError |
233 asyncLSRParityError |
234 asyncLSRBreakInterrupt )) != 0) {
235 (void) out8 (asyncLSRport1,
236 asyncLSRFramingError |
237 asyncLSROverrunError |
238 asyncLSRParityError |
239 asyncLSRBreakInterrupt );
240 }
241 }
242 return (0x000000ff & (int) in8 (asyncRxBufferport1));
243}
244
fe8c2806
WD		 245int serial_tstc ()
246{
247 unsigned char status;
248
249 status = in8 (asyncLSRport1);
250 if ((status & asyncLSRDataReady) != 0x0) {
251 return (1);
252 }
253 if ((status & ( asyncLSRFramingError |
254 asyncLSROverrunError |
255 asyncLSRParityError |
256 asyncLSRBreakInterrupt )) != 0) {
257 (void) out8 (asyncLSRport1,
258 asyncLSRFramingError |
259 asyncLSROverrunError |
260 asyncLSRParityError |
261 asyncLSRBreakInterrupt);
262 }
263 return 0;
264}
265
266#endif /* CONFIG_IOP480 */
267
fe8c2806 268/*****************************************************************************/
8749cfb4 269#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
fe8c2806
WD		 270
271#if defined(CONFIG_440)
c157d8e2
SR		 272#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
273#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
274#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
275#else
fe8c2806
WD		 276#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
277#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
c157d8e2
SR		 278#endif
279#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
ba56f625
WD		 280#define CR0_MASK 0xdfffffff
281#define CR0_EXTCLK_ENA 0x00800000
282#define CR0_UDIV_POS 0
283#else
fe8c2806
WD		 284#define CR0_MASK 0x3fff0000
285#define CR0_EXTCLK_ENA 0x00600000
286#define CR0_UDIV_POS 16
ba56f625 287#endif /* CONFIG_440_GX */
8749cfb4
SR		 288#elif defined(CONFIG_405EP)
289#define UART0_BASE 0xef600300
290#define UART1_BASE 0xef600400
291#define UCR0_MASK 0x0000007f
292#define UCR1_MASK 0x00007f00
293#define UCR0_UDIV_POS 0
294#define UCR1_UDIV_POS 8
295#define UDIV_MAX 127
296#else /* CONFIG_405GP || CONFIG_405CR */
fe8c2806
WD		 297#define UART0_BASE 0xef600300
298#define UART1_BASE 0xef600400
299#define CR0_MASK 0x00001fff
d7787c6e 300#define CR0_EXTCLK_ENA 0x000000c0
fe8c2806 301#define CR0_UDIV_POS 1
8749cfb4
SR		 302#define UDIV_MAX 32
303#endif
304
305/* using serial port 0 or 1 as U-Boot console ? */
306#if defined(CONFIG_UART1_CONSOLE)
307#define ACTING_UART0_BASE UART1_BASE
308#define ACTING_UART1_BASE UART0_BASE
c157d8e2 309#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
ba56f625
WD		 310#define UART0_SDR sdr_uart1
311#define UART1_SDR sdr_uart0
312#endif /* CONFIG_440_GX */
8749cfb4
SR		 313#else
314#define ACTING_UART0_BASE UART0_BASE
315#define ACTING_UART1_BASE UART1_BASE
c157d8e2 316#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
ba56f625
WD		 317#define UART0_SDR sdr_uart0
318#define UART1_SDR sdr_uart1
319#endif /* CONFIG_440_GX */
8749cfb4
SR		 320#endif
321
322#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
323#error "External serial clock not supported on IBM PPC405EP!"
fe8c2806
WD		 324#endif
325
326#define UART_RBR 0x00
327#define UART_THR 0x00
328#define UART_IER 0x01
329#define UART_IIR 0x02
330#define UART_FCR 0x02
331#define UART_LCR 0x03
332#define UART_MCR 0x04
333#define UART_LSR 0x05
334#define UART_MSR 0x06
335#define UART_SCR 0x07
336#define UART_DLL 0x00
337#define UART_DLM 0x01
338
339/*-----------------------------------------------------------------------------+
340 | Line Status Register.
341 +-----------------------------------------------------------------------------*/
8749cfb4 342/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
fe8c2806
WD		 343#define asyncLSRDataReady1 0x01
344#define asyncLSROverrunError1 0x02
345#define asyncLSRParityError1 0x04
346#define asyncLSRFramingError1 0x08
347#define asyncLSRBreakInterrupt1 0x10
348#define asyncLSRTxHoldEmpty1 0x20
349#define asyncLSRTxShiftEmpty1 0x40
350#define asyncLSRRxFifoError1 0x80
351
352/*-----------------------------------------------------------------------------+
353 | Miscellanies defines.
354 +-----------------------------------------------------------------------------*/
8749cfb4
SR		 355/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
356/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
fe8c2806 357
42dfe7a1 358#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 359/*-----------------------------------------------------------------------------+
360 | Fifo
361 +-----------------------------------------------------------------------------*/
362typedef struct {
363 char *rx_buffer;
364 ulong rx_put;
365 ulong rx_get;
366} serial_buffer_t;
367
368volatile static serial_buffer_t buf_info;
369#endif
370
fe8c2806
WD		 371#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
372static void serial_divs (int baudrate, unsigned long *pudiv,
373 unsigned short *pbdiv )
374{
375 sys_info_t sysinfo;
376 unsigned long div; /* total divisor udiv * bdiv */
377 unsigned long umin; /* minimum udiv */
378 unsigned short diff; /* smallest diff */
379 unsigned long udiv; /* best udiv */
380
381 unsigned short idiff; /* current diff */
382 unsigned short ibdiv; /* current bdiv */
383 unsigned long i;
384 unsigned long est; /* current estimate */
385
386 get_sys_info( &sysinfo );
387
388 udiv = 32; /* Assume lowest possible serial clk */
389 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
390 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
391 diff = 32; /* highest possible */
392
393 /* i is the test udiv value -- start with the largest
394 * possible (32) to minimize serial clock and constrain
395 * search to umin.
396 */
397 for( i = 32; i > umin; i-- ){
398 ibdiv = div/i;
399 est = i * ibdiv;
400 idiff = (est > div) ? (est-div) : (div-est);
401 if( idiff == 0 ){
402 udiv = i;
403 break; /* can't do better */
404 }
405 else if( idiff < diff ){
406 udiv = i; /* best so far */
407 diff = idiff; /* update lowest diff*/
408 }
409 }
410
411 *pudiv = udiv;
412 *pbdiv = div/udiv;
413
414}
415#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
416
fe8c2806
WD		 417/*
418 * Minimal serial functions needed to use one of the SMC ports
419 * as serial console interface.
420 */
421
422#if defined(CONFIG_440)
ff36fd85
WD		 423#if defined(CONFIG_SERIAL_MULTI)
424int serial_init_dev (unsigned long dev_base)
425#else
426int serial_init(void)
427#endif
fe8c2806
WD		 428{
429 DECLARE_GLOBAL_DATA_PTR;
430
431 unsigned long reg;
432 unsigned long udiv;
433 unsigned short bdiv;
434 volatile char val;
435#ifdef CFG_EXT_SERIAL_CLOCK
436 unsigned long tmp;
437#endif
438
ba56f625 439#if defined(CONFIG_440_GX)
ff36fd85
WD		 440#if defined(CONFIG_SERIAL_MULTI)
441 if (UART0_BASE == dev_base) {
442 mfsdr(UART0_SDR,reg);
443 reg &= ~CR0_MASK;
444 } else {
445 mfsdr(UART1_SDR,reg);
446 reg &= ~CR0_MASK;
447 }
448#else
ba56f625
WD		 449 mfsdr(UART0_SDR,reg);
450 reg &= ~CR0_MASK;
ff36fd85 451#endif
ba56f625 452#else
fe8c2806 453 reg = mfdcr(cntrl0) & ~CR0_MASK;
ba56f625 454#endif /* CONFIG_440_GX */
fe8c2806
WD		 455#ifdef CFG_EXT_SERIAL_CLOCK
456 reg |= CR0_EXTCLK_ENA;
457 udiv = 1;
458 tmp = gd->baudrate * 16;
459 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
460#else
461 /* For 440, the cpu clock is on divider chain A, UART on divider
462 * chain B ... so cpu clock is irrelevant. Get the "optimized"
463 * values that are subject to the 1/2 opb clock constraint
464 */
465 serial_divs (gd->baudrate, &udiv, &bdiv);
466#endif
467
c157d8e2 468#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
ba56f625 469 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
ff36fd85
WD		 470#if defined(CONFIG_SERIAL_MULTI)
471 if (UART0_BASE == dev_base) {
472 mtsdr (UART0_SDR,reg);
473 } else {
474 mtsdr (UART1_SDR,reg);
475 }
476#else
ba56f625 477 mtsdr (UART0_SDR,reg);
ff36fd85 478#endif
ba56f625 479#else
fe8c2806
WD		 480 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
481 mtdcr (cntrl0, reg);
ba56f625 482#endif
ff36fd85
WD		 483
484#if defined(CONFIG_SERIAL_MULTI)
485 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
486 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
487 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
488 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
489 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
490 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
491 val = in8 (dev_base + UART_LSR); /* clear line status */
492 val = in8 (dev_base + UART_RBR); /* read receive buffer */
493 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
494 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
495#else
8749cfb4
SR		 496 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
497 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
498 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
499 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
500 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
501 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
502 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
503 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
504 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
505 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
ff36fd85 506#endif
fe8c2806
WD		 507 return (0);
508}
509
510#else /* !defined(CONFIG_440) */
511
ff36fd85
WD		 512#if defined(CONFIG_SERIAL_MULTI)
513int serial_init_dev (unsigned long dev_base)
514#else
fe8c2806 515int serial_init (void)
ff36fd85 516#endif
fe8c2806
WD		 517{
518 DECLARE_GLOBAL_DATA_PTR;
519
520 unsigned long reg;
521 unsigned long tmp;
522 unsigned long clk;
523 unsigned long udiv;
524 unsigned short bdiv;
525 volatile char val;
526
8749cfb4
SR		 527#ifdef CONFIG_405EP
528 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
529 clk = gd->cpu_clk;
530 tmp = CFG_BASE_BAUD * 16;
531 udiv = (clk + tmp / 2) / tmp;
532 if (udiv > UDIV_MAX) /* max. n bits for udiv */
533 udiv = UDIV_MAX;
534 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
535 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
536 mtdcr (cpc0_ucr, reg);
537#else /* CONFIG_405EP */
fe8c2806
WD		 538 reg = mfdcr(cntrl0) & ~CR0_MASK;
539#ifdef CFG_EXT_SERIAL_CLOCK
540 clk = CFG_EXT_SERIAL_CLOCK;
541 udiv = 1;
542 reg |= CR0_EXTCLK_ENA;
543#else
544 clk = gd->cpu_clk;
545#ifdef CFG_405_UART_ERRATA_59
546 udiv = 31; /* Errata 59: stuck at 31 */
547#else
548 tmp = CFG_BASE_BAUD * 16;
549 udiv = (clk + tmp / 2) / tmp;
8749cfb4
SR		 550 if (udiv > UDIV_MAX) /* max. n bits for udiv */
551 udiv = UDIV_MAX;
fe8c2806
WD		 552#endif
553#endif
fe8c2806
WD		 554 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
555 mtdcr (cntrl0, reg);
8749cfb4 556#endif /* CONFIG_405EP */
fe8c2806
WD		 557
558 tmp = gd->baudrate * udiv * 16;
559 bdiv = (clk + tmp / 2) / tmp;
560
ff36fd85
WD		 561#if defined(CONFIG_SERIAL_MULTI)
562 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
563 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
564 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
565 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
566 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
567 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
568 val = in8 (dev_base + UART_LSR); /* clear line status */
569 val = in8 (dev_base + UART_RBR); /* read receive buffer */
570 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
571 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
572#else
8749cfb4
SR		 573 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
574 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
575 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
576 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
577 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
578 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
579 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
580 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
581 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
582 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
ff36fd85 583#endif
fe8c2806
WD		 584 return (0);
585}
586
587#endif /* if defined(CONFIG_440) */
588
ff36fd85
WD		 589#if defined(CONFIG_SERIAL_MULTI)
590void serial_setbrg_dev (unsigned long dev_base)
591#else
fe8c2806 592void serial_setbrg (void)
ff36fd85 593#endif
fe8c2806
WD		 594{
595 DECLARE_GLOBAL_DATA_PTR;
596
597 unsigned long tmp;
598 unsigned long clk;
599 unsigned long udiv;
600 unsigned short bdiv;
601
602#ifdef CFG_EXT_SERIAL_CLOCK
603 clk = CFG_EXT_SERIAL_CLOCK;
604#else
605 clk = gd->cpu_clk;
606#endif
8749cfb4
SR		 607
608#ifdef CONFIG_405EP
609 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
610#else
fe8c2806 611 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
8749cfb4 612#endif /* CONFIG_405EP */
fe8c2806
WD		 613 tmp = gd->baudrate * udiv * 16;
614 bdiv = (clk + tmp / 2) / tmp;
615
ff36fd85
WD		 616#if defined(CONFIG_SERIAL_MULTI)
617 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
618 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
619 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
620 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
621#else
8749cfb4
SR		 622 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
623 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
624 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
625 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
ff36fd85 626#endif
fe8c2806
WD		 627}
628
ff36fd85
WD		 629#if defined(CONFIG_SERIAL_MULTI)
630void serial_putc_dev (unsigned long dev_base, const char c)
631#else
fe8c2806 632void serial_putc (const char c)
ff36fd85 633#endif
fe8c2806
WD		 634{
635 int i;
636
637 if (c == '\n')
ff36fd85
WD		 638#if defined(CONFIG_SERIAL_MULTI)
639 serial_putc_dev (dev_base, '\r');
640#else
fe8c2806 641 serial_putc ('\r');
ff36fd85 642#endif
fe8c2806
WD		 643
644 /* check THRE bit, wait for transmiter available */
645 for (i = 1; i < 3500; i++) {
ff36fd85
WD		 646#if defined(CONFIG_SERIAL_MULTI)
647 if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
648#else
8749cfb4 649 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
ff36fd85 650#endif
fe8c2806
WD		 651 break;
652 udelay (100);
653 }
ff36fd85
WD		 654#if defined(CONFIG_SERIAL_MULTI)
655 out8 (dev_base + UART_THR, c); /* put character out */
656#else
8749cfb4 657 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
ff36fd85 658#endif
fe8c2806
WD		 659}
660
ff36fd85
WD		 661#if defined(CONFIG_SERIAL_MULTI)
662void serial_puts_dev (unsigned long dev_base, const char *s)
663#else
fe8c2806 664void serial_puts (const char *s)
ff36fd85 665#endif
fe8c2806
WD		 666{
667 while (*s) {
ff36fd85
WD		 668#if defined(CONFIG_SERIAL_MULTI)
669 serial_putc_dev (dev_base, *s++);
670#else
fe8c2806 671 serial_putc (*s++);
ff36fd85 672#endif
fe8c2806
WD		 673 }
674}
675
ff36fd85
WD		 676#if defined(CONFIG_SERIAL_MULTI)
677int serial_getc_dev (unsigned long dev_base)
678#else
679int serial_getc (void)
680#endif
fe8c2806
WD		 681{
682 unsigned char status = 0;
683
684 while (1) {
685#if defined(CONFIG_HW_WATCHDOG)
686 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
687#endif /* CONFIG_HW_WATCHDOG */
ff36fd85
WD		 688#if defined(CONFIG_SERIAL_MULTI)
689 status = in8 (dev_base + UART_LSR);
690#else
8749cfb4 691 status = in8 (ACTING_UART0_BASE + UART_LSR);
ff36fd85 692#endif
fe8c2806
WD		 693 if ((status & asyncLSRDataReady1) != 0x0) {
694 break;
695 }
696 if ((status & ( asyncLSRFramingError1 |
697 asyncLSROverrunError1 |
698 asyncLSRParityError1 |
699 asyncLSRBreakInterrupt1 )) != 0) {
ff36fd85
WD		 700#if defined(CONFIG_SERIAL_MULTI)
701 out8 (dev_base + UART_LSR,
702#else
8749cfb4 703 out8 (ACTING_UART0_BASE + UART_LSR,
ff36fd85 704#endif
fe8c2806
WD		 705 asyncLSRFramingError1 |
706 asyncLSROverrunError1 |
707 asyncLSRParityError1 |
708 asyncLSRBreakInterrupt1);
709 }
710 }
ff36fd85
WD		 711#if defined(CONFIG_SERIAL_MULTI)
712 return (0x000000ff & (int) in8 (dev_base));
713#else
8749cfb4 714 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
ff36fd85 715#endif
fe8c2806
WD		 716}
717
ff36fd85
WD		 718#if defined(CONFIG_SERIAL_MULTI)
719int serial_tstc_dev (unsigned long dev_base)
720#else
721int serial_tstc (void)
722#endif
fe8c2806
WD		 723{
724 unsigned char status;
725
ff36fd85
WD		 726#if defined(CONFIG_SERIAL_MULTI)
727 status = in8 (dev_base + UART_LSR);
728#else
8749cfb4 729 status = in8 (ACTING_UART0_BASE + UART_LSR);
ff36fd85 730#endif
fe8c2806
WD		 731 if ((status & asyncLSRDataReady1) != 0x0) {
732 return (1);
733 }
734 if ((status & ( asyncLSRFramingError1 |
735 asyncLSROverrunError1 |
736 asyncLSRParityError1 |
737 asyncLSRBreakInterrupt1 )) != 0) {
ff36fd85
WD		 738#if defined(CONFIG_SERIAL_MULTI)
739 out8 (dev_base + UART_LSR,
740#else
8749cfb4 741 out8 (ACTING_UART0_BASE + UART_LSR,
ff36fd85 742#endif
fe8c2806
WD		 743 asyncLSRFramingError1 |
744 asyncLSROverrunError1 |
745 asyncLSRParityError1 |
746 asyncLSRBreakInterrupt1);
747 }
748 return 0;
749}
750
42dfe7a1 751#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 752
753void serial_isr (void *arg)
754{
755 int space;
756 int c;
757 const int rx_get = buf_info.rx_get;
758 int rx_put = buf_info.rx_put;
759
760 if (rx_get <= rx_put) {
761 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
762 } else {
763 space = rx_get - rx_put;
764 }
ff36fd85
WD		 765 while (serial_tstc_dev (ACTING_UART0_BASE)) {
766 c = serial_getc_dev (ACTING_UART0_BASE);
fe8c2806
WD		 767 if (space) {
768 buf_info.rx_buffer[rx_put++] = c;
769 space--;
770 }
771 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
772 rx_put = 0;
773 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
774 /* Stop flow by setting RTS inactive */
8749cfb4
SR		 775 out8 (ACTING_UART0_BASE + UART_MCR,
776 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
fe8c2806
WD		 777 }
778 }
779 buf_info.rx_put = rx_put;
780}
781
782void serial_buffered_init (void)
783{
784 serial_puts ("Switching to interrupt driven serial input mode.\n");
785 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
786 buf_info.rx_put = 0;
787 buf_info.rx_get = 0;
788
8749cfb4 789 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
fe8c2806
WD		 790 serial_puts ("Check CTS signal present on serial port: OK.\n");
791 } else {
792 serial_puts ("WARNING: CTS signal not present on serial port.\n");
793 }
794
795 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
796 serial_isr /*interrupt_handler_t *handler */ ,
797 (void *) &buf_info /*void *arg */ );
798
799 /* Enable "RX Data Available" Interrupt on UART */
8749cfb4
SR		 800 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
801 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
fe8c2806 802 /* Set DTR active */
8749cfb4 803 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
fe8c2806 804 /* Start flow by setting RTS active */
8749cfb4 805 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806 806 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
8749cfb4 807 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
fe8c2806
WD		 808}
809
810void serial_buffered_putc (const char c)
811{
812 /* Wait for CTS */
813#if defined(CONFIG_HW_WATCHDOG)
8749cfb4 814 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
fe8c2806
WD		 815 WATCHDOG_RESET ();
816#else
8749cfb4 817 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
fe8c2806
WD		 818#endif
819 serial_putc (c);
820}
821
822void serial_buffered_puts (const char *s)
823{
824 serial_puts (s);
825}
826
827int serial_buffered_getc (void)
828{
829 int space;
830 int c;
831 int rx_get = buf_info.rx_get;
832 int rx_put;
833
834#if defined(CONFIG_HW_WATCHDOG)
835 while (rx_get == buf_info.rx_put)
836 WATCHDOG_RESET ();
837#else
838 while (rx_get == buf_info.rx_put);
839#endif
840 c = buf_info.rx_buffer[rx_get++];
841 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
842 rx_get = 0;
843 buf_info.rx_get = rx_get;
844
845 rx_put = buf_info.rx_put;
846 if (rx_get <= rx_put) {
847 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
848 } else {
849 space = rx_get - rx_put;
850 }
851 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
852 /* Start flow by setting RTS active */
8749cfb4 853 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806
WD		 854 }
855
856 return c;
857}
858
859int serial_buffered_tstc (void)
860{
861 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
862}
863
864#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
865
fe8c2806
WD		 866#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
867/*
868 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
869 number 0 or number 1
870 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
871 configuration has been already done
872 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
873 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
874*/
875#if (CONFIG_KGDB_SER_INDEX & 2)
876void kgdb_serial_init (void)
877{
878 DECLARE_GLOBAL_DATA_PTR;
879
880 volatile char val;
881 unsigned short br_reg;
882
883 get_clocks ();
884 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
885 5) / 10;
886 /*
887 * Init onboard 16550 UART
888 */
8749cfb4
SR		 889 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
890 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
891 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
892 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
893 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
894 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
895 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
896 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
897 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
898 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
fe8c2806
WD		 899}
900
fe8c2806
WD		 901void putDebugChar (const char c)
902{
903 if (c == '\n')
904 serial_putc ('\r');
905
8749cfb4 906 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
fe8c2806
WD		 907
908 /* check THRE bit, wait for transfer done */
8749cfb4 909 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
fe8c2806
WD		 910}
911
fe8c2806
WD		 912void putDebugStr (const char *s)
913{
914 while (*s) {
915 serial_putc (*s++);
916 }
917}
918
fe8c2806
WD		 919int getDebugChar (void)
920{
921 unsigned char status = 0;
922
923 while (1) {
8749cfb4 924 status = in8 (ACTING_UART1_BASE + UART_LSR);
fe8c2806
WD		 925 if ((status & asyncLSRDataReady1) != 0x0) {
926 break;
927 }
928 if ((status & ( asyncLSRFramingError1 |
929 asyncLSROverrunError1 |
930 asyncLSRParityError1 |
931 asyncLSRBreakInterrupt1 )) != 0) {
8749cfb4 932 out8 (ACTING_UART1_BASE + UART_LSR,
fe8c2806
WD		 933 asyncLSRFramingError1 |
934 asyncLSROverrunError1 |
935 asyncLSRParityError1 |
936 asyncLSRBreakInterrupt1);
937 }
938 }
8749cfb4 939 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
fe8c2806
WD		 940}
941
fe8c2806
WD		 942void kgdb_interruptible (int yes)
943{
944 return;
945}
946
947#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
948
949void kgdb_serial_init (void)
950{
951 serial_printf ("[on serial] ");
952}
953
954void putDebugChar (int c)
955{
956 serial_putc (c);
957}
958
959void putDebugStr (const char *str)
960{
961 serial_puts (str);
962}
963
964int getDebugChar (void)
965{
966 return serial_getc ();
967}
968
969void kgdb_interruptible (int yes)
970{
971 return;
972}
973#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
974#endif /* CFG_CMD_KGDB */
975
ff36fd85
WD		 976
977#if defined(CONFIG_SERIAL_MULTI)
978int serial0_init(void)
979{
980 return (serial_init_dev(UART0_BASE));
981}
982
983int serial1_init(void)
984{
985 return (serial_init_dev(UART1_BASE));
986}
987void serial0_setbrg (void)
988{
989 serial_setbrg_dev(UART0_BASE);
990}
991void serial1_setbrg (void)
992{
993 serial_setbrg_dev(UART1_BASE);
994}
995
996void serial0_putc(const char c)
997{
998 serial_putc_dev(UART0_BASE,c);
999}
1000
1001void serial1_putc(const char c)
1002{
1003 serial_putc_dev(UART1_BASE, c);
1004}
1005void serial0_puts(const char *s)
1006{
1007 serial_puts_dev(UART0_BASE, s);
1008}
1009
1010void serial1_puts(const char *s)
1011{
1012 serial_puts_dev(UART1_BASE, s);
1013}
1014
1015int serial0_getc(void)
1016{
1017 return(serial_getc_dev(UART0_BASE));
1018}
1019
1020int serial1_getc(void)
1021{
1022 return(serial_getc_dev(UART1_BASE));
1023}
1024int serial0_tstc(void)
1025{
1026 return (serial_tstc_dev(UART0_BASE));
1027}
1028
1029int serial1_tstc(void)
1030{
1031 return (serial_tstc_dev(UART1_BASE));
1032}
1033
1034struct serial_device serial0_device =
1035{
1036 "serial0",
1037 "UART0",
1038 serial0_init,
1039 serial0_setbrg,
1040 serial0_getc,
1041 serial0_tstc,
1042 serial0_putc,
1043 serial0_puts,
1044};
1045
1046struct serial_device serial1_device =
1047{
1048 "serial1",
1049 "UART1",
1050 serial1_init,
1051 serial1_setbrg,
1052 serial1_getc,
1053 serial1_tstc,
1054 serial1_putc,
1055 serial1_puts,
1056};
1057#endif /* CONFIG_SERIAL_MULTI */
1058
fe8c2806 1059#endif /* CONFIG_405GP || CONFIG_405CR */
"Das U-Boot" Source Tree