[thirdparty/openssl.git] / crypto / arm_arch.h

/*
 * Copyright 2011-2023 The OpenSSL Project Authors. All Rights Reserved.
 *
 * Licensed under the Apache License 2.0 (the "License").  You may not use
 * this file except in compliance with the License.  You can obtain a copy
 * in the file LICENSE in the source distribution or at
 * https://www.openssl.org/source/license.html
 */

#ifndef OSSL_CRYPTO_ARM_ARCH_H
# define OSSL_CRYPTO_ARM_ARCH_H

# if !defined(__ARM_ARCH__)
#  if defined(__CC_ARM)
#   define __ARM_ARCH__ __TARGET_ARCH_ARM
#   if defined(__BIG_ENDIAN)
#    define __ARMEB__
#   else
#    define __ARMEL__
#   endif
#  elif defined(__GNUC__)
#   if   defined(__aarch64__)
#    define __ARM_ARCH__ 8
  /*
   * Why doesn't gcc define __ARM_ARCH__? Instead it defines
   * bunch of below macros. See all_architectures[] table in
   * gcc/config/arm/arm.c. On a side note it defines
   * __ARMEL__/__ARMEB__ for little-/big-endian.
   */
#   elif defined(__ARM_ARCH)
#    define __ARM_ARCH__ __ARM_ARCH
#   elif defined(__ARM_ARCH_8A__)
#    define __ARM_ARCH__ 8
#   elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)     || \
        defined(__ARM_ARCH_7R__)|| defined(__ARM_ARCH_7M__)     || \
        defined(__ARM_ARCH_7EM__)
#    define __ARM_ARCH__ 7
#   elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__)     || \
        defined(__ARM_ARCH_6K__)|| defined(__ARM_ARCH_6M__)     || \
        defined(__ARM_ARCH_6Z__)|| defined(__ARM_ARCH_6ZK__)    || \
        defined(__ARM_ARCH_6T2__)
#    define __ARM_ARCH__ 6
#   elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__)     || \
        defined(__ARM_ARCH_5E__)|| defined(__ARM_ARCH_5TE__)    || \
        defined(__ARM_ARCH_5TEJ__)
#    define __ARM_ARCH__ 5
#   elif defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
#    define __ARM_ARCH__ 4
#   else
#    error "unsupported ARM architecture"
#   endif
#  elif defined(__ARM_ARCH)
#   define __ARM_ARCH__ __ARM_ARCH
#  endif
# endif

# if !defined(__ARM_MAX_ARCH__)
#  define __ARM_MAX_ARCH__ __ARM_ARCH__
# endif

# if __ARM_MAX_ARCH__<__ARM_ARCH__
#  error "__ARM_MAX_ARCH__ can't be less than __ARM_ARCH__"
# elif __ARM_MAX_ARCH__!=__ARM_ARCH__
#  if __ARM_ARCH__<7 && __ARM_MAX_ARCH__>=7 && defined(__ARMEB__)
#   error "can't build universal big-endian binary"
#  endif
# endif

# ifndef __ASSEMBLER__
extern unsigned int OPENSSL_armcap_P;
extern unsigned int OPENSSL_arm_midr;
extern unsigned int OPENSSL_armv8_rsa_neonized;
# endif

# define ARMV7_NEON      (1<<0)
# define ARMV7_TICK      (1<<1)
# define ARMV8_AES       (1<<2)
# define ARMV8_SHA1      (1<<3)
# define ARMV8_SHA256    (1<<4)
# define ARMV8_PMULL     (1<<5)
# define ARMV8_SHA512    (1<<6)
# define ARMV8_CPUID     (1<<7)
# define ARMV8_RNG       (1<<8)
# define ARMV8_SM3       (1<<9)
# define ARMV8_SM4       (1<<10)
# define ARMV8_SHA3      (1<<11)
# define ARMV8_UNROLL8_EOR3      (1<<12)
# define ARMV8_SVE       (1<<13)
# define ARMV8_SVE2      (1<<14)
# define ARMV8_HAVE_SHA3_AND_WORTH_USING     (1<<15)
# define ARMV8_UNROLL12_EOR3     (1<<16)

/*
 * MIDR_EL1 system register
 *
 * 63___ _ ___32_31___ _ ___24_23_____20_19_____16_15__ _ __4_3_______0
 * |            |             |         |         |          |        |
 * |RES0        | Implementer | Variant | Arch    | PartNum  |Revision|
 * |____ _ _____|_____ _ _____|_________|_______ _|____ _ ___|________|
 *
 */

# define ARM_CPU_IMP_ARM           0x41
# define HISI_CPU_IMP              0x48
# define ARM_CPU_IMP_APPLE         0x61

# define ARM_CPU_PART_CORTEX_A72   0xD08
# define ARM_CPU_PART_N1           0xD0C
# define ARM_CPU_PART_V1           0xD40
# define ARM_CPU_PART_N2           0xD49
# define HISI_CPU_PART_KP920       0xD01
# define ARM_CPU_PART_V2           0xD4F

# define APPLE_CPU_PART_M1_ICESTORM         0x022
# define APPLE_CPU_PART_M1_FIRESTORM        0x023
# define APPLE_CPU_PART_M1_ICESTORM_PRO     0x024
# define APPLE_CPU_PART_M1_FIRESTORM_PRO    0x025
# define APPLE_CPU_PART_M1_ICESTORM_MAX     0x028
# define APPLE_CPU_PART_M1_FIRESTORM_MAX    0x029
# define APPLE_CPU_PART_M2_BLIZZARD         0x032
# define APPLE_CPU_PART_M2_AVALANCHE        0x033
# define APPLE_CPU_PART_M2_BLIZZARD_PRO     0x034
# define APPLE_CPU_PART_M2_AVALANCHE_PRO    0x035
# define APPLE_CPU_PART_M2_BLIZZARD_MAX     0x038
# define APPLE_CPU_PART_M2_AVALANCHE_MAX    0x039

# define MIDR_PARTNUM_SHIFT       4
# define MIDR_PARTNUM_MASK        (0xfffU << MIDR_PARTNUM_SHIFT)
# define MIDR_PARTNUM(midr)       \
           (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)

# define MIDR_IMPLEMENTER_SHIFT   24
# define MIDR_IMPLEMENTER_MASK    (0xffU << MIDR_IMPLEMENTER_SHIFT)
# define MIDR_IMPLEMENTER(midr)   \
           (((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)

# define MIDR_ARCHITECTURE_SHIFT  16
# define MIDR_ARCHITECTURE_MASK   (0xfU << MIDR_ARCHITECTURE_SHIFT)
# define MIDR_ARCHITECTURE(midr)  \
           (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)

# define MIDR_CPU_MODEL_MASK \
           (MIDR_IMPLEMENTER_MASK | \
            MIDR_PARTNUM_MASK     | \
            MIDR_ARCHITECTURE_MASK)

# define MIDR_CPU_MODEL(imp, partnum) \
           (((imp)     << MIDR_IMPLEMENTER_SHIFT)  | \
            (0xfU      << MIDR_ARCHITECTURE_SHIFT) | \
            ((partnum) << MIDR_PARTNUM_SHIFT))

# define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
           (((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))

#if defined(__ASSEMBLER__)

   /*
    * Support macros for
    *   - Armv8.3-A Pointer Authentication and
    *   - Armv8.5-A Branch Target Identification
    * features which require emitting a .note.gnu.property section with the
    * appropriate architecture-dependent feature bits set.
    * Read more: "ELF for the Arm® 64-bit Architecture"
    */

#  if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT == 1
#   define GNU_PROPERTY_AARCH64_BTI (1 << 0)   /* Has Branch Target Identification */
#   define AARCH64_VALID_CALL_TARGET hint #34  /* BTI 'c' */
#  else
#   define GNU_PROPERTY_AARCH64_BTI 0  /* No Branch Target Identification */
#   define AARCH64_VALID_CALL_TARGET
#  endif

#  if defined(__ARM_FEATURE_PAC_DEFAULT) && \
       (__ARM_FEATURE_PAC_DEFAULT & 1) == 1  /* Signed with A-key */
#   define GNU_PROPERTY_AARCH64_POINTER_AUTH \
     (1 << 1)                                       /* Has Pointer Authentication */
#   define AARCH64_SIGN_LINK_REGISTER hint #25      /* PACIASP */
#   define AARCH64_VALIDATE_LINK_REGISTER hint #29  /* AUTIASP */
#  elif defined(__ARM_FEATURE_PAC_DEFAULT) && \
       (__ARM_FEATURE_PAC_DEFAULT & 2) == 2  /* Signed with B-key */
#   define GNU_PROPERTY_AARCH64_POINTER_AUTH \
     (1 << 1)                                       /* Has Pointer Authentication */
#   define AARCH64_SIGN_LINK_REGISTER hint #27      /* PACIBSP */
#   define AARCH64_VALIDATE_LINK_REGISTER hint #31  /* AUTIBSP */
#  else
#   define GNU_PROPERTY_AARCH64_POINTER_AUTH 0  /* No Pointer Authentication */
#   if GNU_PROPERTY_AARCH64_BTI != 0
#    define AARCH64_SIGN_LINK_REGISTER AARCH64_VALID_CALL_TARGET
#   else
#    define AARCH64_SIGN_LINK_REGISTER
#   endif
#   define AARCH64_VALIDATE_LINK_REGISTER
#  endif

#  if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 || GNU_PROPERTY_AARCH64_BTI != 0
    .pushsection .note.gnu.property, "a";
    .balign 8;
    .long 4;
    .long 0x10;
    .long 0x5;
    .asciz "GNU";
    .long 0xc0000000; /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */
    .long 4;
    .long (GNU_PROPERTY_AARCH64_POINTER_AUTH | GNU_PROPERTY_AARCH64_BTI);
    .long 0;
    .popsection;
#  endif

# endif  /* defined __ASSEMBLER__ */

# define IS_CPU_SUPPORT_UNROLL8_EOR3() \
           (OPENSSL_armcap_P & ARMV8_UNROLL8_EOR3)

#endif
Commit	Line	Data
d2e9e320	1	/*
da1c088f	2	* Copyright 2011-2023 The OpenSSL Project Authors. All Rights Reserved.
d2e9e320	3	*
0e9725bc	4	* Licensed under the Apache License 2.0 (the "License"). You may not use
d2e9e320 RS	5	* this file except in compliance with the License. You can obtain a copy
	6	* in the file LICENSE in the source distribution or at
	7	* https://www.openssl.org/source/license.html
	8	*/
	9
ae4186b0 DMSP	10	#ifndef OSSL_CRYPTO_ARM_ARCH_H
ae4186b0 DMSP	11	# define OSSL_CRYPTO_ARM_ARCH_H
e5123751	12
0f113f3e MC	13	# if !defined(__ARM_ARCH__)
	14	# if defined(__CC_ARM)
	15	# define __ARM_ARCH__ __TARGET_ARCH_ARM
	16	# if defined(__BIG_ENDIAN)
e8d93e34 AP	17	# define __ARMEB__
	18	# else
	19	# define __ARMEL__
	20	# endif
0f113f3e MC	21	# elif defined(__GNUC__)
	22	# if defined(__aarch64__)
	23	# define __ARM_ARCH__ 8
e5123751 AP	24	/*
e5123751 AP	25	* Why doesn't gcc define __ARM_ARCH__? Instead it defines
46f4e1be	26	* bunch of below macros. See all_architectures[] table in
e5123751 AP	27	* gcc/config/arm/arm.c. On a side note it defines
	28	* __ARMEL__/__ARMEB__ for little-/big-endian.
	29	*/
0f113f3e MC	30	# elif defined(__ARM_ARCH)
	31	# define __ARM_ARCH__ __ARM_ARCH
	32	# elif defined(__ARM_ARCH_8A__)
	33	# define __ARM_ARCH__ 8
	34	# elif defined(__ARM_ARCH_7__) \|\| defined(__ARM_ARCH_7A__) \|\| \
	35	defined(__ARM_ARCH_7R__)\|\| defined(__ARM_ARCH_7M__) \|\| \
	36	defined(__ARM_ARCH_7EM__)
	37	# define __ARM_ARCH__ 7
	38	# elif defined(__ARM_ARCH_6__) \|\| defined(__ARM_ARCH_6J__) \|\| \
	39	defined(__ARM_ARCH_6K__)\|\| defined(__ARM_ARCH_6M__) \|\| \
	40	defined(__ARM_ARCH_6Z__)\|\| defined(__ARM_ARCH_6ZK__) \|\| \
	41	defined(__ARM_ARCH_6T2__)
	42	# define __ARM_ARCH__ 6
	43	# elif defined(__ARM_ARCH_5__) \|\| defined(__ARM_ARCH_5T__) \|\| \
	44	defined(__ARM_ARCH_5E__)\|\| defined(__ARM_ARCH_5TE__) \|\| \
	45	defined(__ARM_ARCH_5TEJ__)
	46	# define __ARM_ARCH__ 5
	47	# elif defined(__ARM_ARCH_4__) \|\| defined(__ARM_ARCH_4T__)
	48	# define __ARM_ARCH__ 4
	49	# else
	50	# error "unsupported ARM architecture"
	51	# endif
636ee1d0 EK	52	# elif defined(__ARM_ARCH)
636ee1d0 EK	53	# define __ARM_ARCH__ __ARM_ARCH
e5123751 AP	54	# endif
	55	# endif
	56
0f113f3e MC	57	# if !defined(__ARM_MAX_ARCH__)
	58	# define __ARM_MAX_ARCH__ __ARM_ARCH__
	59	# endif
c1669e1c	60
0f113f3e MC	61	# if __ARM_MAX_ARCH__<__ARM_ARCH__
	62	# error "__ARM_MAX_ARCH__ can't be less than __ARM_ARCH__"
	63	# elif __ARM_MAX_ARCH__!=__ARM_ARCH__
	64	# if __ARM_ARCH__<7 && __ARM_MAX_ARCH__>=7 && defined(__ARMEB__)
	65	# error "can't build universal big-endian binary"
	66	# endif
c1669e1c	67	# endif
c1669e1c	68
0e0f8116	69	# ifndef __ASSEMBLER__
87873f43	70	extern unsigned int OPENSSL_armcap_P;
5ea64b45	71	extern unsigned int OPENSSL_arm_midr;
2bdec3b0	72	extern unsigned int OPENSSL_armv8_rsa_neonized;
0f113f3e MC	73	# endif
	74
	75	# define ARMV7_NEON (1<<0)
	76	# define ARMV7_TICK (1<<1)
	77	# define ARMV8_AES (1<<2)
	78	# define ARMV8_SHA1 (1<<3)
	79	# define ARMV8_SHA256 (1<<4)
	80	# define ARMV8_PMULL (1<<5)
77f3612e	81	# define ARMV8_SHA512 (1<<6)
5ea64b45	82	# define ARMV8_CPUID (1<<7)
efa1f224	83	# define ARMV8_RNG (1<<8)
71396cd0	84	# define ARMV8_SM3 (1<<9)
15b7175f	85	# define ARMV8_SM4 (1<<10)
954f45ba X	86	# define ARMV8_SHA3 (1<<11)
954f45ba X	87	# define ARMV8_UNROLL8_EOR3 (1<<12)
b1b2146d DH	88	# define ARMV8_SVE (1<<13)
b1b2146d DH	89	# define ARMV8_SVE2 (1<<14)
ba9472c1	90	# define ARMV8_HAVE_SHA3_AND_WORTH_USING (1<<15)
cc82b09c	91	# define ARMV8_UNROLL12_EOR3 (1<<16)
87873f43	92
5ea64b45 FF	93	/*
	94	* MIDR_EL1 system register
	95	*
	96	* 63___ _ ___32_31___ _ ___24_23_____20_19_____16_15__ _ __4_3_______0
	97	* \| \| \| \| \| \| \|
	98	* \|RES0 \| Implementer \| Variant \| Arch \| PartNum \|Revision\|
	99	* \|____ _ _____\|_____ _ _____\|_________\|_______ _\|____ _ ___\|________\|
	100	*
	101	*/
	102
	103	# define ARM_CPU_IMP_ARM 0x41
88c53cf1	104	# define HISI_CPU_IMP 0x48
f6484de2	105	# define ARM_CPU_IMP_APPLE 0x61
5ea64b45 FF	106
	107	# define ARM_CPU_PART_CORTEX_A72 0xD08
	108	# define ARM_CPU_PART_N1 0xD0C
954f45ba	109	# define ARM_CPU_PART_V1 0xD40
9224a407	110	# define ARM_CPU_PART_N2 0xD49
88c53cf1	111	# define HISI_CPU_PART_KP920 0xD01
513e103f	112	# define ARM_CPU_PART_V2 0xD4F
5ea64b45	113
f6484de2	114	# define APPLE_CPU_PART_M1_ICESTORM 0x022
	115	# define APPLE_CPU_PART_M1_FIRESTORM 0x023
	116	# define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
	117	# define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
	118	# define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
	119	# define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
	120	# define APPLE_CPU_PART_M2_BLIZZARD 0x032
	121	# define APPLE_CPU_PART_M2_AVALANCHE 0x033
	122	# define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
	123	# define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
	124	# define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
	125	# define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
	126
5ea64b45	127	# define MIDR_PARTNUM_SHIFT 4
1efd8533	128	# define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
5ea64b45 FF	129	# define MIDR_PARTNUM(midr) \
	130	(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
	131
	132	# define MIDR_IMPLEMENTER_SHIFT 24
1efd8533	133	# define MIDR_IMPLEMENTER_MASK (0xffU << MIDR_IMPLEMENTER_SHIFT)
5ea64b45 FF	134	# define MIDR_IMPLEMENTER(midr) \
	135	(((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
	136
	137	# define MIDR_ARCHITECTURE_SHIFT 16
1efd8533	138	# define MIDR_ARCHITECTURE_MASK (0xfU << MIDR_ARCHITECTURE_SHIFT)
5ea64b45 FF	139	# define MIDR_ARCHITECTURE(midr) \
	140	(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
	141
	142	# define MIDR_CPU_MODEL_MASK \
	143	(MIDR_IMPLEMENTER_MASK \| \
	144	MIDR_PARTNUM_MASK \| \
	145	MIDR_ARCHITECTURE_MASK)
	146
	147	# define MIDR_CPU_MODEL(imp, partnum) \
	148	(((imp) << MIDR_IMPLEMENTER_SHIFT) \| \
1efd8533	149	(0xfU << MIDR_ARCHITECTURE_SHIFT) \| \
5ea64b45 FF	150	((partnum) << MIDR_PARTNUM_SHIFT))
	151
	152	# define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
	153	(((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
19e277dd RB	154
	155	#if defined(__ASSEMBLER__)
	156
	157	/*
	158	* Support macros for
	159	* - Armv8.3-A Pointer Authentication and
	160	* - Armv8.5-A Branch Target Identification
	161	* features which require emitting a .note.gnu.property section with the
	162	* appropriate architecture-dependent feature bits set.
	163	* Read more: "ELF for the Arm® 64-bit Architecture"
	164	*/
	165
	166	# if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT == 1
	167	# define GNU_PROPERTY_AARCH64_BTI (1 << 0) /* Has Branch Target Identification */
	168	# define AARCH64_VALID_CALL_TARGET hint #34 /* BTI 'c' */
	169	# else
	170	# define GNU_PROPERTY_AARCH64_BTI 0 /* No Branch Target Identification */
	171	# define AARCH64_VALID_CALL_TARGET
	172	# endif
	173
	174	# if defined(__ARM_FEATURE_PAC_DEFAULT) && \
	175	(__ARM_FEATURE_PAC_DEFAULT & 1) == 1 /* Signed with A-key */
	176	# define GNU_PROPERTY_AARCH64_POINTER_AUTH \
	177	(1 << 1) /* Has Pointer Authentication */
	178	# define AARCH64_SIGN_LINK_REGISTER hint #25 /* PACIASP */
	179	# define AARCH64_VALIDATE_LINK_REGISTER hint #29 /* AUTIASP */
	180	# elif defined(__ARM_FEATURE_PAC_DEFAULT) && \
	181	(__ARM_FEATURE_PAC_DEFAULT & 2) == 2 /* Signed with B-key */
	182	# define GNU_PROPERTY_AARCH64_POINTER_AUTH \
	183	(1 << 1) /* Has Pointer Authentication */
	184	# define AARCH64_SIGN_LINK_REGISTER hint #27 /* PACIBSP */
	185	# define AARCH64_VALIDATE_LINK_REGISTER hint #31 /* AUTIBSP */
	186	# else
	187	# define GNU_PROPERTY_AARCH64_POINTER_AUTH 0 /* No Pointer Authentication */
	188	# if GNU_PROPERTY_AARCH64_BTI != 0
	189	# define AARCH64_SIGN_LINK_REGISTER AARCH64_VALID_CALL_TARGET
	190	# else
	191	# define AARCH64_SIGN_LINK_REGISTER
	192	# endif
	193	# define AARCH64_VALIDATE_LINK_REGISTER
	194	# endif
	195
	196	# if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 \|\| GNU_PROPERTY_AARCH64_BTI != 0
	197	.pushsection .note.gnu.property, "a";
	198	.balign 8;
	199	.long 4;
	200	.long 0x10;
	201	.long 0x5;
	202	.asciz "GNU";
	203	.long 0xc0000000; /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */
	204	.long 4;
	205	.long (GNU_PROPERTY_AARCH64_POINTER_AUTH \| GNU_PROPERTY_AARCH64_BTI);
	206	.long 0;
	207	.popsection;
	208	# endif
	209
	210	# endif /* defined __ASSEMBLER__ */
	211
954f45ba X	212	# define IS_CPU_SUPPORT_UNROLL8_EOR3() \
	213	(OPENSSL_armcap_P & ARMV8_UNROLL8_EOR3)
	214
e5123751	215	#endif