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52c0d300 | 1 | .explicit |
4cb73bf8 | 2 | .text |
e2f2a9af | 3 | .ident "ia64.S, Version 2.1" |
e3713c36 | 4 | .ident "IA-64 ISA artwork by Andy Polyakov <appro@openssl.org>" |
4cb73bf8 | 5 | |
44c8a5e2 RS |
6 | // Copyright 2001-2016 The OpenSSL Project Authors. All Rights Reserved. |
7 | // | |
8 | // Licensed under the OpenSSL license (the "License"). You may not use | |
9 | // this file except in compliance with the License. You can obtain a copy | |
10 | // in the file LICENSE in the source distribution or at | |
11 | // https://www.openssl.org/source/license.html | |
12 | ||
4cb73bf8 AP |
13 | // |
14 | // ==================================================================== | |
e3713c36 | 15 | // Written by Andy Polyakov <appro@openssl.org> for the OpenSSL |
4cb73bf8 AP |
16 | // project. |
17 | // | |
18 | // Rights for redistribution and usage in source and binary forms are | |
19 | // granted according to the OpenSSL license. Warranty of any kind is | |
20 | // disclaimed. | |
21 | // ==================================================================== | |
22 | // | |
46f4e1be | 23 | // Version 2.x is Itanium2 re-tune. Few words about how Itanium2 is |
722d17cb AP |
24 | // different from Itanium to this module viewpoint. Most notably, is it |
25 | // "wider" than Itanium? Can you experience loop scalability as | |
26 | // discussed in commentary sections? Not really:-( Itanium2 has 6 | |
27 | // integer ALU ports, i.e. it's 2 ports wider, but it's not enough to | |
28 | // spin twice as fast, as I need 8 IALU ports. Amount of floating point | |
29 | // ports is the same, i.e. 2, while I need 4. In other words, to this | |
30 | // module Itanium2 remains effectively as "wide" as Itanium. Yet it's | |
31 | // essentially different in respect to this module, and a re-tune was | |
60250017 | 32 | // required. Well, because some instruction latencies has changed. Most |
722d17cb AP |
33 | // noticeably those intensively used: |
34 | // | |
35 | // Itanium Itanium2 | |
36 | // ldf8 9 6 L2 hit | |
37 | // ld8 2 1 L1 hit | |
38 | // getf 2 5 | |
39 | // xma[->getf] 7[+1] 4[+0] | |
40 | // add[->st8] 1[+1] 1[+0] | |
41 | // | |
42 | // What does it mean? You might ratiocinate that the original code | |
43 | // should run just faster... Because sum of latencies is smaller... | |
44 | // Wrong! Note that getf latency increased. This means that if a loop is | |
e2f2a9af | 45 | // scheduled for lower latency (as they were), then it will suffer from |
722d17cb AP |
46 | // stall condition and the code will therefore turn anti-scalable, e.g. |
47 | // original bn_mul_words spun at 5*n or 2.5 times slower than expected | |
48 | // on Itanium2! What to do? Reschedule loops for Itanium2? But then | |
49 | // Itanium would exhibit anti-scalability. So I've chosen to reschedule | |
50 | // for worst latency for every instruction aiming for best *all-round* | |
51 | // performance. | |
4cb73bf8 AP |
52 | |
53 | // Q. How much faster does it get? | |
54 | // A. Here is the output from 'openssl speed rsa dsa' for vanilla | |
55 | // 0.9.6a compiled with gcc version 2.96 20000731 (Red Hat | |
56 | // Linux 7.1 2.96-81): | |
57 | // | |
58 | // sign verify sign/s verify/s | |
59 | // rsa 512 bits 0.0036s 0.0003s 275.3 2999.2 | |
60 | // rsa 1024 bits 0.0203s 0.0011s 49.3 894.1 | |
61 | // rsa 2048 bits 0.1331s 0.0040s 7.5 250.9 | |
62 | // rsa 4096 bits 0.9270s 0.0147s 1.1 68.1 | |
63 | // sign verify sign/s verify/s | |
64 | // dsa 512 bits 0.0035s 0.0043s 288.3 234.8 | |
65 | // dsa 1024 bits 0.0111s 0.0135s 90.0 74.2 | |
66 | // | |
67 | // And here is similar output but for this assembler | |
68 | // implementation:-) | |
69 | // | |
70 | // sign verify sign/s verify/s | |
71 | // rsa 512 bits 0.0021s 0.0001s 549.4 9638.5 | |
72 | // rsa 1024 bits 0.0055s 0.0002s 183.8 4481.1 | |
73 | // rsa 2048 bits 0.0244s 0.0006s 41.4 1726.3 | |
74 | // rsa 4096 bits 0.1295s 0.0018s 7.7 561.5 | |
75 | // sign verify sign/s verify/s | |
76 | // dsa 512 bits 0.0012s 0.0013s 891.9 756.6 | |
77 | // dsa 1024 bits 0.0023s 0.0028s 440.4 376.2 | |
78 | // | |
79 | // Yes, you may argue that it's not fair comparison as it's | |
80 | // possible to craft the C implementation with BN_UMULT_HIGH | |
81 | // inline assembler macro. But of course! Here is the output | |
82 | // with the macro: | |
83 | // | |
84 | // sign verify sign/s verify/s | |
85 | // rsa 512 bits 0.0020s 0.0002s 495.0 6561.0 | |
86 | // rsa 1024 bits 0.0086s 0.0004s 116.2 2235.7 | |
87 | // rsa 2048 bits 0.0519s 0.0015s 19.3 667.3 | |
88 | // rsa 4096 bits 0.3464s 0.0053s 2.9 187.7 | |
89 | // sign verify sign/s verify/s | |
90 | // dsa 512 bits 0.0016s 0.0020s 613.1 510.5 | |
91 | // dsa 1024 bits 0.0045s 0.0054s 221.0 183.9 | |
92 | // | |
93 | // My code is still way faster, huh:-) And I believe that even | |
94 | // higher performance can be achieved. Note that as keys get | |
95 | // longer, performance gain is larger. Why? According to the | |
96 | // profiler there is another player in the field, namely | |
97 | // BN_from_montgomery consuming larger and larger portion of CPU | |
98 | // time as keysize decreases. I therefore consider putting effort | |
99 | // to assembler implementation of the following routine: | |
100 | // | |
101 | // void bn_mul_add_mont (BN_ULONG *rp,BN_ULONG *np,int nl,BN_ULONG n0) | |
102 | // { | |
103 | // int i,j; | |
104 | // BN_ULONG v; | |
105 | // | |
106 | // for (i=0; i<nl; i++) | |
107 | // { | |
108 | // v=bn_mul_add_words(rp,np,nl,(rp[0]*n0)&BN_MASK2); | |
109 | // nrp++; | |
110 | // rp++; | |
111 | // if (((nrp[-1]+=v)&BN_MASK2) < v) | |
112 | // for (j=0; ((++nrp[j])&BN_MASK2) == 0; j++) ; | |
113 | // } | |
114 | // } | |
115 | // | |
116 | // It might as well be beneficial to implement even combaX | |
117 | // variants, as it appears as it can literally unleash the | |
118 | // performance (see comment section to bn_mul_comba8 below). | |
119 | // | |
120 | // And finally for your reference the output for 0.9.6a compiled | |
121 | // with SGIcc version 0.01.0-12 (keep in mind that for the moment | |
122 | // of this writing it's not possible to convince SGIcc to use | |
123 | // BN_UMULT_HIGH inline assembler macro, yet the code is fast, | |
124 | // i.e. for a compiler generated one:-): | |
125 | // | |
126 | // sign verify sign/s verify/s | |
127 | // rsa 512 bits 0.0022s 0.0002s 452.7 5894.3 | |
128 | // rsa 1024 bits 0.0097s 0.0005s 102.7 2002.9 | |
129 | // rsa 2048 bits 0.0578s 0.0017s 17.3 600.2 | |
130 | // rsa 4096 bits 0.3838s 0.0061s 2.6 164.5 | |
131 | // sign verify sign/s verify/s | |
132 | // dsa 512 bits 0.0018s 0.0022s 547.3 459.6 | |
133 | // dsa 1024 bits 0.0051s 0.0062s 196.6 161.3 | |
134 | // | |
135 | // Oh! Benchmarks were performed on 733MHz Lion-class Itanium | |
136 | // system running Redhat Linux 7.1 (very special thanks to Ray | |
137 | // McCaffity of Williams Communications for providing an account). | |
138 | // | |
139 | // Q. What's the heck with 'rum 1<<5' at the end of every function? | |
140 | // A. Well, by clearing the "upper FP registers written" bit of the | |
141 | // User Mask I want to excuse the kernel from preserving upper | |
142 | // (f32-f128) FP register bank over process context switch, thus | |
143 | // minimizing bus bandwidth consumption during the switch (i.e. | |
46f4e1be | 144 | // after PKI operation completes and the program is off doing |
4cb73bf8 AP |
145 | // something else like bulk symmetric encryption). Having said |
146 | // this, I also want to point out that it might be good idea | |
147 | // to compile the whole toolkit (as well as majority of the | |
148 | // programs for that matter) with -mfixed-range=f32-f127 command | |
149 | // line option. No, it doesn't prevent the compiler from writing | |
150 | // to upper bank, but at least discourages to do so. If you don't | |
151 | // like the idea you have the option to compile the module with | |
152 | // -Drum=nop.m in command line. | |
153 | // | |
154 | ||
e2f2a9af AP |
155 | #if defined(_HPUX_SOURCE) && !defined(_LP64) |
156 | #define ADDP addp4 | |
157 | #else | |
158 | #define ADDP add | |
159 | #endif | |
160 | ||
4cb73bf8 AP |
161 | #if 1 |
162 | // | |
163 | // bn_[add|sub]_words routines. | |
164 | // | |
46f4e1be | 165 | // Loops are spinning in 2*(n+5) ticks on Itanium (provided that the |
4cb73bf8 AP |
166 | // data reside in L1 cache, i.e. 2 ticks away). It's possible to |
167 | // compress the epilogue and get down to 2*n+6, but at the cost of | |
168 | // scalability (the neat feature of this implementation is that it | |
169 | // shall automagically spin in n+5 on "wider" IA-64 implementations:-) | |
170 | // I consider that the epilogue is short enough as it is to trade tiny | |
171 | // performance loss on Itanium for scalability. | |
172 | // | |
173 | // BN_ULONG bn_add_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num) | |
174 | // | |
175 | .global bn_add_words# | |
176 | .proc bn_add_words# | |
177 | .align 64 | |
622d3d35 | 178 | .skip 32 // makes the loop body aligned at 64-byte boundary |
4cb73bf8 AP |
179 | bn_add_words: |
180 | .prologue | |
4cb73bf8 | 181 | .save ar.pfs,r2 |
622d3d35 | 182 | { .mii; alloc r2=ar.pfs,4,12,0,16 |
4cb73bf8 | 183 | cmp4.le p6,p0=r35,r0 };; |
622d3d35 | 184 | { .mfb; mov r8=r0 // return value |
4cb73bf8 AP |
185 | (p6) br.ret.spnt.many b0 };; |
186 | ||
622d3d35 | 187 | { .mib; sub r10=r35,r0,1 |
ef428d56 | 188 | .save ar.lc,r3 |
4cb73bf8 AP |
189 | mov r3=ar.lc |
190 | brp.loop.imp .L_bn_add_words_ctop,.L_bn_add_words_cend-16 | |
191 | } | |
e2f2a9af | 192 | { .mib; ADDP r14=0,r32 // rp |
7cfe2a5e | 193 | .save pr,r9 |
4cb73bf8 | 194 | mov r9=pr };; |
7cfe2a5e | 195 | .body |
e2f2a9af | 196 | { .mii; ADDP r15=0,r33 // ap |
4cb73bf8 AP |
197 | mov ar.lc=r10 |
198 | mov ar.ec=6 } | |
e2f2a9af | 199 | { .mib; ADDP r16=0,r34 // bp |
622d3d35 | 200 | mov pr.rot=1<<16 };; |
4cb73bf8 | 201 | |
622d3d35 AP |
202 | .L_bn_add_words_ctop: |
203 | { .mii; (p16) ld8 r32=[r16],8 // b=*(bp++) | |
4cb73bf8 AP |
204 | (p18) add r39=r37,r34 |
205 | (p19) cmp.ltu.unc p56,p0=r40,r38 } | |
622d3d35 | 206 | { .mfb; (p0) nop.m 0x0 |
4cb73bf8 AP |
207 | (p0) nop.f 0x0 |
208 | (p0) nop.b 0x0 } | |
622d3d35 | 209 | { .mii; (p16) ld8 r35=[r15],8 // a=*(ap++) |
4cb73bf8 AP |
210 | (p58) cmp.eq.or p57,p0=-1,r41 // (p20) |
211 | (p58) add r41=1,r41 } // (p20) | |
622d3d35 | 212 | { .mfb; (p21) st8 [r14]=r42,8 // *(rp++)=r |
4cb73bf8 AP |
213 | (p0) nop.f 0x0 |
214 | br.ctop.sptk .L_bn_add_words_ctop };; | |
215 | .L_bn_add_words_cend: | |
216 | ||
622d3d35 | 217 | { .mii; |
4cb73bf8 | 218 | (p59) add r8=1,r8 // return value |
46a0d4fb | 219 | mov pr=r9,0x1ffff |
4cb73bf8 | 220 | mov ar.lc=r3 } |
622d3d35 | 221 | { .mbb; nop.b 0x0 |
4cb73bf8 AP |
222 | br.ret.sptk.many b0 };; |
223 | .endp bn_add_words# | |
224 | ||
225 | // | |
226 | // BN_ULONG bn_sub_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num) | |
227 | // | |
228 | .global bn_sub_words# | |
229 | .proc bn_sub_words# | |
230 | .align 64 | |
622d3d35 | 231 | .skip 32 // makes the loop body aligned at 64-byte boundary |
4cb73bf8 AP |
232 | bn_sub_words: |
233 | .prologue | |
4cb73bf8 | 234 | .save ar.pfs,r2 |
622d3d35 | 235 | { .mii; alloc r2=ar.pfs,4,12,0,16 |
4cb73bf8 | 236 | cmp4.le p6,p0=r35,r0 };; |
622d3d35 | 237 | { .mfb; mov r8=r0 // return value |
4cb73bf8 AP |
238 | (p6) br.ret.spnt.many b0 };; |
239 | ||
622d3d35 | 240 | { .mib; sub r10=r35,r0,1 |
ef428d56 | 241 | .save ar.lc,r3 |
4cb73bf8 AP |
242 | mov r3=ar.lc |
243 | brp.loop.imp .L_bn_sub_words_ctop,.L_bn_sub_words_cend-16 | |
244 | } | |
e2f2a9af | 245 | { .mib; ADDP r14=0,r32 // rp |
7cfe2a5e | 246 | .save pr,r9 |
4cb73bf8 | 247 | mov r9=pr };; |
7cfe2a5e | 248 | .body |
e2f2a9af | 249 | { .mii; ADDP r15=0,r33 // ap |
4cb73bf8 AP |
250 | mov ar.lc=r10 |
251 | mov ar.ec=6 } | |
e2f2a9af | 252 | { .mib; ADDP r16=0,r34 // bp |
622d3d35 | 253 | mov pr.rot=1<<16 };; |
4cb73bf8 | 254 | |
622d3d35 AP |
255 | .L_bn_sub_words_ctop: |
256 | { .mii; (p16) ld8 r32=[r16],8 // b=*(bp++) | |
4cb73bf8 AP |
257 | (p18) sub r39=r37,r34 |
258 | (p19) cmp.gtu.unc p56,p0=r40,r38 } | |
622d3d35 | 259 | { .mfb; (p0) nop.m 0x0 |
4cb73bf8 AP |
260 | (p0) nop.f 0x0 |
261 | (p0) nop.b 0x0 } | |
622d3d35 | 262 | { .mii; (p16) ld8 r35=[r15],8 // a=*(ap++) |
4cb73bf8 AP |
263 | (p58) cmp.eq.or p57,p0=0,r41 // (p20) |
264 | (p58) add r41=-1,r41 } // (p20) | |
622d3d35 | 265 | { .mbb; (p21) st8 [r14]=r42,8 // *(rp++)=r |
4cb73bf8 AP |
266 | (p0) nop.b 0x0 |
267 | br.ctop.sptk .L_bn_sub_words_ctop };; | |
268 | .L_bn_sub_words_cend: | |
269 | ||
622d3d35 | 270 | { .mii; |
4cb73bf8 | 271 | (p59) add r8=1,r8 // return value |
46a0d4fb | 272 | mov pr=r9,0x1ffff |
4cb73bf8 | 273 | mov ar.lc=r3 } |
622d3d35 | 274 | { .mbb; nop.b 0x0 |
4cb73bf8 AP |
275 | br.ret.sptk.many b0 };; |
276 | .endp bn_sub_words# | |
277 | #endif | |
278 | ||
279 | #if 0 | |
280 | #define XMA_TEMPTATION | |
281 | #endif | |
282 | ||
283 | #if 1 | |
284 | // | |
285 | // BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w) | |
286 | // | |
287 | .global bn_mul_words# | |
288 | .proc bn_mul_words# | |
289 | .align 64 | |
622d3d35 | 290 | .skip 32 // makes the loop body aligned at 64-byte boundary |
4cb73bf8 AP |
291 | bn_mul_words: |
292 | .prologue | |
4cb73bf8 AP |
293 | .save ar.pfs,r2 |
294 | #ifdef XMA_TEMPTATION | |
622d3d35 | 295 | { .mfi; alloc r2=ar.pfs,4,0,0,0 };; |
4cb73bf8 | 296 | #else |
722d17cb | 297 | { .mfi; alloc r2=ar.pfs,4,12,0,16 };; |
4cb73bf8 | 298 | #endif |
622d3d35 | 299 | { .mib; mov r8=r0 // return value |
4cb73bf8 AP |
300 | cmp4.le p6,p0=r34,r0 |
301 | (p6) br.ret.spnt.many b0 };; | |
302 | ||
622d3d35 | 303 | { .mii; sub r10=r34,r0,1 |
ef428d56 | 304 | .save ar.lc,r3 |
4cb73bf8 | 305 | mov r3=ar.lc |
7cfe2a5e | 306 | .save pr,r9 |
4cb73bf8 AP |
307 | mov r9=pr };; |
308 | ||
309 | .body | |
622d3d35 | 310 | { .mib; setf.sig f8=r35 // w |
722d17cb AP |
311 | mov pr.rot=0x800001<<16 |
312 | // ------^----- serves as (p50) at first (p27) | |
4cb73bf8 AP |
313 | brp.loop.imp .L_bn_mul_words_ctop,.L_bn_mul_words_cend-16 |
314 | } | |
315 | ||
316 | #ifndef XMA_TEMPTATION | |
317 | ||
e2f2a9af AP |
318 | { .mmi; ADDP r14=0,r32 // rp |
319 | ADDP r15=0,r33 // ap | |
4cb73bf8 | 320 | mov ar.lc=r10 } |
e2f2a9af | 321 | { .mmi; mov r40=0 // serves as r35 at first (p27) |
722d17cb | 322 | mov ar.ec=13 };; |
4cb73bf8 | 323 | |
722d17cb AP |
324 | // This loop spins in 2*(n+12) ticks. It's scheduled for data in Itanium |
325 | // L2 cache (i.e. 9 ticks away) as floating point load/store instructions | |
4cb73bf8 | 326 | // bypass L1 cache and L2 latency is actually best-case scenario for |
722d17cb AP |
327 | // ldf8. The loop is not scalable and shall run in 2*(n+12) even on |
328 | // "wider" IA-64 implementations. It's a trade-off here. n+24 loop | |
4cb73bf8 AP |
329 | // would give us ~5% in *overall* performance improvement on "wider" |
330 | // IA-64, but would hurt Itanium for about same because of longer | |
331 | // epilogue. As it's a matter of few percents in either case I've | |
332 | // chosen to trade the scalability for development time (you can see | |
333 | // this very instruction sequence in bn_mul_add_words loop which in | |
334 | // turn is scalable). | |
622d3d35 | 335 | .L_bn_mul_words_ctop: |
722d17cb AP |
336 | { .mfi; (p25) getf.sig r36=f52 // low |
337 | (p21) xmpy.lu f48=f37,f8 | |
338 | (p28) cmp.ltu p54,p50=r41,r39 } | |
622d3d35 | 339 | { .mfi; (p16) ldf8 f32=[r15],8 |
722d17cb | 340 | (p21) xmpy.hu f40=f37,f8 |
4cb73bf8 | 341 | (p0) nop.i 0x0 };; |
722d17cb AP |
342 | { .mii; (p25) getf.sig r32=f44 // high |
343 | .pred.rel "mutex",p50,p54 | |
344 | (p50) add r40=r38,r35 // (p27) | |
345 | (p54) add r40=r38,r35,1 } // (p27) | |
346 | { .mfb; (p28) st8 [r14]=r41,8 | |
4cb73bf8 AP |
347 | (p0) nop.f 0x0 |
348 | br.ctop.sptk .L_bn_mul_words_ctop };; | |
349 | .L_bn_mul_words_cend: | |
350 | ||
622d3d35 | 351 | { .mii; nop.m 0x0 |
722d17cb AP |
352 | .pred.rel "mutex",p51,p55 |
353 | (p51) add r8=r36,r0 | |
354 | (p55) add r8=r36,r0,1 } | |
622d3d35 | 355 | { .mfb; nop.m 0x0 |
4cb73bf8 AP |
356 | nop.f 0x0 |
357 | nop.b 0x0 } | |
358 | ||
359 | #else // XMA_TEMPTATION | |
360 | ||
361 | setf.sig f37=r0 // serves as carry at (p18) tick | |
362 | mov ar.lc=r10 | |
622d3d35 | 363 | mov ar.ec=5;; |
4cb73bf8 AP |
364 | |
365 | // Most of you examining this code very likely wonder why in the name | |
366 | // of Intel the following loop is commented out? Indeed, it looks so | |
367 | // neat that you find it hard to believe that it's something wrong | |
368 | // with it, right? The catch is that every iteration depends on the | |
369 | // result from previous one and the latter isn't available instantly. | |
370 | // The loop therefore spins at the latency of xma minus 1, or in other | |
371 | // words at 6*(n+4) ticks:-( Compare to the "production" loop above | |
372 | // that runs in 2*(n+11) where the low latency problem is worked around | |
60250017 | 373 | // by moving the dependency to one-tick latent integer ALU. Note that |
4cb73bf8 AP |
374 | // "distance" between ldf8 and xma is not latency of ldf8, but the |
375 | // *difference* between xma and ldf8 latencies. | |
622d3d35 AP |
376 | .L_bn_mul_words_ctop: |
377 | { .mfi; (p16) ldf8 f32=[r33],8 | |
4cb73bf8 | 378 | (p18) xma.hu f38=f34,f8,f39 } |
622d3d35 | 379 | { .mfb; (p20) stf8 [r32]=f37,8 |
4cb73bf8 AP |
380 | (p18) xma.lu f35=f34,f8,f39 |
381 | br.ctop.sptk .L_bn_mul_words_ctop };; | |
382 | .L_bn_mul_words_cend: | |
383 | ||
384 | getf.sig r8=f41 // the return value | |
385 | ||
386 | #endif // XMA_TEMPTATION | |
387 | ||
622d3d35 | 388 | { .mii; nop.m 0x0 |
46a0d4fb | 389 | mov pr=r9,0x1ffff |
4cb73bf8 | 390 | mov ar.lc=r3 } |
622d3d35 | 391 | { .mfb; rum 1<<5 // clear um.mfh |
4cb73bf8 AP |
392 | nop.f 0x0 |
393 | br.ret.sptk.many b0 };; | |
394 | .endp bn_mul_words# | |
395 | #endif | |
396 | ||
397 | #if 1 | |
398 | // | |
399 | // BN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w) | |
400 | // | |
401 | .global bn_mul_add_words# | |
402 | .proc bn_mul_add_words# | |
403 | .align 64 | |
e2f2a9af | 404 | .skip 48 // makes the loop body aligned at 64-byte boundary |
4cb73bf8 AP |
405 | bn_mul_add_words: |
406 | .prologue | |
4cb73bf8 | 407 | .save ar.pfs,r2 |
e2f2a9af AP |
408 | { .mmi; alloc r2=ar.pfs,4,4,0,8 |
409 | cmp4.le p6,p0=r34,r0 | |
ef428d56 | 410 | .save ar.lc,r3 |
e2f2a9af AP |
411 | mov r3=ar.lc };; |
412 | { .mib; mov r8=r0 // return value | |
413 | sub r10=r34,r0,1 | |
414 | (p6) br.ret.spnt.many b0 };; | |
4cb73bf8 | 415 | |
e2f2a9af | 416 | { .mib; setf.sig f8=r35 // w |
ef428d56 | 417 | .save pr,r9 |
e2f2a9af | 418 | mov r9=pr |
4cb73bf8 AP |
419 | brp.loop.imp .L_bn_mul_add_words_ctop,.L_bn_mul_add_words_cend-16 |
420 | } | |
7cfe2a5e | 421 | .body |
e2f2a9af AP |
422 | { .mmi; ADDP r14=0,r32 // rp |
423 | ADDP r15=0,r33 // ap | |
4cb73bf8 | 424 | mov ar.lc=r10 } |
e2f2a9af AP |
425 | { .mii; ADDP r16=0,r32 // rp copy |
426 | mov pr.rot=0x2001<<16 | |
427 | // ------^----- serves as (p40) at first (p27) | |
428 | mov ar.ec=11 };; | |
429 | ||
430 | // This loop spins in 3*(n+10) ticks on Itanium and in 2*(n+10) on | |
431 | // Itanium 2. Yes, unlike previous versions it scales:-) Previous | |
d900a015 | 432 | // version was performing *all* additions in IALU and was starving |
e2f2a9af AP |
433 | // for those even on Itanium 2. In this version one addition is |
434 | // moved to FPU and is folded with multiplication. This is at cost | |
60250017 | 435 | // of propagating the result from previous call to this subroutine |
e2f2a9af AP |
436 | // to L2 cache... In other words negligible even for shorter keys. |
437 | // *Overall* performance improvement [over previous version] varies | |
438 | // from 11 to 22 percent depending on key length. | |
622d3d35 | 439 | .L_bn_mul_add_words_ctop: |
e2f2a9af AP |
440 | .pred.rel "mutex",p40,p42 |
441 | { .mfi; (p23) getf.sig r36=f45 // low | |
442 | (p20) xma.lu f42=f36,f8,f50 // low | |
443 | (p40) add r39=r39,r35 } // (p27) | |
444 | { .mfi; (p16) ldf8 f32=[r15],8 // *(ap++) | |
445 | (p20) xma.hu f36=f36,f8,f50 // high | |
446 | (p42) add r39=r39,r35,1 };; // (p27) | |
447 | { .mmi; (p24) getf.sig r32=f40 // high | |
448 | (p16) ldf8 f46=[r16],8 // *(rp1++) | |
449 | (p40) cmp.ltu p41,p39=r39,r35 } // (p27) | |
450 | { .mib; (p26) st8 [r14]=r39,8 // *(rp2++) | |
451 | (p42) cmp.leu p41,p39=r39,r35 // (p27) | |
4cb73bf8 AP |
452 | br.ctop.sptk .L_bn_mul_add_words_ctop};; |
453 | .L_bn_mul_add_words_cend: | |
454 | ||
e2f2a9af AP |
455 | { .mmi; .pred.rel "mutex",p40,p42 |
456 | (p40) add r8=r35,r0 | |
457 | (p42) add r8=r35,r0,1 | |
458 | mov pr=r9,0x1ffff } | |
459 | { .mib; rum 1<<5 // clear um.mfh | |
460 | mov ar.lc=r3 | |
4cb73bf8 AP |
461 | br.ret.sptk.many b0 };; |
462 | .endp bn_mul_add_words# | |
463 | #endif | |
464 | ||
465 | #if 1 | |
466 | // | |
467 | // void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num) | |
468 | // | |
469 | .global bn_sqr_words# | |
470 | .proc bn_sqr_words# | |
471 | .align 64 | |
622d3d35 | 472 | .skip 32 // makes the loop body aligned at 64-byte boundary |
4cb73bf8 AP |
473 | bn_sqr_words: |
474 | .prologue | |
4cb73bf8 | 475 | .save ar.pfs,r2 |
622d3d35 | 476 | { .mii; alloc r2=ar.pfs,3,0,0,0 |
4cb73bf8 | 477 | sxt4 r34=r34 };; |
622d3d35 | 478 | { .mii; cmp.le p6,p0=r34,r0 |
4cb73bf8 | 479 | mov r8=r0 } // return value |
e2f2a9af AP |
480 | { .mfb; ADDP r32=0,r32 |
481 | nop.f 0x0 | |
4cb73bf8 AP |
482 | (p6) br.ret.spnt.many b0 };; |
483 | ||
622d3d35 | 484 | { .mii; sub r10=r34,r0,1 |
ef428d56 | 485 | .save ar.lc,r3 |
4cb73bf8 | 486 | mov r3=ar.lc |
ef428d56 | 487 | .save pr,r9 |
4cb73bf8 AP |
488 | mov r9=pr };; |
489 | ||
490 | .body | |
e2f2a9af | 491 | { .mib; ADDP r33=0,r33 |
4cb73bf8 AP |
492 | mov pr.rot=1<<16 |
493 | brp.loop.imp .L_bn_sqr_words_ctop,.L_bn_sqr_words_cend-16 | |
494 | } | |
622d3d35 | 495 | { .mii; add r34=8,r32 |
4cb73bf8 | 496 | mov ar.lc=r10 |
622d3d35 | 497 | mov ar.ec=18 };; |
4cb73bf8 AP |
498 | |
499 | // 2*(n+17) on Itanium, (n+17) on "wider" IA-64 implementations. It's | |
500 | // possible to compress the epilogue (I'm getting tired to write this | |
501 | // comment over and over) and get down to 2*n+16 at the cost of | |
502 | // scalability. The decision will very likely be reconsidered after the | |
46f4e1be | 503 | // benchmark program is profiled. I.e. if performance gain on Itanium |
4cb73bf8 | 504 | // will appear larger than loss on "wider" IA-64, then the loop should |
0d4fb843 | 505 | // be explicitly split and the epilogue compressed. |
622d3d35 AP |
506 | .L_bn_sqr_words_ctop: |
507 | { .mfi; (p16) ldf8 f32=[r33],8 | |
4cb73bf8 AP |
508 | (p25) xmpy.lu f42=f41,f41 |
509 | (p0) nop.i 0x0 } | |
622d3d35 | 510 | { .mib; (p33) stf8 [r32]=f50,16 |
4cb73bf8 AP |
511 | (p0) nop.i 0x0 |
512 | (p0) nop.b 0x0 } | |
622d3d35 | 513 | { .mfi; (p0) nop.m 0x0 |
4cb73bf8 AP |
514 | (p25) xmpy.hu f52=f41,f41 |
515 | (p0) nop.i 0x0 } | |
622d3d35 | 516 | { .mib; (p33) stf8 [r34]=f60,16 |
4cb73bf8 AP |
517 | (p0) nop.i 0x0 |
518 | br.ctop.sptk .L_bn_sqr_words_ctop };; | |
519 | .L_bn_sqr_words_cend: | |
520 | ||
622d3d35 | 521 | { .mii; nop.m 0x0 |
46a0d4fb | 522 | mov pr=r9,0x1ffff |
4cb73bf8 | 523 | mov ar.lc=r3 } |
622d3d35 | 524 | { .mfb; rum 1<<5 // clear um.mfh |
4cb73bf8 AP |
525 | nop.f 0x0 |
526 | br.ret.sptk.many b0 };; | |
527 | .endp bn_sqr_words# | |
528 | #endif | |
529 | ||
530 | #if 1 | |
a95541d6 | 531 | // Apparently we win nothing by implementing special bn_sqr_comba8. |
4cb73bf8 AP |
532 | // Yes, it is possible to reduce the number of multiplications by |
533 | // almost factor of two, but then the amount of additions would | |
534 | // increase by factor of two (as we would have to perform those | |
535 | // otherwise performed by xma ourselves). Normally we would trade | |
536 | // anyway as multiplications are way more expensive, but not this | |
537 | // time... Multiplication kernel is fully pipelined and as we drain | |
538 | // one 128-bit multiplication result per clock cycle multiplications | |
539 | // are effectively as inexpensive as additions. Special implementation | |
540 | // might become of interest for "wider" IA-64 implementation as you'll | |
541 | // be able to get through the multiplication phase faster (there won't | |
542 | // be any stall issues as discussed in the commentary section below and | |
543 | // you therefore will be able to employ all 4 FP units)... But these | |
544 | // Itanium days it's simply too hard to justify the effort so I just | |
545 | // drop down to bn_mul_comba8 code:-) | |
546 | // | |
547 | // void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a) | |
548 | // | |
549 | .global bn_sqr_comba8# | |
550 | .proc bn_sqr_comba8# | |
551 | .align 64 | |
552 | bn_sqr_comba8: | |
553 | .prologue | |
4cb73bf8 | 554 | .save ar.pfs,r2 |
e2f2a9af | 555 | #if defined(_HPUX_SOURCE) && !defined(_LP64) |
622d3d35 | 556 | { .mii; alloc r2=ar.pfs,2,1,0,0 |
46a0d4fb AP |
557 | addp4 r33=0,r33 |
558 | addp4 r32=0,r32 };; | |
559 | { .mii; | |
560 | #else | |
561 | { .mii; alloc r2=ar.pfs,2,1,0,0 | |
562 | #endif | |
4cb73bf8 AP |
563 | mov r34=r33 |
564 | add r14=8,r33 };; | |
565 | .body | |
622d3d35 | 566 | { .mii; add r17=8,r34 |
4cb73bf8 AP |
567 | add r15=16,r33 |
568 | add r18=16,r34 } | |
622d3d35 | 569 | { .mfb; add r16=24,r33 |
4cb73bf8 | 570 | br .L_cheat_entry_point8 };; |
622d3d35 | 571 | .endp bn_sqr_comba8# |
4cb73bf8 AP |
572 | #endif |
573 | ||
574 | #if 1 | |
575 | // I've estimated this routine to run in ~120 ticks, but in reality | |
576 | // (i.e. according to ar.itc) it takes ~160 ticks. Are those extra | |
577 | // cycles consumed for instructions fetch? Or did I misinterpret some | |
053fa39a | 578 | // clause in Itanium µ-architecture manual? Comments are welcomed and |
4cb73bf8 AP |
579 | // highly appreciated. |
580 | // | |
e2f2a9af AP |
581 | // On Itanium 2 it takes ~190 ticks. This is because of stalls on |
582 | // result from getf.sig. I do nothing about it at this point for | |
583 | // reasons depicted below. | |
584 | // | |
4cb73bf8 AP |
585 | // However! It should be noted that even 160 ticks is darn good result |
586 | // as it's over 10 (yes, ten, spelled as t-e-n) times faster than the | |
587 | // C version (compiled with gcc with inline assembler). I really | |
588 | // kicked compiler's butt here, didn't I? Yeah! This brings us to the | |
589 | // following statement. It's damn shame that this routine isn't called | |
590 | // very often nowadays! According to the profiler most CPU time is | |
591 | // consumed by bn_mul_add_words called from BN_from_montgomery. In | |
592 | // order to estimate what we're missing, I've compared the performance | |
593 | // of this routine against "traditional" implementation, i.e. against | |
594 | // following routine: | |
595 | // | |
596 | // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b) | |
597 | // { r[ 8]=bn_mul_words( &(r[0]),a,8,b[0]); | |
598 | // r[ 9]=bn_mul_add_words(&(r[1]),a,8,b[1]); | |
599 | // r[10]=bn_mul_add_words(&(r[2]),a,8,b[2]); | |
600 | // r[11]=bn_mul_add_words(&(r[3]),a,8,b[3]); | |
601 | // r[12]=bn_mul_add_words(&(r[4]),a,8,b[4]); | |
602 | // r[13]=bn_mul_add_words(&(r[5]),a,8,b[5]); | |
603 | // r[14]=bn_mul_add_words(&(r[6]),a,8,b[6]); | |
604 | // r[15]=bn_mul_add_words(&(r[7]),a,8,b[7]); | |
605 | // } | |
606 | // | |
607 | // The one below is over 8 times faster than the one above:-( Even | |
608 | // more reasons to "combafy" bn_mul_add_mont... | |
609 | // | |
610 | // And yes, this routine really made me wish there were an optimizing | |
611 | // assembler! It also feels like it deserves a dedication. | |
612 | // | |
613 | // To my wife for being there and to my kids... | |
614 | // | |
615 | // void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b) | |
616 | // | |
617 | #define carry1 r14 | |
618 | #define carry2 r15 | |
619 | #define carry3 r34 | |
620 | .global bn_mul_comba8# | |
621 | .proc bn_mul_comba8# | |
622 | .align 64 | |
623 | bn_mul_comba8: | |
624 | .prologue | |
4cb73bf8 | 625 | .save ar.pfs,r2 |
e2f2a9af | 626 | #if defined(_HPUX_SOURCE) && !defined(_LP64) |
622d3d35 | 627 | { .mii; alloc r2=ar.pfs,3,0,0,0 |
46a0d4fb AP |
628 | addp4 r33=0,r33 |
629 | addp4 r34=0,r34 };; | |
630 | { .mii; addp4 r32=0,r32 | |
631 | #else | |
632 | { .mii; alloc r2=ar.pfs,3,0,0,0 | |
633 | #endif | |
4cb73bf8 AP |
634 | add r14=8,r33 |
635 | add r17=8,r34 } | |
636 | .body | |
622d3d35 | 637 | { .mii; add r15=16,r33 |
4cb73bf8 | 638 | add r18=16,r34 |
622d3d35 | 639 | add r16=24,r33 } |
4cb73bf8 | 640 | .L_cheat_entry_point8: |
622d3d35 | 641 | { .mmi; add r19=24,r34 |
4cb73bf8 | 642 | |
622d3d35 | 643 | ldf8 f32=[r33],32 };; |
4cb73bf8 | 644 | |
622d3d35 AP |
645 | { .mmi; ldf8 f120=[r34],32 |
646 | ldf8 f121=[r17],32 } | |
647 | { .mmi; ldf8 f122=[r18],32 | |
648 | ldf8 f123=[r19],32 };; | |
649 | { .mmi; ldf8 f124=[r34] | |
4cb73bf8 | 650 | ldf8 f125=[r17] } |
622d3d35 | 651 | { .mmi; ldf8 f126=[r18] |
4cb73bf8 AP |
652 | ldf8 f127=[r19] } |
653 | ||
622d3d35 | 654 | { .mmi; ldf8 f33=[r14],32 |
4cb73bf8 | 655 | ldf8 f34=[r15],32 } |
622d3d35 | 656 | { .mmi; ldf8 f35=[r16],32;; |
4cb73bf8 | 657 | ldf8 f36=[r33] } |
622d3d35 | 658 | { .mmi; ldf8 f37=[r14] |
4cb73bf8 | 659 | ldf8 f38=[r15] } |
622d3d35 | 660 | { .mfi; ldf8 f39=[r16] |
4cb73bf8 AP |
661 | // -------\ Entering multiplier's heaven /------- |
662 | // ------------\ /------------ | |
663 | // -----------------\ /----------------- | |
664 | // ----------------------\/---------------------- | |
665 | xma.hu f41=f32,f120,f0 } | |
622d3d35 AP |
666 | { .mfi; xma.lu f40=f32,f120,f0 };; // (*) |
667 | { .mfi; xma.hu f51=f32,f121,f0 } | |
668 | { .mfi; xma.lu f50=f32,f121,f0 };; | |
669 | { .mfi; xma.hu f61=f32,f122,f0 } | |
670 | { .mfi; xma.lu f60=f32,f122,f0 };; | |
671 | { .mfi; xma.hu f71=f32,f123,f0 } | |
672 | { .mfi; xma.lu f70=f32,f123,f0 };; | |
673 | { .mfi; xma.hu f81=f32,f124,f0 } | |
674 | { .mfi; xma.lu f80=f32,f124,f0 };; | |
675 | { .mfi; xma.hu f91=f32,f125,f0 } | |
676 | { .mfi; xma.lu f90=f32,f125,f0 };; | |
677 | { .mfi; xma.hu f101=f32,f126,f0 } | |
678 | { .mfi; xma.lu f100=f32,f126,f0 };; | |
679 | { .mfi; xma.hu f111=f32,f127,f0 } | |
680 | { .mfi; xma.lu f110=f32,f127,f0 };;// | |
4cb73bf8 AP |
681 | // (*) You can argue that splitting at every second bundle would |
682 | // prevent "wider" IA-64 implementations from achieving the peak | |
683 | // performance. Well, not really... The catch is that if you | |
684 | // intend to keep 4 FP units busy by splitting at every fourth | |
685 | // bundle and thus perform these 16 multiplications in 4 ticks, | |
686 | // the first bundle *below* would stall because the result from | |
687 | // the first xma bundle *above* won't be available for another 3 | |
688 | // ticks (if not more, being an optimist, I assume that "wider" | |
689 | // implementation will have same latency:-). This stall will hold | |
690 | // you back and the performance would be as if every second bundle | |
691 | // were split *anyway*... | |
622d3d35 | 692 | { .mfi; getf.sig r16=f40 |
4cb73bf8 AP |
693 | xma.hu f42=f33,f120,f41 |
694 | add r33=8,r32 } | |
622d3d35 AP |
695 | { .mfi; xma.lu f41=f33,f120,f41 };; |
696 | { .mfi; getf.sig r24=f50 | |
4cb73bf8 | 697 | xma.hu f52=f33,f121,f51 } |
622d3d35 AP |
698 | { .mfi; xma.lu f51=f33,f121,f51 };; |
699 | { .mfi; st8 [r32]=r16,16 | |
4cb73bf8 | 700 | xma.hu f62=f33,f122,f61 } |
622d3d35 AP |
701 | { .mfi; xma.lu f61=f33,f122,f61 };; |
702 | { .mfi; xma.hu f72=f33,f123,f71 } | |
703 | { .mfi; xma.lu f71=f33,f123,f71 };; | |
704 | { .mfi; xma.hu f82=f33,f124,f81 } | |
705 | { .mfi; xma.lu f81=f33,f124,f81 };; | |
706 | { .mfi; xma.hu f92=f33,f125,f91 } | |
707 | { .mfi; xma.lu f91=f33,f125,f91 };; | |
708 | { .mfi; xma.hu f102=f33,f126,f101 } | |
709 | { .mfi; xma.lu f101=f33,f126,f101 };; | |
710 | { .mfi; xma.hu f112=f33,f127,f111 } | |
711 | { .mfi; xma.lu f111=f33,f127,f111 };;// | |
4cb73bf8 | 712 | //-------------------------------------------------// |
622d3d35 | 713 | { .mfi; getf.sig r25=f41 |
4cb73bf8 | 714 | xma.hu f43=f34,f120,f42 } |
622d3d35 AP |
715 | { .mfi; xma.lu f42=f34,f120,f42 };; |
716 | { .mfi; getf.sig r16=f60 | |
4cb73bf8 | 717 | xma.hu f53=f34,f121,f52 } |
622d3d35 AP |
718 | { .mfi; xma.lu f52=f34,f121,f52 };; |
719 | { .mfi; getf.sig r17=f51 | |
4cb73bf8 AP |
720 | xma.hu f63=f34,f122,f62 |
721 | add r25=r25,r24 } | |
622d3d35 | 722 | { .mfi; xma.lu f62=f34,f122,f62 |
4cb73bf8 | 723 | mov carry1=0 };; |
622d3d35 | 724 | { .mfi; cmp.ltu p6,p0=r25,r24 |
4cb73bf8 | 725 | xma.hu f73=f34,f123,f72 } |
622d3d35 AP |
726 | { .mfi; xma.lu f72=f34,f123,f72 };; |
727 | { .mfi; st8 [r33]=r25,16 | |
4cb73bf8 AP |
728 | xma.hu f83=f34,f124,f82 |
729 | (p6) add carry1=1,carry1 } | |
622d3d35 AP |
730 | { .mfi; xma.lu f82=f34,f124,f82 };; |
731 | { .mfi; xma.hu f93=f34,f125,f92 } | |
732 | { .mfi; xma.lu f92=f34,f125,f92 };; | |
733 | { .mfi; xma.hu f103=f34,f126,f102 } | |
734 | { .mfi; xma.lu f102=f34,f126,f102 };; | |
735 | { .mfi; xma.hu f113=f34,f127,f112 } | |
736 | { .mfi; xma.lu f112=f34,f127,f112 };;// | |
4cb73bf8 | 737 | //-------------------------------------------------// |
622d3d35 | 738 | { .mfi; getf.sig r18=f42 |
4cb73bf8 AP |
739 | xma.hu f44=f35,f120,f43 |
740 | add r17=r17,r16 } | |
622d3d35 AP |
741 | { .mfi; xma.lu f43=f35,f120,f43 };; |
742 | { .mfi; getf.sig r24=f70 | |
4cb73bf8 | 743 | xma.hu f54=f35,f121,f53 } |
622d3d35 | 744 | { .mfi; mov carry2=0 |
4cb73bf8 | 745 | xma.lu f53=f35,f121,f53 };; |
622d3d35 | 746 | { .mfi; getf.sig r25=f61 |
4cb73bf8 AP |
747 | xma.hu f64=f35,f122,f63 |
748 | cmp.ltu p7,p0=r17,r16 } | |
622d3d35 | 749 | { .mfi; add r18=r18,r17 |
4cb73bf8 | 750 | xma.lu f63=f35,f122,f63 };; |
622d3d35 | 751 | { .mfi; getf.sig r26=f52 |
4cb73bf8 AP |
752 | xma.hu f74=f35,f123,f73 |
753 | (p7) add carry2=1,carry2 } | |
622d3d35 | 754 | { .mfi; cmp.ltu p7,p0=r18,r17 |
4cb73bf8 AP |
755 | xma.lu f73=f35,f123,f73 |
756 | add r18=r18,carry1 };; | |
622d3d35 | 757 | { .mfi; |
4cb73bf8 AP |
758 | xma.hu f84=f35,f124,f83 |
759 | (p7) add carry2=1,carry2 } | |
622d3d35 | 760 | { .mfi; cmp.ltu p7,p0=r18,carry1 |
4cb73bf8 | 761 | xma.lu f83=f35,f124,f83 };; |
622d3d35 | 762 | { .mfi; st8 [r32]=r18,16 |
4cb73bf8 AP |
763 | xma.hu f94=f35,f125,f93 |
764 | (p7) add carry2=1,carry2 } | |
622d3d35 AP |
765 | { .mfi; xma.lu f93=f35,f125,f93 };; |
766 | { .mfi; xma.hu f104=f35,f126,f103 } | |
767 | { .mfi; xma.lu f103=f35,f126,f103 };; | |
768 | { .mfi; xma.hu f114=f35,f127,f113 } | |
769 | { .mfi; mov carry1=0 | |
4cb73bf8 | 770 | xma.lu f113=f35,f127,f113 |
622d3d35 | 771 | add r25=r25,r24 };;// |
4cb73bf8 | 772 | //-------------------------------------------------// |
622d3d35 | 773 | { .mfi; getf.sig r27=f43 |
4cb73bf8 AP |
774 | xma.hu f45=f36,f120,f44 |
775 | cmp.ltu p6,p0=r25,r24 } | |
622d3d35 | 776 | { .mfi; xma.lu f44=f36,f120,f44 |
4cb73bf8 | 777 | add r26=r26,r25 };; |
622d3d35 | 778 | { .mfi; getf.sig r16=f80 |
4cb73bf8 AP |
779 | xma.hu f55=f36,f121,f54 |
780 | (p6) add carry1=1,carry1 } | |
622d3d35 AP |
781 | { .mfi; xma.lu f54=f36,f121,f54 };; |
782 | { .mfi; getf.sig r17=f71 | |
4cb73bf8 AP |
783 | xma.hu f65=f36,f122,f64 |
784 | cmp.ltu p6,p0=r26,r25 } | |
622d3d35 | 785 | { .mfi; xma.lu f64=f36,f122,f64 |
4cb73bf8 | 786 | add r27=r27,r26 };; |
622d3d35 | 787 | { .mfi; getf.sig r18=f62 |
4cb73bf8 AP |
788 | xma.hu f75=f36,f123,f74 |
789 | (p6) add carry1=1,carry1 } | |
622d3d35 | 790 | { .mfi; cmp.ltu p6,p0=r27,r26 |
4cb73bf8 AP |
791 | xma.lu f74=f36,f123,f74 |
792 | add r27=r27,carry2 };; | |
622d3d35 | 793 | { .mfi; getf.sig r19=f53 |
4cb73bf8 AP |
794 | xma.hu f85=f36,f124,f84 |
795 | (p6) add carry1=1,carry1 } | |
622d3d35 | 796 | { .mfi; xma.lu f84=f36,f124,f84 |
4cb73bf8 | 797 | cmp.ltu p6,p0=r27,carry2 };; |
622d3d35 | 798 | { .mfi; st8 [r33]=r27,16 |
4cb73bf8 AP |
799 | xma.hu f95=f36,f125,f94 |
800 | (p6) add carry1=1,carry1 } | |
622d3d35 AP |
801 | { .mfi; xma.lu f94=f36,f125,f94 };; |
802 | { .mfi; xma.hu f105=f36,f126,f104 } | |
803 | { .mfi; mov carry2=0 | |
4cb73bf8 AP |
804 | xma.lu f104=f36,f126,f104 |
805 | add r17=r17,r16 };; | |
622d3d35 | 806 | { .mfi; xma.hu f115=f36,f127,f114 |
4cb73bf8 | 807 | cmp.ltu p7,p0=r17,r16 } |
622d3d35 AP |
808 | { .mfi; xma.lu f114=f36,f127,f114 |
809 | add r18=r18,r17 };;// | |
4cb73bf8 | 810 | //-------------------------------------------------// |
622d3d35 | 811 | { .mfi; getf.sig r20=f44 |
4cb73bf8 AP |
812 | xma.hu f46=f37,f120,f45 |
813 | (p7) add carry2=1,carry2 } | |
622d3d35 | 814 | { .mfi; cmp.ltu p7,p0=r18,r17 |
4cb73bf8 AP |
815 | xma.lu f45=f37,f120,f45 |
816 | add r19=r19,r18 };; | |
622d3d35 | 817 | { .mfi; getf.sig r24=f90 |
4cb73bf8 | 818 | xma.hu f56=f37,f121,f55 } |
622d3d35 AP |
819 | { .mfi; xma.lu f55=f37,f121,f55 };; |
820 | { .mfi; getf.sig r25=f81 | |
4cb73bf8 AP |
821 | xma.hu f66=f37,f122,f65 |
822 | (p7) add carry2=1,carry2 } | |
622d3d35 | 823 | { .mfi; cmp.ltu p7,p0=r19,r18 |
4cb73bf8 AP |
824 | xma.lu f65=f37,f122,f65 |
825 | add r20=r20,r19 };; | |
622d3d35 | 826 | { .mfi; getf.sig r26=f72 |
4cb73bf8 AP |
827 | xma.hu f76=f37,f123,f75 |
828 | (p7) add carry2=1,carry2 } | |
622d3d35 | 829 | { .mfi; cmp.ltu p7,p0=r20,r19 |
4cb73bf8 AP |
830 | xma.lu f75=f37,f123,f75 |
831 | add r20=r20,carry1 };; | |
622d3d35 | 832 | { .mfi; getf.sig r27=f63 |
4cb73bf8 AP |
833 | xma.hu f86=f37,f124,f85 |
834 | (p7) add carry2=1,carry2 } | |
622d3d35 | 835 | { .mfi; xma.lu f85=f37,f124,f85 |
4cb73bf8 | 836 | cmp.ltu p7,p0=r20,carry1 };; |
622d3d35 | 837 | { .mfi; getf.sig r28=f54 |
4cb73bf8 AP |
838 | xma.hu f96=f37,f125,f95 |
839 | (p7) add carry2=1,carry2 } | |
622d3d35 | 840 | { .mfi; st8 [r32]=r20,16 |
4cb73bf8 | 841 | xma.lu f95=f37,f125,f95 };; |
622d3d35 AP |
842 | { .mfi; xma.hu f106=f37,f126,f105 } |
843 | { .mfi; mov carry1=0 | |
4cb73bf8 AP |
844 | xma.lu f105=f37,f126,f105 |
845 | add r25=r25,r24 };; | |
622d3d35 | 846 | { .mfi; xma.hu f116=f37,f127,f115 |
4cb73bf8 | 847 | cmp.ltu p6,p0=r25,r24 } |
622d3d35 AP |
848 | { .mfi; xma.lu f115=f37,f127,f115 |
849 | add r26=r26,r25 };;// | |
4cb73bf8 | 850 | //-------------------------------------------------// |
622d3d35 | 851 | { .mfi; getf.sig r29=f45 |
4cb73bf8 AP |
852 | xma.hu f47=f38,f120,f46 |
853 | (p6) add carry1=1,carry1 } | |
622d3d35 | 854 | { .mfi; cmp.ltu p6,p0=r26,r25 |
4cb73bf8 AP |
855 | xma.lu f46=f38,f120,f46 |
856 | add r27=r27,r26 };; | |
622d3d35 | 857 | { .mfi; getf.sig r16=f100 |
4cb73bf8 AP |
858 | xma.hu f57=f38,f121,f56 |
859 | (p6) add carry1=1,carry1 } | |
622d3d35 | 860 | { .mfi; cmp.ltu p6,p0=r27,r26 |
4cb73bf8 AP |
861 | xma.lu f56=f38,f121,f56 |
862 | add r28=r28,r27 };; | |
622d3d35 | 863 | { .mfi; getf.sig r17=f91 |
4cb73bf8 AP |
864 | xma.hu f67=f38,f122,f66 |
865 | (p6) add carry1=1,carry1 } | |
622d3d35 | 866 | { .mfi; cmp.ltu p6,p0=r28,r27 |
4cb73bf8 AP |
867 | xma.lu f66=f38,f122,f66 |
868 | add r29=r29,r28 };; | |
622d3d35 | 869 | { .mfi; getf.sig r18=f82 |
4cb73bf8 AP |
870 | xma.hu f77=f38,f123,f76 |
871 | (p6) add carry1=1,carry1 } | |
622d3d35 | 872 | { .mfi; cmp.ltu p6,p0=r29,r28 |
4cb73bf8 AP |
873 | xma.lu f76=f38,f123,f76 |
874 | add r29=r29,carry2 };; | |
622d3d35 | 875 | { .mfi; getf.sig r19=f73 |
4cb73bf8 AP |
876 | xma.hu f87=f38,f124,f86 |
877 | (p6) add carry1=1,carry1 } | |
622d3d35 | 878 | { .mfi; xma.lu f86=f38,f124,f86 |
4cb73bf8 | 879 | cmp.ltu p6,p0=r29,carry2 };; |
622d3d35 | 880 | { .mfi; getf.sig r20=f64 |
4cb73bf8 AP |
881 | xma.hu f97=f38,f125,f96 |
882 | (p6) add carry1=1,carry1 } | |
622d3d35 | 883 | { .mfi; st8 [r33]=r29,16 |
4cb73bf8 | 884 | xma.lu f96=f38,f125,f96 };; |
622d3d35 | 885 | { .mfi; getf.sig r21=f55 |
4cb73bf8 | 886 | xma.hu f107=f38,f126,f106 } |
622d3d35 | 887 | { .mfi; mov carry2=0 |
4cb73bf8 AP |
888 | xma.lu f106=f38,f126,f106 |
889 | add r17=r17,r16 };; | |
622d3d35 | 890 | { .mfi; xma.hu f117=f38,f127,f116 |
4cb73bf8 | 891 | cmp.ltu p7,p0=r17,r16 } |
622d3d35 AP |
892 | { .mfi; xma.lu f116=f38,f127,f116 |
893 | add r18=r18,r17 };;// | |
4cb73bf8 | 894 | //-------------------------------------------------// |
622d3d35 | 895 | { .mfi; getf.sig r22=f46 |
4cb73bf8 AP |
896 | xma.hu f48=f39,f120,f47 |
897 | (p7) add carry2=1,carry2 } | |
622d3d35 | 898 | { .mfi; cmp.ltu p7,p0=r18,r17 |
4cb73bf8 AP |
899 | xma.lu f47=f39,f120,f47 |
900 | add r19=r19,r18 };; | |
622d3d35 | 901 | { .mfi; getf.sig r24=f110 |
4cb73bf8 AP |
902 | xma.hu f58=f39,f121,f57 |
903 | (p7) add carry2=1,carry2 } | |
622d3d35 | 904 | { .mfi; cmp.ltu p7,p0=r19,r18 |
4cb73bf8 AP |
905 | xma.lu f57=f39,f121,f57 |
906 | add r20=r20,r19 };; | |
622d3d35 | 907 | { .mfi; getf.sig r25=f101 |
4cb73bf8 AP |
908 | xma.hu f68=f39,f122,f67 |
909 | (p7) add carry2=1,carry2 } | |
622d3d35 | 910 | { .mfi; cmp.ltu p7,p0=r20,r19 |
4cb73bf8 AP |
911 | xma.lu f67=f39,f122,f67 |
912 | add r21=r21,r20 };; | |
622d3d35 | 913 | { .mfi; getf.sig r26=f92 |
4cb73bf8 AP |
914 | xma.hu f78=f39,f123,f77 |
915 | (p7) add carry2=1,carry2 } | |
622d3d35 | 916 | { .mfi; cmp.ltu p7,p0=r21,r20 |
4cb73bf8 AP |
917 | xma.lu f77=f39,f123,f77 |
918 | add r22=r22,r21 };; | |
622d3d35 | 919 | { .mfi; getf.sig r27=f83 |
4cb73bf8 AP |
920 | xma.hu f88=f39,f124,f87 |
921 | (p7) add carry2=1,carry2 } | |
622d3d35 | 922 | { .mfi; cmp.ltu p7,p0=r22,r21 |
4cb73bf8 AP |
923 | xma.lu f87=f39,f124,f87 |
924 | add r22=r22,carry1 };; | |
622d3d35 | 925 | { .mfi; getf.sig r28=f74 |
4cb73bf8 AP |
926 | xma.hu f98=f39,f125,f97 |
927 | (p7) add carry2=1,carry2 } | |
622d3d35 | 928 | { .mfi; xma.lu f97=f39,f125,f97 |
4cb73bf8 | 929 | cmp.ltu p7,p0=r22,carry1 };; |
622d3d35 | 930 | { .mfi; getf.sig r29=f65 |
4cb73bf8 AP |
931 | xma.hu f108=f39,f126,f107 |
932 | (p7) add carry2=1,carry2 } | |
622d3d35 | 933 | { .mfi; st8 [r32]=r22,16 |
4cb73bf8 | 934 | xma.lu f107=f39,f126,f107 };; |
622d3d35 | 935 | { .mfi; getf.sig r30=f56 |
4cb73bf8 | 936 | xma.hu f118=f39,f127,f117 } |
622d3d35 | 937 | { .mfi; xma.lu f117=f39,f127,f117 };;// |
4cb73bf8 | 938 | //-------------------------------------------------// |
46f4e1be | 939 | // Leaving multiplier's heaven... Quite a ride, huh? |
4cb73bf8 | 940 | |
622d3d35 | 941 | { .mii; getf.sig r31=f47 |
4cb73bf8 AP |
942 | add r25=r25,r24 |
943 | mov carry1=0 };; | |
622d3d35 | 944 | { .mii; getf.sig r16=f111 |
4cb73bf8 AP |
945 | cmp.ltu p6,p0=r25,r24 |
946 | add r26=r26,r25 };; | |
622d3d35 AP |
947 | { .mfb; getf.sig r17=f102 } |
948 | { .mii; | |
4cb73bf8 AP |
949 | (p6) add carry1=1,carry1 |
950 | cmp.ltu p6,p0=r26,r25 | |
951 | add r27=r27,r26 };; | |
622d3d35 AP |
952 | { .mfb; nop.m 0x0 } |
953 | { .mii; | |
4cb73bf8 AP |
954 | (p6) add carry1=1,carry1 |
955 | cmp.ltu p6,p0=r27,r26 | |
956 | add r28=r28,r27 };; | |
622d3d35 | 957 | { .mii; getf.sig r18=f93 |
4cb73bf8 AP |
958 | add r17=r17,r16 |
959 | mov carry3=0 } | |
622d3d35 | 960 | { .mii; |
4cb73bf8 AP |
961 | (p6) add carry1=1,carry1 |
962 | cmp.ltu p6,p0=r28,r27 | |
963 | add r29=r29,r28 };; | |
622d3d35 | 964 | { .mii; getf.sig r19=f84 |
4cb73bf8 | 965 | cmp.ltu p7,p0=r17,r16 } |
622d3d35 | 966 | { .mii; |
4cb73bf8 AP |
967 | (p6) add carry1=1,carry1 |
968 | cmp.ltu p6,p0=r29,r28 | |
969 | add r30=r30,r29 };; | |
622d3d35 | 970 | { .mii; getf.sig r20=f75 |
4cb73bf8 | 971 | add r18=r18,r17 } |
622d3d35 | 972 | { .mii; |
4cb73bf8 AP |
973 | (p6) add carry1=1,carry1 |
974 | cmp.ltu p6,p0=r30,r29 | |
975 | add r31=r31,r30 };; | |
622d3d35 AP |
976 | { .mfb; getf.sig r21=f66 } |
977 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
978 | cmp.ltu p7,p0=r18,r17 |
979 | add r19=r19,r18 } | |
622d3d35 AP |
980 | { .mfb; nop.m 0x0 } |
981 | { .mii; | |
4cb73bf8 AP |
982 | (p6) add carry1=1,carry1 |
983 | cmp.ltu p6,p0=r31,r30 | |
984 | add r31=r31,carry2 };; | |
622d3d35 AP |
985 | { .mfb; getf.sig r22=f57 } |
986 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
987 | cmp.ltu p7,p0=r19,r18 |
988 | add r20=r20,r19 } | |
622d3d35 AP |
989 | { .mfb; nop.m 0x0 } |
990 | { .mii; | |
4cb73bf8 AP |
991 | (p6) add carry1=1,carry1 |
992 | cmp.ltu p6,p0=r31,carry2 };; | |
622d3d35 AP |
993 | { .mfb; getf.sig r23=f48 } |
994 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
995 | cmp.ltu p7,p0=r20,r19 |
996 | add r21=r21,r20 } | |
622d3d35 | 997 | { .mii; |
4cb73bf8 | 998 | (p6) add carry1=1,carry1 } |
622d3d35 | 999 | { .mfb; st8 [r33]=r31,16 };; |
4cb73bf8 | 1000 | |
622d3d35 AP |
1001 | { .mfb; getf.sig r24=f112 } |
1002 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
1003 | cmp.ltu p7,p0=r21,r20 |
1004 | add r22=r22,r21 };; | |
622d3d35 AP |
1005 | { .mfb; getf.sig r25=f103 } |
1006 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
1007 | cmp.ltu p7,p0=r22,r21 |
1008 | add r23=r23,r22 };; | |
622d3d35 AP |
1009 | { .mfb; getf.sig r26=f94 } |
1010 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
1011 | cmp.ltu p7,p0=r23,r22 |
1012 | add r23=r23,carry1 };; | |
622d3d35 AP |
1013 | { .mfb; getf.sig r27=f85 } |
1014 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 | 1015 | cmp.ltu p7,p8=r23,carry1};; |
622d3d35 | 1016 | { .mii; getf.sig r28=f76 |
4cb73bf8 AP |
1017 | add r25=r25,r24 |
1018 | mov carry1=0 } | |
622d3d35 | 1019 | { .mii; st8 [r32]=r23,16 |
4cb73bf8 AP |
1020 | (p7) add carry2=1,carry3 |
1021 | (p8) add carry2=0,carry3 };; | |
1022 | ||
622d3d35 AP |
1023 | { .mfb; nop.m 0x0 } |
1024 | { .mii; getf.sig r29=f67 | |
4cb73bf8 AP |
1025 | cmp.ltu p6,p0=r25,r24 |
1026 | add r26=r26,r25 };; | |
622d3d35 AP |
1027 | { .mfb; getf.sig r30=f58 } |
1028 | { .mii; | |
4cb73bf8 AP |
1029 | (p6) add carry1=1,carry1 |
1030 | cmp.ltu p6,p0=r26,r25 | |
1031 | add r27=r27,r26 };; | |
622d3d35 AP |
1032 | { .mfb; getf.sig r16=f113 } |
1033 | { .mii; | |
4cb73bf8 AP |
1034 | (p6) add carry1=1,carry1 |
1035 | cmp.ltu p6,p0=r27,r26 | |
1036 | add r28=r28,r27 };; | |
622d3d35 AP |
1037 | { .mfb; getf.sig r17=f104 } |
1038 | { .mii; | |
4cb73bf8 AP |
1039 | (p6) add carry1=1,carry1 |
1040 | cmp.ltu p6,p0=r28,r27 | |
1041 | add r29=r29,r28 };; | |
622d3d35 AP |
1042 | { .mfb; getf.sig r18=f95 } |
1043 | { .mii; | |
4cb73bf8 AP |
1044 | (p6) add carry1=1,carry1 |
1045 | cmp.ltu p6,p0=r29,r28 | |
1046 | add r30=r30,r29 };; | |
622d3d35 | 1047 | { .mii; getf.sig r19=f86 |
4cb73bf8 AP |
1048 | add r17=r17,r16 |
1049 | mov carry3=0 } | |
622d3d35 | 1050 | { .mii; |
4cb73bf8 AP |
1051 | (p6) add carry1=1,carry1 |
1052 | cmp.ltu p6,p0=r30,r29 | |
1053 | add r30=r30,carry2 };; | |
622d3d35 | 1054 | { .mii; getf.sig r20=f77 |
4cb73bf8 AP |
1055 | cmp.ltu p7,p0=r17,r16 |
1056 | add r18=r18,r17 } | |
622d3d35 | 1057 | { .mii; |
4cb73bf8 AP |
1058 | (p6) add carry1=1,carry1 |
1059 | cmp.ltu p6,p0=r30,carry2 };; | |
622d3d35 AP |
1060 | { .mfb; getf.sig r21=f68 } |
1061 | { .mii; st8 [r33]=r30,16 | |
4cb73bf8 AP |
1062 | (p6) add carry1=1,carry1 };; |
1063 | ||
622d3d35 AP |
1064 | { .mfb; getf.sig r24=f114 } |
1065 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
1066 | cmp.ltu p7,p0=r18,r17 |
1067 | add r19=r19,r18 };; | |
622d3d35 AP |
1068 | { .mfb; getf.sig r25=f105 } |
1069 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
1070 | cmp.ltu p7,p0=r19,r18 |
1071 | add r20=r20,r19 };; | |
622d3d35 AP |
1072 | { .mfb; getf.sig r26=f96 } |
1073 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
1074 | cmp.ltu p7,p0=r20,r19 |
1075 | add r21=r21,r20 };; | |
622d3d35 AP |
1076 | { .mfb; getf.sig r27=f87 } |
1077 | { .mii; (p7) add carry3=1,carry3 | |
4cb73bf8 AP |
1078 | cmp.ltu p7,p0=r21,r20 |
1079 | add r21=r21,carry1 };; | |
622d3d35 | 1080 | { .mib; getf.sig r28=f78 |
4cb73bf8 | 1081 | add r25=r25,r24 } |
622d3d35 | 1082 | { .mib; (p7) add carry3=1,carry3 |
4cb73bf8 | 1083 | cmp.ltu p7,p8=r21,carry1};; |
622d3d35 | 1084 | { .mii; st8 [r32]=r21,16 |
4cb73bf8 AP |
1085 | (p7) add carry2=1,carry3 |
1086 | (p8) add carry2=0,carry3 } | |
1087 | ||
622d3d35 | 1088 | { .mii; mov carry1=0 |
4cb73bf8 AP |
1089 | cmp.ltu p6,p0=r25,r24 |
1090 | add r26=r26,r25 };; | |
622d3d35 AP |
1091 | { .mfb; getf.sig r16=f115 } |
1092 | { .mii; | |
4cb73bf8 AP |
1093 | (p6) add carry1=1,carry1 |
1094 | cmp.ltu p6,p0=r26,r25 | |
1095 | add r27=r27,r26 };; | |
622d3d35 AP |
1096 | { .mfb; getf.sig r17=f106 } |
1097 | { .mii; | |
4cb73bf8 AP |
1098 | (p6) add carry1=1,carry1 |
1099 | cmp.ltu p6,p0=r27,r26 | |
1100 | add r28=r28,r27 };; | |
622d3d35 AP |
1101 | { .mfb; getf.sig r18=f97 } |
1102 | { .mii; | |
4cb73bf8 AP |
1103 | (p6) add carry1=1,carry1 |
1104 | cmp.ltu p6,p0=r28,r27 | |
1105 | add r28=r28,carry2 };; | |
622d3d35 | 1106 | { .mib; getf.sig r19=f88 |
4cb73bf8 | 1107 | add r17=r17,r16 } |
622d3d35 | 1108 | { .mib; |
4cb73bf8 AP |
1109 | (p6) add carry1=1,carry1 |
1110 | cmp.ltu p6,p0=r28,carry2 };; | |
622d3d35 | 1111 | { .mii; st8 [r33]=r28,16 |
4cb73bf8 AP |
1112 | (p6) add carry1=1,carry1 } |
1113 | ||
622d3d35 | 1114 | { .mii; mov carry2=0 |
4cb73bf8 AP |
1115 | cmp.ltu p7,p0=r17,r16 |
1116 | add r18=r18,r17 };; | |
622d3d35 AP |
1117 | { .mfb; getf.sig r24=f116 } |
1118 | { .mii; (p7) add carry2=1,carry2 | |
4cb73bf8 AP |
1119 | cmp.ltu p7,p0=r18,r17 |
1120 | add r19=r19,r18 };; | |
622d3d35 AP |
1121 | { .mfb; getf.sig r25=f107 } |
1122 | { .mii; (p7) add carry2=1,carry2 | |
4cb73bf8 AP |
1123 | cmp.ltu p7,p0=r19,r18 |
1124 | add r19=r19,carry1 };; | |
622d3d35 AP |
1125 | { .mfb; getf.sig r26=f98 } |
1126 | { .mii; (p7) add carry2=1,carry2 | |
4cb73bf8 | 1127 | cmp.ltu p7,p0=r19,carry1};; |
622d3d35 | 1128 | { .mii; st8 [r32]=r19,16 |
4cb73bf8 AP |
1129 | (p7) add carry2=1,carry2 } |
1130 | ||
622d3d35 | 1131 | { .mfb; add r25=r25,r24 };; |
4cb73bf8 | 1132 | |
622d3d35 AP |
1133 | { .mfb; getf.sig r16=f117 } |
1134 | { .mii; mov carry1=0 | |
4cb73bf8 AP |
1135 | cmp.ltu p6,p0=r25,r24 |
1136 | add r26=r26,r25 };; | |
622d3d35 AP |
1137 | { .mfb; getf.sig r17=f108 } |
1138 | { .mii; | |
4cb73bf8 AP |
1139 | (p6) add carry1=1,carry1 |
1140 | cmp.ltu p6,p0=r26,r25 | |
1141 | add r26=r26,carry2 };; | |
622d3d35 AP |
1142 | { .mfb; nop.m 0x0 } |
1143 | { .mii; | |
4cb73bf8 AP |
1144 | (p6) add carry1=1,carry1 |
1145 | cmp.ltu p6,p0=r26,carry2 };; | |
622d3d35 | 1146 | { .mii; st8 [r33]=r26,16 |
4cb73bf8 AP |
1147 | (p6) add carry1=1,carry1 } |
1148 | ||
622d3d35 AP |
1149 | { .mfb; add r17=r17,r16 };; |
1150 | { .mfb; getf.sig r24=f118 } | |
1151 | { .mii; mov carry2=0 | |
4cb73bf8 AP |
1152 | cmp.ltu p7,p0=r17,r16 |
1153 | add r17=r17,carry1 };; | |
622d3d35 | 1154 | { .mii; (p7) add carry2=1,carry2 |
4cb73bf8 | 1155 | cmp.ltu p7,p0=r17,carry1};; |
622d3d35 | 1156 | { .mii; st8 [r32]=r17 |
4cb73bf8 | 1157 | (p7) add carry2=1,carry2 };; |
622d3d35 AP |
1158 | { .mfb; add r24=r24,carry2 };; |
1159 | { .mib; st8 [r33]=r24 } | |
4cb73bf8 | 1160 | |
622d3d35 | 1161 | { .mib; rum 1<<5 // clear um.mfh |
4cb73bf8 AP |
1162 | br.ret.sptk.many b0 };; |
1163 | .endp bn_mul_comba8# | |
4cb73bf8 AP |
1164 | #undef carry3 |
1165 | #undef carry2 | |
1166 | #undef carry1 | |
1167 | #endif | |
1168 | ||
1169 | #if 1 | |
1170 | // It's possible to make it faster (see comment to bn_sqr_comba8), but | |
1171 | // I reckon it doesn't worth the effort. Basically because the routine | |
1172 | // (actually both of them) practically never called... So I just play | |
1173 | // same trick as with bn_sqr_comba8. | |
1174 | // | |
1175 | // void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a) | |
1176 | // | |
1177 | .global bn_sqr_comba4# | |
1178 | .proc bn_sqr_comba4# | |
1179 | .align 64 | |
1180 | bn_sqr_comba4: | |
1181 | .prologue | |
4cb73bf8 | 1182 | .save ar.pfs,r2 |
e2f2a9af | 1183 | #if defined(_HPUX_SOURCE) && !defined(_LP64) |
46a0d4fb AP |
1184 | { .mii; alloc r2=ar.pfs,2,1,0,0 |
1185 | addp4 r32=0,r32 | |
1186 | addp4 r33=0,r33 };; | |
1187 | { .mii; | |
1188 | #else | |
622d3d35 | 1189 | { .mii; alloc r2=ar.pfs,2,1,0,0 |
46a0d4fb | 1190 | #endif |
4cb73bf8 AP |
1191 | mov r34=r33 |
1192 | add r14=8,r33 };; | |
1193 | .body | |
622d3d35 | 1194 | { .mii; add r17=8,r34 |
4cb73bf8 AP |
1195 | add r15=16,r33 |
1196 | add r18=16,r34 } | |
622d3d35 | 1197 | { .mfb; add r16=24,r33 |
4cb73bf8 | 1198 | br .L_cheat_entry_point4 };; |
622d3d35 | 1199 | .endp bn_sqr_comba4# |
4cb73bf8 AP |
1200 | #endif |
1201 | ||
1202 | #if 1 | |
1203 | // Runs in ~115 cycles and ~4.5 times faster than C. Well, whatever... | |
1204 | // | |
1205 | // void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b) | |
1206 | // | |
622d3d35 | 1207 | #define carry1 r14 |
4cb73bf8 AP |
1208 | #define carry2 r15 |
1209 | .global bn_mul_comba4# | |
1210 | .proc bn_mul_comba4# | |
1211 | .align 64 | |
1212 | bn_mul_comba4: | |
1213 | .prologue | |
4cb73bf8 | 1214 | .save ar.pfs,r2 |
e2f2a9af | 1215 | #if defined(_HPUX_SOURCE) && !defined(_LP64) |
46a0d4fb AP |
1216 | { .mii; alloc r2=ar.pfs,3,0,0,0 |
1217 | addp4 r33=0,r33 | |
1218 | addp4 r34=0,r34 };; | |
1219 | { .mii; addp4 r32=0,r32 | |
1220 | #else | |
622d3d35 | 1221 | { .mii; alloc r2=ar.pfs,3,0,0,0 |
46a0d4fb | 1222 | #endif |
4cb73bf8 AP |
1223 | add r14=8,r33 |
1224 | add r17=8,r34 } | |
1225 | .body | |
622d3d35 | 1226 | { .mii; add r15=16,r33 |
4cb73bf8 AP |
1227 | add r18=16,r34 |
1228 | add r16=24,r33 };; | |
1229 | .L_cheat_entry_point4: | |
622d3d35 | 1230 | { .mmi; add r19=24,r34 |
4cb73bf8 AP |
1231 | |
1232 | ldf8 f32=[r33] } | |
1233 | ||
622d3d35 | 1234 | { .mmi; ldf8 f120=[r34] |
4cb73bf8 | 1235 | ldf8 f121=[r17] };; |
622d3d35 | 1236 | { .mmi; ldf8 f122=[r18] |
4cb73bf8 AP |
1237 | ldf8 f123=[r19] } |
1238 | ||
622d3d35 | 1239 | { .mmi; ldf8 f33=[r14] |
4cb73bf8 | 1240 | ldf8 f34=[r15] } |
622d3d35 | 1241 | { .mfi; ldf8 f35=[r16] |
4cb73bf8 AP |
1242 | |
1243 | xma.hu f41=f32,f120,f0 } | |
622d3d35 AP |
1244 | { .mfi; xma.lu f40=f32,f120,f0 };; |
1245 | { .mfi; xma.hu f51=f32,f121,f0 } | |
1246 | { .mfi; xma.lu f50=f32,f121,f0 };; | |
1247 | { .mfi; xma.hu f61=f32,f122,f0 } | |
1248 | { .mfi; xma.lu f60=f32,f122,f0 };; | |
1249 | { .mfi; xma.hu f71=f32,f123,f0 } | |
1250 | { .mfi; xma.lu f70=f32,f123,f0 };;// | |
4cb73bf8 AP |
1251 | // Major stall takes place here, and 3 more places below. Result from |
1252 | // first xma is not available for another 3 ticks. | |
622d3d35 | 1253 | { .mfi; getf.sig r16=f40 |
4cb73bf8 AP |
1254 | xma.hu f42=f33,f120,f41 |
1255 | add r33=8,r32 } | |
622d3d35 AP |
1256 | { .mfi; xma.lu f41=f33,f120,f41 };; |
1257 | { .mfi; getf.sig r24=f50 | |
4cb73bf8 | 1258 | xma.hu f52=f33,f121,f51 } |
622d3d35 AP |
1259 | { .mfi; xma.lu f51=f33,f121,f51 };; |
1260 | { .mfi; st8 [r32]=r16,16 | |
4cb73bf8 | 1261 | xma.hu f62=f33,f122,f61 } |
622d3d35 AP |
1262 | { .mfi; xma.lu f61=f33,f122,f61 };; |
1263 | { .mfi; xma.hu f72=f33,f123,f71 } | |
1264 | { .mfi; xma.lu f71=f33,f123,f71 };;// | |
4cb73bf8 | 1265 | //-------------------------------------------------// |
622d3d35 | 1266 | { .mfi; getf.sig r25=f41 |
4cb73bf8 | 1267 | xma.hu f43=f34,f120,f42 } |
622d3d35 AP |
1268 | { .mfi; xma.lu f42=f34,f120,f42 };; |
1269 | { .mfi; getf.sig r16=f60 | |
4cb73bf8 | 1270 | xma.hu f53=f34,f121,f52 } |
622d3d35 AP |
1271 | { .mfi; xma.lu f52=f34,f121,f52 };; |
1272 | { .mfi; getf.sig r17=f51 | |
4cb73bf8 AP |
1273 | xma.hu f63=f34,f122,f62 |
1274 | add r25=r25,r24 } | |
622d3d35 | 1275 | { .mfi; mov carry1=0 |
4cb73bf8 | 1276 | xma.lu f62=f34,f122,f62 };; |
622d3d35 | 1277 | { .mfi; st8 [r33]=r25,16 |
4cb73bf8 AP |
1278 | xma.hu f73=f34,f123,f72 |
1279 | cmp.ltu p6,p0=r25,r24 } | |
622d3d35 | 1280 | { .mfi; xma.lu f72=f34,f123,f72 };;// |
4cb73bf8 | 1281 | //-------------------------------------------------// |
622d3d35 | 1282 | { .mfi; getf.sig r18=f42 |
4cb73bf8 AP |
1283 | xma.hu f44=f35,f120,f43 |
1284 | (p6) add carry1=1,carry1 } | |
622d3d35 | 1285 | { .mfi; add r17=r17,r16 |
4cb73bf8 AP |
1286 | xma.lu f43=f35,f120,f43 |
1287 | mov carry2=0 };; | |
622d3d35 | 1288 | { .mfi; getf.sig r24=f70 |
4cb73bf8 AP |
1289 | xma.hu f54=f35,f121,f53 |
1290 | cmp.ltu p7,p0=r17,r16 } | |
622d3d35 AP |
1291 | { .mfi; xma.lu f53=f35,f121,f53 };; |
1292 | { .mfi; getf.sig r25=f61 | |
4cb73bf8 AP |
1293 | xma.hu f64=f35,f122,f63 |
1294 | add r18=r18,r17 } | |
622d3d35 | 1295 | { .mfi; xma.lu f63=f35,f122,f63 |
4cb73bf8 | 1296 | (p7) add carry2=1,carry2 };; |
622d3d35 | 1297 | { .mfi; getf.sig r26=f52 |
4cb73bf8 AP |
1298 | xma.hu f74=f35,f123,f73 |
1299 | cmp.ltu p7,p0=r18,r17 } | |
622d3d35 | 1300 | { .mfi; xma.lu f73=f35,f123,f73 |
4cb73bf8 AP |
1301 | add r18=r18,carry1 };; |
1302 | //-------------------------------------------------// | |
622d3d35 | 1303 | { .mii; st8 [r32]=r18,16 |
4cb73bf8 AP |
1304 | (p7) add carry2=1,carry2 |
1305 | cmp.ltu p7,p0=r18,carry1 };; | |
1306 | ||
622d3d35 | 1307 | { .mfi; getf.sig r27=f43 // last major stall |
4cb73bf8 | 1308 | (p7) add carry2=1,carry2 };; |
622d3d35 | 1309 | { .mii; getf.sig r16=f71 |
4cb73bf8 AP |
1310 | add r25=r25,r24 |
1311 | mov carry1=0 };; | |
622d3d35 | 1312 | { .mii; getf.sig r17=f62 |
4cb73bf8 AP |
1313 | cmp.ltu p6,p0=r25,r24 |
1314 | add r26=r26,r25 };; | |
622d3d35 | 1315 | { .mii; |
4cb73bf8 AP |
1316 | (p6) add carry1=1,carry1 |
1317 | cmp.ltu p6,p0=r26,r25 | |
1318 | add r27=r27,r26 };; | |
622d3d35 | 1319 | { .mii; |
4cb73bf8 AP |
1320 | (p6) add carry1=1,carry1 |
1321 | cmp.ltu p6,p0=r27,r26 | |
1322 | add r27=r27,carry2 };; | |
622d3d35 | 1323 | { .mii; getf.sig r18=f53 |
4cb73bf8 AP |
1324 | (p6) add carry1=1,carry1 |
1325 | cmp.ltu p6,p0=r27,carry2 };; | |
622d3d35 | 1326 | { .mfi; st8 [r33]=r27,16 |
4cb73bf8 AP |
1327 | (p6) add carry1=1,carry1 } |
1328 | ||
622d3d35 | 1329 | { .mii; getf.sig r19=f44 |
4cb73bf8 AP |
1330 | add r17=r17,r16 |
1331 | mov carry2=0 };; | |
622d3d35 | 1332 | { .mii; getf.sig r24=f72 |
4cb73bf8 AP |
1333 | cmp.ltu p7,p0=r17,r16 |
1334 | add r18=r18,r17 };; | |
622d3d35 | 1335 | { .mii; (p7) add carry2=1,carry2 |
4cb73bf8 AP |
1336 | cmp.ltu p7,p0=r18,r17 |
1337 | add r19=r19,r18 };; | |
622d3d35 | 1338 | { .mii; (p7) add carry2=1,carry2 |
4cb73bf8 AP |
1339 | cmp.ltu p7,p0=r19,r18 |
1340 | add r19=r19,carry1 };; | |
622d3d35 | 1341 | { .mii; getf.sig r25=f63 |
4cb73bf8 AP |
1342 | (p7) add carry2=1,carry2 |
1343 | cmp.ltu p7,p0=r19,carry1};; | |
622d3d35 | 1344 | { .mii; st8 [r32]=r19,16 |
4cb73bf8 AP |
1345 | (p7) add carry2=1,carry2 } |
1346 | ||
622d3d35 | 1347 | { .mii; getf.sig r26=f54 |
4cb73bf8 AP |
1348 | add r25=r25,r24 |
1349 | mov carry1=0 };; | |
622d3d35 | 1350 | { .mii; getf.sig r16=f73 |
4cb73bf8 AP |
1351 | cmp.ltu p6,p0=r25,r24 |
1352 | add r26=r26,r25 };; | |
622d3d35 | 1353 | { .mii; |
4cb73bf8 AP |
1354 | (p6) add carry1=1,carry1 |
1355 | cmp.ltu p6,p0=r26,r25 | |
1356 | add r26=r26,carry2 };; | |
622d3d35 | 1357 | { .mii; getf.sig r17=f64 |
4cb73bf8 AP |
1358 | (p6) add carry1=1,carry1 |
1359 | cmp.ltu p6,p0=r26,carry2 };; | |
622d3d35 | 1360 | { .mii; st8 [r33]=r26,16 |
4cb73bf8 AP |
1361 | (p6) add carry1=1,carry1 } |
1362 | ||
622d3d35 | 1363 | { .mii; getf.sig r24=f74 |
4cb73bf8 AP |
1364 | add r17=r17,r16 |
1365 | mov carry2=0 };; | |
622d3d35 | 1366 | { .mii; cmp.ltu p7,p0=r17,r16 |
4cb73bf8 AP |
1367 | add r17=r17,carry1 };; |
1368 | ||
622d3d35 | 1369 | { .mii; (p7) add carry2=1,carry2 |
4cb73bf8 | 1370 | cmp.ltu p7,p0=r17,carry1};; |
622d3d35 | 1371 | { .mii; st8 [r32]=r17,16 |
4cb73bf8 AP |
1372 | (p7) add carry2=1,carry2 };; |
1373 | ||
622d3d35 AP |
1374 | { .mii; add r24=r24,carry2 };; |
1375 | { .mii; st8 [r33]=r24 } | |
4cb73bf8 | 1376 | |
622d3d35 | 1377 | { .mib; rum 1<<5 // clear um.mfh |
4cb73bf8 AP |
1378 | br.ret.sptk.many b0 };; |
1379 | .endp bn_mul_comba4# | |
4cb73bf8 AP |
1380 | #undef carry2 |
1381 | #undef carry1 | |
1382 | #endif | |
1383 | ||
1384 | #if 1 | |
1385 | // | |
1386 | // BN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d) | |
1387 | // | |
1388 | // In the nutshell it's a port of my MIPS III/IV implementation. | |
1389 | // | |
1390 | #define AT r14 | |
1391 | #define H r16 | |
1392 | #define HH r20 | |
1393 | #define L r17 | |
1394 | #define D r18 | |
1395 | #define DH r22 | |
1396 | #define I r21 | |
1397 | ||
622d3d35 | 1398 | #if 0 |
e2f2a9af AP |
1399 | // Some preprocessors (most notably HP-UX) appear to be allergic to |
1400 | // macros enclosed to parenthesis [as these three were]. | |
4cb73bf8 AP |
1401 | #define cont p16 |
1402 | #define break p0 // p20 | |
1403 | #define equ p24 | |
622d3d35 AP |
1404 | #else |
1405 | cont=p16 | |
1406 | break=p0 | |
1407 | equ=p24 | |
1408 | #endif | |
1409 | ||
4cb73bf8 AP |
1410 | .global abort# |
1411 | .global bn_div_words# | |
1412 | .proc bn_div_words# | |
1413 | .align 64 | |
1414 | bn_div_words: | |
1415 | .prologue | |
4cb73bf8 | 1416 | .save ar.pfs,r2 |
622d3d35 | 1417 | { .mii; alloc r2=ar.pfs,3,5,0,8 |
ef428d56 | 1418 | .save b0,r3 |
4cb73bf8 | 1419 | mov r3=b0 |
7cfe2a5e | 1420 | .save pr,r10 |
4cb73bf8 | 1421 | mov r10=pr };; |
622d3d35 | 1422 | { .mmb; cmp.eq p6,p0=r34,r0 |
4cb73bf8 AP |
1423 | mov r8=-1 |
1424 | (p6) br.ret.spnt.many b0 };; | |
1425 | ||
1426 | .body | |
622d3d35 | 1427 | { .mii; mov H=r32 // save h |
4cb73bf8 AP |
1428 | mov ar.ec=0 // don't rotate at exit |
1429 | mov pr.rot=0 } | |
622d3d35 AP |
1430 | { .mii; mov L=r33 // save l |
1431 | mov r36=r0 };; | |
4cb73bf8 | 1432 | |
622d3d35 AP |
1433 | .L_divw_shift: // -vv- note signed comparison |
1434 | { .mfi; (p0) cmp.lt p16,p0=r0,r34 // d | |
4cb73bf8 | 1435 | (p0) shladd r33=r34,1,r0 } |
622d3d35 | 1436 | { .mfb; (p0) add r35=1,r36 |
4cb73bf8 | 1437 | (p0) nop.f 0x0 |
622d3d35 | 1438 | (p16) br.wtop.dpnt .L_divw_shift };; |
4cb73bf8 | 1439 | |
622d3d35 | 1440 | { .mii; mov D=r34 |
4cb73bf8 AP |
1441 | shr.u DH=r34,32 |
1442 | sub r35=64,r36 };; | |
622d3d35 | 1443 | { .mii; setf.sig f7=DH |
4cb73bf8 AP |
1444 | shr.u AT=H,r35 |
1445 | mov I=r36 };; | |
622d3d35 | 1446 | { .mib; cmp.ne p6,p0=r0,AT |
4cb73bf8 AP |
1447 | shl H=H,r36 |
1448 | (p6) br.call.spnt.clr b0=abort };; // overflow, die... | |
1449 | ||
622d3d35 | 1450 | { .mfi; fcvt.xuf.s1 f7=f7 |
4cb73bf8 | 1451 | shr.u AT=L,r35 };; |
622d3d35 | 1452 | { .mii; shl L=L,r36 |
4cb73bf8 AP |
1453 | or H=H,AT };; |
1454 | ||
622d3d35 | 1455 | { .mii; nop.m 0x0 |
4cb73bf8 AP |
1456 | cmp.leu p6,p0=D,H;; |
1457 | (p6) sub H=H,D } | |
1458 | ||
622d3d35 | 1459 | { .mlx; setf.sig f14=D |
a95541d6 | 1460 | movl AT=0xffffffff };; |
4cb73bf8 | 1461 | /////////////////////////////////////////////////////////// |
622d3d35 | 1462 | { .mii; setf.sig f6=H |
4cb73bf8 AP |
1463 | shr.u HH=H,32;; |
1464 | cmp.eq p6,p7=HH,DH };; | |
622d3d35 | 1465 | { .mfb; |
4cb73bf8 AP |
1466 | (p6) setf.sig f8=AT |
1467 | (p7) fcvt.xuf.s1 f6=f6 | |
1468 | (p7) br.call.sptk b6=.L_udiv64_32_b6 };; | |
1469 | ||
622d3d35 | 1470 | { .mfi; getf.sig r33=f8 // q |
4cb73bf8 | 1471 | xmpy.lu f9=f8,f14 } |
622d3d35 | 1472 | { .mfi; xmpy.hu f10=f8,f14 |
4cb73bf8 AP |
1473 | shrp H=H,L,32 };; |
1474 | ||
622d3d35 | 1475 | { .mmi; getf.sig r35=f9 // tl |
4cb73bf8 AP |
1476 | getf.sig r31=f10 };; // th |
1477 | ||
622d3d35 AP |
1478 | .L_divw_1st_iter: |
1479 | { .mii; (p0) add r32=-1,r33 | |
4cb73bf8 | 1480 | (p0) cmp.eq equ,cont=HH,r31 };; |
622d3d35 | 1481 | { .mii; (p0) cmp.ltu p8,p0=r35,D |
4cb73bf8 AP |
1482 | (p0) sub r34=r35,D |
1483 | (equ) cmp.leu break,cont=r35,H };; | |
622d3d35 | 1484 | { .mib; (cont) cmp.leu cont,break=HH,r31 |
4cb73bf8 | 1485 | (p8) add r31=-1,r31 |
622d3d35 | 1486 | (cont) br.wtop.spnt .L_divw_1st_iter };; |
4cb73bf8 | 1487 | /////////////////////////////////////////////////////////// |
622d3d35 | 1488 | { .mii; sub H=H,r35 |
4cb73bf8 | 1489 | shl r8=r33,32 |
a95541d6 | 1490 | shl L=L,32 };; |
4cb73bf8 | 1491 | /////////////////////////////////////////////////////////// |
622d3d35 | 1492 | { .mii; setf.sig f6=H |
4cb73bf8 AP |
1493 | shr.u HH=H,32;; |
1494 | cmp.eq p6,p7=HH,DH };; | |
622d3d35 | 1495 | { .mfb; |
4cb73bf8 AP |
1496 | (p6) setf.sig f8=AT |
1497 | (p7) fcvt.xuf.s1 f6=f6 | |
1498 | (p7) br.call.sptk b6=.L_udiv64_32_b6 };; | |
1499 | ||
622d3d35 | 1500 | { .mfi; getf.sig r33=f8 // q |
4cb73bf8 | 1501 | xmpy.lu f9=f8,f14 } |
622d3d35 | 1502 | { .mfi; xmpy.hu f10=f8,f14 |
4cb73bf8 AP |
1503 | shrp H=H,L,32 };; |
1504 | ||
622d3d35 | 1505 | { .mmi; getf.sig r35=f9 // tl |
4cb73bf8 AP |
1506 | getf.sig r31=f10 };; // th |
1507 | ||
622d3d35 AP |
1508 | .L_divw_2nd_iter: |
1509 | { .mii; (p0) add r32=-1,r33 | |
4cb73bf8 | 1510 | (p0) cmp.eq equ,cont=HH,r31 };; |
622d3d35 | 1511 | { .mii; (p0) cmp.ltu p8,p0=r35,D |
4cb73bf8 AP |
1512 | (p0) sub r34=r35,D |
1513 | (equ) cmp.leu break,cont=r35,H };; | |
622d3d35 | 1514 | { .mib; (cont) cmp.leu cont,break=HH,r31 |
4cb73bf8 | 1515 | (p8) add r31=-1,r31 |
622d3d35 | 1516 | (cont) br.wtop.spnt .L_divw_2nd_iter };; |
4cb73bf8 | 1517 | /////////////////////////////////////////////////////////// |
622d3d35 | 1518 | { .mii; sub H=H,r35 |
4cb73bf8 AP |
1519 | or r8=r8,r33 |
1520 | mov ar.pfs=r2 };; | |
622d3d35 | 1521 | { .mii; shr.u r9=H,I // remainder if anybody wants it |
46a0d4fb | 1522 | mov pr=r10,0x1ffff } |
622d3d35 | 1523 | { .mfb; br.ret.sptk.many b0 };; |
4cb73bf8 AP |
1524 | |
1525 | // Unsigned 64 by 32 (well, by 64 for the moment) bit integer division | |
1526 | // procedure. | |
1527 | // | |
a95541d6 AP |
1528 | // inputs: f6 = (double)a, f7 = (double)b |
1529 | // output: f8 = (int)(a/b) | |
622d3d35 AP |
1530 | // clobbered: f8,f9,f10,f11,pred |
1531 | pred=p15 | |
dcf6e50f RS |
1532 | // This snippet is based on text found in the "Divide, Square |
1533 | // Root and Remainder" section at | |
e2f2a9af AP |
1534 | // http://www.intel.com/software/products/opensource/libraries/num.htm. |
1535 | // Yes, I admit that the referred code was used as template, | |
1536 | // but after I realized that there hardly is any other instruction | |
1537 | // sequence which would perform this operation. I mean I figure that | |
1538 | // any independent attempt to implement high-performance division | |
1539 | // will result in code virtually identical to the Intel code. It | |
1540 | // should be noted though that below division kernel is 1 cycle | |
1541 | // faster than Intel one (note commented splits:-), not to mention | |
1542 | // original prologue (rather lack of one) and epilogue. | |
4cb73bf8 | 1543 | .align 32 |
622d3d35 | 1544 | .skip 16 |
4cb73bf8 | 1545 | .L_udiv64_32_b6: |
622d3d35 AP |
1546 | frcpa.s1 f8,pred=f6,f7;; // [0] y0 = 1 / b |
1547 | ||
1548 | (pred) fnma.s1 f9=f7,f8,f1 // [5] e0 = 1 - b * y0 | |
1549 | (pred) fmpy.s1 f10=f6,f8;; // [5] q0 = a * y0 | |
1550 | (pred) fmpy.s1 f11=f9,f9 // [10] e1 = e0 * e0 | |
1551 | (pred) fma.s1 f10=f9,f10,f10;; // [10] q1 = q0 + e0 * q0 | |
1552 | (pred) fma.s1 f8=f9,f8,f8 //;; // [15] y1 = y0 + e0 * y0 | |
1553 | (pred) fma.s1 f9=f11,f10,f10;; // [15] q2 = q1 + e1 * q1 | |
1554 | (pred) fma.s1 f8=f11,f8,f8 //;; // [20] y2 = y1 + e1 * y1 | |
1555 | (pred) fnma.s1 f10=f7,f9,f6;; // [20] r2 = a - b * q2 | |
1556 | (pred) fma.s1 f8=f10,f8,f9;; // [25] q3 = q2 + r2 * y2 | |
4cb73bf8 AP |
1557 | |
1558 | fcvt.fxu.trunc.s1 f8=f8 // [30] q = trunc(q3) | |
1559 | br.ret.sptk.many b6;; | |
1560 | .endp bn_div_words# | |
1561 | #endif |