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ARM assembly pack: make it Windows-friendly.
[thirdparty/openssl.git] / crypto / sha / asm / sha1-armv4-large.pl
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6aa36e8e
RS		 1#! /usr/bin/env perl
2# Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved.
3#
a598ed0d 4# Licensed under the Apache License 2.0 (the "License"). You may not use
6aa36e8e
RS		 5# this file except in compliance with the License. You can obtain a copy
6# in the file LICENSE in the source distribution or at
7# https://www.openssl.org/source/license.html
8
36b7c069
AP		 9
10# ====================================================================
9250a306 11# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
36b7c069
AP		 12# project. The module is, however, dual licensed under OpenSSL and
13# CRYPTOGAMS licenses depending on where you obtain it. For further
14# details see http://www.openssl.org/~appro/cryptogams/.
15# ====================================================================
16
0b0896cd 17# sha1_block procedure for ARMv4.
36b7c069
AP		 18#
19# January 2007.
20
21# Size/performance trade-off
22# ====================================================================
23# impl size in bytes comp cycles[*] measured performance
24# ====================================================================
25# thumb 304 3212 4420
0b0896cd
AP		 26# armv4-small 392/+29% 1958/+64% 2250/+96%
27# armv4-compact 740/+89% 1552/+26% 1840/+22%
eb1aa135
AP		 28# armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
29# full unroll ~5100/+260% ~1260/+4% ~1300/+5%
36b7c069
AP		 30# ====================================================================
31# thumb = same as 'small' but in Thumb instructions[**] and
32# with recurring code in two private functions;
33# small = detached Xload/update, loops are folded;
34# compact = detached Xload/update, 5x unroll;
35# large = interleaved Xload/update, 5x unroll;
36# full unroll = interleaved Xload/update, full unroll, estimated[!];
37#
38# [*] Manually counted instructions in "grand" loop body. Measured
39# performance is affected by prologue and epilogue overhead,
40# i-cache availability, branch penalties, etc.
41# [**] While each Thumb instruction is twice smaller, they are not as
42# diverse as ARM ones: e.g., there are only two arithmetic
43# instructions with 3 arguments, no [fixed] rotate, addressing
44# modes are limited. As result it takes more instructions to do
45# the same job in Thumb, therefore the code is never twice as
46# small and always slower.
c981086d
AP		 47# [***] which is also ~35% better than compiler generated code. Dual-
48# issue Cortex A8 core was measured to process input block in
49# ~990 cycles.
36b7c069 50
33d9c834
AP		 51# August 2010.
52#
53# Rescheduling for dual-issue pipeline resulted in 13% improvement on
54# Cortex A8 core and in absolute terms ~870 cycles per input block
55# [or 13.6 cycles per byte].
56
1e863180
AP		 57# February 2011.
58#
59# Profiler-assisted and platform-specific optimization resulted in 10%
60# improvement on Cortex A8 core and 12.2 cycles per byte.
33d9c834 61
9250a306
AP		 62# September 2013.
63#
64# Add NEON implementation (see sha1-586.pl for background info). On
65# Cortex A8 it was measured to process one byte in 6.7 cycles or >80%
66# faster than integer-only code. Because [fully unrolled] NEON code
67# is ~2.5x larger and there are some redundant instructions executed
68# when processing last block, improvement is not as big for smallest
69# blocks, only ~30%. Snapdragon S4 is a tad faster, 6.4 cycles per
e390ae50
AP		 70# byte, which is also >80% faster than integer-only code. Cortex-A15
71# is even faster spending 5.6 cycles per byte outperforming integer-
72# only code by factor of 2.
9250a306
AP		 73
74# May 2014.
75#
76# Add ARMv8 code path performing at 2.35 cpb on Apple A7.
77
313e6ec1 78$flavour = shift;
a5aa63a4
RL		 79if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
80else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} }
313e6ec1
AP		 81
82if ($flavour && $flavour ne "void") {
83 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
84 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
85 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
86 die "can't locate arm-xlate.pl";
87
88 open STDOUT,"| \"$^X\" $xlate $flavour $output";
89} else {
90 open STDOUT,">$output";
91}
4c7c5ff6 92
36b7c069
AP		 93$ctx="r0";
94$inp="r1";
95$len="r2";
96$a="r3";
97$b="r4";
98$c="r5";
99$d="r6";
100$e="r7";
101$K="r8";
eb1aa135
AP		 102$t0="r9";
103$t1="r10";
104$t2="r11";
105$t3="r12";
36b7c069
AP		 106$Xi="r14";
107@V=($a,$b,$c,$d,$e);
108
36b7c069 109sub Xupdate {
33d9c834 110my ($a,$b,$c,$d,$e,$opt1,$opt2)=@_;
36b7c069
AP		 111$code.=<<___;
112 ldr $t0,[$Xi,#15*4]
113 ldr $t1,[$Xi,#13*4]
114 ldr $t2,[$Xi,#7*4]
115 add $e,$K,$e,ror#2 @ E+=K_xx_xx
33d9c834 116 ldr $t3,[$Xi,#2*4]
36b7c069 117 eor $t0,$t0,$t1
1e863180 118 eor $t2,$t2,$t3 @ 1 cycle stall
33d9c834 119 eor $t1,$c,$d @ F_xx_xx
36b7c069 120 mov $t0,$t0,ror#31
33d9c834
AP		 121 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
122 eor $t0,$t0,$t2,ror#31
1e863180 123 str $t0,[$Xi,#-4]!
33d9c834
AP		 124 $opt1 @ F_xx_xx
125 $opt2 @ F_xx_xx
36b7c069 126 add $e,$e,$t0 @ E+=X[i]
36b7c069
AP		 127___
128}
129
130sub BODY_00_15 {
131my ($a,$b,$c,$d,$e)=@_;
36b7c069 132$code.=<<___;
1e863180 133#if __ARM_ARCH__<7
3739a772
AP		 134 ldrb $t1,[$inp,#2]
135 ldrb $t0,[$inp,#3]
136 ldrb $t2,[$inp,#1]
33d9c834 137 add $e,$K,$e,ror#2 @ E+=K_00_19
3739a772 138 ldrb $t3,[$inp],#4
3739a772 139 orr $t0,$t0,$t1,lsl#8
33d9c834 140 eor $t1,$c,$d @ F_xx_xx
3739a772 141 orr $t0,$t0,$t2,lsl#16
1e863180 142 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
3739a772 143 orr $t0,$t0,$t3,lsl#24
1e863180
AP		 144#else
145 ldr $t0,[$inp],#4 @ handles unaligned
146 add $e,$K,$e,ror#2 @ E+=K_00_19
147 eor $t1,$c,$d @ F_xx_xx
148 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
149#ifdef __ARMEL__
150 rev $t0,$t0 @ byte swap
151#endif
152#endif
36b7c069 153 and $t1,$b,$t1,ror#2
33d9c834 154 add $e,$e,$t0 @ E+=X[i]
36b7c069 155 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
33d9c834 156 str $t0,[$Xi,#-4]!
36b7c069
AP		 157 add $e,$e,$t1 @ E+=F_00_19(B,C,D)
158___
159}
160
161sub BODY_16_19 {
162my ($a,$b,$c,$d,$e)=@_;
33d9c834 163 &Xupdate(@_,"and $t1,$b,$t1,ror#2");
36b7c069 164$code.=<<___;
36b7c069
AP		 165 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
166 add $e,$e,$t1 @ E+=F_00_19(B,C,D)
167___
168}
169
170sub BODY_20_39 {
171my ($a,$b,$c,$d,$e)=@_;
33d9c834 172 &Xupdate(@_,"eor $t1,$b,$t1,ror#2");
36b7c069 173$code.=<<___;
36b7c069
AP		 174 add $e,$e,$t1 @ E+=F_20_39(B,C,D)
175___
176}
177
178sub BODY_40_59 {
179my ($a,$b,$c,$d,$e)=@_;
33d9c834 180 &Xupdate(@_,"and $t1,$b,$t1,ror#2","and $t2,$c,$d");
5727f1f7 181$code.=<<___;
36b7c069 182 add $e,$e,$t1 @ E+=F_40_59(B,C,D)
33d9c834 183 add $e,$e,$t2,ror#2
36b7c069
AP		 184___
185}
186
187$code=<<___;
1e863180
AP		 188#include "arm_arch.h"
189
a2859927 190#if defined(__thumb2__)
11208dcf
AP		 191.syntax unified
192.thumb
193#else
9250a306 194.code 32
11208dcf 195#endif
36b7c069 196
3405db97
AP		 197.text
198
36b7c069
AP		 199.global sha1_block_data_order
200.type sha1_block_data_order,%function
201
9250a306 202.align 5
36b7c069 203sha1_block_data_order:
c1669e1c 204#if __ARM_MAX_ARCH__>=7
11208dcf 205.Lsha1_block:
9250a306 206 ldr r12,.LOPENSSL_armcap
3405db97
AP		 207# if !defined(_WIN32)
208 adr r3,.Lsha1_block
9250a306 209 ldr r12,[r3,r12] @ OPENSSL_armcap_P
3405db97
AP		 210# endif
211# if defined(__APPLE__) || defined(_WIN32)
313e6ec1 212 ldr r12,[r12]
3405db97 213# endif
797d24be 214 tst r12,#ARMV8_SHA1
9250a306 215 bne .LARMv8
797d24be 216 tst r12,#ARMV7_NEON
9250a306
AP		 217 bne .LNEON
218#endif
36b7c069
AP		 219 stmdb sp!,{r4-r12,lr}
220 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
221 ldmia $ctx,{$a,$b,$c,$d,$e}
222.Lloop:
223 ldr $K,.LK_00_19
224 mov $Xi,sp
225 sub sp,sp,#15*4
226 mov $c,$c,ror#30
227 mov $d,$d,ror#30
228 mov $e,$e,ror#30 @ [6]
229.L_00_15:
230___
231for($i=0;$i<5;$i++) {
232 &BODY_00_15(@V); unshift(@V,pop(@V));
233}
234$code.=<<___;
a2859927 235#if defined(__thumb2__)
11208dcf
AP		 236 mov $t3,sp
237 teq $Xi,$t3
238#else
36b7c069 239 teq $Xi,sp
11208dcf 240#endif
36b7c069 241 bne .L_00_15 @ [((11+4)*5+2)*3]
1a9d60d2 242 sub sp,sp,#25*4
36b7c069
AP		 243___
244 &BODY_00_15(@V); unshift(@V,pop(@V));
245 &BODY_16_19(@V); unshift(@V,pop(@V));
246 &BODY_16_19(@V); unshift(@V,pop(@V));
247 &BODY_16_19(@V); unshift(@V,pop(@V));
248 &BODY_16_19(@V); unshift(@V,pop(@V));
249$code.=<<___;
250
251 ldr $K,.LK_20_39 @ [+15+16*4]
36b7c069
AP		 252 cmn sp,#0 @ [+3], clear carry to denote 20_39
253.L_20_39_or_60_79:
254___
255for($i=0;$i<5;$i++) {
256 &BODY_20_39(@V); unshift(@V,pop(@V));
257}
258$code.=<<___;
a2859927 259#if defined(__thumb2__)
11208dcf
AP		 260 mov $t3,sp
261 teq $Xi,$t3
262#else
36b7c069 263 teq $Xi,sp @ preserve carry
11208dcf 264#endif
36b7c069
AP		 265 bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
266 bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
267
268 ldr $K,.LK_40_59
269 sub sp,sp,#20*4 @ [+2]
270.L_40_59:
271___
272for($i=0;$i<5;$i++) {
273 &BODY_40_59(@V); unshift(@V,pop(@V));
274}
275$code.=<<___;
a2859927 276#if defined(__thumb2__)
11208dcf
AP		 277 mov $t3,sp
278 teq $Xi,$t3
279#else
36b7c069 280 teq $Xi,sp
11208dcf 281#endif
36b7c069
AP		 282 bne .L_40_59 @ [+((12+5)*5+2)*4]
283
284 ldr $K,.LK_60_79
285 sub sp,sp,#20*4
286 cmp sp,#0 @ set carry to denote 60_79
287 b .L_20_39_or_60_79 @ [+4], spare 300 bytes
288.L_done:
289 add sp,sp,#80*4 @ "deallocate" stack frame
96826bfc 290 ldmia $ctx,{$K,$t0,$t1,$t2,$t3}
36b7c069
AP		 291 add $a,$K,$a
292 add $b,$t0,$b
293 add $c,$t1,$c,ror#2
294 add $d,$t2,$d,ror#2
96826bfc 295 add $e,$t3,$e,ror#2
36b7c069
AP		 296 stmia $ctx,{$a,$b,$c,$d,$e}
297 teq $inp,$len
298 bne .Lloop @ [+18], total 1307
299
1e863180
AP		 300#if __ARM_ARCH__>=5
301 ldmia sp!,{r4-r12,pc}
302#else
36b7c069
AP		 303 ldmia sp!,{r4-r12,lr}
304 tst lr,#1
305 moveq pc,lr @ be binary compatible with V4, yet
306 bx lr @ interoperable with Thumb ISA:-)
1e863180 307#endif
9250a306
AP		 308.size sha1_block_data_order,.-sha1_block_data_order
309
310.align 5
36b7c069
AP		 311.LK_00_19: .word 0x5a827999
312.LK_20_39: .word 0x6ed9eba1
313.LK_40_59: .word 0x8f1bbcdc
314.LK_60_79: .word 0xca62c1d6
c1669e1c 315#if __ARM_MAX_ARCH__>=7
9250a306 316.LOPENSSL_armcap:
3405db97
AP		 317# ifdef _WIN32
318.word OPENSSL_armcap_P
319# else
11208dcf 320.word OPENSSL_armcap_P-.Lsha1_block
3405db97 321# endif
c1669e1c 322#endif
9250a306
AP		 323.asciz "SHA1 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
324.align 5
325___
326#####################################################################
327# NEON stuff
328#
329{{{
330my @V=($a,$b,$c,$d,$e);
331my ($K_XX_XX,$Ki,$t0,$t1,$Xfer,$saved_sp)=map("r$_",(8..12,14));
332my $Xi=4;
333my @X=map("q$_",(8..11,0..3));
334my @Tx=("q12","q13");
335my ($K,$zero)=("q14","q15");
336my $j=0;
337
338sub AUTOLOAD() # thunk [simplified] x86-style perlasm
339{ my $opcode = $AUTOLOAD; $opcode =~ s/.*:://; $opcode =~ s/_/\./;
340 my $arg = pop;
341 $arg = "#$arg" if ($arg*1 eq $arg);
342 $code .= "\t$opcode\t".join(',',@_,$arg)."\n";
343}
344
345sub body_00_19 () {
346 (
347 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
348 '&bic ($t0,$d,$b)',
349 '&add ($e,$e,$Ki)', # e+=X[i]+K
350 '&and ($t1,$c,$b)',
351 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))',
352 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
353 '&eor ($t1,$t1,$t0)', # F_00_19
354 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
355 '&add ($e,$e,$t1);'. # e+=F_00_19
356 '$j++; unshift(@V,pop(@V));'
357 )
358}
359sub body_20_39 () {
360 (
361 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
362 '&eor ($t0,$b,$d)',
363 '&add ($e,$e,$Ki)', # e+=X[i]+K
364 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15)) if ($j<79)',
365 '&eor ($t1,$t0,$c)', # F_20_39
366 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
367 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
368 '&add ($e,$e,$t1);'. # e+=F_20_39
369 '$j++; unshift(@V,pop(@V));'
370 )
371}
372sub body_40_59 () {
373 (
374 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
375 '&add ($e,$e,$Ki)', # e+=X[i]+K
376 '&and ($t0,$c,$d)',
377 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))',
378 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
379 '&eor ($t1,$c,$d)',
380 '&add ($e,$e,$t0)',
381 '&and ($t1,$t1,$b)',
382 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
383 '&add ($e,$e,$t1);'. # e+=F_40_59
384 '$j++; unshift(@V,pop(@V));'
385 )
386}
387
388sub Xupdate_16_31 ()
389{ use integer;
390 my $body = shift;
391 my @insns = (&$body,&$body,&$body,&$body);
392 my ($a,$b,$c,$d,$e);
393
394 &vext_8 (@X[0],@X[-4&7],@X[-3&7],8); # compose "X[-14]" in "X[0]"
395 eval(shift(@insns));
396 eval(shift(@insns));
397 eval(shift(@insns));
398 &vadd_i32 (@Tx[1],@X[-1&7],$K);
399 eval(shift(@insns));
400 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0);
401 eval(shift(@insns));
402 &vext_8 (@Tx[0],@X[-1&7],$zero,4); # "X[-3]", 3 words
403 eval(shift(@insns));
404 eval(shift(@insns));
405 eval(shift(@insns));
406 &veor (@X[0],@X[0],@X[-4&7]); # "X[0]"^="X[-16]"
407 eval(shift(@insns));
408 eval(shift(@insns));
409 &veor (@Tx[0],@Tx[0],@X[-2&7]); # "X[-3]"^"X[-8]"
410 eval(shift(@insns));
411 eval(shift(@insns));
412 &veor (@Tx[0],@Tx[0],@X[0]); # "X[0]"^="X[-3]"^"X[-8]
413 eval(shift(@insns));
414 eval(shift(@insns));
415 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer
416 &sub ($Xfer,$Xfer,64) if ($Xi%4==0);
417 eval(shift(@insns));
418 eval(shift(@insns));
419 &vext_8 (@Tx[1],$zero,@Tx[0],4); # "X[0]"<<96, extract one dword
420 eval(shift(@insns));
421 eval(shift(@insns));
422 &vadd_i32 (@X[0],@Tx[0],@Tx[0]);
423 eval(shift(@insns));
424 eval(shift(@insns));
425 &vsri_32 (@X[0],@Tx[0],31); # "X[0]"<<<=1
426 eval(shift(@insns));
427 eval(shift(@insns));
428 eval(shift(@insns));
429 &vshr_u32 (@Tx[0],@Tx[1],30);
430 eval(shift(@insns));
431 eval(shift(@insns));
432 &vshl_u32 (@Tx[1],@Tx[1],2);
433 eval(shift(@insns));
434 eval(shift(@insns));
435 &veor (@X[0],@X[0],@Tx[0]);
436 eval(shift(@insns));
437 eval(shift(@insns));
438 &veor (@X[0],@X[0],@Tx[1]); # "X[0]"^=("X[0]">>96)<<<2
439
440 foreach (@insns) { eval; } # remaining instructions [if any]
441
442 $Xi++; push(@X,shift(@X)); # "rotate" X[]
443}
444
445sub Xupdate_32_79 ()
446{ use integer;
447 my $body = shift;
448 my @insns = (&$body,&$body,&$body,&$body);
449 my ($a,$b,$c,$d,$e);
450
451 &vext_8 (@Tx[0],@X[-2&7],@X[-1&7],8); # compose "X[-6]"
452 eval(shift(@insns));
453 eval(shift(@insns));
454 eval(shift(@insns));
455 &veor (@X[0],@X[0],@X[-4&7]); # "X[0]"="X[-32]"^"X[-16]"
456 eval(shift(@insns));
457 eval(shift(@insns));
458 &veor (@X[0],@X[0],@X[-7&7]); # "X[0]"^="X[-28]"
459 eval(shift(@insns));
460 eval(shift(@insns));
461 &vadd_i32 (@Tx[1],@X[-1&7],$K);
462 eval(shift(@insns));
463 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0);
464 eval(shift(@insns));
465 &veor (@Tx[0],@Tx[0],@X[0]); # "X[-6]"^="X[0]"
466 eval(shift(@insns));
467 eval(shift(@insns));
468 &vshr_u32 (@X[0],@Tx[0],30);
469 eval(shift(@insns));
470 eval(shift(@insns));
471 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer
472 &sub ($Xfer,$Xfer,64) if ($Xi%4==0);
473 eval(shift(@insns));
474 eval(shift(@insns));
475 &vsli_32 (@X[0],@Tx[0],2); # "X[0]"="X[-6]"<<<2
476
477 foreach (@insns) { eval; } # remaining instructions [if any]
478
479 $Xi++; push(@X,shift(@X)); # "rotate" X[]
480}
481
482sub Xuplast_80 ()
483{ use integer;
484 my $body = shift;
485 my @insns = (&$body,&$body,&$body,&$body);
486 my ($a,$b,$c,$d,$e);
487
488 &vadd_i32 (@Tx[1],@X[-1&7],$K);
489 eval(shift(@insns));
490 eval(shift(@insns));
491 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!");
492 &sub ($Xfer,$Xfer,64);
493
494 &teq ($inp,$len);
495 &sub ($K_XX_XX,$K_XX_XX,16); # rewind $K_XX_XX
11208dcf 496 &it ("eq");
9250a306
AP		 497 &subeq ($inp,$inp,64); # reload last block to avoid SEGV
498 &vld1_8 ("{@X[-4&7]-@X[-3&7]}","[$inp]!");
499 eval(shift(@insns));
500 eval(shift(@insns));
501 &vld1_8 ("{@X[-2&7]-@X[-1&7]}","[$inp]!");
502 eval(shift(@insns));
503 eval(shift(@insns));
504 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!"); # load K_00_19
505 eval(shift(@insns));
506 eval(shift(@insns));
507 &vrev32_8 (@X[-4&7],@X[-4&7]);
508
509 foreach (@insns) { eval; } # remaining instructions
510
511 $Xi=0;
512}
513
514sub Xloop()
515{ use integer;
516 my $body = shift;
517 my @insns = (&$body,&$body,&$body,&$body);
518 my ($a,$b,$c,$d,$e);
519
520 &vrev32_8 (@X[($Xi-3)&7],@X[($Xi-3)&7]);
521 eval(shift(@insns));
522 eval(shift(@insns));
523 &vadd_i32 (@X[$Xi&7],@X[($Xi-4)&7],$K);
524 eval(shift(@insns));
525 eval(shift(@insns));
526 &vst1_32 ("{@X[$Xi&7]}","[$Xfer,:128]!");# X[]+K xfer to IALU
527
528 foreach (@insns) { eval; }
529
530 $Xi++;
531}
532
533$code.=<<___;
c1669e1c
AP		 534#if __ARM_MAX_ARCH__>=7
535.arch armv7-a
9250a306
AP		 536.fpu neon
537
538.type sha1_block_data_order_neon,%function
539.align 4
540sha1_block_data_order_neon:
541.LNEON:
542 stmdb sp!,{r4-r12,lr}
543 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
544 @ dmb @ errata #451034 on early Cortex A8
545 @ vstmdb sp!,{d8-d15} @ ABI specification says so
546 mov $saved_sp,sp
11208dcf 547 sub $Xfer,sp,#64
9250a306 548 adr $K_XX_XX,.LK_00_19
11208dcf 549 bic $Xfer,$Xfer,#15 @ align for 128-bit stores
9250a306
AP		 550
551 ldmia $ctx,{$a,$b,$c,$d,$e} @ load context
11208dcf 552 mov sp,$Xfer @ alloca
9250a306
AP		 553
554 vld1.8 {@X[-4&7]-@X[-3&7]},[$inp]! @ handles unaligned
555 veor $zero,$zero,$zero
556 vld1.8 {@X[-2&7]-@X[-1&7]},[$inp]!
557 vld1.32 {${K}\[]},[$K_XX_XX,:32]! @ load K_00_19
558 vrev32.8 @X[-4&7],@X[-4&7] @ yes, even on
559 vrev32.8 @X[-3&7],@X[-3&7] @ big-endian...
560 vrev32.8 @X[-2&7],@X[-2&7]
561 vadd.i32 @X[0],@X[-4&7],$K
562 vrev32.8 @X[-1&7],@X[-1&7]
563 vadd.i32 @X[1],@X[-3&7],$K
564 vst1.32 {@X[0]},[$Xfer,:128]!
565 vadd.i32 @X[2],@X[-2&7],$K
566 vst1.32 {@X[1]},[$Xfer,:128]!
567 vst1.32 {@X[2]},[$Xfer,:128]!
568 ldr $Ki,[sp] @ big RAW stall
569
570.Loop_neon:
571___
572 &Xupdate_16_31(\&body_00_19);
573 &Xupdate_16_31(\&body_00_19);
574 &Xupdate_16_31(\&body_00_19);
575 &Xupdate_16_31(\&body_00_19);
576 &Xupdate_32_79(\&body_00_19);
577 &Xupdate_32_79(\&body_20_39);
578 &Xupdate_32_79(\&body_20_39);
579 &Xupdate_32_79(\&body_20_39);
580 &Xupdate_32_79(\&body_20_39);
581 &Xupdate_32_79(\&body_20_39);
582 &Xupdate_32_79(\&body_40_59);
583 &Xupdate_32_79(\&body_40_59);
584 &Xupdate_32_79(\&body_40_59);
585 &Xupdate_32_79(\&body_40_59);
586 &Xupdate_32_79(\&body_40_59);
587 &Xupdate_32_79(\&body_20_39);
588 &Xuplast_80(\&body_20_39);
589 &Xloop(\&body_20_39);
590 &Xloop(\&body_20_39);
591 &Xloop(\&body_20_39);
592$code.=<<___;
593 ldmia $ctx,{$Ki,$t0,$t1,$Xfer} @ accumulate context
594 add $a,$a,$Ki
595 ldr $Ki,[$ctx,#16]
596 add $b,$b,$t0
597 add $c,$c,$t1
598 add $d,$d,$Xfer
11208dcf 599 it eq
9250a306
AP		 600 moveq sp,$saved_sp
601 add $e,$e,$Ki
11208dcf 602 it ne
9250a306
AP		 603 ldrne $Ki,[sp]
604 stmia $ctx,{$a,$b,$c,$d,$e}
11208dcf 605 itt ne
9250a306
AP		 606 addne $Xfer,sp,#3*16
607 bne .Loop_neon
608
609 @ vldmia sp!,{d8-d15}
610 ldmia sp!,{r4-r12,pc}
611.size sha1_block_data_order_neon,.-sha1_block_data_order_neon
612#endif
613___
614}}}
615#####################################################################
616# ARMv8 stuff
617#
618{{{
619my ($ABCD,$E,$E0,$E1)=map("q$_",(0..3));
620my @MSG=map("q$_",(4..7));
621my @Kxx=map("q$_",(8..11));
622my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
3405db97 623my $_byte = ($flavour =~ /win/ ? "DCB" : ".byte");
9250a306
AP		 624
625$code.=<<___;
c1669e1c 626#if __ARM_MAX_ARCH__>=7
11208dcf 627
a2859927 628# if defined(__thumb2__)
3405db97 629# define INST(a,b,c,d) $_byte c,d|0xf,a,b
11208dcf 630# else
3405db97 631# define INST(a,b,c,d) $_byte a,b,c,d|0x10
11208dcf
AP		 632# endif
633
9250a306
AP		 634.type sha1_block_data_order_armv8,%function
635.align 5
636sha1_block_data_order_armv8:
637.LARMv8:
638 vstmdb sp!,{d8-d15} @ ABI specification says so
639
640 veor $E,$E,$E
641 adr r3,.LK_00_19
642 vld1.32 {$ABCD},[$ctx]!
643 vld1.32 {$E\[0]},[$ctx]
644 sub $ctx,$ctx,#16
645 vld1.32 {@Kxx[0]\[]},[r3,:32]!
646 vld1.32 {@Kxx[1]\[]},[r3,:32]!
647 vld1.32 {@Kxx[2]\[]},[r3,:32]!
648 vld1.32 {@Kxx[3]\[]},[r3,:32]
649
650.Loop_v8:
651 vld1.8 {@MSG[0]-@MSG[1]},[$inp]!
652 vld1.8 {@MSG[2]-@MSG[3]},[$inp]!
653 vrev32.8 @MSG[0],@MSG[0]
654 vrev32.8 @MSG[1],@MSG[1]
655
656 vadd.i32 $W0,@Kxx[0],@MSG[0]
657 vrev32.8 @MSG[2],@MSG[2]
658 vmov $ABCD_SAVE,$ABCD @ offload
659 subs $len,$len,#1
660
661 vadd.i32 $W1,@Kxx[0],@MSG[1]
662 vrev32.8 @MSG[3],@MSG[3]
663 sha1h $E1,$ABCD @ 0
664 sha1c $ABCD,$E,$W0
665 vadd.i32 $W0,@Kxx[$j],@MSG[2]
666 sha1su0 @MSG[0],@MSG[1],@MSG[2]
667___
668for ($j=0,$i=1;$i<20-3;$i++) {
669my $f=("c","p","m","p")[$i/5];
670$code.=<<___;
671 sha1h $E0,$ABCD @ $i
672 sha1$f $ABCD,$E1,$W1
673 vadd.i32 $W1,@Kxx[$j],@MSG[3]
674 sha1su1 @MSG[0],@MSG[3]
675___
676$code.=<<___ if ($i<20-4);
677 sha1su0 @MSG[1],@MSG[2],@MSG[3]
36b7c069 678___
9250a306
AP		 679 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
680 push(@MSG,shift(@MSG)); $j++ if ((($i+3)%5)==0);
681}
682$code.=<<___;
683 sha1h $E0,$ABCD @ $i
684 sha1p $ABCD,$E1,$W1
685 vadd.i32 $W1,@Kxx[$j],@MSG[3]
686
687 sha1h $E1,$ABCD @ 18
688 sha1p $ABCD,$E0,$W0
689
690 sha1h $E0,$ABCD @ 19
691 sha1p $ABCD,$E1,$W1
692
693 vadd.i32 $E,$E,$E0
694 vadd.i32 $ABCD,$ABCD,$ABCD_SAVE
695 bne .Loop_v8
696
697 vst1.32 {$ABCD},[$ctx]!
698 vst1.32 {$E\[0]},[$ctx]
699
700 vldmia sp!,{d8-d15}
5dcf70a1 701 ret @ bx lr
9250a306
AP		 702.size sha1_block_data_order_armv8,.-sha1_block_data_order_armv8
703#endif
704___
705}}}
706$code.=<<___;
c1669e1c 707#if __ARM_MAX_ARCH__>=7
9250a306 708.comm OPENSSL_armcap_P,4,4
c1669e1c 709#endif
9250a306
AP		 710___
711
712{ my %opcode = (
713 "sha1c" => 0xf2000c40, "sha1p" => 0xf2100c40,
714 "sha1m" => 0xf2200c40, "sha1su0" => 0xf2300c40,
715 "sha1h" => 0xf3b902c0, "sha1su1" => 0xf3ba0380 );
716
717 sub unsha1 {
718 my ($mnemonic,$arg)=@_;
719
5dcf70a1
AP		 720 if ($arg =~ m/q([0-9]+)(?:,\s*q([0-9]+))?,\s*q([0-9]+)/o) {
721 my $word = $opcode{$mnemonic}|(($1&7)<<13)|(($1&8)<<19)
722 |(($2&7)<<17)|(($2&8)<<4)
723 |(($3&7)<<1) |(($3&8)<<2);
724 # since ARMv7 instructions are always encoded little-endian.
725 # correct solution is to use .inst directive, but older
726 # assemblers don't implement it:-(
11208dcf
AP		 727
728 # this fix-up provides Thumb encoding in conjunction with INST
729 $word &= ~0x10000000 if (($word & 0x0f000000) == 0x02000000);
730 sprintf "INST(0x%02x,0x%02x,0x%02x,0x%02x)\t@ %s %s",
5dcf70a1
AP		 731 $word&0xff,($word>>8)&0xff,
732 ($word>>16)&0xff,($word>>24)&0xff,
9250a306 733 $mnemonic,$arg;
5dcf70a1 734 }
9250a306
AP		 735 }
736}
737
738foreach (split($/,$code)) {
739 s/{q([0-9]+)\[\]}/sprintf "{d%d[],d%d[]}",2*$1,2*$1+1/eo or
740 s/{q([0-9]+)\[0\]}/sprintf "{d%d[0]}",2*$1/eo;
741
742 s/\b(sha1\w+)\s+(q.*)/unsha1($1,$2)/geo;
743
5dcf70a1 744 s/\bret\b/bx lr/o or
9250a306
AP		 745 s/\bbx\s+lr\b/.word\t0xe12fff1e/o; # make it possible to compile with -march=armv4
746
747 print $_,$/;
748}
36b7c069 749
4c7c5ff6 750close STDOUT; # enforce flush
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