[thirdparty/openssl.git] / crypto / sha / asm / sha1-sparcv9.pl

#! /usr/bin/env perl
# Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
#
# Licensed under the Apache License 2.0 (the "License").  You may not use
# this file except in compliance with the License.  You can obtain a copy
# in the file LICENSE in the source distribution or at
# https://www.openssl.org/source/license.html


# ====================================================================
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
# details see http://www.openssl.org/~appro/cryptogams/.
#
# Hardware SPARC T4 support by David S. Miller
# ====================================================================

# Performance improvement is not really impressive on pre-T1 CPU: +8%
# over Sun C and +25% over gcc [3.3]. While on T1, a.k.a. Niagara, it
# turned to be 40% faster than 64-bit code generated by Sun C 5.8 and
# >2x than 64-bit code generated by gcc 3.4. And there is a gimmick.
# X[16] vector is packed to 8 64-bit registers and as result nothing
# is spilled on stack. In addition input data is loaded in compact
# instruction sequence, thus minimizing the window when the code is
# subject to [inter-thread] cache-thrashing hazard. The goal is to
# ensure scalability on UltraSPARC T1, or rather to avoid decay when
# amount of active threads exceeds the number of physical cores.

# SPARC T4 SHA1 hardware achieves 3.72 cycles per byte, which is 3.1x
# faster than software. Multi-process benchmark saturates at 11x
# single-process result on 8-core processor, or ~9GBps per 2.85GHz
# socket.

$output=pop and open STDOUT,">$output";

@X=("%o0","%o1","%o2","%o3","%o4","%o5","%g1","%o7");
$rot1m="%g2";
$tmp64="%g3";
$Xi="%g4";
$A="%l0";
$B="%l1";
$C="%l2";
$D="%l3";
$E="%l4";
@V=($A,$B,$C,$D,$E);
$K_00_19="%l5";
$K_20_39="%l6";
$K_40_59="%l7";
$K_60_79="%g5";
@K=($K_00_19,$K_20_39,$K_40_59,$K_60_79);

$ctx="%i0";
$inp="%i1";
$len="%i2";
$tmp0="%i3";
$tmp1="%i4";
$tmp2="%i5";

sub BODY_00_15 {
my ($i,$a,$b,$c,$d,$e)=@_;
my $xi=($i&1)?@X[($i/2)%8]:$Xi;

$code.=<<___;
	sll	$a,5,$tmp0		!! $i
	add	@K[$i/20],$e,$e
	srl	$a,27,$tmp1
	add	$tmp0,$e,$e
	and	$c,$b,$tmp0
	add	$tmp1,$e,$e
	sll	$b,30,$tmp2
	andn	$d,$b,$tmp1
	srl	$b,2,$b
	or	$tmp1,$tmp0,$tmp1
	or	$tmp2,$b,$b
	add	$xi,$e,$e
___
if ($i&1 && $i<15) {
	$code.=
	"	srlx	@X[(($i+1)/2)%8],32,$Xi\n";
}
$code.=<<___;
	add	$tmp1,$e,$e
___
}

sub Xupdate {
my ($i,$a,$b,$c,$d,$e)=@_;
my $j=$i/2;

if ($i&1) {
$code.=<<___;
	sll	$a,5,$tmp0		!! $i
	add	@K[$i/20],$e,$e
	srl	$a,27,$tmp1
___
} else {
$code.=<<___;
	sllx	@X[($j+6)%8],32,$Xi	! Xupdate($i)
	xor	@X[($j+1)%8],@X[$j%8],@X[$j%8]
	srlx	@X[($j+7)%8],32,$tmp1
	xor	@X[($j+4)%8],@X[$j%8],@X[$j%8]
	sll	$a,5,$tmp0		!! $i
	or	$tmp1,$Xi,$Xi
	add	@K[$i/20],$e,$e		!!
	xor	$Xi,@X[$j%8],@X[$j%8]
	srlx	@X[$j%8],31,$Xi
	add	@X[$j%8],@X[$j%8],@X[$j%8]
	and	$Xi,$rot1m,$Xi
	andn	@X[$j%8],$rot1m,@X[$j%8]
	srl	$a,27,$tmp1		!!
	or	$Xi,@X[$j%8],@X[$j%8]
___
}
}

sub BODY_16_19 {
my ($i,$a,$b,$c,$d,$e)=@_;

	&Xupdate(@_);
    if ($i&1) {
	$xi=@X[($i/2)%8];
    } else {
	$xi=$Xi;
	$code.="\tsrlx	@X[($i/2)%8],32,$xi\n";
    }
$code.=<<___;
	add	$tmp0,$e,$e		!!
	and	$c,$b,$tmp0
	add	$tmp1,$e,$e
	sll	$b,30,$tmp2
	add	$xi,$e,$e
	andn	$d,$b,$tmp1
	srl	$b,2,$b
	or	$tmp1,$tmp0,$tmp1
	or	$tmp2,$b,$b
	add	$tmp1,$e,$e
___
}

sub BODY_20_39 {
my ($i,$a,$b,$c,$d,$e)=@_;
my $xi;
	&Xupdate(@_);
    if ($i&1) {
	$xi=@X[($i/2)%8];
    } else {
	$xi=$Xi;
	$code.="\tsrlx	@X[($i/2)%8],32,$xi\n";
    }
$code.=<<___;
	add	$tmp0,$e,$e		!!
	xor	$c,$b,$tmp0
	add	$tmp1,$e,$e
	sll	$b,30,$tmp2
	xor	$d,$tmp0,$tmp1
	srl	$b,2,$b
	add	$tmp1,$e,$e
	or	$tmp2,$b,$b
	add	$xi,$e,$e
___
}

sub BODY_40_59 {
my ($i,$a,$b,$c,$d,$e)=@_;
my $xi;
	&Xupdate(@_);
    if ($i&1) {
	$xi=@X[($i/2)%8];
    } else {
	$xi=$Xi;
	$code.="\tsrlx	@X[($i/2)%8],32,$xi\n";
    }
$code.=<<___;
	add	$tmp0,$e,$e		!!
	and	$c,$b,$tmp0
	add	$tmp1,$e,$e
	sll	$b,30,$tmp2
	or	$c,$b,$tmp1
	srl	$b,2,$b
	and	$d,$tmp1,$tmp1
	add	$xi,$e,$e
	or	$tmp1,$tmp0,$tmp1
	or	$tmp2,$b,$b
	add	$tmp1,$e,$e
___
}

$code.=<<___;
#include "sparc_arch.h"

#ifdef __arch64__
.register	%g2,#scratch
.register	%g3,#scratch
#endif

.section	".text",#alloc,#execinstr

#ifdef __PIC__
SPARC_PIC_THUNK(%g1)
#endif

.align	32
.globl	sha1_block_data_order
sha1_block_data_order:
	SPARC_LOAD_ADDRESS_LEAF(OPENSSL_sparcv9cap_P,%g1,%g5)
	ld	[%g1+4],%g1		! OPENSSL_sparcv9cap_P[1]

	andcc	%g1, CFR_SHA1, %g0
	be	.Lsoftware
	nop

	ld	[%o0 + 0x00], %f0	! load context
	ld	[%o0 + 0x04], %f1
	ld	[%o0 + 0x08], %f2
	andcc	%o1, 0x7, %g0
	ld	[%o0 + 0x0c], %f3
	bne,pn	%icc, .Lhwunaligned
	 ld	[%o0 + 0x10], %f4

.Lhw_loop:
	ldd	[%o1 + 0x00], %f8
	ldd	[%o1 + 0x08], %f10
	ldd	[%o1 + 0x10], %f12
	ldd	[%o1 + 0x18], %f14
	ldd	[%o1 + 0x20], %f16
	ldd	[%o1 + 0x28], %f18
	ldd	[%o1 + 0x30], %f20
	subcc	%o2, 1, %o2		! done yet?
	ldd	[%o1 + 0x38], %f22
	add	%o1, 0x40, %o1
	prefetch [%o1 + 63], 20

	.word	0x81b02820		! SHA1

	bne,pt	SIZE_T_CC, .Lhw_loop
	nop

.Lhwfinish:
	st	%f0, [%o0 + 0x00]	! store context
	st	%f1, [%o0 + 0x04]
	st	%f2, [%o0 + 0x08]
	st	%f3, [%o0 + 0x0c]
	retl
	st	%f4, [%o0 + 0x10]

.align	8
.Lhwunaligned:
	alignaddr %o1, %g0, %o1

	ldd	[%o1 + 0x00], %f10
.Lhwunaligned_loop:
	ldd	[%o1 + 0x08], %f12
	ldd	[%o1 + 0x10], %f14
	ldd	[%o1 + 0x18], %f16
	ldd	[%o1 + 0x20], %f18
	ldd	[%o1 + 0x28], %f20
	ldd	[%o1 + 0x30], %f22
	ldd	[%o1 + 0x38], %f24
	subcc	%o2, 1, %o2		! done yet?
	ldd	[%o1 + 0x40], %f26
	add	%o1, 0x40, %o1
	prefetch [%o1 + 63], 20

	faligndata %f10, %f12, %f8
	faligndata %f12, %f14, %f10
	faligndata %f14, %f16, %f12
	faligndata %f16, %f18, %f14
	faligndata %f18, %f20, %f16
	faligndata %f20, %f22, %f18
	faligndata %f22, %f24, %f20
	faligndata %f24, %f26, %f22

	.word	0x81b02820		! SHA1

	bne,pt	SIZE_T_CC, .Lhwunaligned_loop
	for	%f26, %f26, %f10	! %f10=%f26

	ba	.Lhwfinish
	nop

.align	16
.Lsoftware:
	save	%sp,-STACK_FRAME,%sp
	sllx	$len,6,$len
	add	$inp,$len,$len

	or	%g0,1,$rot1m
	sllx	$rot1m,32,$rot1m
	or	$rot1m,1,$rot1m

	ld	[$ctx+0],$A
	ld	[$ctx+4],$B
	ld	[$ctx+8],$C
	ld	[$ctx+12],$D
	ld	[$ctx+16],$E
	andn	$inp,7,$tmp0

	sethi	%hi(0x5a827999),$K_00_19
	or	$K_00_19,%lo(0x5a827999),$K_00_19
	sethi	%hi(0x6ed9eba1),$K_20_39
	or	$K_20_39,%lo(0x6ed9eba1),$K_20_39
	sethi	%hi(0x8f1bbcdc),$K_40_59
	or	$K_40_59,%lo(0x8f1bbcdc),$K_40_59
	sethi	%hi(0xca62c1d6),$K_60_79
	or	$K_60_79,%lo(0xca62c1d6),$K_60_79

.Lloop:
	ldx	[$tmp0+0],@X[0]
	ldx	[$tmp0+16],@X[2]
	ldx	[$tmp0+32],@X[4]
	ldx	[$tmp0+48],@X[6]
	and	$inp,7,$tmp1
	ldx	[$tmp0+8],@X[1]
	sll	$tmp1,3,$tmp1
	ldx	[$tmp0+24],@X[3]
	subcc	%g0,$tmp1,$tmp2	! should be 64-$tmp1, but -$tmp1 works too
	ldx	[$tmp0+40],@X[5]
	bz,pt	%icc,.Laligned
	ldx	[$tmp0+56],@X[7]

	sllx	@X[0],$tmp1,@X[0]
	ldx	[$tmp0+64],$tmp64
___
for($i=0;$i<7;$i++)
{   $code.=<<___;
	srlx	@X[$i+1],$tmp2,$Xi
	sllx	@X[$i+1],$tmp1,@X[$i+1]
	or	$Xi,@X[$i],@X[$i]
___
}
$code.=<<___;
	srlx	$tmp64,$tmp2,$tmp64
	or	$tmp64,@X[7],@X[7]
.Laligned:
	srlx	@X[0],32,$Xi
___
for ($i=0;$i<16;$i++)	{ &BODY_00_15($i,@V); unshift(@V,pop(@V)); }
for (;$i<20;$i++)	{ &BODY_16_19($i,@V); unshift(@V,pop(@V)); }
for (;$i<40;$i++)	{ &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
for (;$i<60;$i++)	{ &BODY_40_59($i,@V); unshift(@V,pop(@V)); }
for (;$i<80;$i++)	{ &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
$code.=<<___;

	ld	[$ctx+0],@X[0]
	ld	[$ctx+4],@X[1]
	ld	[$ctx+8],@X[2]
	ld	[$ctx+12],@X[3]
	add	$inp,64,$inp
	ld	[$ctx+16],@X[4]
	cmp	$inp,$len

	add	$A,@X[0],$A
	st	$A,[$ctx+0]
	add	$B,@X[1],$B
	st	$B,[$ctx+4]
	add	$C,@X[2],$C
	st	$C,[$ctx+8]
	add	$D,@X[3],$D
	st	$D,[$ctx+12]
	add	$E,@X[4],$E
	st	$E,[$ctx+16]

	bne	SIZE_T_CC,.Lloop
	andn	$inp,7,$tmp0

	ret
	restore
.type	sha1_block_data_order,#function
.size	sha1_block_data_order,(.-sha1_block_data_order)
.asciz	"SHA1 block transform for SPARCv9, CRYPTOGAMS by <appro\@openssl.org>"
.align	4
___

# Purpose of these subroutines is to explicitly encode VIS instructions,
# so that one can compile the module without having to specify VIS
# extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
# Idea is to reserve for option to produce "universal" binary and let
# programmer detect if current CPU is VIS capable at run-time.
sub unvis {
my ($mnemonic,$rs1,$rs2,$rd)=@_;
my $ref,$opf;
my %visopf = (	"faligndata"	=> 0x048,
		"for"		=> 0x07c	);

    $ref = "$mnemonic\t$rs1,$rs2,$rd";

    if ($opf=$visopf{$mnemonic}) {
	foreach ($rs1,$rs2,$rd) {
	    return $ref if (!/%f([0-9]{1,2})/);
	    $_=$1;
	    if ($1>=32) {
		return $ref if ($1&1);
		# re-encode for upper double register addressing
		$_=($1|$1>>5)&31;
	    }
	}

	return	sprintf ".word\t0x%08x !%s",
			0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
			$ref;
    } else {
	return $ref;
    }
}
sub unalignaddr {
my ($mnemonic,$rs1,$rs2,$rd)=@_;
my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
my $ref="$mnemonic\t$rs1,$rs2,$rd";

    foreach ($rs1,$rs2,$rd) {
	if (/%([goli])([0-7])/)	{ $_=$bias{$1}+$2; }
	else			{ return $ref; }
    }
    return  sprintf ".word\t0x%08x !%s",
		    0x81b00300|$rd<<25|$rs1<<14|$rs2,
		    $ref;
}

foreach (split("\n",$code)) {
	s/\`([^\`]*)\`/eval $1/ge;

	s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
		&unvis($1,$2,$3,$4)
	 /ge;
	s/\b(alignaddr)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
		&unalignaddr($1,$2,$3,$4)
	 /ge;

	print $_,"\n";
}

close STDOUT or die "error closing STDOUT: $!";
Commit	Line	Data
6aa36e8e	1	#! /usr/bin/env perl
33388b44	2	# Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
6aa36e8e	3	#
a598ed0d	4	# Licensed under the Apache License 2.0 (the "License"). You may not use
6aa36e8e RS	5	# this file except in compliance with the License. You can obtain a copy
	6	# in the file LICENSE in the source distribution or at
	7	# https://www.openssl.org/source/license.html
	8
6fa8a01c AP	9
6fa8a01c AP	10	# ====================================================================
e3713c36	11	# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
6fa8a01c AP	12	# project. The module is, however, dual licensed under OpenSSL and
	13	# CRYPTOGAMS licenses depending on where you obtain it. For further
	14	# details see http://www.openssl.org/~appro/cryptogams/.
3ed6e227	15	#
e3713c36	16	# Hardware SPARC T4 support by David S. Miller
6fa8a01c AP	17	# ====================================================================
	18
	19	# Performance improvement is not really impressive on pre-T1 CPU: +8%
0bd8d6e2 AP	20	# over Sun C and +25% over gcc [3.3]. While on T1, a.k.a. Niagara, it
	21	# turned to be 40% faster than 64-bit code generated by Sun C 5.8 and
	22	# >2x than 64-bit code generated by gcc 3.4. And there is a gimmick.
	23	# X[16] vector is packed to 8 64-bit registers and as result nothing
	24	# is spilled on stack. In addition input data is loaded in compact
	25	# instruction sequence, thus minimizing the window when the code is
	26	# subject to [inter-thread] cache-thrashing hazard. The goal is to
	27	# ensure scalability on UltraSPARC T1, or rather to avoid decay when
	28	# amount of active threads exceeds the number of physical cores.
6fa8a01c	29
3ed6e227 AP	30	# SPARC T4 SHA1 hardware achieves 3.72 cycles per byte, which is 3.1x
	31	# faster than software. Multi-process benchmark saturates at 11x
	32	# single-process result on 8-core processor, or ~9GBps per 2.85GHz
	33	# socket.
	34
1aa89a7a	35	$output=pop and open STDOUT,">$output";
6fa8a01c AP	36
	37	@X=("%o0","%o1","%o2","%o3","%o4","%o5","%g1","%o7");
	38	$rot1m="%g2";
	39	$tmp64="%g3";
	40	$Xi="%g4";
	41	$A="%l0";
	42	$B="%l1";
	43	$C="%l2";
	44	$D="%l3";
	45	$E="%l4";
	46	@V=($A,$B,$C,$D,$E);
	47	$K_00_19="%l5";
	48	$K_20_39="%l6";
	49	$K_40_59="%l7";
	50	$K_60_79="%g5";
	51	@K=($K_00_19,$K_20_39,$K_40_59,$K_60_79);
	52
	53	$ctx="%i0";
	54	$inp="%i1";
	55	$len="%i2";
	56	$tmp0="%i3";
	57	$tmp1="%i4";
	58	$tmp2="%i5";
	59
	60	sub BODY_00_15 {
	61	my ($i,$a,$b,$c,$d,$e)=@_;
	62	my $xi=($i&1)?@X[($i/2)%8]:$Xi;
	63
	64	$code.=<<___;
	65	sll $a,5,$tmp0 !! $i
	66	add @K[$i/20],$e,$e
	67	srl $a,27,$tmp1
	68	add $tmp0,$e,$e
	69	and $c,$b,$tmp0
	70	add $tmp1,$e,$e
	71	sll $b,30,$tmp2
	72	andn $d,$b,$tmp1
	73	srl $b,2,$b
	74	or $tmp1,$tmp0,$tmp1
	75	or $tmp2,$b,$b
	76	add $xi,$e,$e
	77	___
	78	if ($i&1 && $i<15) {
	79	$code.=
	80	" srlx @X[(($i+1)/2)%8],32,$Xi\n";
	81	}
	82	$code.=<<___;
	83	add $tmp1,$e,$e
	84	___
	85	}
	86
	87	sub Xupdate {
	88	my ($i,$a,$b,$c,$d,$e)=@_;
	89	my $j=$i/2;
	90
	91	if ($i&1) {
	92	$code.=<<___;
	93	sll $a,5,$tmp0 !! $i
	94	add @K[$i/20],$e,$e
	95	srl $a,27,$tmp1
	96	___
	97	} else {
	98	$code.=<<___;
	99	sllx @X[($j+6)%8],32,$Xi ! Xupdate($i)
100	xor @X[($j+1)%8],@X[$j%8],@X[$j%8]
101	srlx @X[($j+7)%8],32,$tmp1
102	xor @X[($j+4)%8],@X[$j%8],@X[$j%8]
103	sll $a,5,$tmp0 !! $i
104	or $tmp1,$Xi,$Xi
105	add @K[$i/20],$e,$e !!
106	xor $Xi,@X[$j%8],@X[$j%8]
107	srlx @X[$j%8],31,$Xi
108	add @X[$j%8],@X[$j%8],@X[$j%8]
109	and $Xi,$rot1m,$Xi
110	andn @X[$j%8],$rot1m,@X[$j%8]
111	srl $a,27,$tmp1 !!
112	or $Xi,@X[$j%8],@X[$j%8]
113	___
114	}
115	}
116
117	sub BODY_16_19 {
118	my ($i,$a,$b,$c,$d,$e)=@_;
119
120	&Xupdate(@_);
121	if ($i&1) {
122	$xi=@X[($i/2)%8];
123	} else {
124	$xi=$Xi;
125	$code.="\tsrlx @X[($i/2)%8],32,$xi\n";
126	}
127	$code.=<<___;
128	add $tmp0,$e,$e !!
129	and $c,$b,$tmp0
130	add $tmp1,$e,$e
131	sll $b,30,$tmp2
132	add $xi,$e,$e
133	andn $d,$b,$tmp1
134	srl $b,2,$b
135	or $tmp1,$tmp0,$tmp1
136	or $tmp2,$b,$b
137	add $tmp1,$e,$e
138	___
139	}
140
141	sub BODY_20_39 {
142	my ($i,$a,$b,$c,$d,$e)=@_;
143	my $xi;
144	&Xupdate(@_);
145	if ($i&1) {
146	$xi=@X[($i/2)%8];
147	} else {
148	$xi=$Xi;
149	$code.="\tsrlx @X[($i/2)%8],32,$xi\n";
150	}
151	$code.=<<___;
152	add $tmp0,$e,$e !!
153	xor $c,$b,$tmp0
154	add $tmp1,$e,$e
155	sll $b,30,$tmp2
156	xor $d,$tmp0,$tmp1
157	srl $b,2,$b
158	add $tmp1,$e,$e
159	or $tmp2,$b,$b
160	add $xi,$e,$e
161	___
162	}
163
164	sub BODY_40_59 {
165	my ($i,$a,$b,$c,$d,$e)=@_;
166	my $xi;
167	&Xupdate(@_);
168	if ($i&1) {
169	$xi=@X[($i/2)%8];
170	} else {
171	$xi=$Xi;
172	$code.="\tsrlx @X[($i/2)%8],32,$xi\n";
173	}
174	$code.=<<___;
175	add $tmp0,$e,$e !!
176	and $c,$b,$tmp0
177	add $tmp1,$e,$e
178	sll $b,30,$tmp2
179	or $c,$b,$tmp1
180	srl $b,2,$b
181	and $d,$tmp1,$tmp1
182	add $xi,$e,$e
183	or $tmp1,$tmp0,$tmp1
184	or $tmp2,$b,$b
185	add $tmp1,$e,$e
186	___
187	}
188
6fa8a01c	189	$code.=<<___;
3ed6e227 AP	190	#include "sparc_arch.h"
3ed6e227 AP	191
1efd5830 AP	192	#ifdef __arch64__
	193	.register %g2,#scratch
	194	.register %g3,#scratch
	195	#endif
	196
6fa8a01c AP	197	.section ".text",#alloc,#execinstr
6fa8a01c AP	198
3ed6e227 AP	199	#ifdef __PIC__
	200	SPARC_PIC_THUNK(%g1)
	201	#endif
	202
6fa8a01c AP	203	.align 32
	204	.globl sha1_block_data_order
	205	sha1_block_data_order:
3ed6e227 AP	206	SPARC_LOAD_ADDRESS_LEAF(OPENSSL_sparcv9cap_P,%g1,%g5)
	207	ld [%g1+4],%g1 ! OPENSSL_sparcv9cap_P[1]
	208
	209	andcc %g1, CFR_SHA1, %g0
	210	be .Lsoftware
	211	nop
	212
	213	ld [%o0 + 0x00], %f0 ! load context
	214	ld [%o0 + 0x04], %f1
	215	ld [%o0 + 0x08], %f2
	216	andcc %o1, 0x7, %g0
	217	ld [%o0 + 0x0c], %f3
	218	bne,pn %icc, .Lhwunaligned
	219	ld [%o0 + 0x10], %f4
	220
	221	.Lhw_loop:
	222	ldd [%o1 + 0x00], %f8
	223	ldd [%o1 + 0x08], %f10
	224	ldd [%o1 + 0x10], %f12
	225	ldd [%o1 + 0x18], %f14
	226	ldd [%o1 + 0x20], %f16
	227	ldd [%o1 + 0x28], %f18
	228	ldd [%o1 + 0x30], %f20
609b0852	229	subcc %o2, 1, %o2 ! done yet?
3ed6e227 AP	230	ldd [%o1 + 0x38], %f22
3ed6e227 AP	231	add %o1, 0x40, %o1
aea4126e	232	prefetch [%o1 + 63], 20
3ed6e227 AP	233
	234	.word 0x81b02820 ! SHA1
	235
1efd5830	236	bne,pt SIZE_T_CC, .Lhw_loop
3ed6e227 AP	237	nop
	238
	239	.Lhwfinish:
	240	st %f0, [%o0 + 0x00] ! store context
	241	st %f1, [%o0 + 0x04]
	242	st %f2, [%o0 + 0x08]
	243	st %f3, [%o0 + 0x0c]
	244	retl
	245	st %f4, [%o0 + 0x10]
	246
	247	.align 8
	248	.Lhwunaligned:
	249	alignaddr %o1, %g0, %o1
	250
	251	ldd [%o1 + 0x00], %f10
	252	.Lhwunaligned_loop:
	253	ldd [%o1 + 0x08], %f12
	254	ldd [%o1 + 0x10], %f14
	255	ldd [%o1 + 0x18], %f16
	256	ldd [%o1 + 0x20], %f18
	257	ldd [%o1 + 0x28], %f20
	258	ldd [%o1 + 0x30], %f22
	259	ldd [%o1 + 0x38], %f24
	260	subcc %o2, 1, %o2 ! done yet?
	261	ldd [%o1 + 0x40], %f26
	262	add %o1, 0x40, %o1
aea4126e	263	prefetch [%o1 + 63], 20
3ed6e227 AP	264
	265	faligndata %f10, %f12, %f8
	266	faligndata %f12, %f14, %f10
	267	faligndata %f14, %f16, %f12
	268	faligndata %f16, %f18, %f14
	269	faligndata %f18, %f20, %f16
	270	faligndata %f20, %f22, %f18
	271	faligndata %f22, %f24, %f20
	272	faligndata %f24, %f26, %f22
	273
	274	.word 0x81b02820 ! SHA1
	275
1efd5830	276	bne,pt SIZE_T_CC, .Lhwunaligned_loop
3ed6e227 AP	277	for %f26, %f26, %f10 ! %f10=%f26
	278
	279	ba .Lhwfinish
	280	nop
	281
	282	.align 16
	283	.Lsoftware:
1efd5830	284	save %sp,-STACK_FRAME,%sp
6fa8a01c AP	285	sllx $len,6,$len
	286	add $inp,$len,$len
	287
	288	or %g0,1,$rot1m
	289	sllx $rot1m,32,$rot1m
	290	or $rot1m,1,$rot1m
	291
	292	ld [$ctx+0],$A
	293	ld [$ctx+4],$B
	294	ld [$ctx+8],$C
	295	ld [$ctx+12],$D
	296	ld [$ctx+16],$E
	297	andn $inp,7,$tmp0
	298
	299	sethi %hi(0x5a827999),$K_00_19
	300	or $K_00_19,%lo(0x5a827999),$K_00_19
	301	sethi %hi(0x6ed9eba1),$K_20_39
	302	or $K_20_39,%lo(0x6ed9eba1),$K_20_39
	303	sethi %hi(0x8f1bbcdc),$K_40_59
	304	or $K_40_59,%lo(0x8f1bbcdc),$K_40_59
	305	sethi %hi(0xca62c1d6),$K_60_79
	306	or $K_60_79,%lo(0xca62c1d6),$K_60_79
	307
	308	.Lloop:
	309	ldx [$tmp0+0],@X[0]
	310	ldx [$tmp0+16],@X[2]
	311	ldx [$tmp0+32],@X[4]
	312	ldx [$tmp0+48],@X[6]
	313	and $inp,7,$tmp1
	314	ldx [$tmp0+8],@X[1]
	315	sll $tmp1,3,$tmp1
	316	ldx [$tmp0+24],@X[3]
	317	subcc %g0,$tmp1,$tmp2 ! should be 64-$tmp1, but -$tmp1 works too
	318	ldx [$tmp0+40],@X[5]
	319	bz,pt %icc,.Laligned
	320	ldx [$tmp0+56],@X[7]
	321
	322	sllx @X[0],$tmp1,@X[0]
	323	ldx [$tmp0+64],$tmp64
	324	___
	325	for($i=0;$i<7;$i++)
	326	{ $code.=<<___;
	327	srlx @X[$i+1],$tmp2,$Xi
	328	sllx @X[$i+1],$tmp1,@X[$i+1]
	329	or $Xi,@X[$i],@X[$i]
	330	___
	331	}
	332	$code.=<<___;
	333	srlx $tmp64,$tmp2,$tmp64
	334	or $tmp64,@X[7],@X[7]
	335	.Laligned:
	336	srlx @X[0],32,$Xi
	337	___
	338	for ($i=0;$i<16;$i++) { &BODY_00_15($i,@V); unshift(@V,pop(@V)); }
	339	for (;$i<20;$i++) { &BODY_16_19($i,@V); unshift(@V,pop(@V)); }
	340	for (;$i<40;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
	341	for (;$i<60;$i++) { &BODY_40_59($i,@V); unshift(@V,pop(@V)); }
	342	for (;$i<80;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
	343	$code.=<<___;
	344
	345	ld [$ctx+0],@X[0]
	346	ld [$ctx+4],@X[1]
	347	ld [$ctx+8],@X[2]
	348	ld [$ctx+12],@X[3]
349	add $inp,64,$inp
350	ld [$ctx+16],@X[4]
351	cmp $inp,$len
352
353	add $A,@X[0],$A
354	st $A,[$ctx+0]
355	add $B,@X[1],$B
356	st $B,[$ctx+4]
357	add $C,@X[2],$C
358	st $C,[$ctx+8]
359	add $D,@X[3],$D
360	st $D,[$ctx+12]
361	add $E,@X[4],$E
362	st $E,[$ctx+16]
363
1efd5830	364	bne SIZE_T_CC,.Lloop
6fa8a01c AP	365	andn $inp,7,$tmp0
	366
	367	ret
	368	restore
	369	.type sha1_block_data_order,#function
	370	.size sha1_block_data_order,(.-sha1_block_data_order)
	371	.asciz "SHA1 block transform for SPARCv9, CRYPTOGAMS by <appro\@openssl.org>"
c32fcca6	372	.align 4
6fa8a01c AP	373	___
6fa8a01c AP	374
3ed6e227 AP	375	# Purpose of these subroutines is to explicitly encode VIS instructions,
3ed6e227 AP	376	# so that one can compile the module without having to specify VIS
478b50cf	377	# extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
3ed6e227 AP	378	# Idea is to reserve for option to produce "universal" binary and let
	379	# programmer detect if current CPU is VIS capable at run-time.
	380	sub unvis {
	381	my ($mnemonic,$rs1,$rs2,$rd)=@_;
	382	my $ref,$opf;
	383	my %visopf = ( "faligndata" => 0x048,
	384	"for" => 0x07c );
	385
	386	$ref = "$mnemonic\t$rs1,$rs2,$rd";
	387
	388	if ($opf=$visopf{$mnemonic}) {
	389	foreach ($rs1,$rs2,$rd) {
	390	return $ref if (!/%f([0-9]{1,2})/);
	391	$_=$1;
	392	if ($1>=32) {
	393	return $ref if ($1&1);
	394	# re-encode for upper double register addressing
	395	$_=($1\|$1>>5)&31;
	396	}
	397	}
	398
	399	return sprintf ".word\t0x%08x !%s",
	400	0x81b00000\|$rd<<25\|$rs1<<14\|$opf<<5\|$rs2,
	401	$ref;
	402	} else {
	403	return $ref;
	404	}
	405	}
	406	sub unalignaddr {
	407	my ($mnemonic,$rs1,$rs2,$rd)=@_;
	408	my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
	409	my $ref="$mnemonic\t$rs1,$rs2,$rd";
	410
	411	foreach ($rs1,$rs2,$rd) {
	412	if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
	413	else { return $ref; }
	414	}
	415	return sprintf ".word\t0x%08x !%s",
	416	0x81b00300\|$rd<<25\|$rs1<<14\|$rs2,
	417	$ref;
	418	}
	419
	420	foreach (split("\n",$code)) {
	421	s/\`([^\`]*)\`/eval $1/ge;
	422
	423	s/\b(f[^\s])\s+(%f[0-9]{1,2}),\s(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
	424	&unvis($1,$2,$3,$4)
	425	/ge;
	426	s/\b(alignaddr)\s+(%[goli][0-7]),\s(%[goli][0-7]),\s(%[goli][0-7])/
	427	&unalignaddr($1,$2,$3,$4)
	428	/ge;
	429
	430	print $_,"\n";
	431	}
	432
a21314db	433	close STDOUT or die "error closing STDOUT: $!";