[thirdparty/openssl.git] / crypto / x86cpuid.pl

#!/usr/bin/env perl

$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
push(@INC, "${dir}perlasm", "perlasm");
require "x86asm.pl";

&asm_init($ARGV[0],"x86cpuid");

for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }

&function_begin("OPENSSL_ia32_cpuid");
	&xor	("edx","edx");
	&pushf	();
	&pop	("eax");
	&mov	("ecx","eax");
	&xor	("eax",1<<21);
	&push	("eax");
	&popf	();
	&pushf	();
	&pop	("eax");
	&xor	("ecx","eax");
	&xor	("eax","eax");
	&mov	("esi",&wparam(0));
	&mov	(&DWP(8,"esi"),"eax");	# clear extended feature flags
	&bt	("ecx",21);
	&jnc	(&label("nocpuid"));
	&cpuid	();
	&mov	("edi","eax");		# max value for standard query level

	&xor	("eax","eax");
	&cmp	("ebx",0x756e6547);	# "Genu"
	&setne	(&LB("eax"));
	&mov	("ebp","eax");
	&cmp	("edx",0x49656e69);	# "ineI"
	&setne	(&LB("eax"));
	&or	("ebp","eax");
	&cmp	("ecx",0x6c65746e);	# "ntel"
	&setne	(&LB("eax"));
	&or	("ebp","eax");		# 0 indicates Intel CPU
	&jz	(&label("intel"));

	&cmp	("ebx",0x68747541);	# "Auth"
	&setne	(&LB("eax"));
	&mov	("esi","eax");
	&cmp	("edx",0x69746E65);	# "enti"
	&setne	(&LB("eax"));
	&or	("esi","eax");
	&cmp	("ecx",0x444D4163);	# "cAMD"
	&setne	(&LB("eax"));
	&or	("esi","eax");		# 0 indicates AMD CPU
	&jnz	(&label("intel"));

	# AMD specific
	&mov	("eax",0x80000000);
	&cpuid	();
	&cmp	("eax",0x80000001);
	&jb	(&label("intel"));
	&mov	("esi","eax");
	&mov	("eax",0x80000001);
	&cpuid	();
	&or	("ebp","ecx");
	&and	("ebp",1<<11|1);	# isolate XOP bit
	&cmp	("esi",0x80000008);
	&jb	(&label("intel"));

	&mov	("eax",0x80000008);
	&cpuid	();
	&movz	("esi",&LB("ecx"));	# number of cores - 1
	&inc	("esi");		# number of cores

	&mov	("eax",1);
	&xor	("ecx","ecx");
	&cpuid	();
	&bt	("edx",28);
	&jnc	(&label("generic"));
	&shr	("ebx",16);
	&and	("ebx",0xff);
	&cmp	("ebx","esi");
	&ja	(&label("generic"));
	&and	("edx",0xefffffff);	# clear hyper-threading bit
	&jmp	(&label("generic"));
	
&set_label("intel");
	&cmp	("edi",4);
	&mov	("esi",-1);
	&jb	(&label("nocacheinfo"));

	&mov	("eax",4);
	&mov	("ecx",0);		# query L1D
	&cpuid	();
	&mov	("esi","eax");
	&shr	("esi",14);
	&and	("esi",0xfff);		# number of cores -1 per L1D

&set_label("nocacheinfo");
	&mov	("eax",1);
	&xor	("ecx","ecx");
	&cpuid	();
	&and	("edx",0xbfefffff);	# force reserved bits #20, #30 to 0
	&cmp	("ebp",0);
	&jne	(&label("notintel"));
	&or	("edx",1<<30);		# set reserved bit#30 on Intel CPUs
	&and	(&HB("eax"),15);	# familiy ID
	&cmp	(&HB("eax"),15);	# P4?
	&jne	(&label("notintel"));
	&or	("edx",1<<20);		# set reserved bit#20 to engage RC4_CHAR
&set_label("notintel");
	&bt	("edx",28);		# test hyper-threading bit
	&jnc	(&label("generic"));
	&and	("edx",0xefffffff);
	&cmp	("esi",0);
	&je	(&label("generic"));

	&or	("edx",0x10000000);
	&shr	("ebx",16);
	&cmp	(&LB("ebx"),1);
	&ja	(&label("generic"));
	&and	("edx",0xefffffff);	# clear hyper-threading bit if not

&set_label("generic");
	&and	("ebp",1<<11);		# isolate AMD XOP flag
	&and	("ecx",0xfffff7ff);	# force 11th bit to 0
	&mov	("esi","edx");		# %ebp:%esi is copy of %ecx:%edx
	&or	("ebp","ecx");		# merge AMD XOP flag

	&cmp	("edi",7);
	&mov	("edi",&wparam(0));
	&jb	(&label("no_extended_info"));
	&mov	("eax",7);
	&xor	("ecx","ecx");
	&cpuid	();
	&mov	(&DWP(8,"edi"),"ebx");	# save extended feature flag
&set_label("no_extended_info");

	&bt	("ebp",27);		# check OSXSAVE bit
	&jnc	(&label("clear_avx"));
	&xor	("ecx","ecx");
	&data_byte(0x0f,0x01,0xd0);	# xgetbv
	&and	("eax",6);
	&cmp	("eax",6);
	&je	(&label("done"));
	&cmp	("eax",2);
	&je	(&label("clear_avx"));
&set_label("clear_xmm");
	&and	("ebp",0xfdfffffd);	# clear AESNI and PCLMULQDQ bits
	&and	("esi",0xfeffffff);	# clear FXSR
&set_label("clear_avx");
	&and	("ebp",0xefffe7ff);	# clear AVX, FMA and AMD XOP bits
	&and	(&DWP(8,"edi"),0xffffffdf);	# clear AVX2
&set_label("done");
	&mov	("eax","esi");
	&mov	("edx","ebp");
&set_label("nocpuid");
&function_end("OPENSSL_ia32_cpuid");

&external_label("OPENSSL_ia32cap_P");

&function_begin_B("OPENSSL_rdtsc","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
	&xor	("eax","eax");
	&xor	("edx","edx");
	&picmeup("ecx","OPENSSL_ia32cap_P");
	&bt	(&DWP(0,"ecx"),4);
	&jnc	(&label("notsc"));
	&rdtsc	();
&set_label("notsc");
	&ret	();
&function_end_B("OPENSSL_rdtsc");

# This works in Ring 0 only [read DJGPP+MS-DOS+privileged DPMI host],
# but it's safe to call it on any [supported] 32-bit platform...
# Just check for [non-]zero return value...
&function_begin_B("OPENSSL_instrument_halt","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
	&picmeup("ecx","OPENSSL_ia32cap_P");
	&bt	(&DWP(0,"ecx"),4);
	&jnc	(&label("nohalt"));	# no TSC

	&data_word(0x9058900e);		# push %cs; pop %eax
	&and	("eax",3);
	&jnz	(&label("nohalt"));	# not enough privileges

	&pushf	();
	&pop	("eax");
	&bt	("eax",9);
	&jnc	(&label("nohalt"));	# interrupts are disabled

	&rdtsc	();
	&push	("edx");
	&push	("eax");
	&halt	();
	&rdtsc	();

	&sub	("eax",&DWP(0,"esp"));
	&sbb	("edx",&DWP(4,"esp"));
	&add	("esp",8);
	&ret	();

&set_label("nohalt");
	&xor	("eax","eax");
	&xor	("edx","edx");
	&ret	();
&function_end_B("OPENSSL_instrument_halt");

# Essentially there is only one use for this function. Under DJGPP:
#
#	#include <go32.h>
#	...
#	i=OPENSSL_far_spin(_dos_ds,0x46c);
#	...
# to obtain the number of spins till closest timer interrupt.

&function_begin_B("OPENSSL_far_spin");
	&pushf	();
	&pop	("eax");
	&bt	("eax",9);
	&jnc	(&label("nospin"));	# interrupts are disabled

	&mov	("eax",&DWP(4,"esp"));
	&mov	("ecx",&DWP(8,"esp"));
	&data_word (0x90d88e1e);	# push %ds, mov %eax,%ds
	&xor	("eax","eax");
	&mov	("edx",&DWP(0,"ecx"));
	&jmp	(&label("spin"));

	&align	(16);
&set_label("spin");
	&inc	("eax");
	&cmp	("edx",&DWP(0,"ecx"));
	&je	(&label("spin"));

	&data_word (0x1f909090);	# pop	%ds
	&ret	();

&set_label("nospin");
	&xor	("eax","eax");
	&xor	("edx","edx");
	&ret	();
&function_end_B("OPENSSL_far_spin");

&function_begin_B("OPENSSL_wipe_cpu","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
	&xor	("eax","eax");
	&xor	("edx","edx");
	&picmeup("ecx","OPENSSL_ia32cap_P");
	&mov	("ecx",&DWP(0,"ecx"));
	&bt	(&DWP(0,"ecx"),1);
	&jnc	(&label("no_x87"));
	if ($sse2) {
		&and	("ecx",1<<26|1<<24);	# check SSE2 and FXSR bits
		&cmp	("ecx",1<<26|1<<24);
		&jne	(&label("no_sse2"));
		&pxor	("xmm0","xmm0");
		&pxor	("xmm1","xmm1");
		&pxor	("xmm2","xmm2");
		&pxor	("xmm3","xmm3");
		&pxor	("xmm4","xmm4");
		&pxor	("xmm5","xmm5");
		&pxor	("xmm6","xmm6");
		&pxor	("xmm7","xmm7");
	&set_label("no_sse2");
	}
	# just a bunch of fldz to zap the fp/mm bank followed by finit...
	&data_word(0xeed9eed9,0xeed9eed9,0xeed9eed9,0xeed9eed9,0x90e3db9b);
&set_label("no_x87");
	&lea	("eax",&DWP(4,"esp"));
	&ret	();
&function_end_B("OPENSSL_wipe_cpu");

&function_begin_B("OPENSSL_atomic_add");
	&mov	("edx",&DWP(4,"esp"));	# fetch the pointer, 1st arg
	&mov	("ecx",&DWP(8,"esp"));	# fetch the increment, 2nd arg
	&push	("ebx");
	&nop	();
	&mov	("eax",&DWP(0,"edx"));
&set_label("spin");
	&lea	("ebx",&DWP(0,"eax","ecx"));
	&nop	();
	&data_word(0x1ab10ff0);	# lock;	cmpxchg	%ebx,(%edx)	# %eax is envolved and is always reloaded
	&jne	(&label("spin"));
	&mov	("eax","ebx");	# OpenSSL expects the new value
	&pop	("ebx");
	&ret	();
&function_end_B("OPENSSL_atomic_add");

# This function can become handy under Win32 in situations when
# we don't know which calling convention, __stdcall or __cdecl(*),
# indirect callee is using. In C it can be deployed as
#
#ifdef OPENSSL_CPUID_OBJ
#	type OPENSSL_indirect_call(void *f,...);
#	...
#	OPENSSL_indirect_call(func,[up to $max arguments]);
#endif
#
# (*)	it's designed to work even for __fastcall if number of
#	arguments is 1 or 2!
&function_begin_B("OPENSSL_indirect_call");
	{
	my ($max,$i)=(7,);	# $max has to be chosen as 4*n-1
				# in order to preserve eventual
				# stack alignment
	&push	("ebp");
	&mov	("ebp","esp");
	&sub	("esp",$max*4);
	&mov	("ecx",&DWP(12,"ebp"));
	&mov	(&DWP(0,"esp"),"ecx");
	&mov	("edx",&DWP(16,"ebp"));
	&mov	(&DWP(4,"esp"),"edx");
	for($i=2;$i<$max;$i++)
		{
		# Some copies will be redundant/bogus...
		&mov	("eax",&DWP(12+$i*4,"ebp"));
		&mov	(&DWP(0+$i*4,"esp"),"eax");
		}
	&call_ptr	(&DWP(8,"ebp"));# make the call...
	&mov	("esp","ebp");	# ... and just restore the stack pointer
				# without paying attention to what we called,
				# (__cdecl *func) or (__stdcall *one).
	&pop	("ebp");
	&ret	();
	}
&function_end_B("OPENSSL_indirect_call");

&function_begin_B("OPENSSL_cleanse");
	&mov	("edx",&wparam(0));
	&mov	("ecx",&wparam(1));
	&xor	("eax","eax");
	&cmp	("ecx",7);
	&jae	(&label("lot"));
	&cmp	("ecx",0);
	&je	(&label("ret"));
&set_label("little");
	&mov	(&BP(0,"edx"),"al");
	&sub	("ecx",1);
	&lea	("edx",&DWP(1,"edx"));
	&jnz	(&label("little"));
&set_label("ret");
	&ret	();

&set_label("lot",16);
	&test	("edx",3);
	&jz	(&label("aligned"));
	&mov	(&BP(0,"edx"),"al");
	&lea	("ecx",&DWP(-1,"ecx"));
	&lea	("edx",&DWP(1,"edx"));
	&jmp	(&label("lot"));
&set_label("aligned");
	&mov	(&DWP(0,"edx"),"eax");
	&lea	("ecx",&DWP(-4,"ecx"));
	&test	("ecx",-4);
	&lea	("edx",&DWP(4,"edx"));
	&jnz	(&label("aligned"));
	&cmp	("ecx",0);
	&jne	(&label("little"));
	&ret	();
&function_end_B("OPENSSL_cleanse");

&function_begin_B("OPENSSL_ia32_rdrand");
	&mov	("ecx",8);
&set_label("loop");
	&rdrand	("eax");
	&jc	(&label("break"));
	&loop	(&label("loop"));
&set_label("break");
	&cmp	("eax",0);
	&cmove	("eax","ecx");
	&ret	();
&function_end_B("OPENSSL_ia32_rdrand");

&function_begin_B("OPENSSL_ia32_rdseed");
	&mov	("ecx",8);
&set_label("loop");
	&rdseed	("eax");
	&jc	(&label("break"));
	&loop	(&label("loop"));
&set_label("break");
	&cmp	("eax",0);
	&cmove	("eax","ecx");
	&ret	();
&function_end_B("OPENSSL_ia32_rdseed");

&initseg("OPENSSL_cpuid_setup");

&hidden("OPENSSL_cpuid_setup");
&hidden("OPENSSL_ia32cap_P");

&asm_finish();
Commit	Line	Data
14e21f86 AP	1	#!/usr/bin/env perl
14e21f86 AP	2
4d1f3f7a DSH	3	$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
4d1f3f7a DSH	4	push(@INC, "${dir}perlasm", "perlasm");
14e21f86 AP	5	require "x86asm.pl";
	6
	7	&asm_init($ARGV[0],"x86cpuid");
	8
c5022659 AP	9	for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
c5022659 AP	10
14e21f86 AP	11	&function_begin("OPENSSL_ia32_cpuid");
	12	&xor ("edx","edx");
	13	&pushf ();
	14	&pop ("eax");
	15	&mov ("ecx","eax");
	16	&xor ("eax",1<<21);
	17	&push ("eax");
	18	&popf ();
	19	&pushf ();
	20	&pop ("eax");
	21	&xor ("ecx","eax");
162f677d	22	&xor ("eax","eax");
7eba15f2 AP	23	&mov ("esi",&wparam(0));
7eba15f2 AP	24	&mov (&DWP(8,"esi"),"eax"); # clear extended feature flags
5c2bfad9 AP	25	&bt ("ecx",21);
5c2bfad9 AP	26	&jnc (&label("nocpuid"));
162f677d	27	&cpuid ();
baa5f524 AP	28	&mov ("edi","eax"); # max value for standard query level
baa5f524 AP	29
162f677d AP	30	&xor ("eax","eax");
	31	&cmp ("ebx",0x756e6547); # "Genu"
	32	&setne (&LB("eax"));
	33	&mov ("ebp","eax");
	34	&cmp ("edx",0x49656e69); # "ineI"
	35	&setne (&LB("eax"));
	36	&or ("ebp","eax");
	37	&cmp ("ecx",0x6c65746e); # "ntel"
	38	&setne (&LB("eax"));
baa5f524 AP	39	&or ("ebp","eax"); # 0 indicates Intel CPU
	40	&jz (&label("intel"));
	41
	42	&cmp ("ebx",0x68747541); # "Auth"
	43	&setne (&LB("eax"));
	44	&mov ("esi","eax");
	45	&cmp ("edx",0x69746E65); # "enti"
	46	&setne (&LB("eax"));
	47	&or ("esi","eax");
	48	&cmp ("ecx",0x444D4163); # "cAMD"
	49	&setne (&LB("eax"));
	50	&or ("esi","eax"); # 0 indicates AMD CPU
	51	&jnz (&label("intel"));
	52
	53	# AMD specific
	54	&mov ("eax",0x80000000);
	55	&cpuid ();
10fd0b7b AP	56	&cmp ("eax",0x80000001);
	57	&jb (&label("intel"));
	58	&mov ("esi","eax");
	59	&mov ("eax",0x80000001);
	60	&cpuid ();
	61	&or ("ebp","ecx");
	62	&and ("ebp",1<<11\|1); # isolate XOP bit
	63	&cmp ("esi",0x80000008);
baa5f524 AP	64	&jb (&label("intel"));
	65
	66	&mov ("eax",0x80000008);
	67	&cpuid ();
	68	&movz ("esi",&LB("ecx")); # number of cores - 1
	69	&inc ("esi"); # number of cores
	70
	71	&mov ("eax",1);
2a1ab7b4	72	&xor ("ecx","ecx");
baa5f524 AP	73	&cpuid ();
baa5f524 AP	74	&bt ("edx",28);
10fd0b7b	75	&jnc (&label("generic"));
baa5f524 AP	76	&shr ("ebx",16);
	77	&and ("ebx",0xff);
	78	&cmp ("ebx","esi");
10fd0b7b	79	&ja (&label("generic"));
baa5f524	80	&and ("edx",0xefffffff); # clear hyper-threading bit
10fd0b7b	81	&jmp (&label("generic"));
baa5f524 AP	82
	83	&set_label("intel");
	84	&cmp ("edi",4);
7eba15f2	85	&mov ("esi",-1);
baa5f524 AP	86	&jb (&label("nocacheinfo"));
	87
	88	&mov ("eax",4);
	89	&mov ("ecx",0); # query L1D
	90	&cpuid ();
7eba15f2 AP	91	&mov ("esi","eax");
	92	&shr ("esi",14);
	93	&and ("esi",0xfff); # number of cores -1 per L1D
baa5f524 AP	94
baa5f524 AP	95	&set_label("nocacheinfo");
14e21f86	96	&mov ("eax",1);
2a1ab7b4	97	&xor ("ecx","ecx");
14e21f86	98	&cpuid ();
10fd0b7b	99	&and ("edx",0xbfefffff); # force reserved bits #20, #30 to 0
162f677d	100	&cmp ("ebp",0);
10fd0b7b AP	101	&jne (&label("notintel"));
10fd0b7b AP	102	&or ("edx",1<<30); # set reserved bit#30 on Intel CPUs
3df2eff4 AP	103	&and (&HB("eax"),15); # familiy ID
3df2eff4 AP	104	&cmp (&HB("eax"),15); # P4?
10fd0b7b AP	105	&jne (&label("notintel"));
	106	&or ("edx",1<<20); # set reserved bit#20 to engage RC4_CHAR
	107	&set_label("notintel");
3df2eff4	108	&bt ("edx",28); # test hyper-threading bit
10fd0b7b	109	&jnc (&label("generic"));
baa5f524	110	&and ("edx",0xefffffff);
7eba15f2	111	&cmp ("esi",0);
10fd0b7b	112	&je (&label("generic"));
baa5f524 AP	113
baa5f524 AP	114	&or ("edx",0x10000000);
162f677d	115	&shr ("ebx",16);
baa5f524	116	&cmp (&LB("ebx"),1);
10fd0b7b	117	&ja (&label("generic"));
b1e8b4e6	118	&and ("edx",0xefffffff); # clear hyper-threading bit if not
10fd0b7b AP	119
	120	&set_label("generic");
	121	&and ("ebp",1<<11); # isolate AMD XOP flag
	122	&and ("ecx",0xfffff7ff); # force 11th bit to 0
7eba15f2	123	&mov ("esi","edx"); # %ebp:%esi is copy of %ecx:%edx
10fd0b7b AP	124	&or ("ebp","ecx"); # merge AMD XOP flag
10fd0b7b AP	125
7eba15f2 AP	126	&cmp ("edi",7);
	127	&mov ("edi",&wparam(0));
	128	&jb (&label("no_extended_info"));
	129	&mov ("eax",7);
	130	&xor ("ecx","ecx");
	131	&cpuid ();
	132	&mov (&DWP(8,"edi"),"ebx"); # save extended feature flag
	133	&set_label("no_extended_info");
	134
	135	&bt ("ebp",27); # check OSXSAVE bit
cb457080	136	&jnc (&label("clear_avx"));
10fd0b7b AP	137	&xor ("ecx","ecx");
	138	&data_byte(0x0f,0x01,0xd0); # xgetbv
	139	&and ("eax",6);
	140	&cmp ("eax",6);
	141	&je (&label("done"));
	142	&cmp ("eax",2);
	143	&je (&label("clear_avx"));
	144	&set_label("clear_xmm");
	145	&and ("ebp",0xfdfffffd); # clear AESNI and PCLMULQDQ bits
	146	&and ("esi",0xfeffffff); # clear FXSR
	147	&set_label("clear_avx");
	148	&and ("ebp",0xefffe7ff); # clear AVX, FMA and AMD XOP bits
d75e384f	149	&and (&DWP(8,"edi"),0xffffffdf); # clear AVX2
3df2eff4	150	&set_label("done");
10fd0b7b AP	151	&mov ("eax","esi");
10fd0b7b AP	152	&mov ("edx","ebp");
5c2bfad9	153	&set_label("nocpuid");
14e21f86 AP	154	&function_end("OPENSSL_ia32_cpuid");
14e21f86 AP	155
2b247cf8	156	&external_label("OPENSSL_ia32cap_P");
14e21f86	157
2b247cf8	158	&function_begin_B("OPENSSL_rdtsc","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
14e21f86 AP	159	&xor ("eax","eax");
14e21f86 AP	160	&xor ("edx","edx");
2b247cf8	161	&picmeup("ecx","OPENSSL_ia32cap_P");
14e21f86 AP	162	&bt (&DWP(0,"ecx"),4);
	163	&jnc (&label("notsc"));
	164	&rdtsc ();
	165	&set_label("notsc");
	166	&ret ();
	167	&function_end_B("OPENSSL_rdtsc");
	168
c85c5c40 AP	169	# This works in Ring 0 only [read DJGPP+MS-DOS+privileged DPMI host],
	170	# but it's safe to call it on any [supported] 32-bit platform...
	171	# Just check for [non-]zero return value...
	172	&function_begin_B("OPENSSL_instrument_halt","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
	173	&picmeup("ecx","OPENSSL_ia32cap_P");
	174	&bt (&DWP(0,"ecx"),4);
	175	&jnc (&label("nohalt")); # no TSC
	176
	177	&data_word(0x9058900e); # push %cs; pop %eax
	178	&and ("eax",3);
	179	&jnz (&label("nohalt")); # not enough privileges
	180
	181	&pushf ();
68d2cf51	182	&pop ("eax");
c85c5c40 AP	183	&bt ("eax",9);
	184	&jnc (&label("nohalt")); # interrupts are disabled
	185
	186	&rdtsc ();
	187	&push ("edx");
	188	&push ("eax");
	189	&halt ();
	190	&rdtsc ();
	191
	192	&sub ("eax",&DWP(0,"esp"));
	193	&sbb ("edx",&DWP(4,"esp"));
	194	&add ("esp",8);
	195	&ret ();
	196
	197	&set_label("nohalt");
	198	&xor ("eax","eax");
	199	&xor ("edx","edx");
	200	&ret ();
	201	&function_end_B("OPENSSL_instrument_halt");
	202
cee73df3 AP	203	# Essentially there is only one use for this function. Under DJGPP:
	204	#
	205	# #include <go32.h>
	206	# ...
	207	# i=OPENSSL_far_spin(_dos_ds,0x46c);
	208	# ...
	209	# to obtain the number of spins till closest timer interrupt.
	210
	211	&function_begin_B("OPENSSL_far_spin");
	212	&pushf ();
d75e384f	213	&pop ("eax");
cee73df3 AP	214	&bt ("eax",9);
	215	&jnc (&label("nospin")); # interrupts are disabled
	216
	217	&mov ("eax",&DWP(4,"esp"));
	218	&mov ("ecx",&DWP(8,"esp"));
	219	&data_word (0x90d88e1e); # push %ds, mov %eax,%ds
	220	&xor ("eax","eax");
	221	&mov ("edx",&DWP(0,"ecx"));
	222	&jmp (&label("spin"));
	223
	224	&align (16);
	225	&set_label("spin");
	226	&inc ("eax");
	227	&cmp ("edx",&DWP(0,"ecx"));
	228	&je (&label("spin"));
	229
	230	&data_word (0x1f909090); # pop %ds
	231	&ret ();
	232
	233	&set_label("nospin");
	234	&xor ("eax","eax");
	235	&xor ("edx","edx");
	236	&ret ();
	237	&function_end_B("OPENSSL_far_spin");
	238
	239	&function_begin_B("OPENSSL_wipe_cpu","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
	240	&xor ("eax","eax");
	241	&xor ("edx","edx");
	242	&picmeup("ecx","OPENSSL_ia32cap_P");
	243	&mov ("ecx",&DWP(0,"ecx"));
	244	&bt (&DWP(0,"ecx"),1);
	245	&jnc (&label("no_x87"));
c5022659	246	if ($sse2) {
10fd0b7b AP	247	&and ("ecx",1<<26\|1<<24); # check SSE2 and FXSR bits
	248	&cmp ("ecx",1<<26\|1<<24);
	249	&jne (&label("no_sse2"));
c5022659 AP	250	&pxor ("xmm0","xmm0");
	251	&pxor ("xmm1","xmm1");
	252	&pxor ("xmm2","xmm2");
	253	&pxor ("xmm3","xmm3");
	254	&pxor ("xmm4","xmm4");
	255	&pxor ("xmm5","xmm5");
	256	&pxor ("xmm6","xmm6");
	257	&pxor ("xmm7","xmm7");
	258	&set_label("no_sse2");
	259	}
c49a0aa0 AP	260	# just a bunch of fldz to zap the fp/mm bank followed by finit...
c49a0aa0 AP	261	&data_word(0xeed9eed9,0xeed9eed9,0xeed9eed9,0xeed9eed9,0x90e3db9b);
cee73df3 AP	262	&set_label("no_x87");
	263	&lea ("eax",&DWP(4,"esp"));
	264	&ret ();
	265	&function_end_B("OPENSSL_wipe_cpu");
	266
	267	&function_begin_B("OPENSSL_atomic_add");
	268	&mov ("edx",&DWP(4,"esp")); # fetch the pointer, 1st arg
	269	&mov ("ecx",&DWP(8,"esp")); # fetch the increment, 2nd arg
	270	&push ("ebx");
	271	&nop ();
	272	&mov ("eax",&DWP(0,"edx"));
	273	&set_label("spin");
	274	&lea ("ebx",&DWP(0,"eax","ecx"));
	275	&nop ();
	276	&data_word(0x1ab10ff0); # lock; cmpxchg %ebx,(%edx) # %eax is envolved and is always reloaded
	277	&jne (&label("spin"));
	278	&mov ("eax","ebx"); # OpenSSL expects the new value
	279	&pop ("ebx");
	280	&ret ();
	281	&function_end_B("OPENSSL_atomic_add");
	282
061bebc0 AP	283	# This function can become handy under Win32 in situations when
	284	# we don't know which calling convention, __stdcall or __cdecl(*),
	285	# indirect callee is using. In C it can be deployed as
	286	#
	287	#ifdef OPENSSL_CPUID_OBJ
	288	# type OPENSSL_indirect_call(void *f,...);
	289	# ...
	290	# OPENSSL_indirect_call(func,[up to $max arguments]);
	291	#endif
	292	#
	293	# (*) it's designed to work even for __fastcall if number of
	294	# arguments is 1 or 2!
	295	&function_begin_B("OPENSSL_indirect_call");
	296	{
68d2cf51	297	my ($max,$i)=(7,); # $max has to be chosen as 4*n-1
061bebc0 AP	298	# in order to preserve eventual
	299	# stack alignment
	300	&push ("ebp");
	301	&mov ("ebp","esp");
	302	&sub ("esp",$max*4);
	303	&mov ("ecx",&DWP(12,"ebp"));
	304	&mov (&DWP(0,"esp"),"ecx");
	305	&mov ("edx",&DWP(16,"ebp"));
	306	&mov (&DWP(4,"esp"),"edx");
	307	for($i=2;$i<$max;$i++)
	308	{
	309	# Some copies will be redundant/bogus...
	310	&mov ("eax",&DWP(12+$i*4,"ebp"));
	311	&mov (&DWP(0+$i*4,"esp"),"eax");
	312	}
3ebf898e	313	&call_ptr (&DWP(8,"ebp"));# make the call...
061bebc0 AP	314	&mov ("esp","ebp"); # ... and just restore the stack pointer
	315	# without paying attention to what we called,
	316	# (__cdecl func) or (__stdcall one).
	317	&pop ("ebp");
	318	&ret ();
	319	}
	320	&function_end_B("OPENSSL_indirect_call");
	321
b2dba9bf AP	322	&function_begin_B("OPENSSL_cleanse");
	323	&mov ("edx",&wparam(0));
	324	&mov ("ecx",&wparam(1));
	325	&xor ("eax","eax");
	326	&cmp ("ecx",7);
	327	&jae (&label("lot"));
1d8fa09c DSH	328	&cmp ("ecx",0);
1d8fa09c DSH	329	&je (&label("ret"));
b2dba9bf AP	330	&set_label("little");
	331	&mov (&BP(0,"edx"),"al");
	332	&sub ("ecx",1);
	333	&lea ("edx",&DWP(1,"edx"));
	334	&jnz (&label("little"));
1d8fa09c	335	&set_label("ret");
b2dba9bf AP	336	&ret ();
	337
	338	&set_label("lot",16);
	339	&test ("edx",3);
	340	&jz (&label("aligned"));
	341	&mov (&BP(0,"edx"),"al");
	342	&lea ("ecx",&DWP(-1,"ecx"));
	343	&lea ("edx",&DWP(1,"edx"));
	344	&jmp (&label("lot"));
	345	&set_label("aligned");
	346	&mov (&DWP(0,"edx"),"eax");
	347	&lea ("ecx",&DWP(-4,"ecx"));
	348	&test ("ecx",-4);
	349	&lea ("edx",&DWP(4,"edx"));
	350	&jnz (&label("aligned"));
	351	&cmp ("ecx",0);
	352	&jne (&label("little"));
	353	&ret ();
	354	&function_end_B("OPENSSL_cleanse");
	355
922ac25f AP	356	&function_begin_B("OPENSSL_ia32_rdrand");
	357	&mov ("ecx",8);
	358	&set_label("loop");
	359	&rdrand ("eax");
	360	&jc (&label("break"));
	361	&loop (&label("loop"));
	362	&set_label("break");
	363	&cmp ("eax",0);
	364	&cmove ("eax","ecx");
	365	&ret ();
	366	&function_end_B("OPENSSL_ia32_rdrand");
	367
104c032b AP	368	&function_begin_B("OPENSSL_ia32_rdseed");
	369	&mov ("ecx",8);
	370	&set_label("loop");
	371	&rdseed ("eax");
	372	&jc (&label("break"));
	373	&loop (&label("loop"));
	374	&set_label("break");
	375	&cmp ("eax",0);
	376	&cmove ("eax","ecx");
	377	&ret ();
	378	&function_end_B("OPENSSL_ia32_rdseed");
	379
2b247cf8	380	&initseg("OPENSSL_cpuid_setup");
14e21f86	381
3ebe8747 AP	382	&hidden("OPENSSL_cpuid_setup");
	383	&hidden("OPENSSL_ia32cap_P");
	384
14e21f86	385	&asm_finish();