[people/ms/u-boot.git] / drivers / i2c / designware_i2c.c

/*
 * (C) Copyright 2009
 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include "designware_i2c.h"

static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 4
	case 3:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
#endif
	case 0:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	default:
		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	}

	return NULL;
}

static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;
	int timeout = 100;

	do {
		writel(ena, &i2c_base->ic_enable);
		if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
			return;

		/*
		 * Wait 10 times the signaling period of the highest I2C
		 * transfer supported by the driver (for 400KHz this is
		 * 25us) as described in the DesignWare I2C databook.
		 */
		udelay(25);
	} while (timeout--);

	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
}

/*
 * set_speed - Set the i2c speed mode (standard, high, fast)
 * @i2c_spd:	required i2c speed mode
 *
 * Set the i2c speed mode (standard, high, fast)
 */
static void set_speed(struct i2c_adapter *adap, int i2c_spd)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned int cntl;
	unsigned int hcnt, lcnt;

	/* to set speed cltr must be disabled */
	dw_i2c_enable(i2c_base, false);

	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));

	switch (i2c_spd) {
	case IC_SPEED_MODE_MAX:
		cntl |= IC_CON_SPD_HS;
		hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
		lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
		break;

	case IC_SPEED_MODE_STANDARD:
		cntl |= IC_CON_SPD_SS;
		hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
		lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
		break;

	case IC_SPEED_MODE_FAST:
	default:
		cntl |= IC_CON_SPD_FS;
		hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
		lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
		break;
	}

	writel(cntl, &i2c_base->ic_con);

	/* Enable back i2c now speed set */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_set_bus_speed - Set the i2c speed
 * @speed:	required i2c speed
 *
 * Set the i2c speed.
 */
static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
					 unsigned int speed)
{
	int i2c_spd;

	if (speed >= I2C_MAX_SPEED)
		i2c_spd = IC_SPEED_MODE_MAX;
	else if (speed >= I2C_FAST_SPEED)
		i2c_spd = IC_SPEED_MODE_FAST;
	else
		i2c_spd = IC_SPEED_MODE_STANDARD;

	set_speed(adap, i2c_spd);
	adap->speed = speed;

	return 0;
}

/*
 * i2c_init - Init function
 * @speed:	required i2c speed
 * @slaveaddr:	slave address for the device
 *
 * Initialization function.
 */
static void dw_i2c_init(struct i2c_adapter *adap, int speed,
			int slaveaddr)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	dw_i2c_set_bus_speed(adap, speed);
	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	writel(slaveaddr, &i2c_base->ic_sar);

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_setaddress - Sets the target slave address
 * @i2c_addr:	target i2c address
 *
 * Sets the target slave address.
 */
static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel(i2c_addr, &i2c_base->ic_tar);

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 *
 * Flushes the i2c RX FIFO
 */
static void i2c_flush_rxfifo(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
		readl(&i2c_base->ic_cmd_data);
}

/*
 * i2c_wait_for_bb - Waits for bus busy
 *
 * Waits for bus busy
 */
static int i2c_wait_for_bb(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned long start_time_bb = get_timer(0);

	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
	       !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {

		/* Evaluate timeout */
		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
			return 1;
	}

	return 0;
}

static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
			 int alen)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	if (i2c_wait_for_bb(adap))
		return 1;

	i2c_setaddress(adap, chip);
	while (alen) {
		alen--;
		/* high byte address going out first */
		writel((addr >> (alen * 8)) & 0xff,
		       &i2c_base->ic_cmd_data);
	}
	return 0;
}

static int i2c_xfer_finish(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	ulong start_stop_det = get_timer(0);

	while (1) {
		if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
			readl(&i2c_base->ic_clr_stop_det);
			break;
		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
			break;
		}
	}

	if (i2c_wait_for_bb(adap)) {
		printf("Timed out waiting for bus\n");
		return 1;
	}

	i2c_flush_rxfifo(adap);

	return 0;
}

/*
 * i2c_read - Read from i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Read from i2c memory.
 */
static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
		       int alen, u8 *buffer, int len)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned long start_time_rx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(adap, dev, addr, alen))
		return 1;

	start_time_rx = get_timer(0);
	while (len) {
		if (len == 1)
			writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
		else
			writel(IC_CMD, &i2c_base->ic_cmd_data);

		if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
			*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
			len--;
			start_time_rx = get_timer(0);

		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
				return 1;
		}
	}

	return i2c_xfer_finish(adap);
}

/*
 * i2c_write - Write to i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Write to i2c memory.
 */
static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			int alen, u8 *buffer, int len)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	int nb = len;
	unsigned long start_time_tx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(adap, dev, addr, alen))
		return 1;

	start_time_tx = get_timer(0);
	while (len) {
		if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
			if (--len == 0) {
				writel(*buffer | IC_STOP,
				       &i2c_base->ic_cmd_data);
			} else {
				writel(*buffer, &i2c_base->ic_cmd_data);
			}
			buffer++;
			start_time_tx = get_timer(0);

		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
				printf("Timed out. i2c write Failed\n");
				return 1;
		}
	}

	return i2c_xfer_finish(adap);
}

/*
 * i2c_probe - Probe the i2c chip
 */
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	u32 tmp;
	int ret;

	/*
	 * Try to read the first location of the chip.
	 */
	ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		dw_i2c_init(adap, adap->speed, adap->slaveaddr);

	return ret;
}

U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)

#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 4
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif
Commit	Line	Data
2403f8f4 VK	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
2403f8f4 VK	6	*/
	7
	8	#include <common.h>
678398b1	9	#include <i2c.h>
2403f8f4	10	#include <asm/io.h>
031ed2fa	11	#include "designware_i2c.h"
2403f8f4	12
678398b1 SR	13	static struct i2c_regs i2c_get_base(struct i2c_adapter adap)
	14	{
	15	switch (adap->hwadapnr) {
	16	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	17	case 3:
	18	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
	19	#endif
	20	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	21	case 2:
	22	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
	23	#endif
	24	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	25	case 1:
	26	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
ac6e2fe6	27	#endif
678398b1 SR	28	case 0:
	29	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	30	default:
	31	printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	32	}
ac6e2fe6	33
678398b1 SR	34	return NULL;
678398b1 SR	35	}
2403f8f4	36
1c8b089b SR	37	static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
	38	{
	39	u32 ena = enable ? IC_ENABLE_0B : 0;
	40	int timeout = 100;
	41
	42	do {
	43	writel(ena, &i2c_base->ic_enable);
	44	if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
	45	return;
	46
	47	/*
	48	* Wait 10 times the signaling period of the highest I2C
	49	* transfer supported by the driver (for 400KHz this is
	50	* 25us) as described in the DesignWare I2C databook.
	51	*/
	52	udelay(25);
	53	} while (timeout--);
	54
	55	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
	56	}
	57
2403f8f4 VK	58	/*
	59	* set_speed - Set the i2c speed mode (standard, high, fast)
	60	* @i2c_spd: required i2c speed mode
	61	*
	62	* Set the i2c speed mode (standard, high, fast)
	63	*/
678398b1	64	static void set_speed(struct i2c_adapter *adap, int i2c_spd)
2403f8f4	65	{
678398b1	66	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	67	unsigned int cntl;
2403f8f4 VK	68	unsigned int hcnt, lcnt;
5e3e8dda AV	69
5e3e8dda AV	70	/* to set speed cltr must be disabled */
1c8b089b	71	dw_i2c_enable(i2c_base, false);
5e3e8dda	72
678398b1	73	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
2403f8f4 VK	74
	75	switch (i2c_spd) {
	76	case IC_SPEED_MODE_MAX:
	77	cntl \|= IC_CON_SPD_HS;
5b8439bb	78	hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	79	writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
5b8439bb	80	lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	81	writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
2403f8f4 VK	82	break;
	83
	84	case IC_SPEED_MODE_STANDARD:
	85	cntl \|= IC_CON_SPD_SS;
5b8439bb	86	hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	87	writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
5b8439bb	88	lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	89	writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
2403f8f4 VK	90	break;
	91
	92	case IC_SPEED_MODE_FAST:
	93	default:
	94	cntl \|= IC_CON_SPD_FS;
5b8439bb	95	hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	96	writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
5b8439bb	97	lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	98	writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
2403f8f4 VK	99	break;
	100	}
	101
678398b1	102	writel(cntl, &i2c_base->ic_con);
2403f8f4	103
5b8439bb	104	/* Enable back i2c now speed set */
1c8b089b	105	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	106	}
	107
	108	/*
	109	* i2c_set_bus_speed - Set the i2c speed
	110	* @speed: required i2c speed
	111	*
	112	* Set the i2c speed.
	113	*/
678398b1 SR	114	static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
678398b1 SR	115	unsigned int speed)
2403f8f4	116	{
c69ecd97 JH	117	int i2c_spd;
c69ecd97 JH	118
2403f8f4	119	if (speed >= I2C_MAX_SPEED)
c69ecd97	120	i2c_spd = IC_SPEED_MODE_MAX;
2403f8f4	121	else if (speed >= I2C_FAST_SPEED)
c69ecd97	122	i2c_spd = IC_SPEED_MODE_FAST;
2403f8f4	123	else
c69ecd97	124	i2c_spd = IC_SPEED_MODE_STANDARD;
496ba48f	125
678398b1 SR	126	set_speed(adap, i2c_spd);
678398b1 SR	127	adap->speed = speed;
2403f8f4 VK	128
	129	return 0;
	130	}
	131
	132	/*
	133	* i2c_init - Init function
	134	* @speed: required i2c speed
678398b1	135	* @slaveaddr: slave address for the device
2403f8f4 VK	136	*
	137	* Initialization function.
	138	*/
678398b1 SR	139	static void dw_i2c_init(struct i2c_adapter *adap, int speed,
678398b1 SR	140	int slaveaddr)
2403f8f4	141	{
678398b1	142	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	143
2403f8f4 VK	144	/* Disable i2c */
1c8b089b	145	dw_i2c_enable(i2c_base, false);
2403f8f4	146
678398b1 SR	147	writel((IC_CON_SD \| IC_CON_SPD_FS \| IC_CON_MM), &i2c_base->ic_con);
	148	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	149	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	150	dw_i2c_set_bus_speed(adap, speed);
	151	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	152	writel(slaveaddr, &i2c_base->ic_sar);
2403f8f4 VK	153
2403f8f4 VK	154	/* Enable i2c */
1c8b089b	155	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	156	}
	157
	158	/*
	159	* i2c_setaddress - Sets the target slave address
	160	* @i2c_addr: target i2c address
	161	*
	162	* Sets the target slave address.
	163	*/
678398b1	164	static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
2403f8f4	165	{
678398b1	166	struct i2c_regs *i2c_base = i2c_get_base(adap);
8b7c8725 AB	167
8b7c8725 AB	168	/* Disable i2c */
1c8b089b	169	dw_i2c_enable(i2c_base, false);
8b7c8725	170
678398b1	171	writel(i2c_addr, &i2c_base->ic_tar);
8b7c8725 AB	172
8b7c8725 AB	173	/* Enable i2c */
1c8b089b	174	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	175	}
	176
	177	/*
	178	* i2c_flush_rxfifo - Flushes the i2c RX FIFO
	179	*
	180	* Flushes the i2c RX FIFO
	181	*/
678398b1	182	static void i2c_flush_rxfifo(struct i2c_adapter *adap)
2403f8f4	183	{
678398b1 SR	184	struct i2c_regs *i2c_base = i2c_get_base(adap);
	185
	186	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
	187	readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	188	}
	189
	190	/*
	191	* i2c_wait_for_bb - Waits for bus busy
	192	*
	193	* Waits for bus busy
	194	*/
678398b1	195	static int i2c_wait_for_bb(struct i2c_adapter *adap)
2403f8f4	196	{
678398b1	197	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	198	unsigned long start_time_bb = get_timer(0);
2403f8f4 VK	199
678398b1 SR	200	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) \|\|
678398b1 SR	201	!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
2403f8f4 VK	202
	203	/* Evaluate timeout */
	204	if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
	205	return 1;
	206	}
	207
	208	return 0;
	209	}
	210
678398b1 SR	211	static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
678398b1 SR	212	int alen)
2403f8f4	213	{
678398b1 SR	214	struct i2c_regs *i2c_base = i2c_get_base(adap);
	215
	216	if (i2c_wait_for_bb(adap))
2403f8f4	217	return 1;
2403f8f4	218
678398b1	219	i2c_setaddress(adap, chip);
070cbaf8 CLS	220	while (alen) {
	221	alen--;
	222	/* high byte address going out first */
	223	writel((addr >> (alen * 8)) & 0xff,
678398b1	224	&i2c_base->ic_cmd_data);
070cbaf8	225	}
2403f8f4 VK	226	return 0;
	227	}
	228
678398b1	229	static int i2c_xfer_finish(struct i2c_adapter *adap)
2403f8f4	230	{
678398b1	231	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	232	ulong start_stop_det = get_timer(0);
	233
	234	while (1) {
678398b1 SR	235	if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
678398b1 SR	236	readl(&i2c_base->ic_clr_stop_det);
2403f8f4 VK	237	break;
	238	} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
	239	break;
	240	}
	241	}
	242
678398b1	243	if (i2c_wait_for_bb(adap)) {
2403f8f4 VK	244	printf("Timed out waiting for bus\n");
	245	return 1;
	246	}
	247
678398b1	248	i2c_flush_rxfifo(adap);
2403f8f4	249
2403f8f4 VK	250	return 0;
	251	}
	252
	253	/*
	254	* i2c_read - Read from i2c memory
	255	* @chip: target i2c address
	256	* @addr: address to read from
	257	* @alen:
	258	* @buffer: buffer for read data
	259	* @len: no of bytes to be read
	260	*
	261	* Read from i2c memory.
	262	*/
678398b1 SR	263	static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
678398b1 SR	264	int alen, u8 *buffer, int len)
2403f8f4	265	{
678398b1	266	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	267	unsigned long start_time_rx;
2403f8f4 VK	268
32d041e2 AB	269	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	270	/*
	271	* EEPROM chips that implement "address overflow" are ones
	272	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	273	* address and the extra bits end up in the "chip address"
	274	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	275	* four 256 byte chips.
	276	*
	277	* Note that we consider the length of the address field to
	278	* still be one byte because the extra address bits are
	279	* hidden in the chip address.
	280	*/
678398b1	281	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	282	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	283
678398b1	284	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	285	addr);
	286	#endif
	287
678398b1	288	if (i2c_xfer_init(adap, dev, addr, alen))
2403f8f4 VK	289	return 1;
	290
	291	start_time_rx = get_timer(0);
	292	while (len) {
491739bb	293	if (len == 1)
678398b1	294	writel(IC_CMD \| IC_STOP, &i2c_base->ic_cmd_data);
491739bb	295	else
678398b1	296	writel(IC_CMD, &i2c_base->ic_cmd_data);
2403f8f4	297
678398b1 SR	298	if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
678398b1 SR	299	*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	300	len--;
	301	start_time_rx = get_timer(0);
	302
	303	} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
2403f8f4 VK	304	return 1;
	305	}
	306	}
	307
678398b1	308	return i2c_xfer_finish(adap);
2403f8f4 VK	309	}
	310
	311	/*
	312	* i2c_write - Write to i2c memory
	313	* @chip: target i2c address
	314	* @addr: address to read from
	315	* @alen:
	316	* @buffer: buffer for read data
	317	* @len: no of bytes to be read
	318	*
	319	* Write to i2c memory.
	320	*/
678398b1 SR	321	static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
678398b1 SR	322	int alen, u8 *buffer, int len)
2403f8f4	323	{
678398b1	324	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	325	int nb = len;
	326	unsigned long start_time_tx;
	327
32d041e2 AB	328	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	329	/*
	330	* EEPROM chips that implement "address overflow" are ones
	331	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	332	* address and the extra bits end up in the "chip address"
	333	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	334	* four 256 byte chips.
	335	*
	336	* Note that we consider the length of the address field to
	337	* still be one byte because the extra address bits are
	338	* hidden in the chip address.
	339	*/
678398b1	340	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	341	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	342
678398b1	343	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	344	addr);
	345	#endif
	346
678398b1	347	if (i2c_xfer_init(adap, dev, addr, alen))
2403f8f4 VK	348	return 1;
	349
	350	start_time_tx = get_timer(0);
	351	while (len) {
678398b1 SR	352	if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
	353	if (--len == 0) {
	354	writel(*buffer \| IC_STOP,
	355	&i2c_base->ic_cmd_data);
	356	} else {
	357	writel(*buffer, &i2c_base->ic_cmd_data);
	358	}
2403f8f4	359	buffer++;
2403f8f4 VK	360	start_time_tx = get_timer(0);
	361
	362	} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
	363	printf("Timed out. i2c write Failed\n");
	364	return 1;
	365	}
	366	}
	367
678398b1	368	return i2c_xfer_finish(adap);
2403f8f4 VK	369	}
	370
	371	/*
	372	* i2c_probe - Probe the i2c chip
	373	*/
678398b1	374	static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
2403f8f4 VK	375	{
2403f8f4 VK	376	u32 tmp;
496ba48f	377	int ret;
2403f8f4 VK	378
	379	/*
	380	* Try to read the first location of the chip.
	381	*/
678398b1	382	ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
496ba48f	383	if (ret)
678398b1	384	dw_i2c_init(adap, adap->speed, adap->slaveaddr);
496ba48f SR	385
496ba48f SR	386	return ret;
2403f8f4	387	}
ac6e2fe6	388
678398b1 SR	389	U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	390	dw_i2c_write, dw_i2c_set_bus_speed,
	391	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
ac6e2fe6	392
678398b1 SR	393	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	394	U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	395	dw_i2c_write, dw_i2c_set_bus_speed,
	396	CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
	397	#endif
ac6e2fe6	398
678398b1 SR	399	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	400	U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	401	dw_i2c_write, dw_i2c_set_bus_speed,
	402	CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
	403	#endif
ac6e2fe6	404
678398b1 SR	405	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	406	U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	407	dw_i2c_write, dw_i2c_set_bus_speed,
	408	CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
ac6e2fe6	409	#endif