3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include "designware_i2c.h"
13 static struct i2c_regs
*i2c_get_base(struct i2c_adapter
*adap
)
15 switch (adap
->hwadapnr
) {
16 #if CONFIG_SYS_I2C_BUS_MAX >= 4
18 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE3
;
20 #if CONFIG_SYS_I2C_BUS_MAX >= 3
22 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE2
;
24 #if CONFIG_SYS_I2C_BUS_MAX >= 2
26 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE1
;
29 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE
;
31 printf("Wrong I2C-adapter number %d\n", adap
->hwadapnr
);
37 static void dw_i2c_enable(struct i2c_regs
*i2c_base
, bool enable
)
39 u32 ena
= enable
? IC_ENABLE_0B
: 0;
43 writel(ena
, &i2c_base
->ic_enable
);
44 if ((readl(&i2c_base
->ic_enable_status
) & IC_ENABLE_0B
) == ena
)
48 * Wait 10 times the signaling period of the highest I2C
49 * transfer supported by the driver (for 400KHz this is
50 * 25us) as described in the DesignWare I2C databook.
55 printf("timeout in %sabling I2C adapter\n", enable
? "en" : "dis");
59 * set_speed - Set the i2c speed mode (standard, high, fast)
60 * @i2c_spd: required i2c speed mode
62 * Set the i2c speed mode (standard, high, fast)
64 static void set_speed(struct i2c_adapter
*adap
, int i2c_spd
)
66 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
68 unsigned int hcnt
, lcnt
;
70 /* to set speed cltr must be disabled */
71 dw_i2c_enable(i2c_base
, false);
73 cntl
= (readl(&i2c_base
->ic_con
) & (~IC_CON_SPD_MSK
));
76 case IC_SPEED_MODE_MAX
:
77 cntl
|= IC_CON_SPD_HS
;
78 hcnt
= (IC_CLK
* MIN_HS_SCL_HIGHTIME
) / NANO_TO_MICRO
;
79 writel(hcnt
, &i2c_base
->ic_hs_scl_hcnt
);
80 lcnt
= (IC_CLK
* MIN_HS_SCL_LOWTIME
) / NANO_TO_MICRO
;
81 writel(lcnt
, &i2c_base
->ic_hs_scl_lcnt
);
84 case IC_SPEED_MODE_STANDARD
:
85 cntl
|= IC_CON_SPD_SS
;
86 hcnt
= (IC_CLK
* MIN_SS_SCL_HIGHTIME
) / NANO_TO_MICRO
;
87 writel(hcnt
, &i2c_base
->ic_ss_scl_hcnt
);
88 lcnt
= (IC_CLK
* MIN_SS_SCL_LOWTIME
) / NANO_TO_MICRO
;
89 writel(lcnt
, &i2c_base
->ic_ss_scl_lcnt
);
92 case IC_SPEED_MODE_FAST
:
94 cntl
|= IC_CON_SPD_FS
;
95 hcnt
= (IC_CLK
* MIN_FS_SCL_HIGHTIME
) / NANO_TO_MICRO
;
96 writel(hcnt
, &i2c_base
->ic_fs_scl_hcnt
);
97 lcnt
= (IC_CLK
* MIN_FS_SCL_LOWTIME
) / NANO_TO_MICRO
;
98 writel(lcnt
, &i2c_base
->ic_fs_scl_lcnt
);
102 writel(cntl
, &i2c_base
->ic_con
);
104 /* Enable back i2c now speed set */
105 dw_i2c_enable(i2c_base
, true);
109 * i2c_set_bus_speed - Set the i2c speed
110 * @speed: required i2c speed
114 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter
*adap
,
119 if (speed
>= I2C_MAX_SPEED
)
120 i2c_spd
= IC_SPEED_MODE_MAX
;
121 else if (speed
>= I2C_FAST_SPEED
)
122 i2c_spd
= IC_SPEED_MODE_FAST
;
124 i2c_spd
= IC_SPEED_MODE_STANDARD
;
126 set_speed(adap
, i2c_spd
);
133 * i2c_init - Init function
134 * @speed: required i2c speed
135 * @slaveaddr: slave address for the device
137 * Initialization function.
139 static void dw_i2c_init(struct i2c_adapter
*adap
, int speed
,
142 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
145 dw_i2c_enable(i2c_base
, false);
147 writel((IC_CON_SD
| IC_CON_SPD_FS
| IC_CON_MM
), &i2c_base
->ic_con
);
148 writel(IC_RX_TL
, &i2c_base
->ic_rx_tl
);
149 writel(IC_TX_TL
, &i2c_base
->ic_tx_tl
);
150 dw_i2c_set_bus_speed(adap
, speed
);
151 writel(IC_STOP_DET
, &i2c_base
->ic_intr_mask
);
152 writel(slaveaddr
, &i2c_base
->ic_sar
);
155 dw_i2c_enable(i2c_base
, true);
159 * i2c_setaddress - Sets the target slave address
160 * @i2c_addr: target i2c address
162 * Sets the target slave address.
164 static void i2c_setaddress(struct i2c_adapter
*adap
, unsigned int i2c_addr
)
166 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
169 dw_i2c_enable(i2c_base
, false);
171 writel(i2c_addr
, &i2c_base
->ic_tar
);
174 dw_i2c_enable(i2c_base
, true);
178 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
180 * Flushes the i2c RX FIFO
182 static void i2c_flush_rxfifo(struct i2c_adapter
*adap
)
184 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
186 while (readl(&i2c_base
->ic_status
) & IC_STATUS_RFNE
)
187 readl(&i2c_base
->ic_cmd_data
);
191 * i2c_wait_for_bb - Waits for bus busy
195 static int i2c_wait_for_bb(struct i2c_adapter
*adap
)
197 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
198 unsigned long start_time_bb
= get_timer(0);
200 while ((readl(&i2c_base
->ic_status
) & IC_STATUS_MA
) ||
201 !(readl(&i2c_base
->ic_status
) & IC_STATUS_TFE
)) {
203 /* Evaluate timeout */
204 if (get_timer(start_time_bb
) > (unsigned long)(I2C_BYTE_TO_BB
))
211 static int i2c_xfer_init(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
214 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
216 if (i2c_wait_for_bb(adap
))
219 i2c_setaddress(adap
, chip
);
222 /* high byte address going out first */
223 writel((addr
>> (alen
* 8)) & 0xff,
224 &i2c_base
->ic_cmd_data
);
229 static int i2c_xfer_finish(struct i2c_adapter
*adap
)
231 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
232 ulong start_stop_det
= get_timer(0);
235 if ((readl(&i2c_base
->ic_raw_intr_stat
) & IC_STOP_DET
)) {
236 readl(&i2c_base
->ic_clr_stop_det
);
238 } else if (get_timer(start_stop_det
) > I2C_STOPDET_TO
) {
243 if (i2c_wait_for_bb(adap
)) {
244 printf("Timed out waiting for bus\n");
248 i2c_flush_rxfifo(adap
);
254 * i2c_read - Read from i2c memory
255 * @chip: target i2c address
256 * @addr: address to read from
258 * @buffer: buffer for read data
259 * @len: no of bytes to be read
261 * Read from i2c memory.
263 static int dw_i2c_read(struct i2c_adapter
*adap
, u8 dev
, uint addr
,
264 int alen
, u8
*buffer
, int len
)
266 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
267 unsigned long start_time_rx
;
269 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
271 * EEPROM chips that implement "address overflow" are ones
272 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
273 * address and the extra bits end up in the "chip address"
274 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
275 * four 256 byte chips.
277 * Note that we consider the length of the address field to
278 * still be one byte because the extra address bits are
279 * hidden in the chip address.
281 dev
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
282 addr
&= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
<< (alen
* 8));
284 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__
, dev
,
288 if (i2c_xfer_init(adap
, dev
, addr
, alen
))
291 start_time_rx
= get_timer(0);
294 writel(IC_CMD
| IC_STOP
, &i2c_base
->ic_cmd_data
);
296 writel(IC_CMD
, &i2c_base
->ic_cmd_data
);
298 if (readl(&i2c_base
->ic_status
) & IC_STATUS_RFNE
) {
299 *buffer
++ = (uchar
)readl(&i2c_base
->ic_cmd_data
);
301 start_time_rx
= get_timer(0);
303 } else if (get_timer(start_time_rx
) > I2C_BYTE_TO
) {
308 return i2c_xfer_finish(adap
);
312 * i2c_write - Write to i2c memory
313 * @chip: target i2c address
314 * @addr: address to read from
316 * @buffer: buffer for read data
317 * @len: no of bytes to be read
319 * Write to i2c memory.
321 static int dw_i2c_write(struct i2c_adapter
*adap
, u8 dev
, uint addr
,
322 int alen
, u8
*buffer
, int len
)
324 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
326 unsigned long start_time_tx
;
328 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
330 * EEPROM chips that implement "address overflow" are ones
331 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
332 * address and the extra bits end up in the "chip address"
333 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
334 * four 256 byte chips.
336 * Note that we consider the length of the address field to
337 * still be one byte because the extra address bits are
338 * hidden in the chip address.
340 dev
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
341 addr
&= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
<< (alen
* 8));
343 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__
, dev
,
347 if (i2c_xfer_init(adap
, dev
, addr
, alen
))
350 start_time_tx
= get_timer(0);
352 if (readl(&i2c_base
->ic_status
) & IC_STATUS_TFNF
) {
354 writel(*buffer
| IC_STOP
,
355 &i2c_base
->ic_cmd_data
);
357 writel(*buffer
, &i2c_base
->ic_cmd_data
);
360 start_time_tx
= get_timer(0);
362 } else if (get_timer(start_time_tx
) > (nb
* I2C_BYTE_TO
)) {
363 printf("Timed out. i2c write Failed\n");
368 return i2c_xfer_finish(adap
);
372 * i2c_probe - Probe the i2c chip
374 static int dw_i2c_probe(struct i2c_adapter
*adap
, u8 dev
)
380 * Try to read the first location of the chip.
382 ret
= dw_i2c_read(adap
, dev
, 0, 1, (uchar
*)&tmp
, 1);
384 dw_i2c_init(adap
, adap
->speed
, adap
->slaveaddr
);
389 U_BOOT_I2C_ADAP_COMPLETE(dw_0
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
390 dw_i2c_write
, dw_i2c_set_bus_speed
,
391 CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
, 0)
393 #if CONFIG_SYS_I2C_BUS_MAX >= 2
394 U_BOOT_I2C_ADAP_COMPLETE(dw_1
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
395 dw_i2c_write
, dw_i2c_set_bus_speed
,
396 CONFIG_SYS_I2C_SPEED1
, CONFIG_SYS_I2C_SLAVE1
, 1)
399 #if CONFIG_SYS_I2C_BUS_MAX >= 3
400 U_BOOT_I2C_ADAP_COMPLETE(dw_2
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
401 dw_i2c_write
, dw_i2c_set_bus_speed
,
402 CONFIG_SYS_I2C_SPEED2
, CONFIG_SYS_I2C_SLAVE2
, 2)
405 #if CONFIG_SYS_I2C_BUS_MAX >= 4
406 U_BOOT_I2C_ADAP_COMPLETE(dw_3
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
407 dw_i2c_write
, dw_i2c_set_bus_speed
,
408 CONFIG_SYS_I2C_SPEED3
, CONFIG_SYS_I2C_SLAVE3
, 3)