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50586ef2 | 1 | /* |
d621da00 | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
50586ef2 AF |
3 | * Andy Fleming |
4 | * | |
5 | * Based vaguely on the pxa mmc code: | |
6 | * (C) Copyright 2003 | |
7 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
50586ef2 AF |
10 | */ |
11 | ||
12 | #include <config.h> | |
13 | #include <common.h> | |
14 | #include <command.h> | |
b33433a6 | 15 | #include <hwconfig.h> |
50586ef2 AF |
16 | #include <mmc.h> |
17 | #include <part.h> | |
18 | #include <malloc.h> | |
19 | #include <mmc.h> | |
20 | #include <fsl_esdhc.h> | |
b33433a6 | 21 | #include <fdt_support.h> |
50586ef2 | 22 | #include <asm/io.h> |
96f0407b PF |
23 | #include <dm.h> |
24 | #include <asm-generic/gpio.h> | |
50586ef2 | 25 | |
50586ef2 AF |
26 | DECLARE_GLOBAL_DATA_PTR; |
27 | ||
a3d6e386 YL |
28 | #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ |
29 | IRQSTATEN_CINT | \ | |
30 | IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ | |
31 | IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ | |
32 | IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ | |
33 | IRQSTATEN_DINT) | |
34 | ||
50586ef2 | 35 | struct fsl_esdhc { |
511948b2 HZ |
36 | uint dsaddr; /* SDMA system address register */ |
37 | uint blkattr; /* Block attributes register */ | |
38 | uint cmdarg; /* Command argument register */ | |
39 | uint xfertyp; /* Transfer type register */ | |
40 | uint cmdrsp0; /* Command response 0 register */ | |
41 | uint cmdrsp1; /* Command response 1 register */ | |
42 | uint cmdrsp2; /* Command response 2 register */ | |
43 | uint cmdrsp3; /* Command response 3 register */ | |
44 | uint datport; /* Buffer data port register */ | |
45 | uint prsstat; /* Present state register */ | |
46 | uint proctl; /* Protocol control register */ | |
47 | uint sysctl; /* System Control Register */ | |
48 | uint irqstat; /* Interrupt status register */ | |
49 | uint irqstaten; /* Interrupt status enable register */ | |
50 | uint irqsigen; /* Interrupt signal enable register */ | |
51 | uint autoc12err; /* Auto CMD error status register */ | |
52 | uint hostcapblt; /* Host controller capabilities register */ | |
53 | uint wml; /* Watermark level register */ | |
54 | uint mixctrl; /* For USDHC */ | |
55 | char reserved1[4]; /* reserved */ | |
56 | uint fevt; /* Force event register */ | |
57 | uint admaes; /* ADMA error status register */ | |
58 | uint adsaddr; /* ADMA system address register */ | |
f022d36e OS |
59 | char reserved2[100]; /* reserved */ |
60 | uint vendorspec; /* Vendor Specific register */ | |
323aaaa1 | 61 | char reserved3[56]; /* reserved */ |
511948b2 | 62 | uint hostver; /* Host controller version register */ |
511948b2 | 63 | char reserved4[4]; /* reserved */ |
f022d36e | 64 | uint dmaerraddr; /* DMA error address register */ |
511948b2 | 65 | char reserved5[4]; /* reserved */ |
f022d36e OS |
66 | uint dmaerrattr; /* DMA error attribute register */ |
67 | char reserved6[4]; /* reserved */ | |
511948b2 | 68 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
f022d36e | 69 | char reserved7[8]; /* reserved */ |
511948b2 | 70 | uint tcr; /* Tuning control register */ |
f022d36e | 71 | char reserved8[28]; /* reserved */ |
511948b2 | 72 | uint sddirctl; /* SD direction control register */ |
f022d36e | 73 | char reserved9[712]; /* reserved */ |
511948b2 | 74 | uint scr; /* eSDHC control register */ |
50586ef2 AF |
75 | }; |
76 | ||
96f0407b PF |
77 | /** |
78 | * struct fsl_esdhc_priv | |
79 | * | |
80 | * @esdhc_regs: registers of the sdhc controller | |
81 | * @sdhc_clk: Current clk of the sdhc controller | |
82 | * @bus_width: bus width, 1bit, 4bit or 8bit | |
83 | * @cfg: mmc config | |
84 | * @mmc: mmc | |
85 | * Following is used when Driver Model is enabled for MMC | |
86 | * @dev: pointer for the device | |
87 | * @non_removable: 0: removable; 1: non-removable | |
88 | * @cd_gpio: gpio for card detection | |
89 | */ | |
90 | struct fsl_esdhc_priv { | |
91 | struct fsl_esdhc *esdhc_regs; | |
92 | unsigned int sdhc_clk; | |
93 | unsigned int bus_width; | |
94 | struct mmc_config cfg; | |
95 | struct mmc *mmc; | |
96 | struct udevice *dev; | |
97 | int non_removable; | |
98 | struct gpio_desc cd_gpio; | |
99 | }; | |
100 | ||
50586ef2 | 101 | /* Return the XFERTYP flags for a given command and data packet */ |
eafa90a1 | 102 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
50586ef2 AF |
103 | { |
104 | uint xfertyp = 0; | |
105 | ||
106 | if (data) { | |
77c1458d DD |
107 | xfertyp |= XFERTYP_DPSEL; |
108 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO | |
109 | xfertyp |= XFERTYP_DMAEN; | |
110 | #endif | |
50586ef2 AF |
111 | if (data->blocks > 1) { |
112 | xfertyp |= XFERTYP_MSBSEL; | |
113 | xfertyp |= XFERTYP_BCEN; | |
d621da00 JH |
114 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
115 | xfertyp |= XFERTYP_AC12EN; | |
116 | #endif | |
50586ef2 AF |
117 | } |
118 | ||
119 | if (data->flags & MMC_DATA_READ) | |
120 | xfertyp |= XFERTYP_DTDSEL; | |
121 | } | |
122 | ||
123 | if (cmd->resp_type & MMC_RSP_CRC) | |
124 | xfertyp |= XFERTYP_CCCEN; | |
125 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
126 | xfertyp |= XFERTYP_CICEN; | |
127 | if (cmd->resp_type & MMC_RSP_136) | |
128 | xfertyp |= XFERTYP_RSPTYP_136; | |
129 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
130 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; | |
131 | else if (cmd->resp_type & MMC_RSP_PRESENT) | |
132 | xfertyp |= XFERTYP_RSPTYP_48; | |
133 | ||
4571de33 JL |
134 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
135 | xfertyp |= XFERTYP_CMDTYP_ABORT; | |
25503443 | 136 | |
50586ef2 AF |
137 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
138 | } | |
139 | ||
77c1458d DD |
140 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
141 | /* | |
142 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. | |
143 | */ | |
7b43db92 | 144 | static void |
77c1458d DD |
145 | esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) |
146 | { | |
96f0407b PF |
147 | struct fsl_esdhc_priv *priv = mmc->priv; |
148 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
77c1458d DD |
149 | uint blocks; |
150 | char *buffer; | |
151 | uint databuf; | |
152 | uint size; | |
153 | uint irqstat; | |
154 | uint timeout; | |
155 | ||
156 | if (data->flags & MMC_DATA_READ) { | |
157 | blocks = data->blocks; | |
158 | buffer = data->dest; | |
159 | while (blocks) { | |
160 | timeout = PIO_TIMEOUT; | |
161 | size = data->blocksize; | |
162 | irqstat = esdhc_read32(®s->irqstat); | |
163 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) | |
164 | && --timeout); | |
165 | if (timeout <= 0) { | |
166 | printf("\nData Read Failed in PIO Mode."); | |
7b43db92 | 167 | return; |
77c1458d DD |
168 | } |
169 | while (size && (!(irqstat & IRQSTAT_TC))) { | |
170 | udelay(100); /* Wait before last byte transfer complete */ | |
171 | irqstat = esdhc_read32(®s->irqstat); | |
172 | databuf = in_le32(®s->datport); | |
173 | *((uint *)buffer) = databuf; | |
174 | buffer += 4; | |
175 | size -= 4; | |
176 | } | |
177 | blocks--; | |
178 | } | |
179 | } else { | |
180 | blocks = data->blocks; | |
7b43db92 | 181 | buffer = (char *)data->src; |
77c1458d DD |
182 | while (blocks) { |
183 | timeout = PIO_TIMEOUT; | |
184 | size = data->blocksize; | |
185 | irqstat = esdhc_read32(®s->irqstat); | |
186 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) | |
187 | && --timeout); | |
188 | if (timeout <= 0) { | |
189 | printf("\nData Write Failed in PIO Mode."); | |
7b43db92 | 190 | return; |
77c1458d DD |
191 | } |
192 | while (size && (!(irqstat & IRQSTAT_TC))) { | |
193 | udelay(100); /* Wait before last byte transfer complete */ | |
194 | databuf = *((uint *)buffer); | |
195 | buffer += 4; | |
196 | size -= 4; | |
197 | irqstat = esdhc_read32(®s->irqstat); | |
198 | out_le32(®s->datport, databuf); | |
199 | } | |
200 | blocks--; | |
201 | } | |
202 | } | |
203 | } | |
204 | #endif | |
205 | ||
50586ef2 AF |
206 | static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) |
207 | { | |
50586ef2 | 208 | int timeout; |
96f0407b PF |
209 | struct fsl_esdhc_priv *priv = mmc->priv; |
210 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
8ef0d5c4 | 211 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
212 | dma_addr_t addr; |
213 | #endif | |
7b43db92 | 214 | uint wml_value; |
50586ef2 AF |
215 | |
216 | wml_value = data->blocksize/4; | |
217 | ||
218 | if (data->flags & MMC_DATA_READ) { | |
32c8cfb2 PJ |
219 | if (wml_value > WML_RD_WML_MAX) |
220 | wml_value = WML_RD_WML_MAX_VAL; | |
50586ef2 | 221 | |
ab467c51 | 222 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
71689776 | 223 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
8ef0d5c4 | 224 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
225 | addr = virt_to_phys((void *)(data->dest)); |
226 | if (upper_32_bits(addr)) | |
227 | printf("Error found for upper 32 bits\n"); | |
228 | else | |
229 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); | |
230 | #else | |
c67bee14 | 231 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
8b06460e | 232 | #endif |
71689776 | 233 | #endif |
50586ef2 | 234 | } else { |
71689776 | 235 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
e576bd90 EN |
236 | flush_dcache_range((ulong)data->src, |
237 | (ulong)data->src+data->blocks | |
238 | *data->blocksize); | |
71689776 | 239 | #endif |
32c8cfb2 PJ |
240 | if (wml_value > WML_WR_WML_MAX) |
241 | wml_value = WML_WR_WML_MAX_VAL; | |
c67bee14 | 242 | if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { |
50586ef2 AF |
243 | printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); |
244 | return TIMEOUT; | |
245 | } | |
ab467c51 RZ |
246 | |
247 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, | |
248 | wml_value << 16); | |
71689776 | 249 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
8ef0d5c4 | 250 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
251 | addr = virt_to_phys((void *)(data->src)); |
252 | if (upper_32_bits(addr)) | |
253 | printf("Error found for upper 32 bits\n"); | |
254 | else | |
255 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); | |
256 | #else | |
c67bee14 | 257 | esdhc_write32(®s->dsaddr, (u32)data->src); |
8b06460e | 258 | #endif |
71689776 | 259 | #endif |
50586ef2 AF |
260 | } |
261 | ||
c67bee14 | 262 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
50586ef2 AF |
263 | |
264 | /* Calculate the timeout period for data transactions */ | |
b71ea336 PJ |
265 | /* |
266 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles | |
267 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec | |
268 | * So, Number of SD Clock cycles for 0.25sec should be minimum | |
269 | * (SD Clock/sec * 0.25 sec) SD Clock cycles | |
fb823981 | 270 | * = (mmc->clock * 1/4) SD Clock cycles |
b71ea336 | 271 | * As 1) >= 2) |
fb823981 | 272 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
b71ea336 | 273 | * Taking log2 both the sides |
fb823981 | 274 | * => timeout + 13 >= log2(mmc->clock/4) |
b71ea336 | 275 | * Rounding up to next power of 2 |
fb823981 AG |
276 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
277 | * => timeout + 13 = fls(mmc->clock/4) | |
e978a31b YL |
278 | * |
279 | * However, the MMC spec "It is strongly recommended for hosts to | |
280 | * implement more than 500ms timeout value even if the card | |
281 | * indicates the 250ms maximum busy length." Even the previous | |
282 | * value of 300ms is known to be insufficient for some cards. | |
283 | * So, we use | |
284 | * => timeout + 13 = fls(mmc->clock/2) | |
b71ea336 | 285 | */ |
e978a31b | 286 | timeout = fls(mmc->clock/2); |
50586ef2 AF |
287 | timeout -= 13; |
288 | ||
289 | if (timeout > 14) | |
290 | timeout = 14; | |
291 | ||
292 | if (timeout < 0) | |
293 | timeout = 0; | |
294 | ||
5103a03a KG |
295 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
296 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) | |
297 | timeout++; | |
298 | #endif | |
299 | ||
1336e2d3 HZ |
300 | #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
301 | timeout = 0xE; | |
302 | #endif | |
c67bee14 | 303 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
50586ef2 AF |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
e576bd90 EN |
308 | static void check_and_invalidate_dcache_range |
309 | (struct mmc_cmd *cmd, | |
310 | struct mmc_data *data) { | |
8b06460e | 311 | unsigned start = 0; |
cc634e28 | 312 | unsigned end = 0; |
e576bd90 EN |
313 | unsigned size = roundup(ARCH_DMA_MINALIGN, |
314 | data->blocks*data->blocksize); | |
8ef0d5c4 | 315 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
316 | dma_addr_t addr; |
317 | ||
318 | addr = virt_to_phys((void *)(data->dest)); | |
319 | if (upper_32_bits(addr)) | |
320 | printf("Error found for upper 32 bits\n"); | |
321 | else | |
322 | start = lower_32_bits(addr); | |
cc634e28 YL |
323 | #else |
324 | start = (unsigned)data->dest; | |
8b06460e | 325 | #endif |
cc634e28 | 326 | end = start + size; |
e576bd90 EN |
327 | invalidate_dcache_range(start, end); |
328 | } | |
10dc7771 | 329 | |
50586ef2 AF |
330 | /* |
331 | * Sends a command out on the bus. Takes the mmc pointer, | |
332 | * a command pointer, and an optional data pointer. | |
333 | */ | |
334 | static int | |
335 | esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) | |
336 | { | |
8a573022 | 337 | int err = 0; |
50586ef2 AF |
338 | uint xfertyp; |
339 | uint irqstat; | |
96f0407b PF |
340 | struct fsl_esdhc_priv *priv = mmc->priv; |
341 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
50586ef2 | 342 | |
d621da00 JH |
343 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
344 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) | |
345 | return 0; | |
346 | #endif | |
347 | ||
c67bee14 | 348 | esdhc_write32(®s->irqstat, -1); |
50586ef2 AF |
349 | |
350 | sync(); | |
351 | ||
352 | /* Wait for the bus to be idle */ | |
c67bee14 SB |
353 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
354 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) | |
355 | ; | |
50586ef2 | 356 | |
c67bee14 SB |
357 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
358 | ; | |
50586ef2 AF |
359 | |
360 | /* Wait at least 8 SD clock cycles before the next command */ | |
361 | /* | |
362 | * Note: This is way more than 8 cycles, but 1ms seems to | |
363 | * resolve timing issues with some cards | |
364 | */ | |
365 | udelay(1000); | |
366 | ||
367 | /* Set up for a data transfer if we have one */ | |
368 | if (data) { | |
50586ef2 AF |
369 | err = esdhc_setup_data(mmc, data); |
370 | if(err) | |
371 | return err; | |
4683b220 PF |
372 | |
373 | if (data->flags & MMC_DATA_READ) | |
374 | check_and_invalidate_dcache_range(cmd, data); | |
50586ef2 AF |
375 | } |
376 | ||
377 | /* Figure out the transfer arguments */ | |
378 | xfertyp = esdhc_xfertyp(cmd, data); | |
379 | ||
01b77353 AG |
380 | /* Mask all irqs */ |
381 | esdhc_write32(®s->irqsigen, 0); | |
382 | ||
50586ef2 | 383 | /* Send the command */ |
c67bee14 | 384 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
4692708d JL |
385 | #if defined(CONFIG_FSL_USDHC) |
386 | esdhc_write32(®s->mixctrl, | |
0e1bf614 VR |
387 | (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) |
388 | | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); | |
4692708d JL |
389 | esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); |
390 | #else | |
c67bee14 | 391 | esdhc_write32(®s->xfertyp, xfertyp); |
4692708d | 392 | #endif |
7a5b8029 | 393 | |
50586ef2 | 394 | /* Wait for the command to complete */ |
7a5b8029 | 395 | while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) |
c67bee14 | 396 | ; |
50586ef2 | 397 | |
c67bee14 | 398 | irqstat = esdhc_read32(®s->irqstat); |
50586ef2 | 399 | |
8a573022 AG |
400 | if (irqstat & CMD_ERR) { |
401 | err = COMM_ERR; | |
402 | goto out; | |
7a5b8029 DB |
403 | } |
404 | ||
8a573022 AG |
405 | if (irqstat & IRQSTAT_CTOE) { |
406 | err = TIMEOUT; | |
407 | goto out; | |
408 | } | |
50586ef2 | 409 | |
f022d36e OS |
410 | /* Switch voltage to 1.8V if CMD11 succeeded */ |
411 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { | |
412 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); | |
413 | ||
414 | printf("Run CMD11 1.8V switch\n"); | |
415 | /* Sleep for 5 ms - max time for card to switch to 1.8V */ | |
416 | udelay(5000); | |
417 | } | |
418 | ||
7a5b8029 DB |
419 | /* Workaround for ESDHC errata ENGcm03648 */ |
420 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { | |
253d5bdd | 421 | int timeout = 6000; |
7a5b8029 | 422 | |
253d5bdd | 423 | /* Poll on DATA0 line for cmd with busy signal for 600 ms */ |
7a5b8029 DB |
424 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
425 | PRSSTAT_DAT0)) { | |
426 | udelay(100); | |
427 | timeout--; | |
428 | } | |
429 | ||
430 | if (timeout <= 0) { | |
431 | printf("Timeout waiting for DAT0 to go high!\n"); | |
8a573022 AG |
432 | err = TIMEOUT; |
433 | goto out; | |
7a5b8029 DB |
434 | } |
435 | } | |
436 | ||
50586ef2 AF |
437 | /* Copy the response to the response buffer */ |
438 | if (cmd->resp_type & MMC_RSP_136) { | |
439 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; | |
440 | ||
c67bee14 SB |
441 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
442 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); | |
443 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); | |
444 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); | |
998be3dd RV |
445 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
446 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); | |
447 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); | |
448 | cmd->response[3] = (cmdrsp0 << 8); | |
50586ef2 | 449 | } else |
c67bee14 | 450 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
50586ef2 AF |
451 | |
452 | /* Wait until all of the blocks are transferred */ | |
453 | if (data) { | |
77c1458d DD |
454 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
455 | esdhc_pio_read_write(mmc, data); | |
456 | #else | |
50586ef2 | 457 | do { |
c67bee14 | 458 | irqstat = esdhc_read32(®s->irqstat); |
50586ef2 | 459 | |
8a573022 AG |
460 | if (irqstat & IRQSTAT_DTOE) { |
461 | err = TIMEOUT; | |
462 | goto out; | |
463 | } | |
63fb5a7e | 464 | |
8a573022 AG |
465 | if (irqstat & DATA_ERR) { |
466 | err = COMM_ERR; | |
467 | goto out; | |
468 | } | |
9b74dc56 | 469 | } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); |
71689776 | 470 | |
4683b220 PF |
471 | /* |
472 | * Need invalidate the dcache here again to avoid any | |
473 | * cache-fill during the DMA operations such as the | |
474 | * speculative pre-fetching etc. | |
475 | */ | |
54899fc8 EN |
476 | if (data->flags & MMC_DATA_READ) |
477 | check_and_invalidate_dcache_range(cmd, data); | |
71689776 | 478 | #endif |
50586ef2 AF |
479 | } |
480 | ||
8a573022 AG |
481 | out: |
482 | /* Reset CMD and DATA portions on error */ | |
483 | if (err) { | |
484 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | | |
485 | SYSCTL_RSTC); | |
486 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) | |
487 | ; | |
488 | ||
489 | if (data) { | |
490 | esdhc_write32(®s->sysctl, | |
491 | esdhc_read32(®s->sysctl) | | |
492 | SYSCTL_RSTD); | |
493 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) | |
494 | ; | |
495 | } | |
f022d36e OS |
496 | |
497 | /* If this was CMD11, then notify that power cycle is needed */ | |
498 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) | |
499 | printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); | |
8a573022 AG |
500 | } |
501 | ||
c67bee14 | 502 | esdhc_write32(®s->irqstat, -1); |
50586ef2 | 503 | |
8a573022 | 504 | return err; |
50586ef2 AF |
505 | } |
506 | ||
eafa90a1 | 507 | static void set_sysctl(struct mmc *mmc, uint clock) |
50586ef2 | 508 | { |
50586ef2 | 509 | int div, pre_div; |
96f0407b PF |
510 | struct fsl_esdhc_priv *priv = mmc->priv; |
511 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
512 | int sdhc_clk = priv->sdhc_clk; | |
50586ef2 AF |
513 | uint clk; |
514 | ||
93bfd616 PA |
515 | if (clock < mmc->cfg->f_min) |
516 | clock = mmc->cfg->f_min; | |
c67bee14 | 517 | |
50586ef2 AF |
518 | if (sdhc_clk / 16 > clock) { |
519 | for (pre_div = 2; pre_div < 256; pre_div *= 2) | |
520 | if ((sdhc_clk / pre_div) <= (clock * 16)) | |
521 | break; | |
522 | } else | |
523 | pre_div = 2; | |
524 | ||
525 | for (div = 1; div <= 16; div++) | |
526 | if ((sdhc_clk / (div * pre_div)) <= clock) | |
527 | break; | |
528 | ||
0e1bf614 | 529 | pre_div >>= mmc->ddr_mode ? 2 : 1; |
50586ef2 AF |
530 | div -= 1; |
531 | ||
532 | clk = (pre_div << 8) | (div << 4); | |
533 | ||
f0b5f23f EN |
534 | #ifdef CONFIG_FSL_USDHC |
535 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); | |
536 | #else | |
cc4d1226 | 537 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
f0b5f23f | 538 | #endif |
c67bee14 SB |
539 | |
540 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); | |
50586ef2 AF |
541 | |
542 | udelay(10000); | |
543 | ||
f0b5f23f EN |
544 | #ifdef CONFIG_FSL_USDHC |
545 | esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); | |
546 | #else | |
547 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); | |
548 | #endif | |
c67bee14 | 549 | |
50586ef2 AF |
550 | } |
551 | ||
2d9ca2c7 YL |
552 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
553 | static void esdhc_clock_control(struct mmc *mmc, bool enable) | |
554 | { | |
96f0407b PF |
555 | struct fsl_esdhc_priv *priv = mmc->priv; |
556 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
2d9ca2c7 YL |
557 | u32 value; |
558 | u32 time_out; | |
559 | ||
560 | value = esdhc_read32(®s->sysctl); | |
561 | ||
562 | if (enable) | |
563 | value |= SYSCTL_CKEN; | |
564 | else | |
565 | value &= ~SYSCTL_CKEN; | |
566 | ||
567 | esdhc_write32(®s->sysctl, value); | |
568 | ||
569 | time_out = 20; | |
570 | value = PRSSTAT_SDSTB; | |
571 | while (!(esdhc_read32(®s->prsstat) & value)) { | |
572 | if (time_out == 0) { | |
573 | printf("fsl_esdhc: Internal clock never stabilised.\n"); | |
574 | break; | |
575 | } | |
576 | time_out--; | |
577 | mdelay(1); | |
578 | } | |
579 | } | |
580 | #endif | |
581 | ||
50586ef2 AF |
582 | static void esdhc_set_ios(struct mmc *mmc) |
583 | { | |
96f0407b PF |
584 | struct fsl_esdhc_priv *priv = mmc->priv; |
585 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
50586ef2 | 586 | |
2d9ca2c7 YL |
587 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
588 | /* Select to use peripheral clock */ | |
589 | esdhc_clock_control(mmc, false); | |
590 | esdhc_setbits32(®s->scr, ESDHCCTL_PCS); | |
591 | esdhc_clock_control(mmc, true); | |
592 | #endif | |
50586ef2 AF |
593 | /* Set the clock speed */ |
594 | set_sysctl(mmc, mmc->clock); | |
595 | ||
596 | /* Set the bus width */ | |
c67bee14 | 597 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
50586ef2 AF |
598 | |
599 | if (mmc->bus_width == 4) | |
c67bee14 | 600 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
50586ef2 | 601 | else if (mmc->bus_width == 8) |
c67bee14 SB |
602 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
603 | ||
50586ef2 AF |
604 | } |
605 | ||
606 | static int esdhc_init(struct mmc *mmc) | |
607 | { | |
96f0407b PF |
608 | struct fsl_esdhc_priv *priv = mmc->priv; |
609 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
50586ef2 AF |
610 | int timeout = 1000; |
611 | ||
c67bee14 | 612 | /* Reset the entire host controller */ |
a61da72b | 613 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
c67bee14 SB |
614 | |
615 | /* Wait until the controller is available */ | |
616 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) | |
617 | udelay(1000); | |
50586ef2 | 618 | |
16e43f35 | 619 | #ifndef ARCH_MXC |
2c1764ef | 620 | /* Enable cache snooping */ |
16e43f35 BT |
621 | esdhc_write32(®s->scr, 0x00000040); |
622 | #endif | |
2c1764ef | 623 | |
f0b5f23f | 624 | #ifndef CONFIG_FSL_USDHC |
a61da72b | 625 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
f0b5f23f | 626 | #endif |
50586ef2 AF |
627 | |
628 | /* Set the initial clock speed */ | |
4a6ee172 | 629 | mmc_set_clock(mmc, 400000); |
50586ef2 AF |
630 | |
631 | /* Disable the BRR and BWR bits in IRQSTAT */ | |
c67bee14 | 632 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
50586ef2 AF |
633 | |
634 | /* Put the PROCTL reg back to the default */ | |
c67bee14 | 635 | esdhc_write32(®s->proctl, PROCTL_INIT); |
50586ef2 | 636 | |
c67bee14 SB |
637 | /* Set timout to the maximum value */ |
638 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); | |
50586ef2 | 639 | |
ee0c5389 OS |
640 | #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT |
641 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); | |
642 | #endif | |
643 | ||
d48d2e21 TR |
644 | return 0; |
645 | } | |
50586ef2 | 646 | |
d48d2e21 TR |
647 | static int esdhc_getcd(struct mmc *mmc) |
648 | { | |
96f0407b PF |
649 | struct fsl_esdhc_priv *priv = mmc->priv; |
650 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
d48d2e21 TR |
651 | int timeout = 1000; |
652 | ||
f7e27cc5 HZ |
653 | #ifdef CONFIG_ESDHC_DETECT_QUIRK |
654 | if (CONFIG_ESDHC_DETECT_QUIRK) | |
655 | return 1; | |
656 | #endif | |
96f0407b PF |
657 | |
658 | #ifdef CONFIG_DM_MMC | |
659 | if (priv->non_removable) | |
660 | return 1; | |
661 | ||
662 | if (dm_gpio_is_valid(&priv->cd_gpio)) | |
663 | return dm_gpio_get_value(&priv->cd_gpio); | |
664 | #endif | |
665 | ||
d48d2e21 TR |
666 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) |
667 | udelay(1000); | |
c67bee14 | 668 | |
d48d2e21 | 669 | return timeout > 0; |
50586ef2 AF |
670 | } |
671 | ||
48bb3bb5 JH |
672 | static void esdhc_reset(struct fsl_esdhc *regs) |
673 | { | |
674 | unsigned long timeout = 100; /* wait max 100 ms */ | |
675 | ||
676 | /* reset the controller */ | |
a61da72b | 677 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
48bb3bb5 JH |
678 | |
679 | /* hardware clears the bit when it is done */ | |
680 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) | |
681 | udelay(1000); | |
682 | if (!timeout) | |
683 | printf("MMC/SD: Reset never completed.\n"); | |
684 | } | |
685 | ||
ab769f22 PA |
686 | static const struct mmc_ops esdhc_ops = { |
687 | .send_cmd = esdhc_send_cmd, | |
688 | .set_ios = esdhc_set_ios, | |
689 | .init = esdhc_init, | |
690 | .getcd = esdhc_getcd, | |
691 | }; | |
692 | ||
96f0407b PF |
693 | static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, |
694 | struct fsl_esdhc_priv *priv) | |
695 | { | |
696 | if (!cfg || !priv) | |
697 | return -EINVAL; | |
698 | ||
699 | priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); | |
700 | priv->bus_width = cfg->max_bus_width; | |
701 | priv->sdhc_clk = cfg->sdhc_clk; | |
702 | ||
703 | return 0; | |
704 | }; | |
705 | ||
706 | static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) | |
50586ef2 | 707 | { |
c67bee14 | 708 | struct fsl_esdhc *regs; |
50586ef2 | 709 | struct mmc *mmc; |
030955c2 | 710 | u32 caps, voltage_caps; |
50586ef2 | 711 | |
96f0407b PF |
712 | if (!priv) |
713 | return -EINVAL; | |
c67bee14 | 714 | |
96f0407b | 715 | regs = priv->esdhc_regs; |
c67bee14 | 716 | |
48bb3bb5 JH |
717 | /* First reset the eSDHC controller */ |
718 | esdhc_reset(regs); | |
719 | ||
f0b5f23f | 720 | #ifndef CONFIG_FSL_USDHC |
975324a7 JH |
721 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
722 | | SYSCTL_IPGEN | SYSCTL_CKEN); | |
f0b5f23f | 723 | #endif |
975324a7 | 724 | |
a3d6e386 | 725 | writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); |
96f0407b | 726 | memset(&priv->cfg, 0, sizeof(priv->cfg)); |
93bfd616 | 727 | |
030955c2 | 728 | voltage_caps = 0; |
19060bd8 | 729 | caps = esdhc_read32(®s->hostcapblt); |
3b4456ec RZ |
730 | |
731 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
732 | caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | | |
733 | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); | |
734 | #endif | |
ef38f3ff HZ |
735 | |
736 | /* T4240 host controller capabilities register should have VS33 bit */ | |
737 | #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
738 | caps = caps | ESDHC_HOSTCAPBLT_VS33; | |
739 | #endif | |
740 | ||
50586ef2 | 741 | if (caps & ESDHC_HOSTCAPBLT_VS18) |
030955c2 | 742 | voltage_caps |= MMC_VDD_165_195; |
50586ef2 | 743 | if (caps & ESDHC_HOSTCAPBLT_VS30) |
030955c2 | 744 | voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; |
50586ef2 | 745 | if (caps & ESDHC_HOSTCAPBLT_VS33) |
030955c2 LY |
746 | voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; |
747 | ||
96f0407b PF |
748 | priv->cfg.name = "FSL_SDHC"; |
749 | priv->cfg.ops = &esdhc_ops; | |
030955c2 | 750 | #ifdef CONFIG_SYS_SD_VOLTAGE |
96f0407b | 751 | priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; |
030955c2 | 752 | #else |
96f0407b | 753 | priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
030955c2 | 754 | #endif |
96f0407b | 755 | if ((priv->cfg.voltages & voltage_caps) == 0) { |
030955c2 LY |
756 | printf("voltage not supported by controller\n"); |
757 | return -1; | |
758 | } | |
50586ef2 | 759 | |
96f0407b PF |
760 | if (priv->bus_width == 8) |
761 | priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; | |
762 | else if (priv->bus_width == 4) | |
763 | priv->cfg.host_caps = MMC_MODE_4BIT; | |
764 | ||
765 | priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; | |
0e1bf614 | 766 | #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE |
96f0407b | 767 | priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; |
0e1bf614 | 768 | #endif |
50586ef2 | 769 | |
96f0407b PF |
770 | if (priv->bus_width > 0) { |
771 | if (priv->bus_width < 8) | |
772 | priv->cfg.host_caps &= ~MMC_MODE_8BIT; | |
773 | if (priv->bus_width < 4) | |
774 | priv->cfg.host_caps &= ~MMC_MODE_4BIT; | |
aad4659a AR |
775 | } |
776 | ||
50586ef2 | 777 | if (caps & ESDHC_HOSTCAPBLT_HSS) |
96f0407b | 778 | priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
50586ef2 | 779 | |
d47e3d27 HZ |
780 | #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK |
781 | if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) | |
96f0407b | 782 | priv->cfg.host_caps &= ~MMC_MODE_8BIT; |
d47e3d27 HZ |
783 | #endif |
784 | ||
96f0407b PF |
785 | priv->cfg.f_min = 400000; |
786 | priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); | |
50586ef2 | 787 | |
96f0407b | 788 | priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
93bfd616 | 789 | |
96f0407b | 790 | mmc = mmc_create(&priv->cfg, priv); |
93bfd616 PA |
791 | if (mmc == NULL) |
792 | return -1; | |
50586ef2 | 793 | |
96f0407b PF |
794 | priv->mmc = mmc; |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) | |
800 | { | |
801 | struct fsl_esdhc_priv *priv; | |
802 | int ret; | |
803 | ||
804 | if (!cfg) | |
805 | return -EINVAL; | |
806 | ||
807 | priv = calloc(sizeof(struct fsl_esdhc_priv), 1); | |
808 | if (!priv) | |
809 | return -ENOMEM; | |
810 | ||
811 | ret = fsl_esdhc_cfg_to_priv(cfg, priv); | |
812 | if (ret) { | |
813 | debug("%s xlate failure\n", __func__); | |
814 | free(priv); | |
815 | return ret; | |
816 | } | |
817 | ||
818 | ret = fsl_esdhc_init(priv); | |
819 | if (ret) { | |
820 | debug("%s init failure\n", __func__); | |
821 | free(priv); | |
822 | return ret; | |
823 | } | |
824 | ||
50586ef2 AF |
825 | return 0; |
826 | } | |
827 | ||
828 | int fsl_esdhc_mmc_init(bd_t *bis) | |
829 | { | |
c67bee14 SB |
830 | struct fsl_esdhc_cfg *cfg; |
831 | ||
88227a1d | 832 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
c67bee14 | 833 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
e9adeca3 | 834 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
c67bee14 | 835 | return fsl_esdhc_initialize(bis, cfg); |
50586ef2 | 836 | } |
b33433a6 | 837 | |
5a8dbdc6 YL |
838 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
839 | void mmc_adapter_card_type_ident(void) | |
840 | { | |
841 | u8 card_id; | |
842 | u8 value; | |
843 | ||
844 | card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; | |
845 | gd->arch.sdhc_adapter = card_id; | |
846 | ||
847 | switch (card_id) { | |
848 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: | |
cdc69550 YL |
849 | value = QIXIS_READ(brdcfg[5]); |
850 | value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); | |
851 | QIXIS_WRITE(brdcfg[5], value); | |
5a8dbdc6 YL |
852 | break; |
853 | case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: | |
bf50be83 YL |
854 | value = QIXIS_READ(pwr_ctl[1]); |
855 | value |= QIXIS_EVDD_BY_SDHC_VS; | |
856 | QIXIS_WRITE(pwr_ctl[1], value); | |
5a8dbdc6 YL |
857 | break; |
858 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: | |
859 | value = QIXIS_READ(brdcfg[5]); | |
860 | value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); | |
861 | QIXIS_WRITE(brdcfg[5], value); | |
862 | break; | |
863 | case QIXIS_ESDHC_ADAPTER_TYPE_RSV: | |
864 | break; | |
865 | case QIXIS_ESDHC_ADAPTER_TYPE_MMC: | |
866 | break; | |
867 | case QIXIS_ESDHC_ADAPTER_TYPE_SD: | |
868 | break; | |
869 | case QIXIS_ESDHC_NO_ADAPTER: | |
870 | break; | |
871 | default: | |
872 | break; | |
873 | } | |
874 | } | |
875 | #endif | |
876 | ||
c67bee14 | 877 | #ifdef CONFIG_OF_LIBFDT |
b33433a6 AV |
878 | void fdt_fixup_esdhc(void *blob, bd_t *bd) |
879 | { | |
880 | const char *compat = "fsl,esdhc"; | |
b33433a6 | 881 | |
a6da8b81 | 882 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
b33433a6 | 883 | if (!hwconfig("esdhc")) { |
a6da8b81 CZ |
884 | do_fixup_by_compat(blob, compat, "status", "disabled", |
885 | 8 + 1, 1); | |
886 | return; | |
b33433a6 | 887 | } |
a6da8b81 | 888 | #endif |
b33433a6 | 889 | |
2d9ca2c7 YL |
890 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
891 | do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", | |
892 | gd->arch.sdhc_clk, 1); | |
893 | #else | |
b33433a6 | 894 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
e9adeca3 | 895 | gd->arch.sdhc_clk, 1); |
2d9ca2c7 | 896 | #endif |
5a8dbdc6 YL |
897 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
898 | do_fixup_by_compat_u32(blob, compat, "adapter-type", | |
899 | (u32)(gd->arch.sdhc_adapter), 1); | |
900 | #endif | |
a6da8b81 CZ |
901 | do_fixup_by_compat(blob, compat, "status", "okay", |
902 | 4 + 1, 1); | |
b33433a6 | 903 | } |
c67bee14 | 904 | #endif |
96f0407b PF |
905 | |
906 | #ifdef CONFIG_DM_MMC | |
907 | #include <asm/arch/clock.h> | |
908 | static int fsl_esdhc_probe(struct udevice *dev) | |
909 | { | |
910 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
911 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); | |
912 | const void *fdt = gd->fdt_blob; | |
913 | int node = dev->of_offset; | |
914 | fdt_addr_t addr; | |
915 | unsigned int val; | |
916 | int ret; | |
917 | ||
918 | addr = dev_get_addr(dev); | |
919 | if (addr == FDT_ADDR_T_NONE) | |
920 | return -EINVAL; | |
921 | ||
922 | priv->esdhc_regs = (struct fsl_esdhc *)addr; | |
923 | priv->dev = dev; | |
924 | ||
925 | val = fdtdec_get_int(fdt, node, "bus-width", -1); | |
926 | if (val == 8) | |
927 | priv->bus_width = 8; | |
928 | else if (val == 4) | |
929 | priv->bus_width = 4; | |
930 | else | |
931 | priv->bus_width = 1; | |
932 | ||
933 | if (fdt_get_property(fdt, node, "non-removable", NULL)) { | |
934 | priv->non_removable = 1; | |
935 | } else { | |
936 | priv->non_removable = 0; | |
937 | gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0, | |
938 | &priv->cd_gpio, GPIOD_IS_IN); | |
939 | } | |
940 | ||
941 | /* | |
942 | * TODO: | |
943 | * Because lack of clk driver, if SDHC clk is not enabled, | |
944 | * need to enable it first before this driver is invoked. | |
945 | * | |
946 | * we use MXC_ESDHC_CLK to get clk freq. | |
947 | * If one would like to make this function work, | |
948 | * the aliases should be provided in dts as this: | |
949 | * | |
950 | * aliases { | |
951 | * mmc0 = &usdhc1; | |
952 | * mmc1 = &usdhc2; | |
953 | * mmc2 = &usdhc3; | |
954 | * mmc3 = &usdhc4; | |
955 | * }; | |
956 | * Then if your board only supports mmc2 and mmc3, but we can | |
957 | * correctly get the seq as 2 and 3, then let mxc_get_clock | |
958 | * work as expected. | |
959 | */ | |
960 | priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); | |
961 | if (priv->sdhc_clk <= 0) { | |
962 | dev_err(dev, "Unable to get clk for %s\n", dev->name); | |
963 | return -EINVAL; | |
964 | } | |
965 | ||
966 | ret = fsl_esdhc_init(priv); | |
967 | if (ret) { | |
968 | dev_err(dev, "fsl_esdhc_init failure\n"); | |
969 | return ret; | |
970 | } | |
971 | ||
972 | upriv->mmc = priv->mmc; | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
977 | static const struct udevice_id fsl_esdhc_ids[] = { | |
978 | { .compatible = "fsl,imx6ul-usdhc", }, | |
979 | { .compatible = "fsl,imx6sx-usdhc", }, | |
980 | { .compatible = "fsl,imx6sl-usdhc", }, | |
981 | { .compatible = "fsl,imx6q-usdhc", }, | |
982 | { .compatible = "fsl,imx7d-usdhc", }, | |
983 | { /* sentinel */ } | |
984 | }; | |
985 | ||
986 | U_BOOT_DRIVER(fsl_esdhc) = { | |
987 | .name = "fsl-esdhc-mmc", | |
988 | .id = UCLASS_MMC, | |
989 | .of_match = fsl_esdhc_ids, | |
990 | .probe = fsl_esdhc_probe, | |
991 | .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), | |
992 | }; | |
993 | #endif |