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[people/ms/u-boot.git] / drivers / mmc / fsl_esdhc.c
CommitLineData
50586ef2 1/*
d621da00 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
50586ef2
AF		 3 * Andy Fleming
4 *
5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 *
1a459660 9 * SPDX-License-Identifier: GPL-2.0+
50586ef2
AF		 10 */
11
12#include <config.h>
13#include <common.h>
14#include <command.h>
b33433a6 15#include <hwconfig.h>
50586ef2
AF		 16#include <mmc.h>
17#include <part.h>
18#include <malloc.h>
19#include <mmc.h>
20#include <fsl_esdhc.h>
b33433a6 21#include <fdt_support.h>
50586ef2
AF		 22#include <asm/io.h>
23
50586ef2
AF		 24DECLARE_GLOBAL_DATA_PTR;
25
a3d6e386
YL		 26#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
27 IRQSTATEN_CINT | \
28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
31 IRQSTATEN_DINT)
32
50586ef2 33struct fsl_esdhc {
511948b2
HZ		 34 uint dsaddr; /* SDMA system address register */
35 uint blkattr; /* Block attributes register */
36 uint cmdarg; /* Command argument register */
37 uint xfertyp; /* Transfer type register */
38 uint cmdrsp0; /* Command response 0 register */
39 uint cmdrsp1; /* Command response 1 register */
40 uint cmdrsp2; /* Command response 2 register */
41 uint cmdrsp3; /* Command response 3 register */
42 uint datport; /* Buffer data port register */
43 uint prsstat; /* Present state register */
44 uint proctl; /* Protocol control register */
45 uint sysctl; /* System Control Register */
46 uint irqstat; /* Interrupt status register */
47 uint irqstaten; /* Interrupt status enable register */
48 uint irqsigen; /* Interrupt signal enable register */
49 uint autoc12err; /* Auto CMD error status register */
50 uint hostcapblt; /* Host controller capabilities register */
51 uint wml; /* Watermark level register */
52 uint mixctrl; /* For USDHC */
53 char reserved1[4]; /* reserved */
54 uint fevt; /* Force event register */
55 uint admaes; /* ADMA error status register */
56 uint adsaddr; /* ADMA system address register */
f022d36e
OS		 57 char reserved2[100]; /* reserved */
58 uint vendorspec; /* Vendor Specific register */
323aaaa1 59 char reserved3[56]; /* reserved */
511948b2 60 uint hostver; /* Host controller version register */
511948b2 61 char reserved4[4]; /* reserved */
f022d36e 62 uint dmaerraddr; /* DMA error address register */
511948b2 63 char reserved5[4]; /* reserved */
f022d36e
OS		 64 uint dmaerrattr; /* DMA error attribute register */
65 char reserved6[4]; /* reserved */
511948b2 66 uint hostcapblt2; /* Host controller capabilities register 2 */
f022d36e 67 char reserved7[8]; /* reserved */
511948b2 68 uint tcr; /* Tuning control register */
f022d36e 69 char reserved8[28]; /* reserved */
511948b2 70 uint sddirctl; /* SD direction control register */
f022d36e 71 char reserved9[712]; /* reserved */
511948b2 72 uint scr; /* eSDHC control register */
50586ef2
AF		 73};
74
75/* Return the XFERTYP flags for a given command and data packet */
eafa90a1 76static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
50586ef2
AF		 77{
78 uint xfertyp = 0;
79
80 if (data) {
77c1458d
DD		 81 xfertyp |= XFERTYP_DPSEL;
82#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
83 xfertyp |= XFERTYP_DMAEN;
84#endif
50586ef2
AF		 85 if (data->blocks > 1) {
86 xfertyp |= XFERTYP_MSBSEL;
87 xfertyp |= XFERTYP_BCEN;
d621da00
JH		 88#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
89 xfertyp |= XFERTYP_AC12EN;
90#endif
50586ef2
AF		 91 }
92
93 if (data->flags & MMC_DATA_READ)
94 xfertyp |= XFERTYP_DTDSEL;
95 }
96
97 if (cmd->resp_type & MMC_RSP_CRC)
98 xfertyp |= XFERTYP_CCCEN;
99 if (cmd->resp_type & MMC_RSP_OPCODE)
100 xfertyp |= XFERTYP_CICEN;
101 if (cmd->resp_type & MMC_RSP_136)
102 xfertyp |= XFERTYP_RSPTYP_136;
103 else if (cmd->resp_type & MMC_RSP_BUSY)
104 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
105 else if (cmd->resp_type & MMC_RSP_PRESENT)
106 xfertyp |= XFERTYP_RSPTYP_48;
107
8b06460e 108#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
512bdbd4
SX		 109 defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \
110 defined(CONFIG_PPC_T4160)
4571de33
JL		 111 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
112 xfertyp |= XFERTYP_CMDTYP_ABORT;
113#endif
50586ef2
AF		 114 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
115}
116
77c1458d
DD		 117#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
118/*
119 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
120 */
7b43db92 121static void
77c1458d
DD		 122esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
123{
8eee2bd7
IS		 124 struct fsl_esdhc_cfg *cfg = mmc->priv;
125 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
77c1458d
DD		 126 uint blocks;
127 char *buffer;
128 uint databuf;
129 uint size;
130 uint irqstat;
131 uint timeout;
132
133 if (data->flags & MMC_DATA_READ) {
134 blocks = data->blocks;
135 buffer = data->dest;
136 while (blocks) {
137 timeout = PIO_TIMEOUT;
138 size = data->blocksize;
139 irqstat = esdhc_read32(&regs->irqstat);
140 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
141 && --timeout);
142 if (timeout <= 0) {
143 printf("\nData Read Failed in PIO Mode.");
7b43db92 144 return;
77c1458d
DD		 145 }
146 while (size && (!(irqstat & IRQSTAT_TC))) {
147 udelay(100); /* Wait before last byte transfer complete */
148 irqstat = esdhc_read32(&regs->irqstat);
149 databuf = in_le32(&regs->datport);
150 *((uint *)buffer) = databuf;
151 buffer += 4;
152 size -= 4;
153 }
154 blocks--;
155 }
156 } else {
157 blocks = data->blocks;
7b43db92 158 buffer = (char *)data->src;
77c1458d
DD		 159 while (blocks) {
160 timeout = PIO_TIMEOUT;
161 size = data->blocksize;
162 irqstat = esdhc_read32(&regs->irqstat);
163 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
164 && --timeout);
165 if (timeout <= 0) {
166 printf("\nData Write Failed in PIO Mode.");
7b43db92 167 return;
77c1458d
DD		 168 }
169 while (size && (!(irqstat & IRQSTAT_TC))) {
170 udelay(100); /* Wait before last byte transfer complete */
171 databuf = *((uint *)buffer);
172 buffer += 4;
173 size -= 4;
174 irqstat = esdhc_read32(&regs->irqstat);
175 out_le32(&regs->datport, databuf);
176 }
177 blocks--;
178 }
179 }
180}
181#endif
182
50586ef2
AF		 183static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
184{
50586ef2 185 int timeout;
93bfd616 186 struct fsl_esdhc_cfg *cfg = mmc->priv;
c67bee14 187 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
8ef0d5c4 188#ifdef CONFIG_FSL_LAYERSCAPE
8b06460e
YL		 189 dma_addr_t addr;
190#endif
7b43db92 191 uint wml_value;
50586ef2
AF		 192
193 wml_value = data->blocksize/4;
194
195 if (data->flags & MMC_DATA_READ) {
32c8cfb2
PJ		 196 if (wml_value > WML_RD_WML_MAX)
197 wml_value = WML_RD_WML_MAX_VAL;
50586ef2 198
ab467c51 199 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
71689776 200#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
8ef0d5c4 201#ifdef CONFIG_FSL_LAYERSCAPE
8b06460e
YL		 202 addr = virt_to_phys((void *)(data->dest));
203 if (upper_32_bits(addr))
204 printf("Error found for upper 32 bits\n");
205 else
206 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
207#else
c67bee14 208 esdhc_write32(&regs->dsaddr, (u32)data->dest);
8b06460e 209#endif
71689776 210#endif
50586ef2 211 } else {
71689776 212#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
e576bd90
EN		 213 flush_dcache_range((ulong)data->src,
214 (ulong)data->src+data->blocks
215 *data->blocksize);
71689776 216#endif
32c8cfb2
PJ		 217 if (wml_value > WML_WR_WML_MAX)
218 wml_value = WML_WR_WML_MAX_VAL;
c67bee14 219 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
50586ef2
AF		 220 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
221 return TIMEOUT;
222 }
ab467c51
RZ		 223
224 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
225 wml_value << 16);
71689776 226#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
8ef0d5c4 227#ifdef CONFIG_FSL_LAYERSCAPE
8b06460e
YL		 228 addr = virt_to_phys((void *)(data->src));
229 if (upper_32_bits(addr))
230 printf("Error found for upper 32 bits\n");
231 else
232 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
233#else
c67bee14 234 esdhc_write32(&regs->dsaddr, (u32)data->src);
8b06460e 235#endif
71689776 236#endif
50586ef2
AF		 237 }
238
c67bee14 239 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
50586ef2
AF		 240
241 /* Calculate the timeout period for data transactions */
b71ea336
PJ		 242 /*
243 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
244 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
245 * So, Number of SD Clock cycles for 0.25sec should be minimum
246 * (SD Clock/sec * 0.25 sec) SD Clock cycles
fb823981 247 * = (mmc->clock * 1/4) SD Clock cycles
b71ea336 248 * As 1) >= 2)
fb823981 249 * => (2^(timeout+13)) >= mmc->clock * 1/4
b71ea336 250 * Taking log2 both the sides
fb823981 251 * => timeout + 13 >= log2(mmc->clock/4)
b71ea336 252 * Rounding up to next power of 2
fb823981
AG		 253 * => timeout + 13 = log2(mmc->clock/4) + 1
254 * => timeout + 13 = fls(mmc->clock/4)
b71ea336 255 */
fb823981 256 timeout = fls(mmc->clock/4);
50586ef2
AF		 257 timeout -= 13;
258
259 if (timeout > 14)
260 timeout = 14;
261
262 if (timeout < 0)
263 timeout = 0;
264
5103a03a
KG		 265#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
266 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
267 timeout++;
268#endif
269
1336e2d3
HZ		 270#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
271 timeout = 0xE;
272#endif
c67bee14 273 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
50586ef2
AF		 274
275 return 0;
276}
277
e576bd90
EN		 278static void check_and_invalidate_dcache_range
279 (struct mmc_cmd *cmd,
280 struct mmc_data *data) {
8ef0d5c4 281#ifdef CONFIG_FSL_LAYERSCAPE
8b06460e
YL		 282 unsigned start = 0;
283#else
e576bd90 284 unsigned start = (unsigned)data->dest ;
8b06460e 285#endif
e576bd90
EN		 286 unsigned size = roundup(ARCH_DMA_MINALIGN,
287 data->blocks*data->blocksize);
288 unsigned end = start+size ;
8ef0d5c4 289#ifdef CONFIG_FSL_LAYERSCAPE
8b06460e
YL		 290 dma_addr_t addr;
291
292 addr = virt_to_phys((void *)(data->dest));
293 if (upper_32_bits(addr))
294 printf("Error found for upper 32 bits\n");
295 else
296 start = lower_32_bits(addr);
297#endif
e576bd90
EN		 298 invalidate_dcache_range(start, end);
299}
10dc7771 300
50586ef2
AF		 301/*
302 * Sends a command out on the bus. Takes the mmc pointer,
303 * a command pointer, and an optional data pointer.
304 */
305static int
306esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
307{
8a573022 308 int err = 0;
50586ef2
AF		 309 uint xfertyp;
310 uint irqstat;
93bfd616 311 struct fsl_esdhc_cfg *cfg = mmc->priv;
c67bee14 312 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
50586ef2 313
d621da00
JH		 314#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
315 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
316 return 0;
317#endif
318
c67bee14 319 esdhc_write32(&regs->irqstat, -1);
50586ef2
AF		 320
321 sync();
322
323 /* Wait for the bus to be idle */
c67bee14
SB		 324 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
325 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
326 ;
50586ef2 327
c67bee14
SB		 328 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
329 ;
50586ef2
AF		 330
331 /* Wait at least 8 SD clock cycles before the next command */
332 /*
333 * Note: This is way more than 8 cycles, but 1ms seems to
334 * resolve timing issues with some cards
335 */
336 udelay(1000);
337
338 /* Set up for a data transfer if we have one */
339 if (data) {
50586ef2
AF		 340 err = esdhc_setup_data(mmc, data);
341 if(err)
342 return err;
4683b220
PF		 343
344 if (data->flags & MMC_DATA_READ)
345 check_and_invalidate_dcache_range(cmd, data);
50586ef2
AF		 346 }
347
348 /* Figure out the transfer arguments */
349 xfertyp = esdhc_xfertyp(cmd, data);
350
01b77353
AG		 351 /* Mask all irqs */
352 esdhc_write32(&regs->irqsigen, 0);
353
50586ef2 354 /* Send the command */
c67bee14 355 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
4692708d
JL		 356#if defined(CONFIG_FSL_USDHC)
357 esdhc_write32(&regs->mixctrl,
0e1bf614
VR		 358 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
359 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
4692708d
JL		 360 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
361#else
c67bee14 362 esdhc_write32(&regs->xfertyp, xfertyp);
4692708d 363#endif
7a5b8029 364
50586ef2 365 /* Wait for the command to complete */
7a5b8029 366 while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
c67bee14 367 ;
50586ef2 368
c67bee14 369 irqstat = esdhc_read32(&regs->irqstat);
50586ef2 370
8a573022
AG		 371 if (irqstat & CMD_ERR) {
372 err = COMM_ERR;
373 goto out;
7a5b8029
DB		 374 }
375
8a573022
AG		 376 if (irqstat & IRQSTAT_CTOE) {
377 err = TIMEOUT;
378 goto out;
379 }
50586ef2 380
f022d36e
OS		 381 /* Switch voltage to 1.8V if CMD11 succeeded */
382 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
383 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
384
385 printf("Run CMD11 1.8V switch\n");
386 /* Sleep for 5 ms - max time for card to switch to 1.8V */
387 udelay(5000);
388 }
389
7a5b8029
DB		 390 /* Workaround for ESDHC errata ENGcm03648 */
391 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
253d5bdd 392 int timeout = 6000;
7a5b8029 393
253d5bdd 394 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
7a5b8029
DB		 395 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
396 PRSSTAT_DAT0)) {
397 udelay(100);
398 timeout--;
399 }
400
401 if (timeout <= 0) {
402 printf("Timeout waiting for DAT0 to go high!\n");
8a573022
AG		 403 err = TIMEOUT;
404 goto out;
7a5b8029
DB		 405 }
406 }
407
50586ef2
AF		 408 /* Copy the response to the response buffer */
409 if (cmd->resp_type & MMC_RSP_136) {
410 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
411
c67bee14
SB		 412 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
413 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
414 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
415 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
998be3dd
RV		 416 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
417 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
418 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
419 cmd->response[3] = (cmdrsp0 << 8);
50586ef2 420 } else
c67bee14 421 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
50586ef2
AF		 422
423 /* Wait until all of the blocks are transferred */
424 if (data) {
77c1458d
DD		 425#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
426 esdhc_pio_read_write(mmc, data);
427#else
50586ef2 428 do {
c67bee14 429 irqstat = esdhc_read32(&regs->irqstat);
50586ef2 430
8a573022
AG		 431 if (irqstat & IRQSTAT_DTOE) {
432 err = TIMEOUT;
433 goto out;
434 }
63fb5a7e 435
8a573022
AG		 436 if (irqstat & DATA_ERR) {
437 err = COMM_ERR;
438 goto out;
439 }
9b74dc56 440 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
71689776 441
4683b220
PF		 442 /*
443 * Need invalidate the dcache here again to avoid any
444 * cache-fill during the DMA operations such as the
445 * speculative pre-fetching etc.
446 */
54899fc8
EN		 447 if (data->flags & MMC_DATA_READ)
448 check_and_invalidate_dcache_range(cmd, data);
71689776 449#endif
50586ef2
AF		 450 }
451
8a573022
AG		 452out:
453 /* Reset CMD and DATA portions on error */
454 if (err) {
455 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
456 SYSCTL_RSTC);
457 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
458 ;
459
460 if (data) {
461 esdhc_write32(&regs->sysctl,
462 esdhc_read32(&regs->sysctl) |
463 SYSCTL_RSTD);
464 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
465 ;
466 }
f022d36e
OS		 467
468 /* If this was CMD11, then notify that power cycle is needed */
469 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
470 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
8a573022
AG		 471 }
472
c67bee14 473 esdhc_write32(&regs->irqstat, -1);
50586ef2 474
8a573022 475 return err;
50586ef2
AF		 476}
477
eafa90a1 478static void set_sysctl(struct mmc *mmc, uint clock)
50586ef2 479{
50586ef2 480 int div, pre_div;
93bfd616 481 struct fsl_esdhc_cfg *cfg = mmc->priv;
c67bee14 482 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
a2ac1b3a 483 int sdhc_clk = cfg->sdhc_clk;
50586ef2
AF		 484 uint clk;
485
93bfd616
PA		 486 if (clock < mmc->cfg->f_min)
487 clock = mmc->cfg->f_min;
c67bee14 488
50586ef2
AF		 489 if (sdhc_clk / 16 > clock) {
490 for (pre_div = 2; pre_div < 256; pre_div *= 2)
491 if ((sdhc_clk / pre_div) <= (clock * 16))
492 break;
493 } else
494 pre_div = 2;
495
496 for (div = 1; div <= 16; div++)
497 if ((sdhc_clk / (div * pre_div)) <= clock)
498 break;
499
0e1bf614 500 pre_div >>= mmc->ddr_mode ? 2 : 1;
50586ef2
AF		 501 div -= 1;
502
503 clk = (pre_div << 8) | (div << 4);
504
cc4d1226 505 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
c67bee14
SB		 506
507 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
50586ef2
AF		 508
509 udelay(10000);
510
cc4d1226 511 clk = SYSCTL_PEREN | SYSCTL_CKEN;
c67bee14
SB		 512
513 esdhc_setbits32(&regs->sysctl, clk);
50586ef2
AF		 514}
515
2d9ca2c7
YL		 516#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
517static void esdhc_clock_control(struct mmc *mmc, bool enable)
518{
519 struct fsl_esdhc_cfg *cfg = mmc->priv;
520 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
521 u32 value;
522 u32 time_out;
523
524 value = esdhc_read32(&regs->sysctl);
525
526 if (enable)
527 value |= SYSCTL_CKEN;
528 else
529 value &= ~SYSCTL_CKEN;
530
531 esdhc_write32(&regs->sysctl, value);
532
533 time_out = 20;
534 value = PRSSTAT_SDSTB;
535 while (!(esdhc_read32(&regs->prsstat) & value)) {
536 if (time_out == 0) {
537 printf("fsl_esdhc: Internal clock never stabilised.\n");
538 break;
539 }
540 time_out--;
541 mdelay(1);
542 }
543}
544#endif
545
50586ef2
AF		 546static void esdhc_set_ios(struct mmc *mmc)
547{
93bfd616 548 struct fsl_esdhc_cfg *cfg = mmc->priv;
c67bee14 549 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
50586ef2 550
2d9ca2c7
YL		 551#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
552 /* Select to use peripheral clock */
553 esdhc_clock_control(mmc, false);
554 esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
555 esdhc_clock_control(mmc, true);
556#endif
50586ef2
AF		 557 /* Set the clock speed */
558 set_sysctl(mmc, mmc->clock);
559
560 /* Set the bus width */
c67bee14 561 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
50586ef2
AF		 562
563 if (mmc->bus_width == 4)
c67bee14 564 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
50586ef2 565 else if (mmc->bus_width == 8)
c67bee14
SB		 566 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
567
50586ef2
AF		 568}
569
570static int esdhc_init(struct mmc *mmc)
571{
93bfd616 572 struct fsl_esdhc_cfg *cfg = mmc->priv;
c67bee14 573 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
50586ef2
AF		 574 int timeout = 1000;
575
c67bee14 576 /* Reset the entire host controller */
a61da72b 577 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
c67bee14
SB		 578
579 /* Wait until the controller is available */
580 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
581 udelay(1000);
50586ef2 582
16e43f35 583#ifndef ARCH_MXC
2c1764ef 584 /* Enable cache snooping */
16e43f35
BT		 585 esdhc_write32(&regs->scr, 0x00000040);
586#endif
2c1764ef 587
a61da72b 588 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
50586ef2
AF		 589
590 /* Set the initial clock speed */
4a6ee172 591 mmc_set_clock(mmc, 400000);
50586ef2
AF		 592
593 /* Disable the BRR and BWR bits in IRQSTAT */
c67bee14 594 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
50586ef2
AF		 595
596 /* Put the PROCTL reg back to the default */
c67bee14 597 esdhc_write32(&regs->proctl, PROCTL_INIT);
50586ef2 598
c67bee14
SB		 599 /* Set timout to the maximum value */
600 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
50586ef2 601
ee0c5389
OS		 602#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
603 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
604#endif
605
d48d2e21
TR		 606 return 0;
607}
50586ef2 608
d48d2e21
TR		 609static int esdhc_getcd(struct mmc *mmc)
610{
93bfd616 611 struct fsl_esdhc_cfg *cfg = mmc->priv;
d48d2e21
TR		 612 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
613 int timeout = 1000;
614
f7e27cc5
HZ		 615#ifdef CONFIG_ESDHC_DETECT_QUIRK
616 if (CONFIG_ESDHC_DETECT_QUIRK)
617 return 1;
618#endif
d48d2e21
TR		 619 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
620 udelay(1000);
c67bee14 621
d48d2e21 622 return timeout > 0;
50586ef2
AF		 623}
624
48bb3bb5
JH		 625static void esdhc_reset(struct fsl_esdhc *regs)
626{
627 unsigned long timeout = 100; /* wait max 100 ms */
628
629 /* reset the controller */
a61da72b 630 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
48bb3bb5
JH		 631
632 /* hardware clears the bit when it is done */
633 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
634 udelay(1000);
635 if (!timeout)
636 printf("MMC/SD: Reset never completed.\n");
637}
638
ab769f22
PA		 639static const struct mmc_ops esdhc_ops = {
640 .send_cmd = esdhc_send_cmd,
641 .set_ios = esdhc_set_ios,
642 .init = esdhc_init,
643 .getcd = esdhc_getcd,
644};
645
c67bee14 646int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
50586ef2 647{
c67bee14 648 struct fsl_esdhc *regs;
50586ef2 649 struct mmc *mmc;
030955c2 650 u32 caps, voltage_caps;
50586ef2 651
c67bee14
SB		 652 if (!cfg)
653 return -1;
654
c67bee14
SB		 655 regs = (struct fsl_esdhc *)cfg->esdhc_base;
656
48bb3bb5
JH		 657 /* First reset the eSDHC controller */
658 esdhc_reset(regs);
659
975324a7
JH		 660 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
661 | SYSCTL_IPGEN | SYSCTL_CKEN);
662
a3d6e386 663 writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
93bfd616
PA		 664 memset(&cfg->cfg, 0, sizeof(cfg->cfg));
665
030955c2 666 voltage_caps = 0;
19060bd8 667 caps = esdhc_read32(&regs->hostcapblt);
3b4456ec
RZ		 668
669#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
670 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
671 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
672#endif
ef38f3ff
HZ		 673
674/* T4240 host controller capabilities register should have VS33 bit */
675#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
676 caps = caps | ESDHC_HOSTCAPBLT_VS33;
677#endif
678
50586ef2 679 if (caps & ESDHC_HOSTCAPBLT_VS18)
030955c2 680 voltage_caps |= MMC_VDD_165_195;
50586ef2 681 if (caps & ESDHC_HOSTCAPBLT_VS30)
030955c2 682 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
50586ef2 683 if (caps & ESDHC_HOSTCAPBLT_VS33)
030955c2
LY		 684 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
685
93bfd616
PA		 686 cfg->cfg.name = "FSL_SDHC";
687 cfg->cfg.ops = &esdhc_ops;
030955c2 688#ifdef CONFIG_SYS_SD_VOLTAGE
93bfd616 689 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
030955c2 690#else
93bfd616 691 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
030955c2 692#endif
93bfd616 693 if ((cfg->cfg.voltages & voltage_caps) == 0) {
030955c2
LY		 694 printf("voltage not supported by controller\n");
695 return -1;
696 }
50586ef2 697
5a20397b 698 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
0e1bf614
VR		 699#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
700 cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
701#endif
50586ef2 702
aad4659a
AR		 703 if (cfg->max_bus_width > 0) {
704 if (cfg->max_bus_width < 8)
93bfd616 705 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
aad4659a 706 if (cfg->max_bus_width < 4)
93bfd616 707 cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
aad4659a
AR		 708 }
709
50586ef2 710 if (caps & ESDHC_HOSTCAPBLT_HSS)
93bfd616 711 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
50586ef2 712
d47e3d27
HZ		 713#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
714 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
93bfd616 715 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
d47e3d27
HZ		 716#endif
717
93bfd616 718 cfg->cfg.f_min = 400000;
21008ad6 719 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
50586ef2 720
93bfd616
PA		 721 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
722
723 mmc = mmc_create(&cfg->cfg, cfg);
724 if (mmc == NULL)
725 return -1;
50586ef2
AF		 726
727 return 0;
728}
729
730int fsl_esdhc_mmc_init(bd_t *bis)
731{
c67bee14
SB		 732 struct fsl_esdhc_cfg *cfg;
733
88227a1d 734 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
c67bee14 735 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
e9adeca3 736 cfg->sdhc_clk = gd->arch.sdhc_clk;
c67bee14 737 return fsl_esdhc_initialize(bis, cfg);
50586ef2 738}
b33433a6 739
5a8dbdc6
YL		 740#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
741void mmc_adapter_card_type_ident(void)
742{
743 u8 card_id;
744 u8 value;
745
746 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
747 gd->arch.sdhc_adapter = card_id;
748
749 switch (card_id) {
750 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
cdc69550
YL		 751 value = QIXIS_READ(brdcfg[5]);
752 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
753 QIXIS_WRITE(brdcfg[5], value);
5a8dbdc6
YL		 754 break;
755 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
bf50be83
YL		 756 value = QIXIS_READ(pwr_ctl[1]);
757 value |= QIXIS_EVDD_BY_SDHC_VS;
758 QIXIS_WRITE(pwr_ctl[1], value);
5a8dbdc6
YL		 759 break;
760 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
761 value = QIXIS_READ(brdcfg[5]);
762 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
763 QIXIS_WRITE(brdcfg[5], value);
764 break;
765 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
766 break;
767 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
768 break;
769 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
770 break;
771 case QIXIS_ESDHC_NO_ADAPTER:
772 break;
773 default:
774 break;
775 }
776}
777#endif
778
c67bee14 779#ifdef CONFIG_OF_LIBFDT
b33433a6
AV		 780void fdt_fixup_esdhc(void *blob, bd_t *bd)
781{
782 const char *compat = "fsl,esdhc";
b33433a6 783
a6da8b81 784#ifdef CONFIG_FSL_ESDHC_PIN_MUX
b33433a6 785 if (!hwconfig("esdhc")) {
a6da8b81
CZ		 786 do_fixup_by_compat(blob, compat, "status", "disabled",
787 8 + 1, 1);
788 return;
b33433a6 789 }
a6da8b81 790#endif
b33433a6 791
2d9ca2c7
YL		 792#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
793 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
794 gd->arch.sdhc_clk, 1);
795#else
b33433a6 796 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
e9adeca3 797 gd->arch.sdhc_clk, 1);
2d9ca2c7 798#endif
5a8dbdc6
YL		 799#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
800 do_fixup_by_compat_u32(blob, compat, "adapter-type",
801 (u32)(gd->arch.sdhc_adapter), 1);
802#endif
a6da8b81
CZ		 803 do_fixup_by_compat(blob, compat, "status", "okay",
804 4 + 1, 1);
b33433a6 805}
c67bee14 806#endif
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