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Commit | Line | Data |
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50586ef2 | 1 | /* |
d621da00 | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
50586ef2 AF |
3 | * Andy Fleming |
4 | * | |
5 | * Based vaguely on the pxa mmc code: | |
6 | * (C) Copyright 2003 | |
7 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
50586ef2 AF |
10 | */ |
11 | ||
12 | #include <config.h> | |
13 | #include <common.h> | |
14 | #include <command.h> | |
b33433a6 | 15 | #include <hwconfig.h> |
50586ef2 AF |
16 | #include <mmc.h> |
17 | #include <part.h> | |
18 | #include <malloc.h> | |
19 | #include <mmc.h> | |
20 | #include <fsl_esdhc.h> | |
b33433a6 | 21 | #include <fdt_support.h> |
50586ef2 AF |
22 | #include <asm/io.h> |
23 | ||
50586ef2 AF |
24 | DECLARE_GLOBAL_DATA_PTR; |
25 | ||
a3d6e386 YL |
26 | #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ |
27 | IRQSTATEN_CINT | \ | |
28 | IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ | |
29 | IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ | |
30 | IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ | |
31 | IRQSTATEN_DINT) | |
32 | ||
50586ef2 | 33 | struct fsl_esdhc { |
511948b2 HZ |
34 | uint dsaddr; /* SDMA system address register */ |
35 | uint blkattr; /* Block attributes register */ | |
36 | uint cmdarg; /* Command argument register */ | |
37 | uint xfertyp; /* Transfer type register */ | |
38 | uint cmdrsp0; /* Command response 0 register */ | |
39 | uint cmdrsp1; /* Command response 1 register */ | |
40 | uint cmdrsp2; /* Command response 2 register */ | |
41 | uint cmdrsp3; /* Command response 3 register */ | |
42 | uint datport; /* Buffer data port register */ | |
43 | uint prsstat; /* Present state register */ | |
44 | uint proctl; /* Protocol control register */ | |
45 | uint sysctl; /* System Control Register */ | |
46 | uint irqstat; /* Interrupt status register */ | |
47 | uint irqstaten; /* Interrupt status enable register */ | |
48 | uint irqsigen; /* Interrupt signal enable register */ | |
49 | uint autoc12err; /* Auto CMD error status register */ | |
50 | uint hostcapblt; /* Host controller capabilities register */ | |
51 | uint wml; /* Watermark level register */ | |
52 | uint mixctrl; /* For USDHC */ | |
53 | char reserved1[4]; /* reserved */ | |
54 | uint fevt; /* Force event register */ | |
55 | uint admaes; /* ADMA error status register */ | |
56 | uint adsaddr; /* ADMA system address register */ | |
f022d36e OS |
57 | char reserved2[100]; /* reserved */ |
58 | uint vendorspec; /* Vendor Specific register */ | |
323aaaa1 | 59 | char reserved3[56]; /* reserved */ |
511948b2 | 60 | uint hostver; /* Host controller version register */ |
511948b2 | 61 | char reserved4[4]; /* reserved */ |
f022d36e | 62 | uint dmaerraddr; /* DMA error address register */ |
511948b2 | 63 | char reserved5[4]; /* reserved */ |
f022d36e OS |
64 | uint dmaerrattr; /* DMA error attribute register */ |
65 | char reserved6[4]; /* reserved */ | |
511948b2 | 66 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
f022d36e | 67 | char reserved7[8]; /* reserved */ |
511948b2 | 68 | uint tcr; /* Tuning control register */ |
f022d36e | 69 | char reserved8[28]; /* reserved */ |
511948b2 | 70 | uint sddirctl; /* SD direction control register */ |
f022d36e | 71 | char reserved9[712]; /* reserved */ |
511948b2 | 72 | uint scr; /* eSDHC control register */ |
50586ef2 AF |
73 | }; |
74 | ||
75 | /* Return the XFERTYP flags for a given command and data packet */ | |
eafa90a1 | 76 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
50586ef2 AF |
77 | { |
78 | uint xfertyp = 0; | |
79 | ||
80 | if (data) { | |
77c1458d DD |
81 | xfertyp |= XFERTYP_DPSEL; |
82 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO | |
83 | xfertyp |= XFERTYP_DMAEN; | |
84 | #endif | |
50586ef2 AF |
85 | if (data->blocks > 1) { |
86 | xfertyp |= XFERTYP_MSBSEL; | |
87 | xfertyp |= XFERTYP_BCEN; | |
d621da00 JH |
88 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
89 | xfertyp |= XFERTYP_AC12EN; | |
90 | #endif | |
50586ef2 AF |
91 | } |
92 | ||
93 | if (data->flags & MMC_DATA_READ) | |
94 | xfertyp |= XFERTYP_DTDSEL; | |
95 | } | |
96 | ||
97 | if (cmd->resp_type & MMC_RSP_CRC) | |
98 | xfertyp |= XFERTYP_CCCEN; | |
99 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
100 | xfertyp |= XFERTYP_CICEN; | |
101 | if (cmd->resp_type & MMC_RSP_136) | |
102 | xfertyp |= XFERTYP_RSPTYP_136; | |
103 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
104 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; | |
105 | else if (cmd->resp_type & MMC_RSP_PRESENT) | |
106 | xfertyp |= XFERTYP_RSPTYP_48; | |
107 | ||
8b06460e | 108 | #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ |
512bdbd4 SX |
109 | defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \ |
110 | defined(CONFIG_PPC_T4160) | |
4571de33 JL |
111 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
112 | xfertyp |= XFERTYP_CMDTYP_ABORT; | |
113 | #endif | |
50586ef2 AF |
114 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
115 | } | |
116 | ||
77c1458d DD |
117 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
118 | /* | |
119 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. | |
120 | */ | |
7b43db92 | 121 | static void |
77c1458d DD |
122 | esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) |
123 | { | |
8eee2bd7 IS |
124 | struct fsl_esdhc_cfg *cfg = mmc->priv; |
125 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; | |
77c1458d DD |
126 | uint blocks; |
127 | char *buffer; | |
128 | uint databuf; | |
129 | uint size; | |
130 | uint irqstat; | |
131 | uint timeout; | |
132 | ||
133 | if (data->flags & MMC_DATA_READ) { | |
134 | blocks = data->blocks; | |
135 | buffer = data->dest; | |
136 | while (blocks) { | |
137 | timeout = PIO_TIMEOUT; | |
138 | size = data->blocksize; | |
139 | irqstat = esdhc_read32(®s->irqstat); | |
140 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) | |
141 | && --timeout); | |
142 | if (timeout <= 0) { | |
143 | printf("\nData Read Failed in PIO Mode."); | |
7b43db92 | 144 | return; |
77c1458d DD |
145 | } |
146 | while (size && (!(irqstat & IRQSTAT_TC))) { | |
147 | udelay(100); /* Wait before last byte transfer complete */ | |
148 | irqstat = esdhc_read32(®s->irqstat); | |
149 | databuf = in_le32(®s->datport); | |
150 | *((uint *)buffer) = databuf; | |
151 | buffer += 4; | |
152 | size -= 4; | |
153 | } | |
154 | blocks--; | |
155 | } | |
156 | } else { | |
157 | blocks = data->blocks; | |
7b43db92 | 158 | buffer = (char *)data->src; |
77c1458d DD |
159 | while (blocks) { |
160 | timeout = PIO_TIMEOUT; | |
161 | size = data->blocksize; | |
162 | irqstat = esdhc_read32(®s->irqstat); | |
163 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) | |
164 | && --timeout); | |
165 | if (timeout <= 0) { | |
166 | printf("\nData Write Failed in PIO Mode."); | |
7b43db92 | 167 | return; |
77c1458d DD |
168 | } |
169 | while (size && (!(irqstat & IRQSTAT_TC))) { | |
170 | udelay(100); /* Wait before last byte transfer complete */ | |
171 | databuf = *((uint *)buffer); | |
172 | buffer += 4; | |
173 | size -= 4; | |
174 | irqstat = esdhc_read32(®s->irqstat); | |
175 | out_le32(®s->datport, databuf); | |
176 | } | |
177 | blocks--; | |
178 | } | |
179 | } | |
180 | } | |
181 | #endif | |
182 | ||
50586ef2 AF |
183 | static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) |
184 | { | |
50586ef2 | 185 | int timeout; |
93bfd616 | 186 | struct fsl_esdhc_cfg *cfg = mmc->priv; |
c67bee14 | 187 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
8ef0d5c4 | 188 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
189 | dma_addr_t addr; |
190 | #endif | |
7b43db92 | 191 | uint wml_value; |
50586ef2 AF |
192 | |
193 | wml_value = data->blocksize/4; | |
194 | ||
195 | if (data->flags & MMC_DATA_READ) { | |
32c8cfb2 PJ |
196 | if (wml_value > WML_RD_WML_MAX) |
197 | wml_value = WML_RD_WML_MAX_VAL; | |
50586ef2 | 198 | |
ab467c51 | 199 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
71689776 | 200 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
8ef0d5c4 | 201 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
202 | addr = virt_to_phys((void *)(data->dest)); |
203 | if (upper_32_bits(addr)) | |
204 | printf("Error found for upper 32 bits\n"); | |
205 | else | |
206 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); | |
207 | #else | |
c67bee14 | 208 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
8b06460e | 209 | #endif |
71689776 | 210 | #endif |
50586ef2 | 211 | } else { |
71689776 | 212 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
e576bd90 EN |
213 | flush_dcache_range((ulong)data->src, |
214 | (ulong)data->src+data->blocks | |
215 | *data->blocksize); | |
71689776 | 216 | #endif |
32c8cfb2 PJ |
217 | if (wml_value > WML_WR_WML_MAX) |
218 | wml_value = WML_WR_WML_MAX_VAL; | |
c67bee14 | 219 | if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { |
50586ef2 AF |
220 | printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); |
221 | return TIMEOUT; | |
222 | } | |
ab467c51 RZ |
223 | |
224 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, | |
225 | wml_value << 16); | |
71689776 | 226 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
8ef0d5c4 | 227 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
228 | addr = virt_to_phys((void *)(data->src)); |
229 | if (upper_32_bits(addr)) | |
230 | printf("Error found for upper 32 bits\n"); | |
231 | else | |
232 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); | |
233 | #else | |
c67bee14 | 234 | esdhc_write32(®s->dsaddr, (u32)data->src); |
8b06460e | 235 | #endif |
71689776 | 236 | #endif |
50586ef2 AF |
237 | } |
238 | ||
c67bee14 | 239 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
50586ef2 AF |
240 | |
241 | /* Calculate the timeout period for data transactions */ | |
b71ea336 PJ |
242 | /* |
243 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles | |
244 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec | |
245 | * So, Number of SD Clock cycles for 0.25sec should be minimum | |
246 | * (SD Clock/sec * 0.25 sec) SD Clock cycles | |
fb823981 | 247 | * = (mmc->clock * 1/4) SD Clock cycles |
b71ea336 | 248 | * As 1) >= 2) |
fb823981 | 249 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
b71ea336 | 250 | * Taking log2 both the sides |
fb823981 | 251 | * => timeout + 13 >= log2(mmc->clock/4) |
b71ea336 | 252 | * Rounding up to next power of 2 |
fb823981 AG |
253 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
254 | * => timeout + 13 = fls(mmc->clock/4) | |
b71ea336 | 255 | */ |
fb823981 | 256 | timeout = fls(mmc->clock/4); |
50586ef2 AF |
257 | timeout -= 13; |
258 | ||
259 | if (timeout > 14) | |
260 | timeout = 14; | |
261 | ||
262 | if (timeout < 0) | |
263 | timeout = 0; | |
264 | ||
5103a03a KG |
265 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
266 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) | |
267 | timeout++; | |
268 | #endif | |
269 | ||
1336e2d3 HZ |
270 | #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
271 | timeout = 0xE; | |
272 | #endif | |
c67bee14 | 273 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
50586ef2 AF |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
e576bd90 EN |
278 | static void check_and_invalidate_dcache_range |
279 | (struct mmc_cmd *cmd, | |
280 | struct mmc_data *data) { | |
8ef0d5c4 | 281 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
282 | unsigned start = 0; |
283 | #else | |
e576bd90 | 284 | unsigned start = (unsigned)data->dest ; |
8b06460e | 285 | #endif |
e576bd90 EN |
286 | unsigned size = roundup(ARCH_DMA_MINALIGN, |
287 | data->blocks*data->blocksize); | |
288 | unsigned end = start+size ; | |
8ef0d5c4 | 289 | #ifdef CONFIG_FSL_LAYERSCAPE |
8b06460e YL |
290 | dma_addr_t addr; |
291 | ||
292 | addr = virt_to_phys((void *)(data->dest)); | |
293 | if (upper_32_bits(addr)) | |
294 | printf("Error found for upper 32 bits\n"); | |
295 | else | |
296 | start = lower_32_bits(addr); | |
297 | #endif | |
e576bd90 EN |
298 | invalidate_dcache_range(start, end); |
299 | } | |
10dc7771 | 300 | |
50586ef2 AF |
301 | /* |
302 | * Sends a command out on the bus. Takes the mmc pointer, | |
303 | * a command pointer, and an optional data pointer. | |
304 | */ | |
305 | static int | |
306 | esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) | |
307 | { | |
8a573022 | 308 | int err = 0; |
50586ef2 AF |
309 | uint xfertyp; |
310 | uint irqstat; | |
93bfd616 | 311 | struct fsl_esdhc_cfg *cfg = mmc->priv; |
c67bee14 | 312 | volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
50586ef2 | 313 | |
d621da00 JH |
314 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
315 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) | |
316 | return 0; | |
317 | #endif | |
318 | ||
c67bee14 | 319 | esdhc_write32(®s->irqstat, -1); |
50586ef2 AF |
320 | |
321 | sync(); | |
322 | ||
323 | /* Wait for the bus to be idle */ | |
c67bee14 SB |
324 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
325 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) | |
326 | ; | |
50586ef2 | 327 | |
c67bee14 SB |
328 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
329 | ; | |
50586ef2 AF |
330 | |
331 | /* Wait at least 8 SD clock cycles before the next command */ | |
332 | /* | |
333 | * Note: This is way more than 8 cycles, but 1ms seems to | |
334 | * resolve timing issues with some cards | |
335 | */ | |
336 | udelay(1000); | |
337 | ||
338 | /* Set up for a data transfer if we have one */ | |
339 | if (data) { | |
50586ef2 AF |
340 | err = esdhc_setup_data(mmc, data); |
341 | if(err) | |
342 | return err; | |
4683b220 PF |
343 | |
344 | if (data->flags & MMC_DATA_READ) | |
345 | check_and_invalidate_dcache_range(cmd, data); | |
50586ef2 AF |
346 | } |
347 | ||
348 | /* Figure out the transfer arguments */ | |
349 | xfertyp = esdhc_xfertyp(cmd, data); | |
350 | ||
01b77353 AG |
351 | /* Mask all irqs */ |
352 | esdhc_write32(®s->irqsigen, 0); | |
353 | ||
50586ef2 | 354 | /* Send the command */ |
c67bee14 | 355 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
4692708d JL |
356 | #if defined(CONFIG_FSL_USDHC) |
357 | esdhc_write32(®s->mixctrl, | |
0e1bf614 VR |
358 | (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) |
359 | | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); | |
4692708d JL |
360 | esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); |
361 | #else | |
c67bee14 | 362 | esdhc_write32(®s->xfertyp, xfertyp); |
4692708d | 363 | #endif |
7a5b8029 | 364 | |
50586ef2 | 365 | /* Wait for the command to complete */ |
7a5b8029 | 366 | while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) |
c67bee14 | 367 | ; |
50586ef2 | 368 | |
c67bee14 | 369 | irqstat = esdhc_read32(®s->irqstat); |
50586ef2 | 370 | |
8a573022 AG |
371 | if (irqstat & CMD_ERR) { |
372 | err = COMM_ERR; | |
373 | goto out; | |
7a5b8029 DB |
374 | } |
375 | ||
8a573022 AG |
376 | if (irqstat & IRQSTAT_CTOE) { |
377 | err = TIMEOUT; | |
378 | goto out; | |
379 | } | |
50586ef2 | 380 | |
f022d36e OS |
381 | /* Switch voltage to 1.8V if CMD11 succeeded */ |
382 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { | |
383 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); | |
384 | ||
385 | printf("Run CMD11 1.8V switch\n"); | |
386 | /* Sleep for 5 ms - max time for card to switch to 1.8V */ | |
387 | udelay(5000); | |
388 | } | |
389 | ||
7a5b8029 DB |
390 | /* Workaround for ESDHC errata ENGcm03648 */ |
391 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { | |
253d5bdd | 392 | int timeout = 6000; |
7a5b8029 | 393 | |
253d5bdd | 394 | /* Poll on DATA0 line for cmd with busy signal for 600 ms */ |
7a5b8029 DB |
395 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
396 | PRSSTAT_DAT0)) { | |
397 | udelay(100); | |
398 | timeout--; | |
399 | } | |
400 | ||
401 | if (timeout <= 0) { | |
402 | printf("Timeout waiting for DAT0 to go high!\n"); | |
8a573022 AG |
403 | err = TIMEOUT; |
404 | goto out; | |
7a5b8029 DB |
405 | } |
406 | } | |
407 | ||
50586ef2 AF |
408 | /* Copy the response to the response buffer */ |
409 | if (cmd->resp_type & MMC_RSP_136) { | |
410 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; | |
411 | ||
c67bee14 SB |
412 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
413 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); | |
414 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); | |
415 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); | |
998be3dd RV |
416 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
417 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); | |
418 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); | |
419 | cmd->response[3] = (cmdrsp0 << 8); | |
50586ef2 | 420 | } else |
c67bee14 | 421 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
50586ef2 AF |
422 | |
423 | /* Wait until all of the blocks are transferred */ | |
424 | if (data) { | |
77c1458d DD |
425 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
426 | esdhc_pio_read_write(mmc, data); | |
427 | #else | |
50586ef2 | 428 | do { |
c67bee14 | 429 | irqstat = esdhc_read32(®s->irqstat); |
50586ef2 | 430 | |
8a573022 AG |
431 | if (irqstat & IRQSTAT_DTOE) { |
432 | err = TIMEOUT; | |
433 | goto out; | |
434 | } | |
63fb5a7e | 435 | |
8a573022 AG |
436 | if (irqstat & DATA_ERR) { |
437 | err = COMM_ERR; | |
438 | goto out; | |
439 | } | |
9b74dc56 | 440 | } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); |
71689776 | 441 | |
4683b220 PF |
442 | /* |
443 | * Need invalidate the dcache here again to avoid any | |
444 | * cache-fill during the DMA operations such as the | |
445 | * speculative pre-fetching etc. | |
446 | */ | |
54899fc8 EN |
447 | if (data->flags & MMC_DATA_READ) |
448 | check_and_invalidate_dcache_range(cmd, data); | |
71689776 | 449 | #endif |
50586ef2 AF |
450 | } |
451 | ||
8a573022 AG |
452 | out: |
453 | /* Reset CMD and DATA portions on error */ | |
454 | if (err) { | |
455 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | | |
456 | SYSCTL_RSTC); | |
457 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) | |
458 | ; | |
459 | ||
460 | if (data) { | |
461 | esdhc_write32(®s->sysctl, | |
462 | esdhc_read32(®s->sysctl) | | |
463 | SYSCTL_RSTD); | |
464 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) | |
465 | ; | |
466 | } | |
f022d36e OS |
467 | |
468 | /* If this was CMD11, then notify that power cycle is needed */ | |
469 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) | |
470 | printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); | |
8a573022 AG |
471 | } |
472 | ||
c67bee14 | 473 | esdhc_write32(®s->irqstat, -1); |
50586ef2 | 474 | |
8a573022 | 475 | return err; |
50586ef2 AF |
476 | } |
477 | ||
eafa90a1 | 478 | static void set_sysctl(struct mmc *mmc, uint clock) |
50586ef2 | 479 | { |
50586ef2 | 480 | int div, pre_div; |
93bfd616 | 481 | struct fsl_esdhc_cfg *cfg = mmc->priv; |
c67bee14 | 482 | volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
a2ac1b3a | 483 | int sdhc_clk = cfg->sdhc_clk; |
50586ef2 AF |
484 | uint clk; |
485 | ||
93bfd616 PA |
486 | if (clock < mmc->cfg->f_min) |
487 | clock = mmc->cfg->f_min; | |
c67bee14 | 488 | |
50586ef2 AF |
489 | if (sdhc_clk / 16 > clock) { |
490 | for (pre_div = 2; pre_div < 256; pre_div *= 2) | |
491 | if ((sdhc_clk / pre_div) <= (clock * 16)) | |
492 | break; | |
493 | } else | |
494 | pre_div = 2; | |
495 | ||
496 | for (div = 1; div <= 16; div++) | |
497 | if ((sdhc_clk / (div * pre_div)) <= clock) | |
498 | break; | |
499 | ||
0e1bf614 | 500 | pre_div >>= mmc->ddr_mode ? 2 : 1; |
50586ef2 AF |
501 | div -= 1; |
502 | ||
503 | clk = (pre_div << 8) | (div << 4); | |
504 | ||
f0b5f23f EN |
505 | #ifdef CONFIG_FSL_USDHC |
506 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); | |
507 | #else | |
cc4d1226 | 508 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
f0b5f23f | 509 | #endif |
c67bee14 SB |
510 | |
511 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); | |
50586ef2 AF |
512 | |
513 | udelay(10000); | |
514 | ||
f0b5f23f EN |
515 | #ifdef CONFIG_FSL_USDHC |
516 | esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); | |
517 | #else | |
518 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); | |
519 | #endif | |
c67bee14 | 520 | |
50586ef2 AF |
521 | } |
522 | ||
2d9ca2c7 YL |
523 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
524 | static void esdhc_clock_control(struct mmc *mmc, bool enable) | |
525 | { | |
526 | struct fsl_esdhc_cfg *cfg = mmc->priv; | |
527 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; | |
528 | u32 value; | |
529 | u32 time_out; | |
530 | ||
531 | value = esdhc_read32(®s->sysctl); | |
532 | ||
533 | if (enable) | |
534 | value |= SYSCTL_CKEN; | |
535 | else | |
536 | value &= ~SYSCTL_CKEN; | |
537 | ||
538 | esdhc_write32(®s->sysctl, value); | |
539 | ||
540 | time_out = 20; | |
541 | value = PRSSTAT_SDSTB; | |
542 | while (!(esdhc_read32(®s->prsstat) & value)) { | |
543 | if (time_out == 0) { | |
544 | printf("fsl_esdhc: Internal clock never stabilised.\n"); | |
545 | break; | |
546 | } | |
547 | time_out--; | |
548 | mdelay(1); | |
549 | } | |
550 | } | |
551 | #endif | |
552 | ||
50586ef2 AF |
553 | static void esdhc_set_ios(struct mmc *mmc) |
554 | { | |
93bfd616 | 555 | struct fsl_esdhc_cfg *cfg = mmc->priv; |
c67bee14 | 556 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
50586ef2 | 557 | |
2d9ca2c7 YL |
558 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
559 | /* Select to use peripheral clock */ | |
560 | esdhc_clock_control(mmc, false); | |
561 | esdhc_setbits32(®s->scr, ESDHCCTL_PCS); | |
562 | esdhc_clock_control(mmc, true); | |
563 | #endif | |
50586ef2 AF |
564 | /* Set the clock speed */ |
565 | set_sysctl(mmc, mmc->clock); | |
566 | ||
567 | /* Set the bus width */ | |
c67bee14 | 568 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
50586ef2 AF |
569 | |
570 | if (mmc->bus_width == 4) | |
c67bee14 | 571 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
50586ef2 | 572 | else if (mmc->bus_width == 8) |
c67bee14 SB |
573 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
574 | ||
50586ef2 AF |
575 | } |
576 | ||
577 | static int esdhc_init(struct mmc *mmc) | |
578 | { | |
93bfd616 | 579 | struct fsl_esdhc_cfg *cfg = mmc->priv; |
c67bee14 | 580 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
50586ef2 AF |
581 | int timeout = 1000; |
582 | ||
c67bee14 | 583 | /* Reset the entire host controller */ |
a61da72b | 584 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
c67bee14 SB |
585 | |
586 | /* Wait until the controller is available */ | |
587 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) | |
588 | udelay(1000); | |
50586ef2 | 589 | |
16e43f35 | 590 | #ifndef ARCH_MXC |
2c1764ef | 591 | /* Enable cache snooping */ |
16e43f35 BT |
592 | esdhc_write32(®s->scr, 0x00000040); |
593 | #endif | |
2c1764ef | 594 | |
f0b5f23f | 595 | #ifndef CONFIG_FSL_USDHC |
a61da72b | 596 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
f0b5f23f | 597 | #endif |
50586ef2 AF |
598 | |
599 | /* Set the initial clock speed */ | |
4a6ee172 | 600 | mmc_set_clock(mmc, 400000); |
50586ef2 AF |
601 | |
602 | /* Disable the BRR and BWR bits in IRQSTAT */ | |
c67bee14 | 603 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
50586ef2 AF |
604 | |
605 | /* Put the PROCTL reg back to the default */ | |
c67bee14 | 606 | esdhc_write32(®s->proctl, PROCTL_INIT); |
50586ef2 | 607 | |
c67bee14 SB |
608 | /* Set timout to the maximum value */ |
609 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); | |
50586ef2 | 610 | |
ee0c5389 OS |
611 | #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT |
612 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); | |
613 | #endif | |
614 | ||
d48d2e21 TR |
615 | return 0; |
616 | } | |
50586ef2 | 617 | |
d48d2e21 TR |
618 | static int esdhc_getcd(struct mmc *mmc) |
619 | { | |
93bfd616 | 620 | struct fsl_esdhc_cfg *cfg = mmc->priv; |
d48d2e21 TR |
621 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
622 | int timeout = 1000; | |
623 | ||
f7e27cc5 HZ |
624 | #ifdef CONFIG_ESDHC_DETECT_QUIRK |
625 | if (CONFIG_ESDHC_DETECT_QUIRK) | |
626 | return 1; | |
627 | #endif | |
d48d2e21 TR |
628 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) |
629 | udelay(1000); | |
c67bee14 | 630 | |
d48d2e21 | 631 | return timeout > 0; |
50586ef2 AF |
632 | } |
633 | ||
48bb3bb5 JH |
634 | static void esdhc_reset(struct fsl_esdhc *regs) |
635 | { | |
636 | unsigned long timeout = 100; /* wait max 100 ms */ | |
637 | ||
638 | /* reset the controller */ | |
a61da72b | 639 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
48bb3bb5 JH |
640 | |
641 | /* hardware clears the bit when it is done */ | |
642 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) | |
643 | udelay(1000); | |
644 | if (!timeout) | |
645 | printf("MMC/SD: Reset never completed.\n"); | |
646 | } | |
647 | ||
ab769f22 PA |
648 | static const struct mmc_ops esdhc_ops = { |
649 | .send_cmd = esdhc_send_cmd, | |
650 | .set_ios = esdhc_set_ios, | |
651 | .init = esdhc_init, | |
652 | .getcd = esdhc_getcd, | |
653 | }; | |
654 | ||
c67bee14 | 655 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) |
50586ef2 | 656 | { |
c67bee14 | 657 | struct fsl_esdhc *regs; |
50586ef2 | 658 | struct mmc *mmc; |
030955c2 | 659 | u32 caps, voltage_caps; |
50586ef2 | 660 | |
c67bee14 SB |
661 | if (!cfg) |
662 | return -1; | |
663 | ||
c67bee14 SB |
664 | regs = (struct fsl_esdhc *)cfg->esdhc_base; |
665 | ||
48bb3bb5 JH |
666 | /* First reset the eSDHC controller */ |
667 | esdhc_reset(regs); | |
668 | ||
f0b5f23f | 669 | #ifndef CONFIG_FSL_USDHC |
975324a7 JH |
670 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
671 | | SYSCTL_IPGEN | SYSCTL_CKEN); | |
f0b5f23f | 672 | #endif |
975324a7 | 673 | |
a3d6e386 | 674 | writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); |
93bfd616 PA |
675 | memset(&cfg->cfg, 0, sizeof(cfg->cfg)); |
676 | ||
030955c2 | 677 | voltage_caps = 0; |
19060bd8 | 678 | caps = esdhc_read32(®s->hostcapblt); |
3b4456ec RZ |
679 | |
680 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
681 | caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | | |
682 | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); | |
683 | #endif | |
ef38f3ff HZ |
684 | |
685 | /* T4240 host controller capabilities register should have VS33 bit */ | |
686 | #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
687 | caps = caps | ESDHC_HOSTCAPBLT_VS33; | |
688 | #endif | |
689 | ||
50586ef2 | 690 | if (caps & ESDHC_HOSTCAPBLT_VS18) |
030955c2 | 691 | voltage_caps |= MMC_VDD_165_195; |
50586ef2 | 692 | if (caps & ESDHC_HOSTCAPBLT_VS30) |
030955c2 | 693 | voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; |
50586ef2 | 694 | if (caps & ESDHC_HOSTCAPBLT_VS33) |
030955c2 LY |
695 | voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; |
696 | ||
93bfd616 PA |
697 | cfg->cfg.name = "FSL_SDHC"; |
698 | cfg->cfg.ops = &esdhc_ops; | |
030955c2 | 699 | #ifdef CONFIG_SYS_SD_VOLTAGE |
93bfd616 | 700 | cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; |
030955c2 | 701 | #else |
93bfd616 | 702 | cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
030955c2 | 703 | #endif |
93bfd616 | 704 | if ((cfg->cfg.voltages & voltage_caps) == 0) { |
030955c2 LY |
705 | printf("voltage not supported by controller\n"); |
706 | return -1; | |
707 | } | |
50586ef2 | 708 | |
5a20397b | 709 | cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
0e1bf614 VR |
710 | #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE |
711 | cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; | |
712 | #endif | |
50586ef2 | 713 | |
aad4659a AR |
714 | if (cfg->max_bus_width > 0) { |
715 | if (cfg->max_bus_width < 8) | |
93bfd616 | 716 | cfg->cfg.host_caps &= ~MMC_MODE_8BIT; |
aad4659a | 717 | if (cfg->max_bus_width < 4) |
93bfd616 | 718 | cfg->cfg.host_caps &= ~MMC_MODE_4BIT; |
aad4659a AR |
719 | } |
720 | ||
50586ef2 | 721 | if (caps & ESDHC_HOSTCAPBLT_HSS) |
93bfd616 | 722 | cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
50586ef2 | 723 | |
d47e3d27 HZ |
724 | #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK |
725 | if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) | |
93bfd616 | 726 | cfg->cfg.host_caps &= ~MMC_MODE_8BIT; |
d47e3d27 HZ |
727 | #endif |
728 | ||
93bfd616 | 729 | cfg->cfg.f_min = 400000; |
21008ad6 | 730 | cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); |
50586ef2 | 731 | |
93bfd616 PA |
732 | cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
733 | ||
734 | mmc = mmc_create(&cfg->cfg, cfg); | |
735 | if (mmc == NULL) | |
736 | return -1; | |
50586ef2 AF |
737 | |
738 | return 0; | |
739 | } | |
740 | ||
741 | int fsl_esdhc_mmc_init(bd_t *bis) | |
742 | { | |
c67bee14 SB |
743 | struct fsl_esdhc_cfg *cfg; |
744 | ||
88227a1d | 745 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
c67bee14 | 746 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
e9adeca3 | 747 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
c67bee14 | 748 | return fsl_esdhc_initialize(bis, cfg); |
50586ef2 | 749 | } |
b33433a6 | 750 | |
5a8dbdc6 YL |
751 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
752 | void mmc_adapter_card_type_ident(void) | |
753 | { | |
754 | u8 card_id; | |
755 | u8 value; | |
756 | ||
757 | card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; | |
758 | gd->arch.sdhc_adapter = card_id; | |
759 | ||
760 | switch (card_id) { | |
761 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: | |
cdc69550 YL |
762 | value = QIXIS_READ(brdcfg[5]); |
763 | value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); | |
764 | QIXIS_WRITE(brdcfg[5], value); | |
5a8dbdc6 YL |
765 | break; |
766 | case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: | |
bf50be83 YL |
767 | value = QIXIS_READ(pwr_ctl[1]); |
768 | value |= QIXIS_EVDD_BY_SDHC_VS; | |
769 | QIXIS_WRITE(pwr_ctl[1], value); | |
5a8dbdc6 YL |
770 | break; |
771 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: | |
772 | value = QIXIS_READ(brdcfg[5]); | |
773 | value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); | |
774 | QIXIS_WRITE(brdcfg[5], value); | |
775 | break; | |
776 | case QIXIS_ESDHC_ADAPTER_TYPE_RSV: | |
777 | break; | |
778 | case QIXIS_ESDHC_ADAPTER_TYPE_MMC: | |
779 | break; | |
780 | case QIXIS_ESDHC_ADAPTER_TYPE_SD: | |
781 | break; | |
782 | case QIXIS_ESDHC_NO_ADAPTER: | |
783 | break; | |
784 | default: | |
785 | break; | |
786 | } | |
787 | } | |
788 | #endif | |
789 | ||
c67bee14 | 790 | #ifdef CONFIG_OF_LIBFDT |
b33433a6 AV |
791 | void fdt_fixup_esdhc(void *blob, bd_t *bd) |
792 | { | |
793 | const char *compat = "fsl,esdhc"; | |
b33433a6 | 794 | |
a6da8b81 | 795 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
b33433a6 | 796 | if (!hwconfig("esdhc")) { |
a6da8b81 CZ |
797 | do_fixup_by_compat(blob, compat, "status", "disabled", |
798 | 8 + 1, 1); | |
799 | return; | |
b33433a6 | 800 | } |
a6da8b81 | 801 | #endif |
b33433a6 | 802 | |
2d9ca2c7 YL |
803 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
804 | do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", | |
805 | gd->arch.sdhc_clk, 1); | |
806 | #else | |
b33433a6 | 807 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
e9adeca3 | 808 | gd->arch.sdhc_clk, 1); |
2d9ca2c7 | 809 | #endif |
5a8dbdc6 YL |
810 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
811 | do_fixup_by_compat_u32(blob, compat, "adapter-type", | |
812 | (u32)(gd->arch.sdhc_adapter), 1); | |
813 | #endif | |
a6da8b81 CZ |
814 | do_fixup_by_compat(blob, compat, "status", "okay", |
815 | 4 + 1, 1); | |
b33433a6 | 816 | } |
c67bee14 | 817 | #endif |