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50586ef2 | 1 | /* |
d621da00 | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
50586ef2 AF |
3 | * Andy Fleming |
4 | * | |
5 | * Based vaguely on the pxa mmc code: | |
6 | * (C) Copyright 2003 | |
7 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
50586ef2 AF |
10 | */ |
11 | ||
12 | #include <config.h> | |
13 | #include <common.h> | |
14 | #include <command.h> | |
b33433a6 | 15 | #include <hwconfig.h> |
50586ef2 AF |
16 | #include <mmc.h> |
17 | #include <part.h> | |
18 | #include <malloc.h> | |
50586ef2 | 19 | #include <fsl_esdhc.h> |
b33433a6 | 20 | #include <fdt_support.h> |
50586ef2 | 21 | #include <asm/io.h> |
96f0407b PF |
22 | #include <dm.h> |
23 | #include <asm-generic/gpio.h> | |
50586ef2 | 24 | |
50586ef2 AF |
25 | DECLARE_GLOBAL_DATA_PTR; |
26 | ||
a3d6e386 YL |
27 | #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ |
28 | IRQSTATEN_CINT | \ | |
29 | IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ | |
30 | IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ | |
31 | IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ | |
32 | IRQSTATEN_DINT) | |
33 | ||
50586ef2 | 34 | struct fsl_esdhc { |
511948b2 HZ |
35 | uint dsaddr; /* SDMA system address register */ |
36 | uint blkattr; /* Block attributes register */ | |
37 | uint cmdarg; /* Command argument register */ | |
38 | uint xfertyp; /* Transfer type register */ | |
39 | uint cmdrsp0; /* Command response 0 register */ | |
40 | uint cmdrsp1; /* Command response 1 register */ | |
41 | uint cmdrsp2; /* Command response 2 register */ | |
42 | uint cmdrsp3; /* Command response 3 register */ | |
43 | uint datport; /* Buffer data port register */ | |
44 | uint prsstat; /* Present state register */ | |
45 | uint proctl; /* Protocol control register */ | |
46 | uint sysctl; /* System Control Register */ | |
47 | uint irqstat; /* Interrupt status register */ | |
48 | uint irqstaten; /* Interrupt status enable register */ | |
49 | uint irqsigen; /* Interrupt signal enable register */ | |
50 | uint autoc12err; /* Auto CMD error status register */ | |
51 | uint hostcapblt; /* Host controller capabilities register */ | |
52 | uint wml; /* Watermark level register */ | |
53 | uint mixctrl; /* For USDHC */ | |
54 | char reserved1[4]; /* reserved */ | |
55 | uint fevt; /* Force event register */ | |
56 | uint admaes; /* ADMA error status register */ | |
57 | uint adsaddr; /* ADMA system address register */ | |
f53225cc PF |
58 | char reserved2[4]; |
59 | uint dllctrl; | |
60 | uint dllstat; | |
61 | uint clktunectrlstatus; | |
62 | char reserved3[84]; | |
63 | uint vendorspec; | |
64 | uint mmcboot; | |
65 | uint vendorspec2; | |
66 | char reserved4[48]; | |
511948b2 | 67 | uint hostver; /* Host controller version register */ |
511948b2 | 68 | char reserved5[4]; /* reserved */ |
f53225cc | 69 | uint dmaerraddr; /* DMA error address register */ |
f022d36e | 70 | char reserved6[4]; /* reserved */ |
f53225cc PF |
71 | uint dmaerrattr; /* DMA error attribute register */ |
72 | char reserved7[4]; /* reserved */ | |
511948b2 | 73 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
f53225cc | 74 | char reserved8[8]; /* reserved */ |
511948b2 | 75 | uint tcr; /* Tuning control register */ |
f53225cc | 76 | char reserved9[28]; /* reserved */ |
511948b2 | 77 | uint sddirctl; /* SD direction control register */ |
f53225cc | 78 | char reserved10[712];/* reserved */ |
511948b2 | 79 | uint scr; /* eSDHC control register */ |
50586ef2 AF |
80 | }; |
81 | ||
96f0407b PF |
82 | /** |
83 | * struct fsl_esdhc_priv | |
84 | * | |
85 | * @esdhc_regs: registers of the sdhc controller | |
86 | * @sdhc_clk: Current clk of the sdhc controller | |
87 | * @bus_width: bus width, 1bit, 4bit or 8bit | |
88 | * @cfg: mmc config | |
89 | * @mmc: mmc | |
90 | * Following is used when Driver Model is enabled for MMC | |
91 | * @dev: pointer for the device | |
92 | * @non_removable: 0: removable; 1: non-removable | |
1483151e | 93 | * @wp_enable: 1: enable checking wp; 0: no check |
96f0407b | 94 | * @cd_gpio: gpio for card detection |
1483151e | 95 | * @wp_gpio: gpio for write protection |
96f0407b PF |
96 | */ |
97 | struct fsl_esdhc_priv { | |
98 | struct fsl_esdhc *esdhc_regs; | |
99 | unsigned int sdhc_clk; | |
100 | unsigned int bus_width; | |
101 | struct mmc_config cfg; | |
102 | struct mmc *mmc; | |
103 | struct udevice *dev; | |
104 | int non_removable; | |
1483151e | 105 | int wp_enable; |
96f0407b | 106 | struct gpio_desc cd_gpio; |
1483151e | 107 | struct gpio_desc wp_gpio; |
96f0407b PF |
108 | }; |
109 | ||
50586ef2 | 110 | /* Return the XFERTYP flags for a given command and data packet */ |
eafa90a1 | 111 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
50586ef2 AF |
112 | { |
113 | uint xfertyp = 0; | |
114 | ||
115 | if (data) { | |
77c1458d DD |
116 | xfertyp |= XFERTYP_DPSEL; |
117 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO | |
118 | xfertyp |= XFERTYP_DMAEN; | |
119 | #endif | |
50586ef2 AF |
120 | if (data->blocks > 1) { |
121 | xfertyp |= XFERTYP_MSBSEL; | |
122 | xfertyp |= XFERTYP_BCEN; | |
d621da00 JH |
123 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
124 | xfertyp |= XFERTYP_AC12EN; | |
125 | #endif | |
50586ef2 AF |
126 | } |
127 | ||
128 | if (data->flags & MMC_DATA_READ) | |
129 | xfertyp |= XFERTYP_DTDSEL; | |
130 | } | |
131 | ||
132 | if (cmd->resp_type & MMC_RSP_CRC) | |
133 | xfertyp |= XFERTYP_CCCEN; | |
134 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
135 | xfertyp |= XFERTYP_CICEN; | |
136 | if (cmd->resp_type & MMC_RSP_136) | |
137 | xfertyp |= XFERTYP_RSPTYP_136; | |
138 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
139 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; | |
140 | else if (cmd->resp_type & MMC_RSP_PRESENT) | |
141 | xfertyp |= XFERTYP_RSPTYP_48; | |
142 | ||
4571de33 JL |
143 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
144 | xfertyp |= XFERTYP_CMDTYP_ABORT; | |
25503443 | 145 | |
50586ef2 AF |
146 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
147 | } | |
148 | ||
77c1458d DD |
149 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
150 | /* | |
151 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. | |
152 | */ | |
7b43db92 | 153 | static void |
77c1458d DD |
154 | esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) |
155 | { | |
96f0407b PF |
156 | struct fsl_esdhc_priv *priv = mmc->priv; |
157 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
77c1458d DD |
158 | uint blocks; |
159 | char *buffer; | |
160 | uint databuf; | |
161 | uint size; | |
162 | uint irqstat; | |
163 | uint timeout; | |
164 | ||
165 | if (data->flags & MMC_DATA_READ) { | |
166 | blocks = data->blocks; | |
167 | buffer = data->dest; | |
168 | while (blocks) { | |
169 | timeout = PIO_TIMEOUT; | |
170 | size = data->blocksize; | |
171 | irqstat = esdhc_read32(®s->irqstat); | |
172 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) | |
173 | && --timeout); | |
174 | if (timeout <= 0) { | |
175 | printf("\nData Read Failed in PIO Mode."); | |
7b43db92 | 176 | return; |
77c1458d DD |
177 | } |
178 | while (size && (!(irqstat & IRQSTAT_TC))) { | |
179 | udelay(100); /* Wait before last byte transfer complete */ | |
180 | irqstat = esdhc_read32(®s->irqstat); | |
181 | databuf = in_le32(®s->datport); | |
182 | *((uint *)buffer) = databuf; | |
183 | buffer += 4; | |
184 | size -= 4; | |
185 | } | |
186 | blocks--; | |
187 | } | |
188 | } else { | |
189 | blocks = data->blocks; | |
7b43db92 | 190 | buffer = (char *)data->src; |
77c1458d DD |
191 | while (blocks) { |
192 | timeout = PIO_TIMEOUT; | |
193 | size = data->blocksize; | |
194 | irqstat = esdhc_read32(®s->irqstat); | |
195 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) | |
196 | && --timeout); | |
197 | if (timeout <= 0) { | |
198 | printf("\nData Write Failed in PIO Mode."); | |
7b43db92 | 199 | return; |
77c1458d DD |
200 | } |
201 | while (size && (!(irqstat & IRQSTAT_TC))) { | |
202 | udelay(100); /* Wait before last byte transfer complete */ | |
203 | databuf = *((uint *)buffer); | |
204 | buffer += 4; | |
205 | size -= 4; | |
206 | irqstat = esdhc_read32(®s->irqstat); | |
207 | out_le32(®s->datport, databuf); | |
208 | } | |
209 | blocks--; | |
210 | } | |
211 | } | |
212 | } | |
213 | #endif | |
214 | ||
50586ef2 AF |
215 | static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) |
216 | { | |
50586ef2 | 217 | int timeout; |
96f0407b PF |
218 | struct fsl_esdhc_priv *priv = mmc->priv; |
219 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
9702ec00 | 220 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
8b06460e YL |
221 | dma_addr_t addr; |
222 | #endif | |
7b43db92 | 223 | uint wml_value; |
50586ef2 AF |
224 | |
225 | wml_value = data->blocksize/4; | |
226 | ||
227 | if (data->flags & MMC_DATA_READ) { | |
32c8cfb2 PJ |
228 | if (wml_value > WML_RD_WML_MAX) |
229 | wml_value = WML_RD_WML_MAX_VAL; | |
50586ef2 | 230 | |
ab467c51 | 231 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
71689776 | 232 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
9702ec00 | 233 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
8b06460e YL |
234 | addr = virt_to_phys((void *)(data->dest)); |
235 | if (upper_32_bits(addr)) | |
236 | printf("Error found for upper 32 bits\n"); | |
237 | else | |
238 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); | |
239 | #else | |
c67bee14 | 240 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
8b06460e | 241 | #endif |
71689776 | 242 | #endif |
50586ef2 | 243 | } else { |
71689776 | 244 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
e576bd90 EN |
245 | flush_dcache_range((ulong)data->src, |
246 | (ulong)data->src+data->blocks | |
247 | *data->blocksize); | |
71689776 | 248 | #endif |
32c8cfb2 PJ |
249 | if (wml_value > WML_WR_WML_MAX) |
250 | wml_value = WML_WR_WML_MAX_VAL; | |
1483151e PF |
251 | if (priv->wp_enable) { |
252 | if ((esdhc_read32(®s->prsstat) & | |
253 | PRSSTAT_WPSPL) == 0) { | |
254 | printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); | |
255 | return TIMEOUT; | |
256 | } | |
50586ef2 | 257 | } |
ab467c51 RZ |
258 | |
259 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, | |
260 | wml_value << 16); | |
71689776 | 261 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
9702ec00 | 262 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
8b06460e YL |
263 | addr = virt_to_phys((void *)(data->src)); |
264 | if (upper_32_bits(addr)) | |
265 | printf("Error found for upper 32 bits\n"); | |
266 | else | |
267 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); | |
268 | #else | |
c67bee14 | 269 | esdhc_write32(®s->dsaddr, (u32)data->src); |
8b06460e | 270 | #endif |
71689776 | 271 | #endif |
50586ef2 AF |
272 | } |
273 | ||
c67bee14 | 274 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
50586ef2 AF |
275 | |
276 | /* Calculate the timeout period for data transactions */ | |
b71ea336 PJ |
277 | /* |
278 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles | |
279 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec | |
280 | * So, Number of SD Clock cycles for 0.25sec should be minimum | |
281 | * (SD Clock/sec * 0.25 sec) SD Clock cycles | |
fb823981 | 282 | * = (mmc->clock * 1/4) SD Clock cycles |
b71ea336 | 283 | * As 1) >= 2) |
fb823981 | 284 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
b71ea336 | 285 | * Taking log2 both the sides |
fb823981 | 286 | * => timeout + 13 >= log2(mmc->clock/4) |
b71ea336 | 287 | * Rounding up to next power of 2 |
fb823981 AG |
288 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
289 | * => timeout + 13 = fls(mmc->clock/4) | |
e978a31b YL |
290 | * |
291 | * However, the MMC spec "It is strongly recommended for hosts to | |
292 | * implement more than 500ms timeout value even if the card | |
293 | * indicates the 250ms maximum busy length." Even the previous | |
294 | * value of 300ms is known to be insufficient for some cards. | |
295 | * So, we use | |
296 | * => timeout + 13 = fls(mmc->clock/2) | |
b71ea336 | 297 | */ |
e978a31b | 298 | timeout = fls(mmc->clock/2); |
50586ef2 AF |
299 | timeout -= 13; |
300 | ||
301 | if (timeout > 14) | |
302 | timeout = 14; | |
303 | ||
304 | if (timeout < 0) | |
305 | timeout = 0; | |
306 | ||
5103a03a KG |
307 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
308 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) | |
309 | timeout++; | |
310 | #endif | |
311 | ||
1336e2d3 HZ |
312 | #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
313 | timeout = 0xE; | |
314 | #endif | |
c67bee14 | 315 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
50586ef2 AF |
316 | |
317 | return 0; | |
318 | } | |
319 | ||
e576bd90 EN |
320 | static void check_and_invalidate_dcache_range |
321 | (struct mmc_cmd *cmd, | |
322 | struct mmc_data *data) { | |
8b06460e | 323 | unsigned start = 0; |
cc634e28 | 324 | unsigned end = 0; |
e576bd90 EN |
325 | unsigned size = roundup(ARCH_DMA_MINALIGN, |
326 | data->blocks*data->blocksize); | |
9702ec00 | 327 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
8b06460e YL |
328 | dma_addr_t addr; |
329 | ||
330 | addr = virt_to_phys((void *)(data->dest)); | |
331 | if (upper_32_bits(addr)) | |
332 | printf("Error found for upper 32 bits\n"); | |
333 | else | |
334 | start = lower_32_bits(addr); | |
cc634e28 YL |
335 | #else |
336 | start = (unsigned)data->dest; | |
8b06460e | 337 | #endif |
cc634e28 | 338 | end = start + size; |
e576bd90 EN |
339 | invalidate_dcache_range(start, end); |
340 | } | |
10dc7771 | 341 | |
50586ef2 AF |
342 | /* |
343 | * Sends a command out on the bus. Takes the mmc pointer, | |
344 | * a command pointer, and an optional data pointer. | |
345 | */ | |
346 | static int | |
347 | esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) | |
348 | { | |
8a573022 | 349 | int err = 0; |
50586ef2 AF |
350 | uint xfertyp; |
351 | uint irqstat; | |
96f0407b PF |
352 | struct fsl_esdhc_priv *priv = mmc->priv; |
353 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
50586ef2 | 354 | |
d621da00 JH |
355 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
356 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) | |
357 | return 0; | |
358 | #endif | |
359 | ||
c67bee14 | 360 | esdhc_write32(®s->irqstat, -1); |
50586ef2 AF |
361 | |
362 | sync(); | |
363 | ||
364 | /* Wait for the bus to be idle */ | |
c67bee14 SB |
365 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
366 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) | |
367 | ; | |
50586ef2 | 368 | |
c67bee14 SB |
369 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
370 | ; | |
50586ef2 AF |
371 | |
372 | /* Wait at least 8 SD clock cycles before the next command */ | |
373 | /* | |
374 | * Note: This is way more than 8 cycles, but 1ms seems to | |
375 | * resolve timing issues with some cards | |
376 | */ | |
377 | udelay(1000); | |
378 | ||
379 | /* Set up for a data transfer if we have one */ | |
380 | if (data) { | |
50586ef2 AF |
381 | err = esdhc_setup_data(mmc, data); |
382 | if(err) | |
383 | return err; | |
4683b220 PF |
384 | |
385 | if (data->flags & MMC_DATA_READ) | |
386 | check_and_invalidate_dcache_range(cmd, data); | |
50586ef2 AF |
387 | } |
388 | ||
389 | /* Figure out the transfer arguments */ | |
390 | xfertyp = esdhc_xfertyp(cmd, data); | |
391 | ||
01b77353 AG |
392 | /* Mask all irqs */ |
393 | esdhc_write32(®s->irqsigen, 0); | |
394 | ||
50586ef2 | 395 | /* Send the command */ |
c67bee14 | 396 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
4692708d JL |
397 | #if defined(CONFIG_FSL_USDHC) |
398 | esdhc_write32(®s->mixctrl, | |
0e1bf614 VR |
399 | (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) |
400 | | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); | |
4692708d JL |
401 | esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); |
402 | #else | |
c67bee14 | 403 | esdhc_write32(®s->xfertyp, xfertyp); |
4692708d | 404 | #endif |
7a5b8029 | 405 | |
50586ef2 | 406 | /* Wait for the command to complete */ |
7a5b8029 | 407 | while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) |
c67bee14 | 408 | ; |
50586ef2 | 409 | |
c67bee14 | 410 | irqstat = esdhc_read32(®s->irqstat); |
50586ef2 | 411 | |
8a573022 AG |
412 | if (irqstat & CMD_ERR) { |
413 | err = COMM_ERR; | |
414 | goto out; | |
7a5b8029 DB |
415 | } |
416 | ||
8a573022 AG |
417 | if (irqstat & IRQSTAT_CTOE) { |
418 | err = TIMEOUT; | |
419 | goto out; | |
420 | } | |
50586ef2 | 421 | |
f022d36e OS |
422 | /* Switch voltage to 1.8V if CMD11 succeeded */ |
423 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { | |
424 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); | |
425 | ||
426 | printf("Run CMD11 1.8V switch\n"); | |
427 | /* Sleep for 5 ms - max time for card to switch to 1.8V */ | |
428 | udelay(5000); | |
429 | } | |
430 | ||
7a5b8029 DB |
431 | /* Workaround for ESDHC errata ENGcm03648 */ |
432 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { | |
253d5bdd | 433 | int timeout = 6000; |
7a5b8029 | 434 | |
253d5bdd | 435 | /* Poll on DATA0 line for cmd with busy signal for 600 ms */ |
7a5b8029 DB |
436 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
437 | PRSSTAT_DAT0)) { | |
438 | udelay(100); | |
439 | timeout--; | |
440 | } | |
441 | ||
442 | if (timeout <= 0) { | |
443 | printf("Timeout waiting for DAT0 to go high!\n"); | |
8a573022 AG |
444 | err = TIMEOUT; |
445 | goto out; | |
7a5b8029 DB |
446 | } |
447 | } | |
448 | ||
50586ef2 AF |
449 | /* Copy the response to the response buffer */ |
450 | if (cmd->resp_type & MMC_RSP_136) { | |
451 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; | |
452 | ||
c67bee14 SB |
453 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
454 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); | |
455 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); | |
456 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); | |
998be3dd RV |
457 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
458 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); | |
459 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); | |
460 | cmd->response[3] = (cmdrsp0 << 8); | |
50586ef2 | 461 | } else |
c67bee14 | 462 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
50586ef2 AF |
463 | |
464 | /* Wait until all of the blocks are transferred */ | |
465 | if (data) { | |
77c1458d DD |
466 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
467 | esdhc_pio_read_write(mmc, data); | |
468 | #else | |
50586ef2 | 469 | do { |
c67bee14 | 470 | irqstat = esdhc_read32(®s->irqstat); |
50586ef2 | 471 | |
8a573022 AG |
472 | if (irqstat & IRQSTAT_DTOE) { |
473 | err = TIMEOUT; | |
474 | goto out; | |
475 | } | |
63fb5a7e | 476 | |
8a573022 AG |
477 | if (irqstat & DATA_ERR) { |
478 | err = COMM_ERR; | |
479 | goto out; | |
480 | } | |
9b74dc56 | 481 | } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); |
71689776 | 482 | |
4683b220 PF |
483 | /* |
484 | * Need invalidate the dcache here again to avoid any | |
485 | * cache-fill during the DMA operations such as the | |
486 | * speculative pre-fetching etc. | |
487 | */ | |
54899fc8 EN |
488 | if (data->flags & MMC_DATA_READ) |
489 | check_and_invalidate_dcache_range(cmd, data); | |
71689776 | 490 | #endif |
50586ef2 AF |
491 | } |
492 | ||
8a573022 AG |
493 | out: |
494 | /* Reset CMD and DATA portions on error */ | |
495 | if (err) { | |
496 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | | |
497 | SYSCTL_RSTC); | |
498 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) | |
499 | ; | |
500 | ||
501 | if (data) { | |
502 | esdhc_write32(®s->sysctl, | |
503 | esdhc_read32(®s->sysctl) | | |
504 | SYSCTL_RSTD); | |
505 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) | |
506 | ; | |
507 | } | |
f022d36e OS |
508 | |
509 | /* If this was CMD11, then notify that power cycle is needed */ | |
510 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) | |
511 | printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); | |
8a573022 AG |
512 | } |
513 | ||
c67bee14 | 514 | esdhc_write32(®s->irqstat, -1); |
50586ef2 | 515 | |
8a573022 | 516 | return err; |
50586ef2 AF |
517 | } |
518 | ||
eafa90a1 | 519 | static void set_sysctl(struct mmc *mmc, uint clock) |
50586ef2 | 520 | { |
50586ef2 | 521 | int div, pre_div; |
96f0407b PF |
522 | struct fsl_esdhc_priv *priv = mmc->priv; |
523 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
524 | int sdhc_clk = priv->sdhc_clk; | |
50586ef2 AF |
525 | uint clk; |
526 | ||
93bfd616 PA |
527 | if (clock < mmc->cfg->f_min) |
528 | clock = mmc->cfg->f_min; | |
c67bee14 | 529 | |
50586ef2 AF |
530 | if (sdhc_clk / 16 > clock) { |
531 | for (pre_div = 2; pre_div < 256; pre_div *= 2) | |
532 | if ((sdhc_clk / pre_div) <= (clock * 16)) | |
533 | break; | |
534 | } else | |
535 | pre_div = 2; | |
536 | ||
537 | for (div = 1; div <= 16; div++) | |
538 | if ((sdhc_clk / (div * pre_div)) <= clock) | |
539 | break; | |
540 | ||
0e1bf614 | 541 | pre_div >>= mmc->ddr_mode ? 2 : 1; |
50586ef2 AF |
542 | div -= 1; |
543 | ||
544 | clk = (pre_div << 8) | (div << 4); | |
545 | ||
f0b5f23f | 546 | #ifdef CONFIG_FSL_USDHC |
84ecdf6d | 547 | esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); |
f0b5f23f | 548 | #else |
cc4d1226 | 549 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
f0b5f23f | 550 | #endif |
c67bee14 SB |
551 | |
552 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); | |
50586ef2 AF |
553 | |
554 | udelay(10000); | |
555 | ||
f0b5f23f | 556 | #ifdef CONFIG_FSL_USDHC |
84ecdf6d | 557 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); |
f0b5f23f EN |
558 | #else |
559 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); | |
560 | #endif | |
c67bee14 | 561 | |
50586ef2 AF |
562 | } |
563 | ||
2d9ca2c7 YL |
564 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
565 | static void esdhc_clock_control(struct mmc *mmc, bool enable) | |
566 | { | |
96f0407b PF |
567 | struct fsl_esdhc_priv *priv = mmc->priv; |
568 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
2d9ca2c7 YL |
569 | u32 value; |
570 | u32 time_out; | |
571 | ||
572 | value = esdhc_read32(®s->sysctl); | |
573 | ||
574 | if (enable) | |
575 | value |= SYSCTL_CKEN; | |
576 | else | |
577 | value &= ~SYSCTL_CKEN; | |
578 | ||
579 | esdhc_write32(®s->sysctl, value); | |
580 | ||
581 | time_out = 20; | |
582 | value = PRSSTAT_SDSTB; | |
583 | while (!(esdhc_read32(®s->prsstat) & value)) { | |
584 | if (time_out == 0) { | |
585 | printf("fsl_esdhc: Internal clock never stabilised.\n"); | |
586 | break; | |
587 | } | |
588 | time_out--; | |
589 | mdelay(1); | |
590 | } | |
591 | } | |
592 | #endif | |
593 | ||
50586ef2 AF |
594 | static void esdhc_set_ios(struct mmc *mmc) |
595 | { | |
96f0407b PF |
596 | struct fsl_esdhc_priv *priv = mmc->priv; |
597 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
50586ef2 | 598 | |
2d9ca2c7 YL |
599 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
600 | /* Select to use peripheral clock */ | |
601 | esdhc_clock_control(mmc, false); | |
602 | esdhc_setbits32(®s->scr, ESDHCCTL_PCS); | |
603 | esdhc_clock_control(mmc, true); | |
604 | #endif | |
50586ef2 AF |
605 | /* Set the clock speed */ |
606 | set_sysctl(mmc, mmc->clock); | |
607 | ||
608 | /* Set the bus width */ | |
c67bee14 | 609 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
50586ef2 AF |
610 | |
611 | if (mmc->bus_width == 4) | |
c67bee14 | 612 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
50586ef2 | 613 | else if (mmc->bus_width == 8) |
c67bee14 SB |
614 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
615 | ||
50586ef2 AF |
616 | } |
617 | ||
618 | static int esdhc_init(struct mmc *mmc) | |
619 | { | |
96f0407b PF |
620 | struct fsl_esdhc_priv *priv = mmc->priv; |
621 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
50586ef2 AF |
622 | int timeout = 1000; |
623 | ||
c67bee14 | 624 | /* Reset the entire host controller */ |
a61da72b | 625 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
c67bee14 SB |
626 | |
627 | /* Wait until the controller is available */ | |
628 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) | |
629 | udelay(1000); | |
50586ef2 | 630 | |
f53225cc PF |
631 | #if defined(CONFIG_FSL_USDHC) |
632 | /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ | |
633 | esdhc_write32(®s->mmcboot, 0x0); | |
634 | /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ | |
635 | esdhc_write32(®s->mixctrl, 0x0); | |
636 | esdhc_write32(®s->clktunectrlstatus, 0x0); | |
637 | ||
638 | /* Put VEND_SPEC to default value */ | |
639 | esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); | |
640 | ||
641 | /* Disable DLL_CTRL delay line */ | |
642 | esdhc_write32(®s->dllctrl, 0x0); | |
643 | #endif | |
644 | ||
16e43f35 | 645 | #ifndef ARCH_MXC |
2c1764ef | 646 | /* Enable cache snooping */ |
16e43f35 BT |
647 | esdhc_write32(®s->scr, 0x00000040); |
648 | #endif | |
2c1764ef | 649 | |
f0b5f23f | 650 | #ifndef CONFIG_FSL_USDHC |
a61da72b | 651 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
84ecdf6d YL |
652 | #else |
653 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); | |
f0b5f23f | 654 | #endif |
50586ef2 AF |
655 | |
656 | /* Set the initial clock speed */ | |
4a6ee172 | 657 | mmc_set_clock(mmc, 400000); |
50586ef2 AF |
658 | |
659 | /* Disable the BRR and BWR bits in IRQSTAT */ | |
c67bee14 | 660 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
50586ef2 AF |
661 | |
662 | /* Put the PROCTL reg back to the default */ | |
c67bee14 | 663 | esdhc_write32(®s->proctl, PROCTL_INIT); |
50586ef2 | 664 | |
c67bee14 SB |
665 | /* Set timout to the maximum value */ |
666 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); | |
50586ef2 | 667 | |
ee0c5389 OS |
668 | #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT |
669 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); | |
670 | #endif | |
671 | ||
d48d2e21 TR |
672 | return 0; |
673 | } | |
50586ef2 | 674 | |
d48d2e21 TR |
675 | static int esdhc_getcd(struct mmc *mmc) |
676 | { | |
96f0407b PF |
677 | struct fsl_esdhc_priv *priv = mmc->priv; |
678 | struct fsl_esdhc *regs = priv->esdhc_regs; | |
d48d2e21 TR |
679 | int timeout = 1000; |
680 | ||
f7e27cc5 HZ |
681 | #ifdef CONFIG_ESDHC_DETECT_QUIRK |
682 | if (CONFIG_ESDHC_DETECT_QUIRK) | |
683 | return 1; | |
684 | #endif | |
96f0407b PF |
685 | |
686 | #ifdef CONFIG_DM_MMC | |
687 | if (priv->non_removable) | |
688 | return 1; | |
689 | ||
690 | if (dm_gpio_is_valid(&priv->cd_gpio)) | |
691 | return dm_gpio_get_value(&priv->cd_gpio); | |
692 | #endif | |
693 | ||
d48d2e21 TR |
694 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) |
695 | udelay(1000); | |
c67bee14 | 696 | |
d48d2e21 | 697 | return timeout > 0; |
50586ef2 AF |
698 | } |
699 | ||
48bb3bb5 JH |
700 | static void esdhc_reset(struct fsl_esdhc *regs) |
701 | { | |
702 | unsigned long timeout = 100; /* wait max 100 ms */ | |
703 | ||
704 | /* reset the controller */ | |
a61da72b | 705 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
48bb3bb5 JH |
706 | |
707 | /* hardware clears the bit when it is done */ | |
708 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) | |
709 | udelay(1000); | |
710 | if (!timeout) | |
711 | printf("MMC/SD: Reset never completed.\n"); | |
712 | } | |
713 | ||
ab769f22 PA |
714 | static const struct mmc_ops esdhc_ops = { |
715 | .send_cmd = esdhc_send_cmd, | |
716 | .set_ios = esdhc_set_ios, | |
717 | .init = esdhc_init, | |
718 | .getcd = esdhc_getcd, | |
719 | }; | |
720 | ||
96f0407b PF |
721 | static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, |
722 | struct fsl_esdhc_priv *priv) | |
723 | { | |
724 | if (!cfg || !priv) | |
725 | return -EINVAL; | |
726 | ||
727 | priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); | |
728 | priv->bus_width = cfg->max_bus_width; | |
729 | priv->sdhc_clk = cfg->sdhc_clk; | |
1483151e | 730 | priv->wp_enable = cfg->wp_enable; |
96f0407b PF |
731 | |
732 | return 0; | |
733 | }; | |
734 | ||
735 | static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) | |
50586ef2 | 736 | { |
c67bee14 | 737 | struct fsl_esdhc *regs; |
50586ef2 | 738 | struct mmc *mmc; |
030955c2 | 739 | u32 caps, voltage_caps; |
50586ef2 | 740 | |
96f0407b PF |
741 | if (!priv) |
742 | return -EINVAL; | |
c67bee14 | 743 | |
96f0407b | 744 | regs = priv->esdhc_regs; |
c67bee14 | 745 | |
48bb3bb5 JH |
746 | /* First reset the eSDHC controller */ |
747 | esdhc_reset(regs); | |
748 | ||
f0b5f23f | 749 | #ifndef CONFIG_FSL_USDHC |
975324a7 JH |
750 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
751 | | SYSCTL_IPGEN | SYSCTL_CKEN); | |
84ecdf6d YL |
752 | #else |
753 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | | |
754 | VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); | |
f0b5f23f | 755 | #endif |
975324a7 | 756 | |
a3d6e386 | 757 | writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); |
96f0407b | 758 | memset(&priv->cfg, 0, sizeof(priv->cfg)); |
93bfd616 | 759 | |
030955c2 | 760 | voltage_caps = 0; |
19060bd8 | 761 | caps = esdhc_read32(®s->hostcapblt); |
3b4456ec RZ |
762 | |
763 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
764 | caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | | |
765 | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); | |
766 | #endif | |
ef38f3ff HZ |
767 | |
768 | /* T4240 host controller capabilities register should have VS33 bit */ | |
769 | #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
770 | caps = caps | ESDHC_HOSTCAPBLT_VS33; | |
771 | #endif | |
772 | ||
50586ef2 | 773 | if (caps & ESDHC_HOSTCAPBLT_VS18) |
030955c2 | 774 | voltage_caps |= MMC_VDD_165_195; |
50586ef2 | 775 | if (caps & ESDHC_HOSTCAPBLT_VS30) |
030955c2 | 776 | voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; |
50586ef2 | 777 | if (caps & ESDHC_HOSTCAPBLT_VS33) |
030955c2 LY |
778 | voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; |
779 | ||
96f0407b PF |
780 | priv->cfg.name = "FSL_SDHC"; |
781 | priv->cfg.ops = &esdhc_ops; | |
030955c2 | 782 | #ifdef CONFIG_SYS_SD_VOLTAGE |
96f0407b | 783 | priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; |
030955c2 | 784 | #else |
96f0407b | 785 | priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
030955c2 | 786 | #endif |
96f0407b | 787 | if ((priv->cfg.voltages & voltage_caps) == 0) { |
030955c2 LY |
788 | printf("voltage not supported by controller\n"); |
789 | return -1; | |
790 | } | |
50586ef2 | 791 | |
96f0407b PF |
792 | if (priv->bus_width == 8) |
793 | priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; | |
794 | else if (priv->bus_width == 4) | |
795 | priv->cfg.host_caps = MMC_MODE_4BIT; | |
796 | ||
797 | priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; | |
0e1bf614 | 798 | #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE |
96f0407b | 799 | priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; |
0e1bf614 | 800 | #endif |
50586ef2 | 801 | |
96f0407b PF |
802 | if (priv->bus_width > 0) { |
803 | if (priv->bus_width < 8) | |
804 | priv->cfg.host_caps &= ~MMC_MODE_8BIT; | |
805 | if (priv->bus_width < 4) | |
806 | priv->cfg.host_caps &= ~MMC_MODE_4BIT; | |
aad4659a AR |
807 | } |
808 | ||
50586ef2 | 809 | if (caps & ESDHC_HOSTCAPBLT_HSS) |
96f0407b | 810 | priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
50586ef2 | 811 | |
d47e3d27 HZ |
812 | #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK |
813 | if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) | |
96f0407b | 814 | priv->cfg.host_caps &= ~MMC_MODE_8BIT; |
d47e3d27 HZ |
815 | #endif |
816 | ||
96f0407b PF |
817 | priv->cfg.f_min = 400000; |
818 | priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); | |
50586ef2 | 819 | |
96f0407b | 820 | priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
93bfd616 | 821 | |
96f0407b | 822 | mmc = mmc_create(&priv->cfg, priv); |
93bfd616 PA |
823 | if (mmc == NULL) |
824 | return -1; | |
50586ef2 | 825 | |
96f0407b PF |
826 | priv->mmc = mmc; |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
831 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) | |
832 | { | |
833 | struct fsl_esdhc_priv *priv; | |
834 | int ret; | |
835 | ||
836 | if (!cfg) | |
837 | return -EINVAL; | |
838 | ||
839 | priv = calloc(sizeof(struct fsl_esdhc_priv), 1); | |
840 | if (!priv) | |
841 | return -ENOMEM; | |
842 | ||
843 | ret = fsl_esdhc_cfg_to_priv(cfg, priv); | |
844 | if (ret) { | |
845 | debug("%s xlate failure\n", __func__); | |
846 | free(priv); | |
847 | return ret; | |
848 | } | |
849 | ||
850 | ret = fsl_esdhc_init(priv); | |
851 | if (ret) { | |
852 | debug("%s init failure\n", __func__); | |
853 | free(priv); | |
854 | return ret; | |
855 | } | |
856 | ||
50586ef2 AF |
857 | return 0; |
858 | } | |
859 | ||
860 | int fsl_esdhc_mmc_init(bd_t *bis) | |
861 | { | |
c67bee14 SB |
862 | struct fsl_esdhc_cfg *cfg; |
863 | ||
88227a1d | 864 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
c67bee14 | 865 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
e9adeca3 | 866 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
c67bee14 | 867 | return fsl_esdhc_initialize(bis, cfg); |
50586ef2 | 868 | } |
b33433a6 | 869 | |
5a8dbdc6 YL |
870 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
871 | void mmc_adapter_card_type_ident(void) | |
872 | { | |
873 | u8 card_id; | |
874 | u8 value; | |
875 | ||
876 | card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; | |
877 | gd->arch.sdhc_adapter = card_id; | |
878 | ||
879 | switch (card_id) { | |
880 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: | |
cdc69550 YL |
881 | value = QIXIS_READ(brdcfg[5]); |
882 | value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); | |
883 | QIXIS_WRITE(brdcfg[5], value); | |
5a8dbdc6 YL |
884 | break; |
885 | case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: | |
bf50be83 YL |
886 | value = QIXIS_READ(pwr_ctl[1]); |
887 | value |= QIXIS_EVDD_BY_SDHC_VS; | |
888 | QIXIS_WRITE(pwr_ctl[1], value); | |
5a8dbdc6 YL |
889 | break; |
890 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: | |
891 | value = QIXIS_READ(brdcfg[5]); | |
892 | value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); | |
893 | QIXIS_WRITE(brdcfg[5], value); | |
894 | break; | |
895 | case QIXIS_ESDHC_ADAPTER_TYPE_RSV: | |
896 | break; | |
897 | case QIXIS_ESDHC_ADAPTER_TYPE_MMC: | |
898 | break; | |
899 | case QIXIS_ESDHC_ADAPTER_TYPE_SD: | |
900 | break; | |
901 | case QIXIS_ESDHC_NO_ADAPTER: | |
902 | break; | |
903 | default: | |
904 | break; | |
905 | } | |
906 | } | |
907 | #endif | |
908 | ||
c67bee14 | 909 | #ifdef CONFIG_OF_LIBFDT |
b33433a6 AV |
910 | void fdt_fixup_esdhc(void *blob, bd_t *bd) |
911 | { | |
912 | const char *compat = "fsl,esdhc"; | |
b33433a6 | 913 | |
a6da8b81 | 914 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
b33433a6 | 915 | if (!hwconfig("esdhc")) { |
a6da8b81 CZ |
916 | do_fixup_by_compat(blob, compat, "status", "disabled", |
917 | 8 + 1, 1); | |
918 | return; | |
b33433a6 | 919 | } |
a6da8b81 | 920 | #endif |
b33433a6 | 921 | |
2d9ca2c7 YL |
922 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
923 | do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", | |
924 | gd->arch.sdhc_clk, 1); | |
925 | #else | |
b33433a6 | 926 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
e9adeca3 | 927 | gd->arch.sdhc_clk, 1); |
2d9ca2c7 | 928 | #endif |
5a8dbdc6 YL |
929 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
930 | do_fixup_by_compat_u32(blob, compat, "adapter-type", | |
931 | (u32)(gd->arch.sdhc_adapter), 1); | |
932 | #endif | |
a6da8b81 CZ |
933 | do_fixup_by_compat(blob, compat, "status", "okay", |
934 | 4 + 1, 1); | |
b33433a6 | 935 | } |
c67bee14 | 936 | #endif |
96f0407b PF |
937 | |
938 | #ifdef CONFIG_DM_MMC | |
939 | #include <asm/arch/clock.h> | |
940 | static int fsl_esdhc_probe(struct udevice *dev) | |
941 | { | |
942 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
943 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); | |
944 | const void *fdt = gd->fdt_blob; | |
945 | int node = dev->of_offset; | |
946 | fdt_addr_t addr; | |
947 | unsigned int val; | |
948 | int ret; | |
949 | ||
950 | addr = dev_get_addr(dev); | |
951 | if (addr == FDT_ADDR_T_NONE) | |
952 | return -EINVAL; | |
953 | ||
954 | priv->esdhc_regs = (struct fsl_esdhc *)addr; | |
955 | priv->dev = dev; | |
956 | ||
957 | val = fdtdec_get_int(fdt, node, "bus-width", -1); | |
958 | if (val == 8) | |
959 | priv->bus_width = 8; | |
960 | else if (val == 4) | |
961 | priv->bus_width = 4; | |
962 | else | |
963 | priv->bus_width = 1; | |
964 | ||
965 | if (fdt_get_property(fdt, node, "non-removable", NULL)) { | |
966 | priv->non_removable = 1; | |
967 | } else { | |
968 | priv->non_removable = 0; | |
969 | gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0, | |
970 | &priv->cd_gpio, GPIOD_IS_IN); | |
971 | } | |
972 | ||
1483151e PF |
973 | priv->wp_enable = 1; |
974 | ||
975 | ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0, | |
976 | &priv->wp_gpio, GPIOD_IS_IN); | |
977 | if (ret) | |
978 | priv->wp_enable = 0; | |
979 | ||
96f0407b PF |
980 | /* |
981 | * TODO: | |
982 | * Because lack of clk driver, if SDHC clk is not enabled, | |
983 | * need to enable it first before this driver is invoked. | |
984 | * | |
985 | * we use MXC_ESDHC_CLK to get clk freq. | |
986 | * If one would like to make this function work, | |
987 | * the aliases should be provided in dts as this: | |
988 | * | |
989 | * aliases { | |
990 | * mmc0 = &usdhc1; | |
991 | * mmc1 = &usdhc2; | |
992 | * mmc2 = &usdhc3; | |
993 | * mmc3 = &usdhc4; | |
994 | * }; | |
995 | * Then if your board only supports mmc2 and mmc3, but we can | |
996 | * correctly get the seq as 2 and 3, then let mxc_get_clock | |
997 | * work as expected. | |
998 | */ | |
999 | priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); | |
1000 | if (priv->sdhc_clk <= 0) { | |
1001 | dev_err(dev, "Unable to get clk for %s\n", dev->name); | |
1002 | return -EINVAL; | |
1003 | } | |
1004 | ||
1005 | ret = fsl_esdhc_init(priv); | |
1006 | if (ret) { | |
1007 | dev_err(dev, "fsl_esdhc_init failure\n"); | |
1008 | return ret; | |
1009 | } | |
1010 | ||
1011 | upriv->mmc = priv->mmc; | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | static const struct udevice_id fsl_esdhc_ids[] = { | |
1017 | { .compatible = "fsl,imx6ul-usdhc", }, | |
1018 | { .compatible = "fsl,imx6sx-usdhc", }, | |
1019 | { .compatible = "fsl,imx6sl-usdhc", }, | |
1020 | { .compatible = "fsl,imx6q-usdhc", }, | |
1021 | { .compatible = "fsl,imx7d-usdhc", }, | |
1022 | { /* sentinel */ } | |
1023 | }; | |
1024 | ||
1025 | U_BOOT_DRIVER(fsl_esdhc) = { | |
1026 | .name = "fsl-esdhc-mmc", | |
1027 | .id = UCLASS_MMC, | |
1028 | .of_match = fsl_esdhc_ids, | |
1029 | .probe = fsl_esdhc_probe, | |
1030 | .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), | |
1031 | }; | |
1032 | #endif |