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50586ef2 | 1 | /* |
d621da00 | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
50586ef2 AF |
3 | * Andy Fleming |
4 | * | |
5 | * Based vaguely on the pxa mmc code: | |
6 | * (C) Copyright 2003 | |
7 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
50586ef2 AF |
10 | */ |
11 | ||
12 | #include <config.h> | |
13 | #include <common.h> | |
14 | #include <command.h> | |
915ffa52 | 15 | #include <errno.h> |
b33433a6 | 16 | #include <hwconfig.h> |
50586ef2 AF |
17 | #include <mmc.h> |
18 | #include <part.h> | |
4483b7eb | 19 | #include <power/regulator.h> |
50586ef2 | 20 | #include <malloc.h> |
50586ef2 | 21 | #include <fsl_esdhc.h> |
b33433a6 | 22 | #include <fdt_support.h> |
50586ef2 | 23 | #include <asm/io.h> |
96f0407b PF |
24 | #include <dm.h> |
25 | #include <asm-generic/gpio.h> | |
50586ef2 | 26 | |
50586ef2 AF |
27 | DECLARE_GLOBAL_DATA_PTR; |
28 | ||
a3d6e386 YL |
29 | #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ |
30 | IRQSTATEN_CINT | \ | |
31 | IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ | |
32 | IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ | |
33 | IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ | |
34 | IRQSTATEN_DINT) | |
35 | ||
50586ef2 | 36 | struct fsl_esdhc { |
511948b2 HZ |
37 | uint dsaddr; /* SDMA system address register */ |
38 | uint blkattr; /* Block attributes register */ | |
39 | uint cmdarg; /* Command argument register */ | |
40 | uint xfertyp; /* Transfer type register */ | |
41 | uint cmdrsp0; /* Command response 0 register */ | |
42 | uint cmdrsp1; /* Command response 1 register */ | |
43 | uint cmdrsp2; /* Command response 2 register */ | |
44 | uint cmdrsp3; /* Command response 3 register */ | |
45 | uint datport; /* Buffer data port register */ | |
46 | uint prsstat; /* Present state register */ | |
47 | uint proctl; /* Protocol control register */ | |
48 | uint sysctl; /* System Control Register */ | |
49 | uint irqstat; /* Interrupt status register */ | |
50 | uint irqstaten; /* Interrupt status enable register */ | |
51 | uint irqsigen; /* Interrupt signal enable register */ | |
52 | uint autoc12err; /* Auto CMD error status register */ | |
53 | uint hostcapblt; /* Host controller capabilities register */ | |
54 | uint wml; /* Watermark level register */ | |
55 | uint mixctrl; /* For USDHC */ | |
56 | char reserved1[4]; /* reserved */ | |
57 | uint fevt; /* Force event register */ | |
58 | uint admaes; /* ADMA error status register */ | |
59 | uint adsaddr; /* ADMA system address register */ | |
f53225cc PF |
60 | char reserved2[4]; |
61 | uint dllctrl; | |
62 | uint dllstat; | |
63 | uint clktunectrlstatus; | |
64 | char reserved3[84]; | |
65 | uint vendorspec; | |
66 | uint mmcboot; | |
67 | uint vendorspec2; | |
68 | char reserved4[48]; | |
511948b2 | 69 | uint hostver; /* Host controller version register */ |
511948b2 | 70 | char reserved5[4]; /* reserved */ |
f53225cc | 71 | uint dmaerraddr; /* DMA error address register */ |
f022d36e | 72 | char reserved6[4]; /* reserved */ |
f53225cc PF |
73 | uint dmaerrattr; /* DMA error attribute register */ |
74 | char reserved7[4]; /* reserved */ | |
511948b2 | 75 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
f53225cc | 76 | char reserved8[8]; /* reserved */ |
511948b2 | 77 | uint tcr; /* Tuning control register */ |
f53225cc | 78 | char reserved9[28]; /* reserved */ |
511948b2 | 79 | uint sddirctl; /* SD direction control register */ |
f53225cc | 80 | char reserved10[712];/* reserved */ |
511948b2 | 81 | uint scr; /* eSDHC control register */ |
50586ef2 AF |
82 | }; |
83 | ||
e88e1d9c SG |
84 | struct fsl_esdhc_plat { |
85 | struct mmc_config cfg; | |
86 | struct mmc mmc; | |
87 | }; | |
88 | ||
96f0407b PF |
89 | /** |
90 | * struct fsl_esdhc_priv | |
91 | * | |
92 | * @esdhc_regs: registers of the sdhc controller | |
93 | * @sdhc_clk: Current clk of the sdhc controller | |
94 | * @bus_width: bus width, 1bit, 4bit or 8bit | |
95 | * @cfg: mmc config | |
96 | * @mmc: mmc | |
97 | * Following is used when Driver Model is enabled for MMC | |
98 | * @dev: pointer for the device | |
99 | * @non_removable: 0: removable; 1: non-removable | |
1483151e | 100 | * @wp_enable: 1: enable checking wp; 0: no check |
32a9179f | 101 | * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V |
96f0407b | 102 | * @cd_gpio: gpio for card detection |
1483151e | 103 | * @wp_gpio: gpio for write protection |
96f0407b PF |
104 | */ |
105 | struct fsl_esdhc_priv { | |
106 | struct fsl_esdhc *esdhc_regs; | |
107 | unsigned int sdhc_clk; | |
108 | unsigned int bus_width; | |
653282b5 | 109 | #if !CONFIG_IS_ENABLED(BLK) |
96f0407b | 110 | struct mmc *mmc; |
653282b5 | 111 | #endif |
96f0407b PF |
112 | struct udevice *dev; |
113 | int non_removable; | |
1483151e | 114 | int wp_enable; |
32a9179f | 115 | int vs18_enable; |
fc8048a8 | 116 | #ifdef CONFIG_DM_GPIO |
96f0407b | 117 | struct gpio_desc cd_gpio; |
1483151e | 118 | struct gpio_desc wp_gpio; |
fc8048a8 | 119 | #endif |
96f0407b PF |
120 | }; |
121 | ||
50586ef2 | 122 | /* Return the XFERTYP flags for a given command and data packet */ |
eafa90a1 | 123 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
50586ef2 AF |
124 | { |
125 | uint xfertyp = 0; | |
126 | ||
127 | if (data) { | |
77c1458d DD |
128 | xfertyp |= XFERTYP_DPSEL; |
129 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO | |
130 | xfertyp |= XFERTYP_DMAEN; | |
131 | #endif | |
50586ef2 AF |
132 | if (data->blocks > 1) { |
133 | xfertyp |= XFERTYP_MSBSEL; | |
134 | xfertyp |= XFERTYP_BCEN; | |
d621da00 JH |
135 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
136 | xfertyp |= XFERTYP_AC12EN; | |
137 | #endif | |
50586ef2 AF |
138 | } |
139 | ||
140 | if (data->flags & MMC_DATA_READ) | |
141 | xfertyp |= XFERTYP_DTDSEL; | |
142 | } | |
143 | ||
144 | if (cmd->resp_type & MMC_RSP_CRC) | |
145 | xfertyp |= XFERTYP_CCCEN; | |
146 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
147 | xfertyp |= XFERTYP_CICEN; | |
148 | if (cmd->resp_type & MMC_RSP_136) | |
149 | xfertyp |= XFERTYP_RSPTYP_136; | |
150 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
151 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; | |
152 | else if (cmd->resp_type & MMC_RSP_PRESENT) | |
153 | xfertyp |= XFERTYP_RSPTYP_48; | |
154 | ||
4571de33 JL |
155 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
156 | xfertyp |= XFERTYP_CMDTYP_ABORT; | |
25503443 | 157 | |
50586ef2 AF |
158 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
159 | } | |
160 | ||
77c1458d DD |
161 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
162 | /* | |
163 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. | |
164 | */ | |
09b465fd SG |
165 | static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, |
166 | struct mmc_data *data) | |
77c1458d | 167 | { |
96f0407b | 168 | struct fsl_esdhc *regs = priv->esdhc_regs; |
77c1458d DD |
169 | uint blocks; |
170 | char *buffer; | |
171 | uint databuf; | |
172 | uint size; | |
173 | uint irqstat; | |
bcfb3653 | 174 | ulong start; |
77c1458d DD |
175 | |
176 | if (data->flags & MMC_DATA_READ) { | |
177 | blocks = data->blocks; | |
178 | buffer = data->dest; | |
179 | while (blocks) { | |
bcfb3653 | 180 | start = get_timer(0); |
77c1458d DD |
181 | size = data->blocksize; |
182 | irqstat = esdhc_read32(®s->irqstat); | |
bcfb3653 BT |
183 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { |
184 | if (get_timer(start) > PIO_TIMEOUT) { | |
185 | printf("\nData Read Failed in PIO Mode."); | |
186 | return; | |
187 | } | |
77c1458d DD |
188 | } |
189 | while (size && (!(irqstat & IRQSTAT_TC))) { | |
190 | udelay(100); /* Wait before last byte transfer complete */ | |
191 | irqstat = esdhc_read32(®s->irqstat); | |
192 | databuf = in_le32(®s->datport); | |
193 | *((uint *)buffer) = databuf; | |
194 | buffer += 4; | |
195 | size -= 4; | |
196 | } | |
197 | blocks--; | |
198 | } | |
199 | } else { | |
200 | blocks = data->blocks; | |
7b43db92 | 201 | buffer = (char *)data->src; |
77c1458d | 202 | while (blocks) { |
bcfb3653 | 203 | start = get_timer(0); |
77c1458d DD |
204 | size = data->blocksize; |
205 | irqstat = esdhc_read32(®s->irqstat); | |
bcfb3653 BT |
206 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { |
207 | if (get_timer(start) > PIO_TIMEOUT) { | |
208 | printf("\nData Write Failed in PIO Mode."); | |
209 | return; | |
210 | } | |
77c1458d DD |
211 | } |
212 | while (size && (!(irqstat & IRQSTAT_TC))) { | |
213 | udelay(100); /* Wait before last byte transfer complete */ | |
214 | databuf = *((uint *)buffer); | |
215 | buffer += 4; | |
216 | size -= 4; | |
217 | irqstat = esdhc_read32(®s->irqstat); | |
218 | out_le32(®s->datport, databuf); | |
219 | } | |
220 | blocks--; | |
221 | } | |
222 | } | |
223 | } | |
224 | #endif | |
225 | ||
09b465fd SG |
226 | static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
227 | struct mmc_data *data) | |
50586ef2 | 228 | { |
50586ef2 | 229 | int timeout; |
96f0407b | 230 | struct fsl_esdhc *regs = priv->esdhc_regs; |
9702ec00 | 231 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
8b06460e YL |
232 | dma_addr_t addr; |
233 | #endif | |
7b43db92 | 234 | uint wml_value; |
50586ef2 AF |
235 | |
236 | wml_value = data->blocksize/4; | |
237 | ||
238 | if (data->flags & MMC_DATA_READ) { | |
32c8cfb2 PJ |
239 | if (wml_value > WML_RD_WML_MAX) |
240 | wml_value = WML_RD_WML_MAX_VAL; | |
50586ef2 | 241 | |
ab467c51 | 242 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
71689776 | 243 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
9702ec00 | 244 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
8b06460e YL |
245 | addr = virt_to_phys((void *)(data->dest)); |
246 | if (upper_32_bits(addr)) | |
247 | printf("Error found for upper 32 bits\n"); | |
248 | else | |
249 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); | |
250 | #else | |
c67bee14 | 251 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
8b06460e | 252 | #endif |
71689776 | 253 | #endif |
50586ef2 | 254 | } else { |
71689776 | 255 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
e576bd90 EN |
256 | flush_dcache_range((ulong)data->src, |
257 | (ulong)data->src+data->blocks | |
258 | *data->blocksize); | |
71689776 | 259 | #endif |
32c8cfb2 PJ |
260 | if (wml_value > WML_WR_WML_MAX) |
261 | wml_value = WML_WR_WML_MAX_VAL; | |
1483151e PF |
262 | if (priv->wp_enable) { |
263 | if ((esdhc_read32(®s->prsstat) & | |
264 | PRSSTAT_WPSPL) == 0) { | |
265 | printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); | |
915ffa52 | 266 | return -ETIMEDOUT; |
1483151e | 267 | } |
50586ef2 | 268 | } |
ab467c51 RZ |
269 | |
270 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, | |
271 | wml_value << 16); | |
71689776 | 272 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
9702ec00 | 273 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
8b06460e YL |
274 | addr = virt_to_phys((void *)(data->src)); |
275 | if (upper_32_bits(addr)) | |
276 | printf("Error found for upper 32 bits\n"); | |
277 | else | |
278 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); | |
279 | #else | |
c67bee14 | 280 | esdhc_write32(®s->dsaddr, (u32)data->src); |
8b06460e | 281 | #endif |
71689776 | 282 | #endif |
50586ef2 AF |
283 | } |
284 | ||
c67bee14 | 285 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
50586ef2 AF |
286 | |
287 | /* Calculate the timeout period for data transactions */ | |
b71ea336 PJ |
288 | /* |
289 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles | |
290 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec | |
291 | * So, Number of SD Clock cycles for 0.25sec should be minimum | |
292 | * (SD Clock/sec * 0.25 sec) SD Clock cycles | |
fb823981 | 293 | * = (mmc->clock * 1/4) SD Clock cycles |
b71ea336 | 294 | * As 1) >= 2) |
fb823981 | 295 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
b71ea336 | 296 | * Taking log2 both the sides |
fb823981 | 297 | * => timeout + 13 >= log2(mmc->clock/4) |
b71ea336 | 298 | * Rounding up to next power of 2 |
fb823981 AG |
299 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
300 | * => timeout + 13 = fls(mmc->clock/4) | |
e978a31b YL |
301 | * |
302 | * However, the MMC spec "It is strongly recommended for hosts to | |
303 | * implement more than 500ms timeout value even if the card | |
304 | * indicates the 250ms maximum busy length." Even the previous | |
305 | * value of 300ms is known to be insufficient for some cards. | |
306 | * So, we use | |
307 | * => timeout + 13 = fls(mmc->clock/2) | |
b71ea336 | 308 | */ |
e978a31b | 309 | timeout = fls(mmc->clock/2); |
50586ef2 AF |
310 | timeout -= 13; |
311 | ||
312 | if (timeout > 14) | |
313 | timeout = 14; | |
314 | ||
315 | if (timeout < 0) | |
316 | timeout = 0; | |
317 | ||
5103a03a KG |
318 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
319 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) | |
320 | timeout++; | |
321 | #endif | |
322 | ||
1336e2d3 HZ |
323 | #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
324 | timeout = 0xE; | |
325 | #endif | |
c67bee14 | 326 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
50586ef2 AF |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
e576bd90 EN |
331 | static void check_and_invalidate_dcache_range |
332 | (struct mmc_cmd *cmd, | |
333 | struct mmc_data *data) { | |
8b06460e | 334 | unsigned start = 0; |
cc634e28 | 335 | unsigned end = 0; |
e576bd90 EN |
336 | unsigned size = roundup(ARCH_DMA_MINALIGN, |
337 | data->blocks*data->blocksize); | |
9702ec00 | 338 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
8b06460e YL |
339 | dma_addr_t addr; |
340 | ||
341 | addr = virt_to_phys((void *)(data->dest)); | |
342 | if (upper_32_bits(addr)) | |
343 | printf("Error found for upper 32 bits\n"); | |
344 | else | |
345 | start = lower_32_bits(addr); | |
cc634e28 YL |
346 | #else |
347 | start = (unsigned)data->dest; | |
8b06460e | 348 | #endif |
cc634e28 | 349 | end = start + size; |
e576bd90 EN |
350 | invalidate_dcache_range(start, end); |
351 | } | |
10dc7771 | 352 | |
50586ef2 AF |
353 | /* |
354 | * Sends a command out on the bus. Takes the mmc pointer, | |
355 | * a command pointer, and an optional data pointer. | |
356 | */ | |
9586aa6e SG |
357 | static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
358 | struct mmc_cmd *cmd, struct mmc_data *data) | |
50586ef2 | 359 | { |
8a573022 | 360 | int err = 0; |
50586ef2 AF |
361 | uint xfertyp; |
362 | uint irqstat; | |
96f0407b | 363 | struct fsl_esdhc *regs = priv->esdhc_regs; |
50586ef2 | 364 | |
d621da00 JH |
365 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
366 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) | |
367 | return 0; | |
368 | #endif | |
369 | ||
c67bee14 | 370 | esdhc_write32(®s->irqstat, -1); |
50586ef2 AF |
371 | |
372 | sync(); | |
373 | ||
374 | /* Wait for the bus to be idle */ | |
c67bee14 SB |
375 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
376 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) | |
377 | ; | |
50586ef2 | 378 | |
c67bee14 SB |
379 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
380 | ; | |
50586ef2 AF |
381 | |
382 | /* Wait at least 8 SD clock cycles before the next command */ | |
383 | /* | |
384 | * Note: This is way more than 8 cycles, but 1ms seems to | |
385 | * resolve timing issues with some cards | |
386 | */ | |
387 | udelay(1000); | |
388 | ||
389 | /* Set up for a data transfer if we have one */ | |
390 | if (data) { | |
09b465fd | 391 | err = esdhc_setup_data(priv, mmc, data); |
50586ef2 AF |
392 | if(err) |
393 | return err; | |
4683b220 PF |
394 | |
395 | if (data->flags & MMC_DATA_READ) | |
396 | check_and_invalidate_dcache_range(cmd, data); | |
50586ef2 AF |
397 | } |
398 | ||
399 | /* Figure out the transfer arguments */ | |
400 | xfertyp = esdhc_xfertyp(cmd, data); | |
401 | ||
01b77353 AG |
402 | /* Mask all irqs */ |
403 | esdhc_write32(®s->irqsigen, 0); | |
404 | ||
50586ef2 | 405 | /* Send the command */ |
c67bee14 | 406 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
4692708d JL |
407 | #if defined(CONFIG_FSL_USDHC) |
408 | esdhc_write32(®s->mixctrl, | |
0e1bf614 VR |
409 | (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) |
410 | | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); | |
4692708d JL |
411 | esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); |
412 | #else | |
c67bee14 | 413 | esdhc_write32(®s->xfertyp, xfertyp); |
4692708d | 414 | #endif |
7a5b8029 | 415 | |
50586ef2 | 416 | /* Wait for the command to complete */ |
7a5b8029 | 417 | while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) |
c67bee14 | 418 | ; |
50586ef2 | 419 | |
c67bee14 | 420 | irqstat = esdhc_read32(®s->irqstat); |
50586ef2 | 421 | |
8a573022 | 422 | if (irqstat & CMD_ERR) { |
915ffa52 | 423 | err = -ECOMM; |
8a573022 | 424 | goto out; |
7a5b8029 DB |
425 | } |
426 | ||
8a573022 | 427 | if (irqstat & IRQSTAT_CTOE) { |
915ffa52 | 428 | err = -ETIMEDOUT; |
8a573022 AG |
429 | goto out; |
430 | } | |
50586ef2 | 431 | |
f022d36e OS |
432 | /* Switch voltage to 1.8V if CMD11 succeeded */ |
433 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { | |
434 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); | |
435 | ||
436 | printf("Run CMD11 1.8V switch\n"); | |
437 | /* Sleep for 5 ms - max time for card to switch to 1.8V */ | |
438 | udelay(5000); | |
439 | } | |
440 | ||
7a5b8029 DB |
441 | /* Workaround for ESDHC errata ENGcm03648 */ |
442 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { | |
253d5bdd | 443 | int timeout = 6000; |
7a5b8029 | 444 | |
253d5bdd | 445 | /* Poll on DATA0 line for cmd with busy signal for 600 ms */ |
7a5b8029 DB |
446 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
447 | PRSSTAT_DAT0)) { | |
448 | udelay(100); | |
449 | timeout--; | |
450 | } | |
451 | ||
452 | if (timeout <= 0) { | |
453 | printf("Timeout waiting for DAT0 to go high!\n"); | |
915ffa52 | 454 | err = -ETIMEDOUT; |
8a573022 | 455 | goto out; |
7a5b8029 DB |
456 | } |
457 | } | |
458 | ||
50586ef2 AF |
459 | /* Copy the response to the response buffer */ |
460 | if (cmd->resp_type & MMC_RSP_136) { | |
461 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; | |
462 | ||
c67bee14 SB |
463 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
464 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); | |
465 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); | |
466 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); | |
998be3dd RV |
467 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
468 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); | |
469 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); | |
470 | cmd->response[3] = (cmdrsp0 << 8); | |
50586ef2 | 471 | } else |
c67bee14 | 472 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
50586ef2 AF |
473 | |
474 | /* Wait until all of the blocks are transferred */ | |
475 | if (data) { | |
77c1458d | 476 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
09b465fd | 477 | esdhc_pio_read_write(priv, data); |
77c1458d | 478 | #else |
50586ef2 | 479 | do { |
c67bee14 | 480 | irqstat = esdhc_read32(®s->irqstat); |
50586ef2 | 481 | |
8a573022 | 482 | if (irqstat & IRQSTAT_DTOE) { |
915ffa52 | 483 | err = -ETIMEDOUT; |
8a573022 AG |
484 | goto out; |
485 | } | |
63fb5a7e | 486 | |
8a573022 | 487 | if (irqstat & DATA_ERR) { |
915ffa52 | 488 | err = -ECOMM; |
8a573022 AG |
489 | goto out; |
490 | } | |
9b74dc56 | 491 | } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); |
71689776 | 492 | |
4683b220 PF |
493 | /* |
494 | * Need invalidate the dcache here again to avoid any | |
495 | * cache-fill during the DMA operations such as the | |
496 | * speculative pre-fetching etc. | |
497 | */ | |
54899fc8 EN |
498 | if (data->flags & MMC_DATA_READ) |
499 | check_and_invalidate_dcache_range(cmd, data); | |
71689776 | 500 | #endif |
50586ef2 AF |
501 | } |
502 | ||
8a573022 AG |
503 | out: |
504 | /* Reset CMD and DATA portions on error */ | |
505 | if (err) { | |
506 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | | |
507 | SYSCTL_RSTC); | |
508 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) | |
509 | ; | |
510 | ||
511 | if (data) { | |
512 | esdhc_write32(®s->sysctl, | |
513 | esdhc_read32(®s->sysctl) | | |
514 | SYSCTL_RSTD); | |
515 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) | |
516 | ; | |
517 | } | |
f022d36e OS |
518 | |
519 | /* If this was CMD11, then notify that power cycle is needed */ | |
520 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) | |
521 | printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); | |
8a573022 AG |
522 | } |
523 | ||
c67bee14 | 524 | esdhc_write32(®s->irqstat, -1); |
50586ef2 | 525 | |
8a573022 | 526 | return err; |
50586ef2 AF |
527 | } |
528 | ||
09b465fd | 529 | static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) |
50586ef2 | 530 | { |
4f425280 BT |
531 | int div = 1; |
532 | #ifdef ARCH_MXC | |
533 | int pre_div = 1; | |
534 | #else | |
535 | int pre_div = 2; | |
536 | #endif | |
537 | int ddr_pre_div = mmc->ddr_mode ? 2 : 1; | |
96f0407b PF |
538 | struct fsl_esdhc *regs = priv->esdhc_regs; |
539 | int sdhc_clk = priv->sdhc_clk; | |
50586ef2 AF |
540 | uint clk; |
541 | ||
93bfd616 PA |
542 | if (clock < mmc->cfg->f_min) |
543 | clock = mmc->cfg->f_min; | |
c67bee14 | 544 | |
4f425280 BT |
545 | while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) |
546 | pre_div *= 2; | |
50586ef2 | 547 | |
4f425280 BT |
548 | while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) |
549 | div++; | |
50586ef2 | 550 | |
4f425280 | 551 | pre_div >>= 1; |
50586ef2 AF |
552 | div -= 1; |
553 | ||
554 | clk = (pre_div << 8) | (div << 4); | |
555 | ||
f0b5f23f | 556 | #ifdef CONFIG_FSL_USDHC |
84ecdf6d | 557 | esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); |
f0b5f23f | 558 | #else |
cc4d1226 | 559 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
f0b5f23f | 560 | #endif |
c67bee14 SB |
561 | |
562 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); | |
50586ef2 AF |
563 | |
564 | udelay(10000); | |
565 | ||
f0b5f23f | 566 | #ifdef CONFIG_FSL_USDHC |
84ecdf6d | 567 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); |
f0b5f23f EN |
568 | #else |
569 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); | |
570 | #endif | |
c67bee14 | 571 | |
50586ef2 AF |
572 | } |
573 | ||
2d9ca2c7 | 574 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
09b465fd | 575 | static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) |
2d9ca2c7 | 576 | { |
96f0407b | 577 | struct fsl_esdhc *regs = priv->esdhc_regs; |
2d9ca2c7 YL |
578 | u32 value; |
579 | u32 time_out; | |
580 | ||
581 | value = esdhc_read32(®s->sysctl); | |
582 | ||
583 | if (enable) | |
584 | value |= SYSCTL_CKEN; | |
585 | else | |
586 | value &= ~SYSCTL_CKEN; | |
587 | ||
588 | esdhc_write32(®s->sysctl, value); | |
589 | ||
590 | time_out = 20; | |
591 | value = PRSSTAT_SDSTB; | |
592 | while (!(esdhc_read32(®s->prsstat) & value)) { | |
593 | if (time_out == 0) { | |
594 | printf("fsl_esdhc: Internal clock never stabilised.\n"); | |
595 | break; | |
596 | } | |
597 | time_out--; | |
598 | mdelay(1); | |
599 | } | |
600 | } | |
601 | #endif | |
602 | ||
9586aa6e | 603 | static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
50586ef2 | 604 | { |
96f0407b | 605 | struct fsl_esdhc *regs = priv->esdhc_regs; |
50586ef2 | 606 | |
2d9ca2c7 YL |
607 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
608 | /* Select to use peripheral clock */ | |
09b465fd | 609 | esdhc_clock_control(priv, false); |
2d9ca2c7 | 610 | esdhc_setbits32(®s->scr, ESDHCCTL_PCS); |
09b465fd | 611 | esdhc_clock_control(priv, true); |
2d9ca2c7 | 612 | #endif |
50586ef2 | 613 | /* Set the clock speed */ |
09b465fd | 614 | set_sysctl(priv, mmc, mmc->clock); |
50586ef2 AF |
615 | |
616 | /* Set the bus width */ | |
c67bee14 | 617 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
50586ef2 AF |
618 | |
619 | if (mmc->bus_width == 4) | |
c67bee14 | 620 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
50586ef2 | 621 | else if (mmc->bus_width == 8) |
c67bee14 SB |
622 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
623 | ||
07b0b9c0 | 624 | return 0; |
50586ef2 AF |
625 | } |
626 | ||
9586aa6e | 627 | static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
50586ef2 | 628 | { |
96f0407b | 629 | struct fsl_esdhc *regs = priv->esdhc_regs; |
201e828b | 630 | ulong start; |
50586ef2 | 631 | |
c67bee14 | 632 | /* Reset the entire host controller */ |
a61da72b | 633 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
c67bee14 SB |
634 | |
635 | /* Wait until the controller is available */ | |
201e828b SG |
636 | start = get_timer(0); |
637 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { | |
638 | if (get_timer(start) > 1000) | |
639 | return -ETIMEDOUT; | |
640 | } | |
50586ef2 | 641 | |
f53225cc PF |
642 | #if defined(CONFIG_FSL_USDHC) |
643 | /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ | |
644 | esdhc_write32(®s->mmcboot, 0x0); | |
645 | /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ | |
646 | esdhc_write32(®s->mixctrl, 0x0); | |
647 | esdhc_write32(®s->clktunectrlstatus, 0x0); | |
648 | ||
649 | /* Put VEND_SPEC to default value */ | |
db359efd PF |
650 | if (priv->vs18_enable) |
651 | esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | | |
652 | ESDHC_VENDORSPEC_VSELECT)); | |
653 | else | |
654 | esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); | |
f53225cc PF |
655 | |
656 | /* Disable DLL_CTRL delay line */ | |
657 | esdhc_write32(®s->dllctrl, 0x0); | |
658 | #endif | |
659 | ||
16e43f35 | 660 | #ifndef ARCH_MXC |
2c1764ef | 661 | /* Enable cache snooping */ |
16e43f35 BT |
662 | esdhc_write32(®s->scr, 0x00000040); |
663 | #endif | |
2c1764ef | 664 | |
f0b5f23f | 665 | #ifndef CONFIG_FSL_USDHC |
a61da72b | 666 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
84ecdf6d YL |
667 | #else |
668 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); | |
f0b5f23f | 669 | #endif |
50586ef2 AF |
670 | |
671 | /* Set the initial clock speed */ | |
35f67820 | 672 | mmc_set_clock(mmc, 400000, false); |
50586ef2 AF |
673 | |
674 | /* Disable the BRR and BWR bits in IRQSTAT */ | |
c67bee14 | 675 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
50586ef2 AF |
676 | |
677 | /* Put the PROCTL reg back to the default */ | |
c67bee14 | 678 | esdhc_write32(®s->proctl, PROCTL_INIT); |
50586ef2 | 679 | |
c67bee14 SB |
680 | /* Set timout to the maximum value */ |
681 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); | |
50586ef2 | 682 | |
d48d2e21 TR |
683 | return 0; |
684 | } | |
50586ef2 | 685 | |
9586aa6e | 686 | static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) |
d48d2e21 | 687 | { |
96f0407b | 688 | struct fsl_esdhc *regs = priv->esdhc_regs; |
d48d2e21 TR |
689 | int timeout = 1000; |
690 | ||
f7e27cc5 HZ |
691 | #ifdef CONFIG_ESDHC_DETECT_QUIRK |
692 | if (CONFIG_ESDHC_DETECT_QUIRK) | |
693 | return 1; | |
694 | #endif | |
96f0407b | 695 | |
653282b5 | 696 | #if CONFIG_IS_ENABLED(DM_MMC) |
96f0407b PF |
697 | if (priv->non_removable) |
698 | return 1; | |
fc8048a8 | 699 | #ifdef CONFIG_DM_GPIO |
96f0407b PF |
700 | if (dm_gpio_is_valid(&priv->cd_gpio)) |
701 | return dm_gpio_get_value(&priv->cd_gpio); | |
fc8048a8 | 702 | #endif |
96f0407b PF |
703 | #endif |
704 | ||
d48d2e21 TR |
705 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) |
706 | udelay(1000); | |
c67bee14 | 707 | |
d48d2e21 | 708 | return timeout > 0; |
50586ef2 AF |
709 | } |
710 | ||
446e077a | 711 | static int esdhc_reset(struct fsl_esdhc *regs) |
48bb3bb5 | 712 | { |
446e077a | 713 | ulong start; |
48bb3bb5 JH |
714 | |
715 | /* reset the controller */ | |
a61da72b | 716 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
48bb3bb5 JH |
717 | |
718 | /* hardware clears the bit when it is done */ | |
446e077a SG |
719 | start = get_timer(0); |
720 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { | |
721 | if (get_timer(start) > 100) { | |
722 | printf("MMC/SD: Reset never completed.\n"); | |
723 | return -ETIMEDOUT; | |
724 | } | |
725 | } | |
726 | ||
727 | return 0; | |
48bb3bb5 JH |
728 | } |
729 | ||
e7881d85 | 730 | #if !CONFIG_IS_ENABLED(DM_MMC) |
9586aa6e SG |
731 | static int esdhc_getcd(struct mmc *mmc) |
732 | { | |
733 | struct fsl_esdhc_priv *priv = mmc->priv; | |
734 | ||
735 | return esdhc_getcd_common(priv); | |
736 | } | |
737 | ||
738 | static int esdhc_init(struct mmc *mmc) | |
739 | { | |
740 | struct fsl_esdhc_priv *priv = mmc->priv; | |
741 | ||
742 | return esdhc_init_common(priv, mmc); | |
743 | } | |
744 | ||
745 | static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, | |
746 | struct mmc_data *data) | |
747 | { | |
748 | struct fsl_esdhc_priv *priv = mmc->priv; | |
749 | ||
750 | return esdhc_send_cmd_common(priv, mmc, cmd, data); | |
751 | } | |
752 | ||
753 | static int esdhc_set_ios(struct mmc *mmc) | |
754 | { | |
755 | struct fsl_esdhc_priv *priv = mmc->priv; | |
756 | ||
757 | return esdhc_set_ios_common(priv, mmc); | |
758 | } | |
759 | ||
ab769f22 | 760 | static const struct mmc_ops esdhc_ops = { |
9586aa6e SG |
761 | .getcd = esdhc_getcd, |
762 | .init = esdhc_init, | |
ab769f22 PA |
763 | .send_cmd = esdhc_send_cmd, |
764 | .set_ios = esdhc_set_ios, | |
ab769f22 | 765 | }; |
653282b5 | 766 | #endif |
ab769f22 | 767 | |
e88e1d9c SG |
768 | static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, |
769 | struct fsl_esdhc_plat *plat) | |
50586ef2 | 770 | { |
e88e1d9c | 771 | struct mmc_config *cfg; |
c67bee14 | 772 | struct fsl_esdhc *regs; |
030955c2 | 773 | u32 caps, voltage_caps; |
446e077a | 774 | int ret; |
50586ef2 | 775 | |
96f0407b PF |
776 | if (!priv) |
777 | return -EINVAL; | |
c67bee14 | 778 | |
96f0407b | 779 | regs = priv->esdhc_regs; |
c67bee14 | 780 | |
48bb3bb5 | 781 | /* First reset the eSDHC controller */ |
446e077a SG |
782 | ret = esdhc_reset(regs); |
783 | if (ret) | |
784 | return ret; | |
48bb3bb5 | 785 | |
f0b5f23f | 786 | #ifndef CONFIG_FSL_USDHC |
975324a7 JH |
787 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
788 | | SYSCTL_IPGEN | SYSCTL_CKEN); | |
84ecdf6d YL |
789 | #else |
790 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | | |
791 | VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); | |
f0b5f23f | 792 | #endif |
975324a7 | 793 | |
32a9179f PF |
794 | if (priv->vs18_enable) |
795 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); | |
796 | ||
a3d6e386 | 797 | writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); |
e88e1d9c | 798 | cfg = &plat->cfg; |
653282b5 | 799 | #ifndef CONFIG_DM_MMC |
e88e1d9c | 800 | memset(cfg, '\0', sizeof(*cfg)); |
653282b5 | 801 | #endif |
93bfd616 | 802 | |
030955c2 | 803 | voltage_caps = 0; |
19060bd8 | 804 | caps = esdhc_read32(®s->hostcapblt); |
3b4456ec RZ |
805 | |
806 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
807 | caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | | |
808 | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); | |
809 | #endif | |
ef38f3ff HZ |
810 | |
811 | /* T4240 host controller capabilities register should have VS33 bit */ | |
812 | #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
813 | caps = caps | ESDHC_HOSTCAPBLT_VS33; | |
814 | #endif | |
815 | ||
50586ef2 | 816 | if (caps & ESDHC_HOSTCAPBLT_VS18) |
030955c2 | 817 | voltage_caps |= MMC_VDD_165_195; |
50586ef2 | 818 | if (caps & ESDHC_HOSTCAPBLT_VS30) |
030955c2 | 819 | voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; |
50586ef2 | 820 | if (caps & ESDHC_HOSTCAPBLT_VS33) |
030955c2 LY |
821 | voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; |
822 | ||
e88e1d9c | 823 | cfg->name = "FSL_SDHC"; |
e7881d85 | 824 | #if !CONFIG_IS_ENABLED(DM_MMC) |
e88e1d9c | 825 | cfg->ops = &esdhc_ops; |
653282b5 | 826 | #endif |
030955c2 | 827 | #ifdef CONFIG_SYS_SD_VOLTAGE |
e88e1d9c | 828 | cfg->voltages = CONFIG_SYS_SD_VOLTAGE; |
030955c2 | 829 | #else |
e88e1d9c | 830 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
030955c2 | 831 | #endif |
e88e1d9c | 832 | if ((cfg->voltages & voltage_caps) == 0) { |
030955c2 LY |
833 | printf("voltage not supported by controller\n"); |
834 | return -1; | |
835 | } | |
50586ef2 | 836 | |
96f0407b | 837 | if (priv->bus_width == 8) |
e88e1d9c | 838 | cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
96f0407b | 839 | else if (priv->bus_width == 4) |
e88e1d9c | 840 | cfg->host_caps = MMC_MODE_4BIT; |
96f0407b | 841 | |
e88e1d9c | 842 | cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
0e1bf614 | 843 | #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE |
e88e1d9c | 844 | cfg->host_caps |= MMC_MODE_DDR_52MHz; |
0e1bf614 | 845 | #endif |
50586ef2 | 846 | |
96f0407b PF |
847 | if (priv->bus_width > 0) { |
848 | if (priv->bus_width < 8) | |
e88e1d9c | 849 | cfg->host_caps &= ~MMC_MODE_8BIT; |
96f0407b | 850 | if (priv->bus_width < 4) |
e88e1d9c | 851 | cfg->host_caps &= ~MMC_MODE_4BIT; |
aad4659a AR |
852 | } |
853 | ||
50586ef2 | 854 | if (caps & ESDHC_HOSTCAPBLT_HSS) |
e88e1d9c | 855 | cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
50586ef2 | 856 | |
d47e3d27 HZ |
857 | #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK |
858 | if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) | |
e88e1d9c | 859 | cfg->host_caps &= ~MMC_MODE_8BIT; |
d47e3d27 HZ |
860 | #endif |
861 | ||
e88e1d9c SG |
862 | cfg->f_min = 400000; |
863 | cfg->f_max = min(priv->sdhc_clk, (u32)52000000); | |
50586ef2 | 864 | |
e88e1d9c | 865 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
93bfd616 | 866 | |
96f0407b PF |
867 | return 0; |
868 | } | |
869 | ||
5248930e | 870 | #if !CONFIG_IS_ENABLED(DM_MMC) |
2e87c440 JT |
871 | static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, |
872 | struct fsl_esdhc_priv *priv) | |
873 | { | |
874 | if (!cfg || !priv) | |
875 | return -EINVAL; | |
876 | ||
877 | priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); | |
878 | priv->bus_width = cfg->max_bus_width; | |
879 | priv->sdhc_clk = cfg->sdhc_clk; | |
880 | priv->wp_enable = cfg->wp_enable; | |
32a9179f | 881 | priv->vs18_enable = cfg->vs18_enable; |
2e87c440 JT |
882 | |
883 | return 0; | |
884 | }; | |
885 | ||
96f0407b PF |
886 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) |
887 | { | |
e88e1d9c | 888 | struct fsl_esdhc_plat *plat; |
96f0407b | 889 | struct fsl_esdhc_priv *priv; |
d6eb25e9 | 890 | struct mmc *mmc; |
96f0407b PF |
891 | int ret; |
892 | ||
893 | if (!cfg) | |
894 | return -EINVAL; | |
895 | ||
896 | priv = calloc(sizeof(struct fsl_esdhc_priv), 1); | |
897 | if (!priv) | |
898 | return -ENOMEM; | |
e88e1d9c SG |
899 | plat = calloc(sizeof(struct fsl_esdhc_plat), 1); |
900 | if (!plat) { | |
901 | free(priv); | |
902 | return -ENOMEM; | |
903 | } | |
96f0407b PF |
904 | |
905 | ret = fsl_esdhc_cfg_to_priv(cfg, priv); | |
906 | if (ret) { | |
907 | debug("%s xlate failure\n", __func__); | |
e88e1d9c | 908 | free(plat); |
96f0407b PF |
909 | free(priv); |
910 | return ret; | |
911 | } | |
912 | ||
e88e1d9c | 913 | ret = fsl_esdhc_init(priv, plat); |
96f0407b PF |
914 | if (ret) { |
915 | debug("%s init failure\n", __func__); | |
e88e1d9c | 916 | free(plat); |
96f0407b PF |
917 | free(priv); |
918 | return ret; | |
919 | } | |
920 | ||
d6eb25e9 SG |
921 | mmc = mmc_create(&plat->cfg, priv); |
922 | if (!mmc) | |
923 | return -EIO; | |
924 | ||
925 | priv->mmc = mmc; | |
926 | ||
50586ef2 AF |
927 | return 0; |
928 | } | |
929 | ||
930 | int fsl_esdhc_mmc_init(bd_t *bis) | |
931 | { | |
c67bee14 SB |
932 | struct fsl_esdhc_cfg *cfg; |
933 | ||
88227a1d | 934 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
c67bee14 | 935 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
e9adeca3 | 936 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
c67bee14 | 937 | return fsl_esdhc_initialize(bis, cfg); |
50586ef2 | 938 | } |
2e87c440 | 939 | #endif |
b33433a6 | 940 | |
5a8dbdc6 YL |
941 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
942 | void mmc_adapter_card_type_ident(void) | |
943 | { | |
944 | u8 card_id; | |
945 | u8 value; | |
946 | ||
947 | card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; | |
948 | gd->arch.sdhc_adapter = card_id; | |
949 | ||
950 | switch (card_id) { | |
951 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: | |
cdc69550 YL |
952 | value = QIXIS_READ(brdcfg[5]); |
953 | value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); | |
954 | QIXIS_WRITE(brdcfg[5], value); | |
5a8dbdc6 YL |
955 | break; |
956 | case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: | |
bf50be83 YL |
957 | value = QIXIS_READ(pwr_ctl[1]); |
958 | value |= QIXIS_EVDD_BY_SDHC_VS; | |
959 | QIXIS_WRITE(pwr_ctl[1], value); | |
5a8dbdc6 YL |
960 | break; |
961 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: | |
962 | value = QIXIS_READ(brdcfg[5]); | |
963 | value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); | |
964 | QIXIS_WRITE(brdcfg[5], value); | |
965 | break; | |
966 | case QIXIS_ESDHC_ADAPTER_TYPE_RSV: | |
967 | break; | |
968 | case QIXIS_ESDHC_ADAPTER_TYPE_MMC: | |
969 | break; | |
970 | case QIXIS_ESDHC_ADAPTER_TYPE_SD: | |
971 | break; | |
972 | case QIXIS_ESDHC_NO_ADAPTER: | |
973 | break; | |
974 | default: | |
975 | break; | |
976 | } | |
977 | } | |
978 | #endif | |
979 | ||
c67bee14 | 980 | #ifdef CONFIG_OF_LIBFDT |
fce1e16c | 981 | __weak int esdhc_status_fixup(void *blob, const char *compat) |
b33433a6 | 982 | { |
a6da8b81 | 983 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
b33433a6 | 984 | if (!hwconfig("esdhc")) { |
a6da8b81 | 985 | do_fixup_by_compat(blob, compat, "status", "disabled", |
fce1e16c YL |
986 | sizeof("disabled"), 1); |
987 | return 1; | |
b33433a6 | 988 | } |
a6da8b81 | 989 | #endif |
fce1e16c YL |
990 | return 0; |
991 | } | |
992 | ||
993 | void fdt_fixup_esdhc(void *blob, bd_t *bd) | |
994 | { | |
995 | const char *compat = "fsl,esdhc"; | |
996 | ||
997 | if (esdhc_status_fixup(blob, compat)) | |
998 | return; | |
b33433a6 | 999 | |
2d9ca2c7 YL |
1000 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
1001 | do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", | |
1002 | gd->arch.sdhc_clk, 1); | |
1003 | #else | |
b33433a6 | 1004 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
e9adeca3 | 1005 | gd->arch.sdhc_clk, 1); |
2d9ca2c7 | 1006 | #endif |
5a8dbdc6 YL |
1007 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
1008 | do_fixup_by_compat_u32(blob, compat, "adapter-type", | |
1009 | (u32)(gd->arch.sdhc_adapter), 1); | |
1010 | #endif | |
b33433a6 | 1011 | } |
c67bee14 | 1012 | #endif |
96f0407b | 1013 | |
653282b5 | 1014 | #if CONFIG_IS_ENABLED(DM_MMC) |
96f0407b | 1015 | #include <asm/arch/clock.h> |
b60f1457 PF |
1016 | __weak void init_clk_usdhc(u32 index) |
1017 | { | |
1018 | } | |
1019 | ||
96f0407b PF |
1020 | static int fsl_esdhc_probe(struct udevice *dev) |
1021 | { | |
1022 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
e88e1d9c | 1023 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
96f0407b | 1024 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
9bb272e9 | 1025 | #ifdef CONFIG_DM_REGULATOR |
4483b7eb | 1026 | struct udevice *vqmmc_dev; |
9bb272e9 | 1027 | #endif |
96f0407b PF |
1028 | fdt_addr_t addr; |
1029 | unsigned int val; | |
653282b5 | 1030 | struct mmc *mmc; |
96f0407b PF |
1031 | int ret; |
1032 | ||
4aac33f5 | 1033 | addr = dev_read_addr(dev); |
96f0407b PF |
1034 | if (addr == FDT_ADDR_T_NONE) |
1035 | return -EINVAL; | |
1036 | ||
1037 | priv->esdhc_regs = (struct fsl_esdhc *)addr; | |
1038 | priv->dev = dev; | |
1039 | ||
4aac33f5 | 1040 | val = dev_read_u32_default(dev, "bus-width", -1); |
96f0407b PF |
1041 | if (val == 8) |
1042 | priv->bus_width = 8; | |
1043 | else if (val == 4) | |
1044 | priv->bus_width = 4; | |
1045 | else | |
1046 | priv->bus_width = 1; | |
1047 | ||
4aac33f5 | 1048 | if (dev_read_bool(dev, "non-removable")) { |
96f0407b PF |
1049 | priv->non_removable = 1; |
1050 | } else { | |
1051 | priv->non_removable = 0; | |
fc8048a8 | 1052 | #ifdef CONFIG_DM_GPIO |
4aac33f5 SG |
1053 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, |
1054 | GPIOD_IS_IN); | |
fc8048a8 | 1055 | #endif |
96f0407b PF |
1056 | } |
1057 | ||
1483151e PF |
1058 | priv->wp_enable = 1; |
1059 | ||
fc8048a8 | 1060 | #ifdef CONFIG_DM_GPIO |
4aac33f5 SG |
1061 | ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, |
1062 | GPIOD_IS_IN); | |
1483151e PF |
1063 | if (ret) |
1064 | priv->wp_enable = 0; | |
fc8048a8 | 1065 | #endif |
4483b7eb PF |
1066 | |
1067 | priv->vs18_enable = 0; | |
1068 | ||
1069 | #ifdef CONFIG_DM_REGULATOR | |
1070 | /* | |
1071 | * If emmc I/O has a fixed voltage at 1.8V, this must be provided, | |
1072 | * otherwise, emmc will work abnormally. | |
1073 | */ | |
1074 | ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); | |
1075 | if (ret) { | |
1076 | dev_dbg(dev, "no vqmmc-supply\n"); | |
1077 | } else { | |
1078 | ret = regulator_set_enable(vqmmc_dev, true); | |
1079 | if (ret) { | |
1080 | dev_err(dev, "fail to enable vqmmc-supply\n"); | |
1081 | return ret; | |
1082 | } | |
1083 | ||
1084 | if (regulator_get_value(vqmmc_dev) == 1800000) | |
1085 | priv->vs18_enable = 1; | |
1086 | } | |
1087 | #endif | |
1088 | ||
96f0407b PF |
1089 | /* |
1090 | * TODO: | |
1091 | * Because lack of clk driver, if SDHC clk is not enabled, | |
1092 | * need to enable it first before this driver is invoked. | |
1093 | * | |
1094 | * we use MXC_ESDHC_CLK to get clk freq. | |
1095 | * If one would like to make this function work, | |
1096 | * the aliases should be provided in dts as this: | |
1097 | * | |
1098 | * aliases { | |
1099 | * mmc0 = &usdhc1; | |
1100 | * mmc1 = &usdhc2; | |
1101 | * mmc2 = &usdhc3; | |
1102 | * mmc3 = &usdhc4; | |
1103 | * }; | |
1104 | * Then if your board only supports mmc2 and mmc3, but we can | |
1105 | * correctly get the seq as 2 and 3, then let mxc_get_clock | |
1106 | * work as expected. | |
1107 | */ | |
b60f1457 PF |
1108 | |
1109 | init_clk_usdhc(dev->seq); | |
1110 | ||
96f0407b PF |
1111 | priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); |
1112 | if (priv->sdhc_clk <= 0) { | |
1113 | dev_err(dev, "Unable to get clk for %s\n", dev->name); | |
1114 | return -EINVAL; | |
1115 | } | |
1116 | ||
e88e1d9c | 1117 | ret = fsl_esdhc_init(priv, plat); |
96f0407b PF |
1118 | if (ret) { |
1119 | dev_err(dev, "fsl_esdhc_init failure\n"); | |
1120 | return ret; | |
1121 | } | |
1122 | ||
653282b5 SG |
1123 | mmc = &plat->mmc; |
1124 | mmc->cfg = &plat->cfg; | |
1125 | mmc->dev = dev; | |
1126 | upriv->mmc = mmc; | |
96f0407b | 1127 | |
653282b5 | 1128 | return esdhc_init_common(priv, mmc); |
96f0407b PF |
1129 | } |
1130 | ||
e7881d85 | 1131 | #if CONFIG_IS_ENABLED(DM_MMC) |
653282b5 SG |
1132 | static int fsl_esdhc_get_cd(struct udevice *dev) |
1133 | { | |
1134 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); | |
1135 | ||
1136 | return true; | |
1137 | return esdhc_getcd_common(priv); | |
1138 | } | |
1139 | ||
1140 | static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, | |
1141 | struct mmc_data *data) | |
1142 | { | |
1143 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); | |
1144 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); | |
1145 | ||
1146 | return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); | |
1147 | } | |
1148 | ||
1149 | static int fsl_esdhc_set_ios(struct udevice *dev) | |
1150 | { | |
1151 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); | |
1152 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); | |
1153 | ||
1154 | return esdhc_set_ios_common(priv, &plat->mmc); | |
1155 | } | |
1156 | ||
1157 | static const struct dm_mmc_ops fsl_esdhc_ops = { | |
1158 | .get_cd = fsl_esdhc_get_cd, | |
1159 | .send_cmd = fsl_esdhc_send_cmd, | |
1160 | .set_ios = fsl_esdhc_set_ios, | |
1161 | }; | |
1162 | #endif | |
1163 | ||
96f0407b PF |
1164 | static const struct udevice_id fsl_esdhc_ids[] = { |
1165 | { .compatible = "fsl,imx6ul-usdhc", }, | |
1166 | { .compatible = "fsl,imx6sx-usdhc", }, | |
1167 | { .compatible = "fsl,imx6sl-usdhc", }, | |
1168 | { .compatible = "fsl,imx6q-usdhc", }, | |
1169 | { .compatible = "fsl,imx7d-usdhc", }, | |
b60f1457 | 1170 | { .compatible = "fsl,imx7ulp-usdhc", }, |
a6473f8e | 1171 | { .compatible = "fsl,esdhc", }, |
96f0407b PF |
1172 | { /* sentinel */ } |
1173 | }; | |
1174 | ||
653282b5 SG |
1175 | #if CONFIG_IS_ENABLED(BLK) |
1176 | static int fsl_esdhc_bind(struct udevice *dev) | |
1177 | { | |
1178 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); | |
1179 | ||
1180 | return mmc_bind(dev, &plat->mmc, &plat->cfg); | |
1181 | } | |
1182 | #endif | |
1183 | ||
96f0407b PF |
1184 | U_BOOT_DRIVER(fsl_esdhc) = { |
1185 | .name = "fsl-esdhc-mmc", | |
1186 | .id = UCLASS_MMC, | |
1187 | .of_match = fsl_esdhc_ids, | |
653282b5 | 1188 | .ops = &fsl_esdhc_ops, |
653282b5 SG |
1189 | #if CONFIG_IS_ENABLED(BLK) |
1190 | .bind = fsl_esdhc_bind, | |
1191 | #endif | |
96f0407b | 1192 | .probe = fsl_esdhc_probe, |
e88e1d9c | 1193 | .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), |
96f0407b PF |
1194 | .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), |
1195 | }; | |
1196 | #endif |