[people/ms/u-boot.git] / drivers / mtd / nand / davinci_nand.c

/*
 * NAND driver for TI DaVinci based boards.
 *
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
 */

/*
 *
 * linux/drivers/mtd/nand/nand_davinci.c
 *
 * NAND Flash Driver
 *
 * Copyright (C) 2006 Texas Instruments.
 *
 * ----------------------------------------------------------------------------
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * ----------------------------------------------------------------------------
 *
 *  Overview:
 *   This is a device driver for the NAND flash device found on the
 *   DaVinci board which utilizes the Samsung k9k2g08 part.
 *
 Modifications:
 ver. 1.0: Feb 2005, Vinod/Sudhakar
 -
 */

#include <common.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emif_defs.h>

/* Definitions for 4-bit hardware ECC */
#define NAND_TIMEOUT			10240
#define NAND_ECC_BUSY			0xC
#define NAND_4BITECC_MASK		0x03FF03FF
#define EMIF_NANDFSR_ECC_STATE_MASK  	0x00000F00
#define ECC_STATE_NO_ERR		0x0
#define ECC_STATE_TOO_MANY_ERRS		0x1
#define ECC_STATE_ERR_CORR_COMP_P	0x2
#define ECC_STATE_ERR_CORR_COMP_N	0x3

/*
 * Exploit the little endianness of the ARM to do multi-byte transfers
 * per device read. This can perform over twice as quickly as individual
 * byte transfers when buffer alignment is conducive.
 *
 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
 * the address bus. On Davinci EVM platforms this has always been true.
 */
static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct nand_chip *chip = mtd->priv;
	const u32 *nand = chip->IO_ADDR_R;

	/* Make sure that buf is 32 bit aligned */
	if (((int)buf & 0x3) != 0) {
		if (((int)buf & 0x1) != 0) {
			if (len) {
				*buf = readb(nand);
				buf += 1;
				len--;
			}
		}

		if (((int)buf & 0x3) != 0) {
			if (len >= 2) {
				*(u16 *)buf = readw(nand);
				buf += 2;
				len -= 2;
			}
		}
	}

	/* copy aligned data */
	while (len >= 4) {
		*(u32 *)buf = __raw_readl(nand);
		buf += 4;
		len -= 4;
	}

	/* mop up any remaining bytes */
	if (len) {
		if (len >= 2) {
			*(u16 *)buf = readw(nand);
			buf += 2;
			len -= 2;
		}

		if (len)
			*buf = readb(nand);
	}
}

static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
				   int len)
{
	struct nand_chip *chip = mtd->priv;
	const u32 *nand = chip->IO_ADDR_W;

	/* Make sure that buf is 32 bit aligned */
	if (((int)buf & 0x3) != 0) {
		if (((int)buf & 0x1) != 0) {
			if (len) {
				writeb(*buf, nand);
				buf += 1;
				len--;
			}
		}

		if (((int)buf & 0x3) != 0) {
			if (len >= 2) {
				writew(*(u16 *)buf, nand);
				buf += 2;
				len -= 2;
			}
		}
	}

	/* copy aligned data */
	while (len >= 4) {
		__raw_writel(*(u32 *)buf, nand);
		buf += 4;
		len -= 4;
	}

	/* mop up any remaining bytes */
	if (len) {
		if (len >= 2) {
			writew(*(u16 *)buf, nand);
			buf += 2;
			len -= 2;
		}

		if (len)
			writeb(*buf, nand);
	}
}

static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
		unsigned int ctrl)
{
	struct		nand_chip *this = mtd->priv;
	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;

	if (ctrl & NAND_CTRL_CHANGE) {
		IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);

		if (ctrl & NAND_CLE)
			IO_ADDR_W |= MASK_CLE;
		if (ctrl & NAND_ALE)
			IO_ADDR_W |= MASK_ALE;
		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
	}

	if (cmd != NAND_CMD_NONE)
		writeb(cmd, IO_ADDR_W);
}

#ifdef CONFIG_SYS_NAND_HW_ECC

static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
{
	u_int32_t	ecc = 0;

	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
				CONFIG_SYS_NAND_CS - 2]));

	return ecc;
}

static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
	u_int32_t	val;

	/* reading the ECC result register resets the ECC calculation */
	nand_davinci_readecc(mtd);

	val = __raw_readl(&davinci_emif_regs->nandfcr);
	val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
	__raw_writel(val, &davinci_emif_regs->nandfcr);
}

static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
		u_char *ecc_code)
{
	u_int32_t		tmp;

	tmp = nand_davinci_readecc(mtd);

	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
	 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
	tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);

	/* Invert so that erased block ECC is correct */
	tmp = ~tmp;

	*ecc_code++ = tmp;
	*ecc_code++ = tmp >>  8;
	*ecc_code++ = tmp >> 16;

	/* NOTE:  the above code matches mainline Linux:
	 *	.PQR.stu ==> ~PQRstu
	 *
	 * MontaVista/TI kernels encode those bytes differently, use
	 * complicated (and allegedly sometimes-wrong) correction code,
	 * and usually shipped with U-Boot that uses software ECC:
	 *	.PQR.stu ==> PsQRtu
	 *
	 * If you need MV/TI compatible NAND I/O in U-Boot, it should
	 * be possible to (a) change the mangling above, (b) reverse
	 * that mangling in nand_davinci_correct_data() below.
	 */

	return 0;
}

static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
		u_char *read_ecc, u_char *calc_ecc)
{
	struct nand_chip *this = mtd->priv;
	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
					  (read_ecc[2] << 16);
	u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
					  (calc_ecc[2] << 16);
	u_int32_t diff = ecc_calc ^ ecc_nand;

	if (diff) {
		if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
			/* Correctable error */
			if ((diff >> (12 + 3)) < this->ecc.size) {
				uint8_t find_bit = 1 << ((diff >> 12) & 7);
				uint32_t find_byte = diff >> (12 + 3);

				dat[find_byte] ^= find_bit;
				MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
					 "bit ECC error at offset: %d, bit: "
					 "%d\n", find_byte, find_bit);
				return 1;
			} else {
				return -1;
			}
		} else if (!(diff & (diff - 1))) {
			/* Single bit ECC error in the ECC itself,
			   nothing to fix */
			MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
				 "ECC.\n");
			return 1;
		} else {
			/* Uncorrectable error */
			MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
			return -1;
		}
	}
	return 0;
}
#endif /* CONFIG_SYS_NAND_HW_ECC */

#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
#if defined(CONFIG_SYS_NAND_PAGE_2K)
	.eccbytes = 40,
	.eccpos = {
		24, 25, 26, 27, 28,
		29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
		39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
		49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
		59, 60, 61, 62, 63,
		},
	.oobfree = {
		{.offset = 2, .length = 22, },
	},
#elif defined(CONFIG_SYS_NAND_PAGE_4K)
	.eccbytes = 80,
	.eccpos = {
		48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
		58, 59, 60, 61, 62, 63,	64, 65, 66, 67,
		68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
		78, 79,	80, 81, 82, 83,	84, 85, 86, 87,
		88, 89, 90, 91, 92, 93,	94, 95, 96, 97,
		98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
		108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
		118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
		},
	.oobfree = {
		{.offset = 2, .length = 46, },
	},
#endif
};

static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{
	u32 val;

	switch (mode) {
	case NAND_ECC_WRITE:
	case NAND_ECC_READ:
		/*
		 * Start a new ECC calculation for reading or writing 512 bytes
		 * of data.
		 */
		val = __raw_readl(&davinci_emif_regs->nandfcr);
		val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
		val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
		val |= DAVINCI_NANDFCR_4BIT_ECC_START;
		__raw_writel(val, &davinci_emif_regs->nandfcr);
		break;
	case NAND_ECC_READSYN:
		val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
		break;
	default:
		break;
	}
}

static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
{
	int i;

	for (i = 0; i < 4; i++) {
		ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
			NAND_4BITECC_MASK;
	}

	return 0;
}

static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
					   const uint8_t *dat,
					   uint8_t *ecc_code)
{
	unsigned int hw_4ecc[4];
	unsigned int i;

	nand_davinci_4bit_readecc(mtd, hw_4ecc);

	/*Convert 10 bit ecc value to 8 bit */
	for (i = 0; i < 2; i++) {
		unsigned int hw_ecc_low = hw_4ecc[i * 2];
		unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];

		/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
		*ecc_code++ = hw_ecc_low & 0xFF;

		/*
		 * Take 2 bits as LSB bits from val1 (count1=0) or val5
		 * (count1=1) and 6 bits from val2 (count1=0) or
		 * val5 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);

		/*
		 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
		 * 4 bits from val3 (count1=0) or val6 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);

		/*
		 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
		 * 2 bits from val4 (count1=0) or  val7 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);

		/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
		*ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
	}

	return 0;
}

static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
					  uint8_t *read_ecc, uint8_t *calc_ecc)
{
	int i;
	unsigned int hw_4ecc[4];
	unsigned int iserror;
	unsigned short *ecc16;
	unsigned int numerrors, erroraddress, errorvalue;
	u32 val;

	/*
	 * Check for an ECC where all bytes are 0xFF.  If this is the case, we
	 * will assume we are looking at an erased page and we should ignore
	 * the ECC.
	 */
	for (i = 0; i < 10; i++) {
		if (read_ecc[i] != 0xFF)
			break;
	}
	if (i == 10)
		return 0;

	/* Convert 8 bit in to 10 bit */
	ecc16 = (unsigned short *)&read_ecc[0];

	/*
	 * Write the parity values in the NAND Flash 4-bit ECC Load register.
	 * Write each parity value one at a time starting from 4bit_ecc_val8
	 * to 4bit_ecc_val1.
	 */

	/*Take 2 bits from 8th byte and 8 bits from 9th byte */
	__raw_writel(((ecc16[4]) >> 6) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
	__raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
			&davinci_emif_regs->nand4biteccload);

	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
	__raw_writel((ecc16[3] >> 2) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
	__raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
			&davinci_emif_regs->nand4biteccload);

	/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
	__raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
			&davinci_emif_regs->nand4biteccload);

	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
	__raw_writel(((ecc16[1]) >> 4) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
	__raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
			&davinci_emif_regs->nand4biteccload);

	/* Take 10 bits from 0th and 1st bytes */
	__raw_writel((ecc16[0]) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/*
	 * Perform a dummy read to the EMIF Revision Code and Status register.
	 * This is required to ensure time for syndrome calculation after
	 * writing the ECC values in previous step.
	 */

	val = __raw_readl(&davinci_emif_regs->nandfsr);

	/*
	 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
	 * A syndrome value of 0 means no bit errors. If the syndrome is
	 * non-zero then go further otherwise return.
	 */
	nand_davinci_4bit_readecc(mtd, hw_4ecc);

	if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
		return 0;

	/*
	 * Clear any previous address calculation by doing a dummy read of an
	 * error address register.
	 */
	val = __raw_readl(&davinci_emif_regs->nanderradd1);

	/*
	 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
	 * register to 1.
	 */
	__raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
			&davinci_emif_regs->nandfcr);

	/*
	 * Wait for the corr_state field (bits 8 to 11) in the
	 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
	 * Otherwise ECC calculation has not even begun and the next loop might
	 * fail because of a false positive!
	 */
	i = NAND_TIMEOUT;
	do {
		val = __raw_readl(&davinci_emif_regs->nandfsr);
		val &= 0xc00;
		i--;
	} while ((i > 0) && !val);

	/*
	 * Wait for the corr_state field (bits 8 to 11) in the
	 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
	 */
	i = NAND_TIMEOUT;
	do {
		val = __raw_readl(&davinci_emif_regs->nandfsr);
		val &= 0xc00;
		i--;
	} while ((i > 0) && val);

	iserror = __raw_readl(&davinci_emif_regs->nandfsr);
	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
	iserror = iserror >> 8;

	/*
	 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
	 * corrected (five or more errors).  The number of errors
	 * calculated (err_num field) differs from the number of errors
	 * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
	 * correction complete (errors on bit 8 or 9).
	 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
	 * complete (error exists).
	 */

	if (iserror == ECC_STATE_NO_ERR) {
		val = __raw_readl(&davinci_emif_regs->nanderrval1);
		return 0;
	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
		val = __raw_readl(&davinci_emif_regs->nanderrval1);
		return -1;
	}

	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
			& 0x3) + 1;

	/* Read the error address, error value and correct */
	for (i = 0; i < numerrors; i++) {
		if (i > 1) {
			erroraddress =
			    ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
			      (16 * (i & 1))) & 0x3FF);
			erroraddress = ((512 + 7) - erroraddress);
			errorvalue =
			    ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
			      (16 * (i & 1))) & 0xFF);
		} else {
			erroraddress =
			    ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
			      (16 * (i & 1))) & 0x3FF);
			erroraddress = ((512 + 7) - erroraddress);
			errorvalue =
			    ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
			      (16 * (i & 1))) & 0xFF);
		}
		/* xor the corrupt data with error value */
		if (erroraddress < 512)
			dat[erroraddress] ^= errorvalue;
	}

	return numerrors;
}
#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */

static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
	return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
}

static void nand_flash_init(void)
{
	/* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
	 * Instead, have your board_init() set EMIF timings, based on its
	 * knowledge of the clocks and what devices are hooked up ... and
	 * don't even do that unless no UBL handled it.
	 */
#ifdef CONFIG_SOC_DM644X
	u_int32_t	acfg1 = 0x3ffffffc;

	/*------------------------------------------------------------------*
	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
	 *                                                                  *
	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
	 *                                                                  *
	 *------------------------------------------------------------------*/
	 acfg1 = 0
		| (0 << 31)	/* selectStrobe */
		| (0 << 30)	/* extWait */
		| (1 << 26)	/* writeSetup	10 ns */
		| (3 << 20)	/* writeStrobe	40 ns */
		| (1 << 17)	/* writeHold	10 ns */
		| (1 << 13)	/* readSetup	10 ns */
		| (5 << 7)	/* readStrobe	60 ns */
		| (1 << 4)	/* readHold	10 ns */
		| (3 << 2)	/* turnAround	?? ns */
		| (0 << 0)	/* asyncSize	8-bit bus */
		;

	__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */

	/* NAND flash on CS2 */
	__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
#endif
}

void davinci_nand_init(struct nand_chip *nand)
{
	nand->chip_delay  = 0;
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
	nand->bbt_options	  |= NAND_BBT_USE_FLASH;
#endif
#ifdef CONFIG_SYS_NAND_HW_ECC
	nand->ecc.mode = NAND_ECC_HW;
	nand->ecc.size = 512;
	nand->ecc.bytes = 3;
	nand->ecc.strength = 1;
	nand->ecc.calculate = nand_davinci_calculate_ecc;
	nand->ecc.correct  = nand_davinci_correct_data;
	nand->ecc.hwctl  = nand_davinci_enable_hwecc;
#else
	nand->ecc.mode = NAND_ECC_SOFT;
#endif /* CONFIG_SYS_NAND_HW_ECC */
#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
	nand->ecc.size = 512;
	nand->ecc.bytes = 10;
	nand->ecc.strength = 4;
	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
	nand->ecc.correct = nand_davinci_4bit_correct_data;
	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
#endif
	/* Set address of hardware control function */
	nand->cmd_ctrl = nand_davinci_hwcontrol;

	nand->read_buf = nand_davinci_read_buf;
	nand->write_buf = nand_davinci_write_buf;

	nand->dev_ready = nand_davinci_dev_ready;

	nand_flash_init();
}

int board_nand_init(struct nand_chip *chip) __attribute__((weak));

int board_nand_init(struct nand_chip *chip)
{
	davinci_nand_init(chip);
	return 0;
}
Commit	Line	Data
c74b2108 SK	1	/*
	2	* NAND driver for TI DaVinci based boards.
	3	*
	4	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	5	*
	6	* Based on Linux DaVinci NAND driver by TI. Original copyright follows:
	7	*/
	8
	9	/*
	10	*
	11	* linux/drivers/mtd/nand/nand_davinci.c
	12	*
	13	* NAND Flash Driver
	14	*
	15	* Copyright (C) 2006 Texas Instruments.
	16	*
	17	* ----------------------------------------------------------------------------
	18	*
1a459660 WD	19	* SPDX-License-Identifier: GPL-2.0+
1a459660 WD	20	*
c74b2108 SK	21	* ----------------------------------------------------------------------------
	22	*
	23	* Overview:
	24	* This is a device driver for the NAND flash device found on the
	25	* DaVinci board which utilizes the Samsung k9k2g08 part.
	26	*
	27	Modifications:
	28	ver. 1.0: Feb 2005, Vinod/Sudhakar
	29	-
c74b2108 SK	30	*/
	31
	32	#include <common.h>
cfa460ad	33	#include <asm/io.h>
c74b2108 SK	34	#include <nand.h>
	35	#include <asm/arch/nand_defs.h>
	36	#include <asm/arch/emif_defs.h>
	37
77b351cd SP	38	/* Definitions for 4-bit hardware ECC */
	39	#define NAND_TIMEOUT 10240
	40	#define NAND_ECC_BUSY 0xC
	41	#define NAND_4BITECC_MASK 0x03FF03FF
	42	#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
	43	#define ECC_STATE_NO_ERR 0x0
	44	#define ECC_STATE_TOO_MANY_ERRS 0x1
	45	#define ECC_STATE_ERR_CORR_COMP_P 0x2
	46	#define ECC_STATE_ERR_CORR_COMP_N 0x3
	47
20da6f4d NT	48	/*
	49	* Exploit the little endianness of the ARM to do multi-byte transfers
	50	* per device read. This can perform over twice as quickly as individual
	51	* byte transfers when buffer alignment is conducive.
	52	*
	53	* NOTE: This only works if the NAND is not connected to the 2 LSBs of
	54	* the address bus. On Davinci EVM platforms this has always been true.
	55	*/
	56	static void nand_davinci_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	57	{
	58	struct nand_chip *chip = mtd->priv;
	59	const u32 *nand = chip->IO_ADDR_R;
	60
	61	/* Make sure that buf is 32 bit aligned */
	62	if (((int)buf & 0x3) != 0) {
	63	if (((int)buf & 0x1) != 0) {
	64	if (len) {
	65	*buf = readb(nand);
	66	buf += 1;
	67	len--;
	68	}
	69	}
	70
	71	if (((int)buf & 0x3) != 0) {
	72	if (len >= 2) {
	73	(u16 )buf = readw(nand);
	74	buf += 2;
	75	len -= 2;
	76	}
	77	}
	78	}
	79
	80	/* copy aligned data */
	81	while (len >= 4) {
cc41a59a	82	(u32 )buf = __raw_readl(nand);
20da6f4d NT	83	buf += 4;
	84	len -= 4;
	85	}
	86
	87	/* mop up any remaining bytes */
	88	if (len) {
	89	if (len >= 2) {
	90	(u16 )buf = readw(nand);
	91	buf += 2;
	92	len -= 2;
	93	}
	94
	95	if (len)
	96	*buf = readb(nand);
	97	}
	98	}
	99
	100	static void nand_davinci_write_buf(struct mtd_info mtd, const uint8_t buf,
	101	int len)
	102	{
	103	struct nand_chip *chip = mtd->priv;
	104	const u32 *nand = chip->IO_ADDR_W;
	105
	106	/* Make sure that buf is 32 bit aligned */
	107	if (((int)buf & 0x3) != 0) {
	108	if (((int)buf & 0x1) != 0) {
	109	if (len) {
	110	writeb(*buf, nand);
	111	buf += 1;
	112	len--;
	113	}
	114	}
	115
	116	if (((int)buf & 0x3) != 0) {
	117	if (len >= 2) {
	118	writew((u16 )buf, nand);
	119	buf += 2;
	120	len -= 2;
	121	}
	122	}
	123	}
	124
	125	/* copy aligned data */
	126	while (len >= 4) {
cc41a59a	127	__raw_writel((u32 )buf, nand);
20da6f4d NT	128	buf += 4;
	129	len -= 4;
	130	}
	131
	132	/* mop up any remaining bytes */
	133	if (len) {
	134	if (len >= 2) {
	135	writew((u16 )buf, nand);
	136	buf += 2;
	137	len -= 2;
	138	}
	139
	140	if (len)
	141	writeb(*buf, nand);
	142	}
	143	}
	144
cc41a59a CC	145	static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
cc41a59a CC	146	unsigned int ctrl)
c74b2108 SK	147	{
	148	struct nand_chip *this = mtd->priv;
	149	u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
	150
cfa460ad	151	if (ctrl & NAND_CTRL_CHANGE) {
20da6f4d NT	152	IO_ADDR_W &= ~(MASK_ALE\|MASK_CLE);
20da6f4d NT	153
cc41a59a	154	if (ctrl & NAND_CLE)
c74b2108	155	IO_ADDR_W \|= MASK_CLE;
cc41a59a	156	if (ctrl & NAND_ALE)
c74b2108	157	IO_ADDR_W \|= MASK_ALE;
cfa460ad	158	this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
c74b2108 SK	159	}
c74b2108 SK	160
5e1dae5c	161	if (cmd != NAND_CMD_NONE)
20da6f4d	162	writeb(cmd, IO_ADDR_W);
c74b2108 SK	163	}
c74b2108 SK	164
6d0f6bcf	165	#ifdef CONFIG_SYS_NAND_HW_ECC
c74b2108	166
60161943	167	static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
c74b2108	168	{
60161943	169	u_int32_t ecc = 0;
c74b2108	170
60161943	171	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
cc41a59a	172	CONFIG_SYS_NAND_CS - 2]));
c74b2108	173
60161943	174	return ecc;
c74b2108 SK	175	}
c74b2108 SK	176
60161943	177	static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
c74b2108	178	{
60161943	179	u_int32_t val;
c74b2108	180
60161943 LW	181	/* reading the ECC result register resets the ECC calculation */
60161943 LW	182	nand_davinci_readecc(mtd);
c74b2108	183
60161943 LW	184	val = __raw_readl(&davinci_emif_regs->nandfcr);
	185	val \|= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
	186	val \|= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
	187	__raw_writel(val, &davinci_emif_regs->nandfcr);
c74b2108 SK	188	}
c74b2108 SK	189
cc41a59a CC	190	static int nand_davinci_calculate_ecc(struct mtd_info mtd, const u_char dat,
cc41a59a CC	191	u_char *ecc_code)
c74b2108 SK	192	{
c74b2108 SK	193	u_int32_t tmp;
9b05aa78	194
60161943	195	tmp = nand_davinci_readecc(mtd);
9b05aa78 HV	196
	197	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
	198	* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
	199	tmp = (tmp & 0x00000fff) \| ((tmp & 0x0fff0000) >> 4);
	200
	201	/* Invert so that erased block ECC is correct */
	202	tmp = ~tmp;
	203
	204	*ecc_code++ = tmp;
	205	*ecc_code++ = tmp >> 8;
	206	*ecc_code++ = tmp >> 16;
c74b2108	207
6e29ed8e DB	208	/* NOTE: the above code matches mainline Linux:
	209	* .PQR.stu ==> ~PQRstu
	210	*
	211	* MontaVista/TI kernels encode those bytes differently, use
	212	* complicated (and allegedly sometimes-wrong) correction code,
	213	* and usually shipped with U-Boot that uses software ECC:
	214	* .PQR.stu ==> PsQRtu
	215	*
	216	* If you need MV/TI compatible NAND I/O in U-Boot, it should
	217	* be possible to (a) change the mangling above, (b) reverse
	218	* that mangling in nand_davinci_correct_data() below.
	219	*/
c74b2108	220
6e29ed8e	221	return 0;
c74b2108 SK	222	}
c74b2108 SK	223
cc41a59a CC	224	static int nand_davinci_correct_data(struct mtd_info mtd, u_char dat,
cc41a59a CC	225	u_char read_ecc, u_char calc_ecc)
c74b2108	226	{
9b05aa78	227	struct nand_chip *this = mtd->priv;
9b05aa78 HV	228	u_int32_t ecc_nand = read_ecc[0] \| (read_ecc[1] << 8) \|
	229	(read_ecc[2] << 16);
	230	u_int32_t ecc_calc = calc_ecc[0] \| (calc_ecc[1] << 8) \|
	231	(calc_ecc[2] << 16);
	232	u_int32_t diff = ecc_calc ^ ecc_nand;
	233
	234	if (diff) {
	235	if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
	236	/* Correctable error */
	237	if ((diff >> (12 + 3)) < this->ecc.size) {
	238	uint8_t find_bit = 1 << ((diff >> 12) & 7);
	239	uint32_t find_byte = diff >> (12 + 3);
	240
	241	dat[find_byte] ^= find_bit;
	242	MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
	243	"bit ECC error at offset: %d, bit: "
	244	"%d\n", find_byte, find_bit);
	245	return 1;
	246	} else {
	247	return -1;
	248	}
	249	} else if (!(diff & (diff - 1))) {
	250	/* Single bit ECC error in the ECC itself,
	251	nothing to fix */
	252	MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
	253	"ECC.\n");
	254	return 1;
	255	} else {
	256	/* Uncorrectable error */
	257	MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
	258	return -1;
	259	}
	260	}
cc41a59a	261	return 0;
c74b2108	262	}
6d0f6bcf	263	#endif /* CONFIG_SYS_NAND_HW_ECC */
c74b2108	264
77b351cd SP	265	#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
77b351cd SP	266	static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
10a5a799	267	#if defined(CONFIG_SYS_NAND_PAGE_2K)
77b351cd SP	268	.eccbytes = 40,
	269	.eccpos = {
	270	24, 25, 26, 27, 28,
	271	29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
	272	39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
	273	49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
	274	59, 60, 61, 62, 63,
	275	},
	276	.oobfree = {
	277	{.offset = 2, .length = 22, },
	278	},
10a5a799 SP	279	#elif defined(CONFIG_SYS_NAND_PAGE_4K)
	280	.eccbytes = 80,
	281	.eccpos = {
	282	48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
	283	58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
	284	68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
	285	78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
	286	88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
	287	98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
	288	108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
	289	118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
	290	},
	291	.oobfree = {
	292	{.offset = 2, .length = 46, },
	293	},
77b351cd SP	294	#endif
77b351cd SP	295	};
77b351cd SP	296
	297	static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
	298	{
	299	u32 val;
	300
	301	switch (mode) {
	302	case NAND_ECC_WRITE:
	303	case NAND_ECC_READ:
	304	/*
	305	* Start a new ECC calculation for reading or writing 512 bytes
	306	* of data.
	307	*/
cc41a59a	308	val = __raw_readl(&davinci_emif_regs->nandfcr);
97f4eb8c	309	val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
26be2c53	310	val \|= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
97f4eb8c NT	311	val \|= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
97f4eb8c NT	312	val \|= DAVINCI_NANDFCR_4BIT_ECC_START;
cc41a59a	313	__raw_writel(val, &davinci_emif_regs->nandfcr);
77b351cd SP	314	break;
77b351cd SP	315	case NAND_ECC_READSYN:
cc41a59a	316	val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
77b351cd SP	317	break;
	318	default:
	319	break;
	320	}
	321	}
	322
	323	static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
	324	{
cc41a59a CC	325	int i;
	326
	327	for (i = 0; i < 4; i++) {
	328	ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
	329	NAND_4BITECC_MASK;
	330	}
77b351cd SP	331
	332	return 0;
	333	}
	334
	335	static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
	336	const uint8_t *dat,
	337	uint8_t *ecc_code)
	338	{
20da6f4d NT	339	unsigned int hw_4ecc[4];
20da6f4d NT	340	unsigned int i;
77b351cd SP	341
	342	nand_davinci_4bit_readecc(mtd, hw_4ecc);
	343
	344	/Convert 10 bit ecc value to 8 bit /
20da6f4d NT	345	for (i = 0; i < 2; i++) {
	346	unsigned int hw_ecc_low = hw_4ecc[i * 2];
	347	unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
77b351cd SP	348
77b351cd SP	349	/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
20da6f4d	350	*ecc_code++ = hw_ecc_low & 0xFF;
77b351cd SP	351
	352	/*
	353	* Take 2 bits as LSB bits from val1 (count1=0) or val5
	354	* (count1=1) and 6 bits from val2 (count1=0) or
	355	* val5 (count1=1)
	356	*/
20da6f4d NT	357	*ecc_code++ =
20da6f4d NT	358	((hw_ecc_low >> 8) & 0x3) \| ((hw_ecc_low >> 14) & 0xFC);
77b351cd SP	359
	360	/*
	361	* Take 4 bits from val2 (count1=0) or val5 (count1=1) and
	362	* 4 bits from val3 (count1=0) or val6 (count1=1)
	363	*/
20da6f4d NT	364	*ecc_code++ =
20da6f4d NT	365	((hw_ecc_low >> 22) & 0xF) \| ((hw_ecc_hi << 4) & 0xF0);
77b351cd SP	366
	367	/*
	368	* Take 6 bits from val3(count1=0) or val6 (count1=1) and
	369	* 2 bits from val4 (count1=0) or val7 (count1=1)
	370	*/
20da6f4d NT	371	*ecc_code++ =
20da6f4d NT	372	((hw_ecc_hi >> 4) & 0x3F) \| ((hw_ecc_hi >> 10) & 0xC0);
77b351cd SP	373
77b351cd SP	374	/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
20da6f4d	375	*ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
77b351cd	376	}
20da6f4d	377
77b351cd SP	378	return 0;
	379	}
	380
77b351cd SP	381	static int nand_davinci_4bit_correct_data(struct mtd_info mtd, uint8_t dat,
	382	uint8_t read_ecc, uint8_t calc_ecc)
	383	{
77b351cd	384	int i;
20da6f4d NT	385	unsigned int hw_4ecc[4];
	386	unsigned int iserror;
	387	unsigned short *ecc16;
77b351cd SP	388	unsigned int numerrors, erroraddress, errorvalue;
	389	u32 val;
	390
	391	/*
	392	* Check for an ECC where all bytes are 0xFF. If this is the case, we
	393	* will assume we are looking at an erased page and we should ignore
	394	* the ECC.
	395	*/
	396	for (i = 0; i < 10; i++) {
	397	if (read_ecc[i] != 0xFF)
	398	break;
	399	}
	400	if (i == 10)
	401	return 0;
	402
	403	/* Convert 8 bit in to 10 bit */
20da6f4d	404	ecc16 = (unsigned short *)&read_ecc[0];
77b351cd	405
20da6f4d NT	406	/*
	407	* Write the parity values in the NAND Flash 4-bit ECC Load register.
	408	* Write each parity value one at a time starting from 4bit_ecc_val8
	409	* to 4bit_ecc_val1.
	410	*/
77b351cd	411
20da6f4d	412	/Take 2 bits from 8th byte and 8 bits from 9th byte /
cc41a59a CC	413	__raw_writel(((ecc16[4]) >> 6) & 0x3FF,
cc41a59a CC	414	&davinci_emif_regs->nand4biteccload);
77b351cd	415
20da6f4d	416	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
cc41a59a CC	417	__raw_writel((((ecc16[3]) >> 12) & 0xF) \| ((((ecc16[4])) << 4) & 0x3F0),
cc41a59a CC	418	&davinci_emif_regs->nand4biteccload);
77b351cd	419
20da6f4d	420	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
cc41a59a CC	421	__raw_writel((ecc16[3] >> 2) & 0x3FF,
cc41a59a CC	422	&davinci_emif_regs->nand4biteccload);
77b351cd SP	423
77b351cd SP	424	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
cc41a59a CC	425	__raw_writel(((ecc16[2]) >> 8) \| ((((ecc16[3])) << 8) & 0x300),
cc41a59a CC	426	&davinci_emif_regs->nand4biteccload);
77b351cd	427
20da6f4d	428	/Take 2 bits from 3rd byte and 8 bits from 4th byte /
cc41a59a CC	429	__raw_writel((((ecc16[1]) >> 14) & 0x3) \| ((((ecc16[2])) << 2) & 0x3FC),
cc41a59a CC	430	&davinci_emif_regs->nand4biteccload);
77b351cd	431
20da6f4d	432	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
cc41a59a CC	433	__raw_writel(((ecc16[1]) >> 4) & 0x3FF,
cc41a59a CC	434	&davinci_emif_regs->nand4biteccload);
77b351cd	435
20da6f4d	436	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
cc41a59a CC	437	__raw_writel((((ecc16[0]) >> 10) & 0x3F) \| (((ecc16[1]) << 6) & 0x3C0),
cc41a59a CC	438	&davinci_emif_regs->nand4biteccload);
77b351cd	439
20da6f4d	440	/* Take 10 bits from 0th and 1st bytes */
cc41a59a CC	441	__raw_writel((ecc16[0]) & 0x3FF,
cc41a59a CC	442	&davinci_emif_regs->nand4biteccload);
77b351cd SP	443
	444	/*
	445	* Perform a dummy read to the EMIF Revision Code and Status register.
	446	* This is required to ensure time for syndrome calculation after
	447	* writing the ECC values in previous step.
	448	*/
	449
cc41a59a	450	val = __raw_readl(&davinci_emif_regs->nandfsr);
77b351cd SP	451
	452	/*
	453	* Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
	454	* A syndrome value of 0 means no bit errors. If the syndrome is
	455	* non-zero then go further otherwise return.
	456	*/
	457	nand_davinci_4bit_readecc(mtd, hw_4ecc);
	458
20da6f4d	459	if (!(hw_4ecc[0] \| hw_4ecc[1] \| hw_4ecc[2] \| hw_4ecc[3]))
77b351cd SP	460	return 0;
	461
	462	/*
	463	* Clear any previous address calculation by doing a dummy read of an
	464	* error address register.
	465	*/
cc41a59a	466	val = __raw_readl(&davinci_emif_regs->nanderradd1);
77b351cd SP	467
	468	/*
	469	* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
	470	* register to 1.
	471	*/
10d6ac94 BG	472	__raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
10d6ac94 BG	473	&davinci_emif_regs->nandfcr);
77b351cd SP	474
77b351cd SP	475	/*
1075b07e WS	476	* Wait for the corr_state field (bits 8 to 11) in the
	477	* NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
	478	* Otherwise ECC calculation has not even begun and the next loop might
	479	* fail because of a false positive!
	480	*/
	481	i = NAND_TIMEOUT;
	482	do {
	483	val = __raw_readl(&davinci_emif_regs->nandfsr);
	484	val &= 0xc00;
	485	i--;
	486	} while ((i > 0) && !val);
	487
	488	/*
	489	* Wait for the corr_state field (bits 8 to 11) in the
77b351cd SP	490	* NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
	491	*/
	492	i = NAND_TIMEOUT;
	493	do {
cc41a59a	494	val = __raw_readl(&davinci_emif_regs->nandfsr);
77b351cd SP	495	val &= 0xc00;
	496	i--;
	497	} while ((i > 0) && val);
	498
cc41a59a	499	iserror = __raw_readl(&davinci_emif_regs->nandfsr);
77b351cd SP	500	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
	501	iserror = iserror >> 8;
	502
	503	/*
	504	* ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
	505	* corrected (five or more errors). The number of errors
	506	* calculated (err_num field) differs from the number of errors
	507	* searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
	508	* correction complete (errors on bit 8 or 9).
	509	* ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
	510	* complete (error exists).
	511	*/
	512
	513	if (iserror == ECC_STATE_NO_ERR) {
cc41a59a	514	val = __raw_readl(&davinci_emif_regs->nanderrval1);
77b351cd SP	515	return 0;
77b351cd SP	516	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
cc41a59a	517	val = __raw_readl(&davinci_emif_regs->nanderrval1);
77b351cd SP	518	return -1;
	519	}
	520
cc41a59a CC	521	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
cc41a59a CC	522	& 0x3) + 1;
77b351cd SP	523
	524	/* Read the error address, error value and correct */
	525	for (i = 0; i < numerrors; i++) {
	526	if (i > 1) {
	527	erroraddress =
cc41a59a	528	((__raw_readl(&davinci_emif_regs->nanderradd2) >>
77b351cd SP	529	(16 * (i & 1))) & 0x3FF);
	530	erroraddress = ((512 + 7) - erroraddress);
	531	errorvalue =
cc41a59a	532	((__raw_readl(&davinci_emif_regs->nanderrval2) >>
77b351cd SP	533	(16 * (i & 1))) & 0xFF);
	534	} else {
	535	erroraddress =
cc41a59a	536	((__raw_readl(&davinci_emif_regs->nanderradd1) >>
77b351cd SP	537	(16 * (i & 1))) & 0x3FF);
	538	erroraddress = ((512 + 7) - erroraddress);
	539	errorvalue =
cc41a59a	540	((__raw_readl(&davinci_emif_regs->nanderrval1) >>
77b351cd SP	541	(16 * (i & 1))) & 0xFF);
	542	}
	543	/* xor the corrupt data with error value */
	544	if (erroraddress < 512)
	545	dat[erroraddress] ^= errorvalue;
	546	}
	547
	548	return numerrors;
	549	}
d44e9c17	550	#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
77b351cd	551
c74b2108 SK	552	static int nand_davinci_dev_ready(struct mtd_info *mtd)
c74b2108 SK	553	{
cc41a59a	554	return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
c74b2108 SK	555	}
	556
	557	static void nand_flash_init(void)
	558	{
fcb77477 DB	559	/* This is for DM6446 EVM and very similar. DO NOT GROW THIS!
	560	* Instead, have your board_init() set EMIF timings, based on its
	561	* knowledge of the clocks and what devices are hooked up ... and
	562	* don't even do that unless no UBL handled it.
	563	*/
ed727d39	564	#ifdef CONFIG_SOC_DM644X
950a3924	565	u_int32_t acfg1 = 0x3ffffffc;
950a3924 WD	566
	567	/------------------------------------------------------------------
	568	* NAND FLASH CHIP TIMEOUT @ 459 MHz *
	569	* *
	570	* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
	571	* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
	572	* *
	573	------------------------------------------------------------------/
	574	acfg1 = 0
cc41a59a CC	575	\| (0 << 31) /* selectStrobe */
	576	\| (0 << 30) /* extWait */
	577	\| (1 << 26) /* writeSetup 10 ns */
	578	\| (3 << 20) /* writeStrobe 40 ns */
	579	\| (1 << 17) /* writeHold 10 ns */
	580	\| (1 << 13) /* readSetup 10 ns */
	581	\| (5 << 7) /* readStrobe 60 ns */
	582	\| (1 << 4) /* readHold 10 ns */
	583	\| (3 << 2) /* turnAround ?? ns */
	584	\| (0 << 0) /* asyncSize 8-bit bus */
53677ef1	585	;
950a3924	586
cc41a59a	587	__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
d583ef51	588
cc41a59a CC	589	/* NAND flash on CS2 */
cc41a59a CC	590	__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
fcb77477	591	#endif
c74b2108 SK	592	}
c74b2108 SK	593
154b5484	594	void davinci_nand_init(struct nand_chip *nand)
c74b2108	595	{
c74b2108	596	nand->chip_delay = 0;
6d0f6bcf	597	#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
dfe64e2c	598	nand->bbt_options \|= NAND_BBT_USE_FLASH;
c74b2108	599	#endif
6d0f6bcf	600	#ifdef CONFIG_SYS_NAND_HW_ECC
5e1dae5c	601	nand->ecc.mode = NAND_ECC_HW;
9b05aa78 HV	602	nand->ecc.size = 512;
9b05aa78 HV	603	nand->ecc.bytes = 3;
dfe64e2c	604	nand->ecc.strength = 1;
cfa460ad WJ	605	nand->ecc.calculate = nand_davinci_calculate_ecc;
cfa460ad WJ	606	nand->ecc.correct = nand_davinci_correct_data;
4cbb651b	607	nand->ecc.hwctl = nand_davinci_enable_hwecc;
c74b2108	608	#else
5e1dae5c	609	nand->ecc.mode = NAND_ECC_SOFT;
6d0f6bcf	610	#endif /* CONFIG_SYS_NAND_HW_ECC */
77b351cd SP	611	#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	612	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
	613	nand->ecc.size = 512;
	614	nand->ecc.bytes = 10;
dfe64e2c	615	nand->ecc.strength = 4;
77b351cd SP	616	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
	617	nand->ecc.correct = nand_davinci_4bit_correct_data;
	618	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
	619	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
	620	#endif
c74b2108	621	/* Set address of hardware control function */
cfa460ad	622	nand->cmd_ctrl = nand_davinci_hwcontrol;
c74b2108	623
20da6f4d NT	624	nand->read_buf = nand_davinci_read_buf;
	625	nand->write_buf = nand_davinci_write_buf;
	626
c74b2108	627	nand->dev_ready = nand_davinci_dev_ready;
c74b2108 SK	628
c74b2108 SK	629	nand_flash_init();
154b5484	630	}
c74b2108	631
154b5484 DB	632	int board_nand_init(struct nand_chip *chip) __attribute__((weak));
	633
	634	int board_nand_init(struct nand_chip *chip)
	635	{
	636	davinci_nand_init(chip);
	637	return 0;
c74b2108	638	}