[people/ms/u-boot.git] / drivers / net / ethoc.c

/*
 * Opencore 10/100 ethernet mac driver
 *
 * Copyright (C) 2007-2008 Avionic Design Development GmbH
 * Copyright (C) 2008-2009 Avionic Design GmbH
 *   Thierry Reding <thierry.reding@avionic-design.de>
 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
 * Copyright (C) 2016 Cadence Design Systems Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <dm/device.h>
#include <dm/platform_data/net_ethoc.h>
#include <linux/io.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include <asm/cache.h>

/* register offsets */
#define	MODER		0x00
#define	INT_SOURCE	0x04
#define	INT_MASK	0x08
#define	IPGT		0x0c
#define	IPGR1		0x10
#define	IPGR2		0x14
#define	PACKETLEN	0x18
#define	COLLCONF	0x1c
#define	TX_BD_NUM	0x20
#define	CTRLMODER	0x24
#define	MIIMODER	0x28
#define	MIICOMMAND	0x2c
#define	MIIADDRESS	0x30
#define	MIITX_DATA	0x34
#define	MIIRX_DATA	0x38
#define	MIISTATUS	0x3c
#define	MAC_ADDR0	0x40
#define	MAC_ADDR1	0x44
#define	ETH_HASH0	0x48
#define	ETH_HASH1	0x4c
#define	ETH_TXCTRL	0x50

/* mode register */
#define	MODER_RXEN	(1 <<  0)	/* receive enable */
#define	MODER_TXEN	(1 <<  1)	/* transmit enable */
#define	MODER_NOPRE	(1 <<  2)	/* no preamble */
#define	MODER_BRO	(1 <<  3)	/* broadcast address */
#define	MODER_IAM	(1 <<  4)	/* individual address mode */
#define	MODER_PRO	(1 <<  5)	/* promiscuous mode */
#define	MODER_IFG	(1 <<  6)	/* interframe gap for incoming frames */
#define	MODER_LOOP	(1 <<  7)	/* loopback */
#define	MODER_NBO	(1 <<  8)	/* no back-off */
#define	MODER_EDE	(1 <<  9)	/* excess defer enable */
#define	MODER_FULLD	(1 << 10)	/* full duplex */
#define	MODER_RESET	(1 << 11)	/* FIXME: reset (undocumented) */
#define	MODER_DCRC	(1 << 12)	/* delayed CRC enable */
#define	MODER_CRC	(1 << 13)	/* CRC enable */
#define	MODER_HUGE	(1 << 14)	/* huge packets enable */
#define	MODER_PAD	(1 << 15)	/* padding enabled */
#define	MODER_RSM	(1 << 16)	/* receive small packets */

/* interrupt source and mask registers */
#define	INT_MASK_TXF	(1 << 0)	/* transmit frame */
#define	INT_MASK_TXE	(1 << 1)	/* transmit error */
#define	INT_MASK_RXF	(1 << 2)	/* receive frame */
#define	INT_MASK_RXE	(1 << 3)	/* receive error */
#define	INT_MASK_BUSY	(1 << 4)
#define	INT_MASK_TXC	(1 << 5)	/* transmit control frame */
#define	INT_MASK_RXC	(1 << 6)	/* receive control frame */

#define	INT_MASK_TX	(INT_MASK_TXF | INT_MASK_TXE)
#define	INT_MASK_RX	(INT_MASK_RXF | INT_MASK_RXE)

#define	INT_MASK_ALL ( \
		INT_MASK_TXF | INT_MASK_TXE | \
		INT_MASK_RXF | INT_MASK_RXE | \
		INT_MASK_TXC | INT_MASK_RXC | \
		INT_MASK_BUSY \
	)

/* packet length register */
#define	PACKETLEN_MIN(min)		(((min) & 0xffff) << 16)
#define	PACKETLEN_MAX(max)		(((max) & 0xffff) <<  0)
#define	PACKETLEN_MIN_MAX(min, max)	(PACKETLEN_MIN(min) | \
					PACKETLEN_MAX(max))

/* transmit buffer number register */
#define	TX_BD_NUM_VAL(x)	(((x) <= 0x80) ? (x) : 0x80)

/* control module mode register */
#define	CTRLMODER_PASSALL	(1 << 0)	/* pass all receive frames */
#define	CTRLMODER_RXFLOW	(1 << 1)	/* receive control flow */
#define	CTRLMODER_TXFLOW	(1 << 2)	/* transmit control flow */

/* MII mode register */
#define	MIIMODER_CLKDIV(x)	((x) & 0xfe)	/* needs to be an even number */
#define	MIIMODER_NOPRE		(1 << 8)	/* no preamble */

/* MII command register */
#define	MIICOMMAND_SCAN		(1 << 0)	/* scan status */
#define	MIICOMMAND_READ		(1 << 1)	/* read status */
#define	MIICOMMAND_WRITE	(1 << 2)	/* write control data */

/* MII address register */
#define	MIIADDRESS_FIAD(x)		(((x) & 0x1f) << 0)
#define	MIIADDRESS_RGAD(x)		(((x) & 0x1f) << 8)
#define	MIIADDRESS_ADDR(phy, reg)	(MIIADDRESS_FIAD(phy) | \
					MIIADDRESS_RGAD(reg))

/* MII transmit data register */
#define	MIITX_DATA_VAL(x)	((x) & 0xffff)

/* MII receive data register */
#define	MIIRX_DATA_VAL(x)	((x) & 0xffff)

/* MII status register */
#define	MIISTATUS_LINKFAIL	(1 << 0)
#define	MIISTATUS_BUSY		(1 << 1)
#define	MIISTATUS_INVALID	(1 << 2)

/* TX buffer descriptor */
#define	TX_BD_CS		(1 <<  0)	/* carrier sense lost */
#define	TX_BD_DF		(1 <<  1)	/* defer indication */
#define	TX_BD_LC		(1 <<  2)	/* late collision */
#define	TX_BD_RL		(1 <<  3)	/* retransmission limit */
#define	TX_BD_RETRY_MASK	(0x00f0)
#define	TX_BD_RETRY(x)		(((x) & 0x00f0) >>  4)
#define	TX_BD_UR		(1 <<  8)	/* transmitter underrun */
#define	TX_BD_CRC		(1 << 11)	/* TX CRC enable */
#define	TX_BD_PAD		(1 << 12)	/* pad enable */
#define	TX_BD_WRAP		(1 << 13)
#define	TX_BD_IRQ		(1 << 14)	/* interrupt request enable */
#define	TX_BD_READY		(1 << 15)	/* TX buffer ready */
#define	TX_BD_LEN(x)		(((x) & 0xffff) << 16)
#define	TX_BD_LEN_MASK		(0xffff << 16)

#define	TX_BD_STATS		(TX_BD_CS | TX_BD_DF | TX_BD_LC | \
				TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)

/* RX buffer descriptor */
#define	RX_BD_LC	(1 <<  0)	/* late collision */
#define	RX_BD_CRC	(1 <<  1)	/* RX CRC error */
#define	RX_BD_SF	(1 <<  2)	/* short frame */
#define	RX_BD_TL	(1 <<  3)	/* too long */
#define	RX_BD_DN	(1 <<  4)	/* dribble nibble */
#define	RX_BD_IS	(1 <<  5)	/* invalid symbol */
#define	RX_BD_OR	(1 <<  6)	/* receiver overrun */
#define	RX_BD_MISS	(1 <<  7)
#define	RX_BD_CF	(1 <<  8)	/* control frame */
#define	RX_BD_WRAP	(1 << 13)
#define	RX_BD_IRQ	(1 << 14)	/* interrupt request enable */
#define	RX_BD_EMPTY	(1 << 15)
#define	RX_BD_LEN(x)	(((x) & 0xffff) << 16)

#define	RX_BD_STATS	(RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
			RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)

#define	ETHOC_BUFSIZ		1536
#define	ETHOC_ZLEN		64
#define	ETHOC_BD_BASE		0x400
#define	ETHOC_TIMEOUT		(HZ / 2)
#define	ETHOC_MII_TIMEOUT	(1 + (HZ / 5))
#define	ETHOC_IOSIZE		0x54

/**
 * struct ethoc - driver-private device structure
 * @num_tx:	number of send buffers
 * @cur_tx:	last send buffer written
 * @dty_tx:	last buffer actually sent
 * @num_rx:	number of receive buffers
 * @cur_rx:	current receive buffer
 */
struct ethoc {
	u32 num_tx;
	u32 cur_tx;
	u32 dty_tx;
	u32 num_rx;
	u32 cur_rx;
	void __iomem *iobase;
};

/**
 * struct ethoc_bd - buffer descriptor
 * @stat:	buffer statistics
 * @addr:	physical memory address
 */
struct ethoc_bd {
	u32 stat;
	u32 addr;
};

static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
{
	return readl(priv->iobase + offset);
}

static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
{
	writel(data, priv->iobase + offset);
}

static inline void ethoc_read_bd(struct ethoc *priv, int index,
				 struct ethoc_bd *bd)
{
	size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
	bd->stat = ethoc_read(priv, offset + 0);
	bd->addr = ethoc_read(priv, offset + 4);
}

static inline void ethoc_write_bd(struct ethoc *priv, int index,
				  const struct ethoc_bd *bd)
{
	size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
	ethoc_write(priv, offset + 0, bd->stat);
	ethoc_write(priv, offset + 4, bd->addr);
}

static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac)
{
	ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
		    (mac[4] << 8) | (mac[5] << 0));
	ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
	return 0;
}

static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
{
	ethoc_write(priv, INT_SOURCE, mask);
}

static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
{
	u32 mode = ethoc_read(priv, MODER);
	mode |= MODER_RXEN | MODER_TXEN;
	ethoc_write(priv, MODER, mode);
}

static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
{
	u32 mode = ethoc_read(priv, MODER);
	mode &= ~(MODER_RXEN | MODER_TXEN);
	ethoc_write(priv, MODER, mode);
}

static int ethoc_init_ring(struct ethoc *priv)
{
	struct ethoc_bd bd;
	int i;

	priv->cur_tx = 0;
	priv->dty_tx = 0;
	priv->cur_rx = 0;

	/* setup transmission buffers */
	bd.stat = TX_BD_IRQ | TX_BD_CRC;
	bd.addr = 0;

	for (i = 0; i < priv->num_tx; i++) {
		if (i == priv->num_tx - 1)
			bd.stat |= TX_BD_WRAP;

		ethoc_write_bd(priv, i, &bd);
	}

	bd.stat = RX_BD_EMPTY | RX_BD_IRQ;

	for (i = 0; i < priv->num_rx; i++) {
		bd.addr = virt_to_phys(net_rx_packets[i]);
		if (i == priv->num_rx - 1)
			bd.stat |= RX_BD_WRAP;

		flush_dcache_range((ulong)net_rx_packets[i],
				   (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
		ethoc_write_bd(priv, priv->num_tx + i, &bd);
	}

	return 0;
}

static int ethoc_reset(struct ethoc *priv)
{
	u32 mode;

	/* TODO: reset controller? */

	ethoc_disable_rx_and_tx(priv);

	/* TODO: setup registers */

	/* enable FCS generation and automatic padding */
	mode = ethoc_read(priv, MODER);
	mode |= MODER_CRC | MODER_PAD;
	ethoc_write(priv, MODER, mode);

	/* set full-duplex mode */
	mode = ethoc_read(priv, MODER);
	mode |= MODER_FULLD;
	ethoc_write(priv, MODER, mode);
	ethoc_write(priv, IPGT, 0x15);

	ethoc_ack_irq(priv, INT_MASK_ALL);
	ethoc_enable_rx_and_tx(priv);
	return 0;
}

static int ethoc_init_common(struct ethoc *priv)
{
	priv->num_tx = 1;
	priv->num_rx = PKTBUFSRX;
	ethoc_write(priv, TX_BD_NUM, priv->num_tx);
	ethoc_init_ring(priv);
	ethoc_reset(priv);

	return 0;
}

static int ethoc_update_rx_stats(struct ethoc_bd *bd)
{
	int ret = 0;

	if (bd->stat & RX_BD_TL) {
		debug("ETHOC: " "RX: frame too long\n");
		ret++;
	}

	if (bd->stat & RX_BD_SF) {
		debug("ETHOC: " "RX: frame too short\n");
		ret++;
	}

	if (bd->stat & RX_BD_DN)
		debug("ETHOC: " "RX: dribble nibble\n");

	if (bd->stat & RX_BD_CRC) {
		debug("ETHOC: " "RX: wrong CRC\n");
		ret++;
	}

	if (bd->stat & RX_BD_OR) {
		debug("ETHOC: " "RX: overrun\n");
		ret++;
	}

	if (bd->stat & RX_BD_LC) {
		debug("ETHOC: " "RX: late collision\n");
		ret++;
	}

	return ret;
}

static int ethoc_rx_common(struct ethoc *priv, uchar **packetp)
{
	struct ethoc_bd bd;
	u32 i = priv->cur_rx % priv->num_rx;
	u32 entry = priv->num_tx + i;

	ethoc_read_bd(priv, entry, &bd);
	if (bd.stat & RX_BD_EMPTY)
		return -EAGAIN;

	debug("%s(): RX buffer %d, %x received\n",
	      __func__, priv->cur_rx, bd.stat);
	if (ethoc_update_rx_stats(&bd) == 0) {
		int size = bd.stat >> 16;

		size -= 4;	/* strip the CRC */
		*packetp = net_rx_packets[i];
		return size;
	} else {
		return 0;
	}
}

static int ethoc_is_new_packet_received(struct ethoc *priv)
{
	u32 pending;

	pending = ethoc_read(priv, INT_SOURCE);
	ethoc_ack_irq(priv, pending);
	if (pending & INT_MASK_BUSY)
		debug("%s(): packet dropped\n", __func__);
	if (pending & INT_MASK_RX) {
		debug("%s(): rx irq\n", __func__);
		return 1;
	}

	return 0;
}

static int ethoc_update_tx_stats(struct ethoc_bd *bd)
{
	if (bd->stat & TX_BD_LC)
		debug("ETHOC: " "TX: late collision\n");

	if (bd->stat & TX_BD_RL)
		debug("ETHOC: " "TX: retransmit limit\n");

	if (bd->stat & TX_BD_UR)
		debug("ETHOC: " "TX: underrun\n");

	if (bd->stat & TX_BD_CS)
		debug("ETHOC: " "TX: carrier sense lost\n");

	return 0;
}

static void ethoc_tx(struct ethoc *priv)
{
	u32 entry = priv->dty_tx % priv->num_tx;
	struct ethoc_bd bd;

	ethoc_read_bd(priv, entry, &bd);
	if ((bd.stat & TX_BD_READY) == 0)
		(void)ethoc_update_tx_stats(&bd);
}

static int ethoc_send_common(struct ethoc *priv, void *packet, int length)
{
	struct ethoc_bd bd;
	u32 entry;
	u32 pending;
	int tmo;

	entry = priv->cur_tx % priv->num_tx;
	ethoc_read_bd(priv, entry, &bd);
	if (unlikely(length < ETHOC_ZLEN))
		bd.stat |= TX_BD_PAD;
	else
		bd.stat &= ~TX_BD_PAD;
	bd.addr = virt_to_phys(packet);

	flush_dcache_range((ulong)packet, (ulong)packet + length);
	bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
	bd.stat |= TX_BD_LEN(length);
	ethoc_write_bd(priv, entry, &bd);

	/* start transmit */
	bd.stat |= TX_BD_READY;
	ethoc_write_bd(priv, entry, &bd);

	/* wait for transfer to succeed */
	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	while (1) {
		pending = ethoc_read(priv, INT_SOURCE);
		ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
		if (pending & INT_MASK_BUSY)
			debug("%s(): packet dropped\n", __func__);

		if (pending & INT_MASK_TX) {
			ethoc_tx(priv);
			break;
		}
		if (get_timer(0) >= tmo) {
			debug("%s(): timed out\n", __func__);
			return -1;
		}
	}

	debug("%s(): packet sent\n", __func__);
	return 0;
}

static int ethoc_free_pkt_common(struct ethoc *priv)
{
	struct ethoc_bd bd;
	u32 i = priv->cur_rx % priv->num_rx;
	u32 entry = priv->num_tx + i;

	ethoc_read_bd(priv, entry, &bd);

	/* clear the buffer descriptor so it can be reused */
	flush_dcache_range((ulong)net_rx_packets[i],
			   (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
	bd.stat &= ~RX_BD_STATS;
	bd.stat |= RX_BD_EMPTY;
	ethoc_write_bd(priv, entry, &bd);
	priv->cur_rx++;

	return 0;
}

#ifdef CONFIG_DM_ETH

static int ethoc_write_hwaddr(struct udevice *dev)
{
	struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
	struct ethoc *priv = dev_get_priv(dev);
	u8 *mac = pdata->eth_pdata.enetaddr;

	return ethoc_write_hwaddr_common(priv, mac);
}

static int ethoc_send(struct udevice *dev, void *packet, int length)
{
	return ethoc_send_common(dev_get_priv(dev), packet, length);
}

static int ethoc_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	return ethoc_free_pkt_common(dev_get_priv(dev));
}

static int ethoc_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct ethoc *priv = dev_get_priv(dev);

	if (flags & ETH_RECV_CHECK_DEVICE)
		if (!ethoc_is_new_packet_received(priv))
			return -EAGAIN;

	return ethoc_rx_common(priv, packetp);
}

static int ethoc_start(struct udevice *dev)
{
	return ethoc_init_common(dev_get_priv(dev));
}

static void ethoc_stop(struct udevice *dev)
{
	struct ethoc *priv = dev_get_priv(dev);

	ethoc_disable_rx_and_tx(priv);
}

static int ethoc_ofdata_to_platdata(struct udevice *dev)
{
	struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);

	pdata->eth_pdata.iobase = dev_get_addr(dev);
	return 0;
}

static int ethoc_probe(struct udevice *dev)
{
	struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
	struct ethoc *priv = dev_get_priv(dev);

	priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
	return 0;
}

static int ethoc_remove(struct udevice *dev)
{
	struct ethoc *priv = dev_get_priv(dev);

	iounmap(priv->iobase);
	return 0;
}

static const struct eth_ops ethoc_ops = {
	.start		= ethoc_start,
	.stop		= ethoc_stop,
	.send		= ethoc_send,
	.recv		= ethoc_recv,
	.free_pkt	= ethoc_free_pkt,
	.write_hwaddr	= ethoc_write_hwaddr,
};

static const struct udevice_id ethoc_ids[] = {
	{ .compatible = "opencores,ethoc" },
	{ }
};

U_BOOT_DRIVER(ethoc) = {
	.name				= "ethoc",
	.id				= UCLASS_ETH,
	.of_match			= ethoc_ids,
	.ofdata_to_platdata		= ethoc_ofdata_to_platdata,
	.probe				= ethoc_probe,
	.remove				= ethoc_remove,
	.ops				= &ethoc_ops,
	.priv_auto_alloc_size		= sizeof(struct ethoc),
	.platdata_auto_alloc_size	= sizeof(struct ethoc_eth_pdata),
};

#else

static int ethoc_init(struct eth_device *dev, bd_t *bd)
{
	struct ethoc *priv = (struct ethoc *)dev->priv;

	return ethoc_init_common(priv);
}

static int ethoc_write_hwaddr(struct eth_device *dev)
{
	struct ethoc *priv = (struct ethoc *)dev->priv;
	u8 *mac = dev->enetaddr;

	return ethoc_write_hwaddr_common(priv, mac);
}

static int ethoc_send(struct eth_device *dev, void *packet, int length)
{
	return ethoc_send_common(dev->priv, packet, length);
}

static void ethoc_halt(struct eth_device *dev)
{
	ethoc_disable_rx_and_tx(dev->priv);
}

static int ethoc_recv(struct eth_device *dev)
{
	struct ethoc *priv = (struct ethoc *)dev->priv;
	int count;

	if (!ethoc_is_new_packet_received(priv))
		return 0;

	for (count = 0; count < PKTBUFSRX; ++count) {
		uchar *packetp;
		int size = ethoc_rx_common(priv, &packetp);

		if (size < 0)
			break;
		if (size > 0)
			net_process_received_packet(packetp, size);
		ethoc_free_pkt_common(priv);
	}
	return 0;
}

int ethoc_initialize(u8 dev_num, int base_addr)
{
	struct ethoc *priv;
	struct eth_device *dev;

	priv = malloc(sizeof(*priv));
	if (!priv)
		return 0;
	dev = malloc(sizeof(*dev));
	if (!dev) {
		free(priv);
		return 0;
	}

	memset(dev, 0, sizeof(*dev));
	dev->priv = priv;
	dev->iobase = base_addr;
	dev->init = ethoc_init;
	dev->halt = ethoc_halt;
	dev->send = ethoc_send;
	dev->recv = ethoc_recv;
	dev->write_hwaddr = ethoc_write_hwaddr;
	sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
	priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);

	eth_register(dev);
	return 1;
}

#endif
Commit	Line	Data
f6569884 TC	1	/*
	2	* Opencore 10/100 ethernet mac driver
	3	*
	4	* Copyright (C) 2007-2008 Avionic Design Development GmbH
	5	* Copyright (C) 2008-2009 Avionic Design GmbH
	6	* Thierry Reding <thierry.reding@avionic-design.de>
	7	* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
5d43feab	8	* Copyright (C) 2016 Cadence Design Systems Inc.
f6569884	9	*
5d43feab	10	* SPDX-License-Identifier: GPL-2.0
f6569884 TC	11	*/
	12
	13	#include <common.h>
5d43feab MF	14	#include <dm/device.h>
5d43feab MF	15	#include <dm/platform_data/net_ethoc.h>
a84a757a	16	#include <linux/io.h>
f6569884 TC	17	#include <malloc.h>
	18	#include <net.h>
	19	#include <miiphy.h>
f6569884 TC	20	#include <asm/cache.h>
	21
	22	/* register offsets */
	23	#define MODER 0x00
	24	#define INT_SOURCE 0x04
	25	#define INT_MASK 0x08
	26	#define IPGT 0x0c
	27	#define IPGR1 0x10
	28	#define IPGR2 0x14
	29	#define PACKETLEN 0x18
	30	#define COLLCONF 0x1c
	31	#define TX_BD_NUM 0x20
	32	#define CTRLMODER 0x24
	33	#define MIIMODER 0x28
	34	#define MIICOMMAND 0x2c
	35	#define MIIADDRESS 0x30
	36	#define MIITX_DATA 0x34
	37	#define MIIRX_DATA 0x38
	38	#define MIISTATUS 0x3c
	39	#define MAC_ADDR0 0x40
	40	#define MAC_ADDR1 0x44
	41	#define ETH_HASH0 0x48
	42	#define ETH_HASH1 0x4c
	43	#define ETH_TXCTRL 0x50
	44
	45	/* mode register */
	46	#define MODER_RXEN (1 << 0) /* receive enable */
	47	#define MODER_TXEN (1 << 1) /* transmit enable */
	48	#define MODER_NOPRE (1 << 2) /* no preamble */
	49	#define MODER_BRO (1 << 3) /* broadcast address */
	50	#define MODER_IAM (1 << 4) /* individual address mode */
	51	#define MODER_PRO (1 << 5) /* promiscuous mode */
	52	#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
	53	#define MODER_LOOP (1 << 7) /* loopback */
	54	#define MODER_NBO (1 << 8) /* no back-off */
	55	#define MODER_EDE (1 << 9) /* excess defer enable */
	56	#define MODER_FULLD (1 << 10) /* full duplex */
	57	#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
	58	#define MODER_DCRC (1 << 12) /* delayed CRC enable */
	59	#define MODER_CRC (1 << 13) /* CRC enable */
	60	#define MODER_HUGE (1 << 14) /* huge packets enable */
	61	#define MODER_PAD (1 << 15) /* padding enabled */
	62	#define MODER_RSM (1 << 16) /* receive small packets */
	63
	64	/* interrupt source and mask registers */
	65	#define INT_MASK_TXF (1 << 0) /* transmit frame */
	66	#define INT_MASK_TXE (1 << 1) /* transmit error */
	67	#define INT_MASK_RXF (1 << 2) /* receive frame */
	68	#define INT_MASK_RXE (1 << 3) /* receive error */
	69	#define INT_MASK_BUSY (1 << 4)
	70	#define INT_MASK_TXC (1 << 5) /* transmit control frame */
	71	#define INT_MASK_RXC (1 << 6) /* receive control frame */
	72
	73	#define INT_MASK_TX (INT_MASK_TXF \| INT_MASK_TXE)
	74	#define INT_MASK_RX (INT_MASK_RXF \| INT_MASK_RXE)
	75
	76	#define INT_MASK_ALL ( \
	77	INT_MASK_TXF \| INT_MASK_TXE \| \
	78	INT_MASK_RXF \| INT_MASK_RXE \| \
	79	INT_MASK_TXC \| INT_MASK_RXC \| \
	80	INT_MASK_BUSY \
	81	)
	82
	83	/* packet length register */
84	#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
85	#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
86	#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) \| \
87	PACKETLEN_MAX(max))
88
89	/* transmit buffer number register */
90	#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
91
92	/* control module mode register */
93	#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
94	#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
95	#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
96
97	/* MII mode register */
98	#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
99	#define MIIMODER_NOPRE (1 << 8) /* no preamble */
100
101	/* MII command register */
102	#define MIICOMMAND_SCAN (1 << 0) /* scan status */
103	#define MIICOMMAND_READ (1 << 1) /* read status */
104	#define MIICOMMAND_WRITE (1 << 2) /* write control data */
105
106	/* MII address register */
107	#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
108	#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
109	#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) \| \
110	MIIADDRESS_RGAD(reg))
111
112	/* MII transmit data register */
113	#define MIITX_DATA_VAL(x) ((x) & 0xffff)
114
115	/* MII receive data register */
116	#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
117
118	/* MII status register */
119	#define MIISTATUS_LINKFAIL (1 << 0)
120	#define MIISTATUS_BUSY (1 << 1)
121	#define MIISTATUS_INVALID (1 << 2)
122
123	/* TX buffer descriptor */
124	#define TX_BD_CS (1 << 0) /* carrier sense lost */
125	#define TX_BD_DF (1 << 1) /* defer indication */
126	#define TX_BD_LC (1 << 2) /* late collision */
127	#define TX_BD_RL (1 << 3) /* retransmission limit */
128	#define TX_BD_RETRY_MASK (0x00f0)
129	#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
130	#define TX_BD_UR (1 << 8) /* transmitter underrun */
131	#define TX_BD_CRC (1 << 11) /* TX CRC enable */
132	#define TX_BD_PAD (1 << 12) /* pad enable */
133	#define TX_BD_WRAP (1 << 13)
134	#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
135	#define TX_BD_READY (1 << 15) /* TX buffer ready */
136	#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
137	#define TX_BD_LEN_MASK (0xffff << 16)
138
139	#define TX_BD_STATS (TX_BD_CS \| TX_BD_DF \| TX_BD_LC \| \
140	TX_BD_RL \| TX_BD_RETRY_MASK \| TX_BD_UR)
141
142	/* RX buffer descriptor */
143	#define RX_BD_LC (1 << 0) /* late collision */
144	#define RX_BD_CRC (1 << 1) /* RX CRC error */
145	#define RX_BD_SF (1 << 2) /* short frame */
146	#define RX_BD_TL (1 << 3) /* too long */
147	#define RX_BD_DN (1 << 4) /* dribble nibble */
148	#define RX_BD_IS (1 << 5) /* invalid symbol */
149	#define RX_BD_OR (1 << 6) /* receiver overrun */
150	#define RX_BD_MISS (1 << 7)
151	#define RX_BD_CF (1 << 8) /* control frame */
152	#define RX_BD_WRAP (1 << 13)
153	#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
154	#define RX_BD_EMPTY (1 << 15)
155	#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
156
157	#define RX_BD_STATS (RX_BD_LC \| RX_BD_CRC \| RX_BD_SF \| RX_BD_TL \| \
158	RX_BD_DN \| RX_BD_IS \| RX_BD_OR \| RX_BD_MISS)
159
160	#define ETHOC_BUFSIZ 1536
161	#define ETHOC_ZLEN 64
162	#define ETHOC_BD_BASE 0x400
163	#define ETHOC_TIMEOUT (HZ / 2)
164	#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
a84a757a	165	#define ETHOC_IOSIZE 0x54
f6569884 TC	166
	167	/**
	168	* struct ethoc - driver-private device structure
	169	* @num_tx: number of send buffers
	170	* @cur_tx: last send buffer written
	171	* @dty_tx: last buffer actually sent
	172	* @num_rx: number of receive buffers
	173	* @cur_rx: current receive buffer
	174	*/
	175	struct ethoc {
	176	u32 num_tx;
	177	u32 cur_tx;
	178	u32 dty_tx;
	179	u32 num_rx;
	180	u32 cur_rx;
a84a757a	181	void __iomem *iobase;
f6569884 TC	182	};
	183
	184	/**
	185	* struct ethoc_bd - buffer descriptor
	186	* @stat: buffer statistics
	187	* @addr: physical memory address
	188	*/
	189	struct ethoc_bd {
	190	u32 stat;
	191	u32 addr;
	192	};
	193
a84a757a	194	static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
f6569884	195	{
a84a757a	196	return readl(priv->iobase + offset);
f6569884 TC	197	}
f6569884 TC	198
a84a757a	199	static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
f6569884	200	{
a84a757a	201	writel(data, priv->iobase + offset);
f6569884 TC	202	}
f6569884 TC	203
a84a757a	204	static inline void ethoc_read_bd(struct ethoc *priv, int index,
f6569884 TC	205	struct ethoc_bd *bd)
f6569884 TC	206	{
9f680d2d	207	size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
a84a757a MF	208	bd->stat = ethoc_read(priv, offset + 0);
a84a757a MF	209	bd->addr = ethoc_read(priv, offset + 4);
f6569884 TC	210	}
f6569884 TC	211
a84a757a	212	static inline void ethoc_write_bd(struct ethoc *priv, int index,
f6569884 TC	213	const struct ethoc_bd *bd)
f6569884 TC	214	{
9f680d2d	215	size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
a84a757a MF	216	ethoc_write(priv, offset + 0, bd->stat);
a84a757a MF	217	ethoc_write(priv, offset + 4, bd->addr);
f6569884 TC	218	}
f6569884 TC	219
5d43feab	220	static int ethoc_write_hwaddr_common(struct ethoc priv, u8 mac)
f6569884	221	{
a84a757a	222	ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) \| (mac[3] << 16) \|
f6569884	223	(mac[4] << 8) \| (mac[5] << 0));
a84a757a	224	ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) \| (mac[1] << 0));
3ac9d6c6	225	return 0;
f6569884 TC	226	}
f6569884 TC	227
a84a757a	228	static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
f6569884	229	{
a84a757a	230	ethoc_write(priv, INT_SOURCE, mask);
f6569884 TC	231	}
f6569884 TC	232
a84a757a	233	static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
f6569884	234	{
a84a757a	235	u32 mode = ethoc_read(priv, MODER);
f6569884	236	mode \|= MODER_RXEN \| MODER_TXEN;
a84a757a	237	ethoc_write(priv, MODER, mode);
f6569884 TC	238	}
f6569884 TC	239
a84a757a	240	static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
f6569884	241	{
a84a757a	242	u32 mode = ethoc_read(priv, MODER);
f6569884	243	mode &= ~(MODER_RXEN \| MODER_TXEN);
a84a757a	244	ethoc_write(priv, MODER, mode);
f6569884 TC	245	}
f6569884 TC	246
a84a757a	247	static int ethoc_init_ring(struct ethoc *priv)
f6569884	248	{
f6569884 TC	249	struct ethoc_bd bd;
	250	int i;
	251
	252	priv->cur_tx = 0;
	253	priv->dty_tx = 0;
	254	priv->cur_rx = 0;
	255
	256	/* setup transmission buffers */
	257	bd.stat = TX_BD_IRQ \| TX_BD_CRC;
02a888b5	258	bd.addr = 0;
f6569884 TC	259
	260	for (i = 0; i < priv->num_tx; i++) {
	261	if (i == priv->num_tx - 1)
	262	bd.stat \|= TX_BD_WRAP;
	263
a84a757a	264	ethoc_write_bd(priv, i, &bd);
f6569884 TC	265	}
	266
	267	bd.stat = RX_BD_EMPTY \| RX_BD_IRQ;
	268
	269	for (i = 0; i < priv->num_rx; i++) {
02a888b5	270	bd.addr = virt_to_phys(net_rx_packets[i]);
f6569884 TC	271	if (i == priv->num_rx - 1)
	272	bd.stat \|= RX_BD_WRAP;
	273
02a888b5 MF	274	flush_dcache_range((ulong)net_rx_packets[i],
02a888b5 MF	275	(ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
a84a757a	276	ethoc_write_bd(priv, priv->num_tx + i, &bd);
f6569884 TC	277	}
	278
	279	return 0;
	280	}
	281
a84a757a	282	static int ethoc_reset(struct ethoc *priv)
f6569884 TC	283	{
	284	u32 mode;
	285
	286	/* TODO: reset controller? */
	287
a84a757a	288	ethoc_disable_rx_and_tx(priv);
f6569884 TC	289
	290	/* TODO: setup registers */
	291
	292	/* enable FCS generation and automatic padding */
a84a757a	293	mode = ethoc_read(priv, MODER);
f6569884	294	mode \|= MODER_CRC \| MODER_PAD;
a84a757a	295	ethoc_write(priv, MODER, mode);
f6569884 TC	296
f6569884 TC	297	/* set full-duplex mode */
a84a757a	298	mode = ethoc_read(priv, MODER);
f6569884	299	mode \|= MODER_FULLD;
a84a757a MF	300	ethoc_write(priv, MODER, mode);
a84a757a MF	301	ethoc_write(priv, IPGT, 0x15);
f6569884	302
a84a757a MF	303	ethoc_ack_irq(priv, INT_MASK_ALL);
a84a757a MF	304	ethoc_enable_rx_and_tx(priv);
f6569884 TC	305	return 0;
	306	}
	307
5d43feab	308	static int ethoc_init_common(struct ethoc *priv)
f6569884	309	{
f6569884 TC	310	priv->num_tx = 1;
f6569884 TC	311	priv->num_rx = PKTBUFSRX;
a84a757a MF	312	ethoc_write(priv, TX_BD_NUM, priv->num_tx);
	313	ethoc_init_ring(priv);
	314	ethoc_reset(priv);
f6569884 TC	315
	316	return 0;
	317	}
	318
	319	static int ethoc_update_rx_stats(struct ethoc_bd *bd)
	320	{
	321	int ret = 0;
	322
	323	if (bd->stat & RX_BD_TL) {
	324	debug("ETHOC: " "RX: frame too long\n");
	325	ret++;
	326	}
	327
	328	if (bd->stat & RX_BD_SF) {
	329	debug("ETHOC: " "RX: frame too short\n");
	330	ret++;
	331	}
	332
	333	if (bd->stat & RX_BD_DN)
	334	debug("ETHOC: " "RX: dribble nibble\n");
	335
	336	if (bd->stat & RX_BD_CRC) {
	337	debug("ETHOC: " "RX: wrong CRC\n");
	338	ret++;
	339	}
	340
	341	if (bd->stat & RX_BD_OR) {
	342	debug("ETHOC: " "RX: overrun\n");
	343	ret++;
	344	}
	345
	346	if (bd->stat & RX_BD_LC) {
	347	debug("ETHOC: " "RX: late collision\n");
	348	ret++;
	349	}
	350
	351	return ret;
	352	}
	353
5d43feab	354	static int ethoc_rx_common(struct ethoc priv, uchar *packetp)
f6569884	355	{
5d43feab	356	struct ethoc_bd bd;
02a888b5 MF	357	u32 i = priv->cur_rx % priv->num_rx;
02a888b5 MF	358	u32 entry = priv->num_tx + i;
f6569884	359
5d43feab MF	360	ethoc_read_bd(priv, entry, &bd);
	361	if (bd.stat & RX_BD_EMPTY)
	362	return -EAGAIN;
	363
	364	debug("%s(): RX buffer %d, %x received\n",
	365	__func__, priv->cur_rx, bd.stat);
	366	if (ethoc_update_rx_stats(&bd) == 0) {
	367	int size = bd.stat >> 16;
	368
	369	size -= 4; /* strip the CRC */
02a888b5	370	*packetp = net_rx_packets[i];
5d43feab MF	371	return size;
	372	} else {
	373	return 0;
	374	}
	375	}
f6569884	376
5d43feab MF	377	static int ethoc_is_new_packet_received(struct ethoc *priv)
	378	{
	379	u32 pending;
f6569884	380
5d43feab MF	381	pending = ethoc_read(priv, INT_SOURCE);
	382	ethoc_ack_irq(priv, pending);
	383	if (pending & INT_MASK_BUSY)
	384	debug("%s(): packet dropped\n", __func__);
	385	if (pending & INT_MASK_RX) {
	386	debug("%s(): rx irq\n", __func__);
	387	return 1;
f6569884 TC	388	}
f6569884 TC	389
5d43feab	390	return 0;
f6569884 TC	391	}
	392
	393	static int ethoc_update_tx_stats(struct ethoc_bd *bd)
	394	{
	395	if (bd->stat & TX_BD_LC)
	396	debug("ETHOC: " "TX: late collision\n");
	397
	398	if (bd->stat & TX_BD_RL)
	399	debug("ETHOC: " "TX: retransmit limit\n");
	400
	401	if (bd->stat & TX_BD_UR)
	402	debug("ETHOC: " "TX: underrun\n");
	403
	404	if (bd->stat & TX_BD_CS)
	405	debug("ETHOC: " "TX: carrier sense lost\n");
	406
	407	return 0;
	408	}
	409
a84a757a	410	static void ethoc_tx(struct ethoc *priv)
f6569884	411	{
f6569884 TC	412	u32 entry = priv->dty_tx % priv->num_tx;
	413	struct ethoc_bd bd;
	414
a84a757a	415	ethoc_read_bd(priv, entry, &bd);
f6569884 TC	416	if ((bd.stat & TX_BD_READY) == 0)
	417	(void)ethoc_update_tx_stats(&bd);
	418	}
	419
5d43feab	420	static int ethoc_send_common(struct ethoc priv, void packet, int length)
f6569884	421	{
f6569884 TC	422	struct ethoc_bd bd;
	423	u32 entry;
	424	u32 pending;
	425	int tmo;
	426
	427	entry = priv->cur_tx % priv->num_tx;
a84a757a	428	ethoc_read_bd(priv, entry, &bd);
f6569884 TC	429	if (unlikely(length < ETHOC_ZLEN))
	430	bd.stat \|= TX_BD_PAD;
	431	else
	432	bd.stat &= ~TX_BD_PAD;
02a888b5	433	bd.addr = virt_to_phys(packet);
f6569884	434
02a888b5	435	flush_dcache_range((ulong)packet, (ulong)packet + length);
f6569884 TC	436	bd.stat &= ~(TX_BD_STATS \| TX_BD_LEN_MASK);
f6569884 TC	437	bd.stat \|= TX_BD_LEN(length);
a84a757a	438	ethoc_write_bd(priv, entry, &bd);
f6569884 TC	439
	440	/* start transmit */
	441	bd.stat \|= TX_BD_READY;
a84a757a	442	ethoc_write_bd(priv, entry, &bd);
f6569884 TC	443
	444	/* wait for transfer to succeed */
	445	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	446	while (1) {
a84a757a MF	447	pending = ethoc_read(priv, INT_SOURCE);
a84a757a MF	448	ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
f6569884 TC	449	if (pending & INT_MASK_BUSY)
	450	debug("%s(): packet dropped\n", __func__);
	451
	452	if (pending & INT_MASK_TX) {
a84a757a	453	ethoc_tx(priv);
f6569884 TC	454	break;
	455	}
	456	if (get_timer(0) >= tmo) {
	457	debug("%s(): timed out\n", __func__);
	458	return -1;
	459	}
	460	}
	461
	462	debug("%s(): packet sent\n", __func__);
	463	return 0;
	464	}
	465
5d43feab MF	466	static int ethoc_free_pkt_common(struct ethoc *priv)
5d43feab MF	467	{
5d43feab	468	struct ethoc_bd bd;
02a888b5 MF	469	u32 i = priv->cur_rx % priv->num_rx;
02a888b5 MF	470	u32 entry = priv->num_tx + i;
5d43feab	471
5d43feab MF	472	ethoc_read_bd(priv, entry, &bd);
	473
	474	/* clear the buffer descriptor so it can be reused */
02a888b5 MF	475	flush_dcache_range((ulong)net_rx_packets[i],
02a888b5 MF	476	(ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
5d43feab MF	477	bd.stat &= ~RX_BD_STATS;
	478	bd.stat \|= RX_BD_EMPTY;
	479	ethoc_write_bd(priv, entry, &bd);
	480	priv->cur_rx++;
	481
	482	return 0;
	483	}
	484
	485	#ifdef CONFIG_DM_ETH
	486
	487	static int ethoc_write_hwaddr(struct udevice *dev)
	488	{
	489	struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
	490	struct ethoc *priv = dev_get_priv(dev);
	491	u8 *mac = pdata->eth_pdata.enetaddr;
	492
	493	return ethoc_write_hwaddr_common(priv, mac);
	494	}
	495
	496	static int ethoc_send(struct udevice dev, void packet, int length)
	497	{
	498	return ethoc_send_common(dev_get_priv(dev), packet, length);
	499	}
	500
	501	static int ethoc_free_pkt(struct udevice dev, uchar packet, int length)
	502	{
	503	return ethoc_free_pkt_common(dev_get_priv(dev));
	504	}
	505
	506	static int ethoc_recv(struct udevice dev, int flags, uchar *packetp)
	507	{
	508	struct ethoc *priv = dev_get_priv(dev);
	509
	510	if (flags & ETH_RECV_CHECK_DEVICE)
	511	if (!ethoc_is_new_packet_received(priv))
	512	return -EAGAIN;
	513
	514	return ethoc_rx_common(priv, packetp);
	515	}
	516
	517	static int ethoc_start(struct udevice *dev)
	518	{
	519	return ethoc_init_common(dev_get_priv(dev));
	520	}
	521
	522	static void ethoc_stop(struct udevice *dev)
	523	{
	524	struct ethoc *priv = dev_get_priv(dev);
	525
	526	ethoc_disable_rx_and_tx(priv);
	527	}
	528
2de18c8d MF	529	static int ethoc_ofdata_to_platdata(struct udevice *dev)
	530	{
	531	struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
	532
	533	pdata->eth_pdata.iobase = dev_get_addr(dev);
	534	return 0;
	535	}
	536
5d43feab MF	537	static int ethoc_probe(struct udevice *dev)
	538	{
	539	struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
	540	struct ethoc *priv = dev_get_priv(dev);
	541
	542	priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
	543	return 0;
	544	}
	545
	546	static int ethoc_remove(struct udevice *dev)
	547	{
	548	struct ethoc *priv = dev_get_priv(dev);
	549
	550	iounmap(priv->iobase);
	551	return 0;
	552	}
	553
	554	static const struct eth_ops ethoc_ops = {
	555	.start = ethoc_start,
	556	.stop = ethoc_stop,
	557	.send = ethoc_send,
	558	.recv = ethoc_recv,
	559	.free_pkt = ethoc_free_pkt,
	560	.write_hwaddr = ethoc_write_hwaddr,
	561	};
	562
2de18c8d MF	563	static const struct udevice_id ethoc_ids[] = {
	564	{ .compatible = "opencores,ethoc" },
	565	{ }
	566	};
	567
5d43feab MF	568	U_BOOT_DRIVER(ethoc) = {
	569	.name = "ethoc",
	570	.id = UCLASS_ETH,
2de18c8d MF	571	.of_match = ethoc_ids,
2de18c8d MF	572	.ofdata_to_platdata = ethoc_ofdata_to_platdata,
5d43feab MF	573	.probe = ethoc_probe,
	574	.remove = ethoc_remove,
	575	.ops = &ethoc_ops,
	576	.priv_auto_alloc_size = sizeof(struct ethoc),
	577	.platdata_auto_alloc_size = sizeof(struct ethoc_eth_pdata),
	578	};
	579
	580	#else
	581
	582	static int ethoc_init(struct eth_device dev, bd_t bd)
	583	{
	584	struct ethoc priv = (struct ethoc )dev->priv;
	585
	586	return ethoc_init_common(priv);
	587	}
	588
	589	static int ethoc_write_hwaddr(struct eth_device *dev)
	590	{
	591	struct ethoc priv = (struct ethoc )dev->priv;
	592	u8 *mac = dev->enetaddr;
	593
	594	return ethoc_write_hwaddr_common(priv, mac);
	595	}
	596
	597	static int ethoc_send(struct eth_device dev, void packet, int length)
	598	{
	599	return ethoc_send_common(dev->priv, packet, length);
	600	}
	601
f6569884 TC	602	static void ethoc_halt(struct eth_device *dev)
f6569884 TC	603	{
a84a757a	604	ethoc_disable_rx_and_tx(dev->priv);
f6569884 TC	605	}
	606
	607	static int ethoc_recv(struct eth_device *dev)
	608	{
a84a757a	609	struct ethoc priv = (struct ethoc )dev->priv;
5d43feab	610	int count;
f6569884	611
5d43feab MF	612	if (!ethoc_is_new_packet_received(priv))
	613	return 0;
	614
	615	for (count = 0; count < PKTBUFSRX; ++count) {
	616	uchar *packetp;
	617	int size = ethoc_rx_common(priv, &packetp);
f6569884	618
5d43feab MF	619	if (size < 0)
	620	break;
	621	if (size > 0)
	622	net_process_received_packet(packetp, size);
	623	ethoc_free_pkt_common(priv);
	624	}
f6569884 TC	625	return 0;
	626	}
	627
	628	int ethoc_initialize(u8 dev_num, int base_addr)
	629	{
	630	struct ethoc *priv;
	631	struct eth_device *dev;
	632
	633	priv = malloc(sizeof(*priv));
	634	if (!priv)
	635	return 0;
	636	dev = malloc(sizeof(*dev));
	637	if (!dev) {
	638	free(priv);
	639	return 0;
	640	}
	641
	642	memset(dev, 0, sizeof(*dev));
	643	dev->priv = priv;
	644	dev->iobase = base_addr;
	645	dev->init = ethoc_init;
	646	dev->halt = ethoc_halt;
	647	dev->send = ethoc_send;
	648	dev->recv = ethoc_recv;
5d43feab	649	dev->write_hwaddr = ethoc_write_hwaddr;
f6569884	650	sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
a84a757a	651	priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
f6569884 TC	652
	653	eth_register(dev);
	654	return 1;
	655	}
5d43feab MF	656
5d43feab MF	657	#endif