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Commit | Line | Data |
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da419027 | 1 | /* |
e4e8cb71 | 2 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
da419027 ML |
3 | * Layerscape PCIe driver |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/arch/fsl_serdes.h> | |
10 | #include <pci.h> | |
11 | #include <asm/io.h> | |
e4e8cb71 ML |
12 | #include <errno.h> |
13 | #include <malloc.h> | |
af523a0d | 14 | #ifndef CONFIG_LS102XA |
9f3183d2 | 15 | #include <asm/arch/fdt.h> |
af523a0d | 16 | #include <asm/arch/soc.h> |
9f3183d2 | 17 | #endif |
da419027 | 18 | |
e4e8cb71 ML |
19 | #ifndef CONFIG_SYS_PCI_MEMORY_BUS |
20 | #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE | |
21 | #endif | |
22 | ||
23 | #ifndef CONFIG_SYS_PCI_MEMORY_PHYS | |
24 | #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE | |
25 | #endif | |
26 | ||
27 | #ifndef CONFIG_SYS_PCI_MEMORY_SIZE | |
28 | #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */ | |
29 | #endif | |
30 | ||
01cafced ML |
31 | #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE |
32 | #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR | |
33 | #endif | |
34 | ||
e4e8cb71 ML |
35 | /* iATU registers */ |
36 | #define PCIE_ATU_VIEWPORT 0x900 | |
37 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) | |
38 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) | |
39 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) | |
40 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) | |
41 | #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) | |
42 | #define PCIE_ATU_REGION_INDEX3 (0x3 << 0) | |
43 | #define PCIE_ATU_CR1 0x904 | |
44 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) | |
45 | #define PCIE_ATU_TYPE_IO (0x2 << 0) | |
46 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) | |
47 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) | |
48 | #define PCIE_ATU_CR2 0x908 | |
49 | #define PCIE_ATU_ENABLE (0x1 << 31) | |
50 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) | |
01cafced | 51 | #define PCIE_ATU_BAR_NUM(bar) ((bar) << 8) |
e4e8cb71 ML |
52 | #define PCIE_ATU_LOWER_BASE 0x90C |
53 | #define PCIE_ATU_UPPER_BASE 0x910 | |
54 | #define PCIE_ATU_LIMIT 0x914 | |
55 | #define PCIE_ATU_LOWER_TARGET 0x918 | |
56 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | |
57 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | |
58 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | |
59 | #define PCIE_ATU_UPPER_TARGET 0x91C | |
60 | ||
00704590 ML |
61 | #define PCIE_DBI_RO_WR_EN 0x8bc |
62 | ||
e4e8cb71 ML |
63 | #define PCIE_LINK_CAP 0x7c |
64 | #define PCIE_LINK_SPEED_MASK 0xf | |
65 | #define PCIE_LINK_STA 0x82 | |
66 | ||
00704590 ML |
67 | #define LTSSM_STATE_MASK 0x3f |
68 | #define LTSSM_PCIE_L0 0x11 /* L0 state */ | |
69 | ||
70 | #define PCIE_DBI_SIZE 0x100000 /* 1M */ | |
e4e8cb71 | 71 | |
01cafced ML |
72 | #define PCIE_LCTRL0_CFG2_ENABLE (1 << 31) |
73 | #define PCIE_LCTRL0_VF(vf) ((vf) << 22) | |
74 | #define PCIE_LCTRL0_PF(pf) ((pf) << 16) | |
75 | #define PCIE_LCTRL0_VF_ACTIVE (1 << 21) | |
76 | #define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \ | |
77 | PCIE_LCTRL0_VF(vf) | \ | |
78 | ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \ | |
79 | PCIE_LCTRL0_CFG2_ENABLE) | |
80 | ||
81 | #define PCIE_NO_SRIOV_BAR_BASE 0x1000 | |
82 | ||
83 | #define PCIE_PF_NUM 2 | |
84 | #define PCIE_VF_NUM 64 | |
85 | ||
86 | #define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ | |
87 | #define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ | |
88 | #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ | |
89 | #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ | |
90 | ||
e4e8cb71 ML |
91 | struct ls_pcie { |
92 | int idx; | |
93 | void __iomem *dbi; | |
94 | void __iomem *va_cfg0; | |
95 | void __iomem *va_cfg1; | |
96 | struct pci_controller hose; | |
97 | }; | |
98 | ||
99 | struct ls_pcie_info { | |
100 | unsigned long regs; | |
101 | int pci_num; | |
01cafced | 102 | u64 phys_base; |
e4e8cb71 ML |
103 | u64 cfg0_phys; |
104 | u64 cfg0_size; | |
105 | u64 cfg1_phys; | |
106 | u64 cfg1_size; | |
107 | u64 mem_bus; | |
108 | u64 mem_phys; | |
109 | u64 mem_size; | |
110 | u64 io_bus; | |
111 | u64 io_phys; | |
112 | u64 io_size; | |
113 | }; | |
114 | ||
115 | #define SET_LS_PCIE_INFO(x, num) \ | |
116 | { \ | |
117 | x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ | |
01cafced | 118 | x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ |
e4e8cb71 ML |
119 | x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \ |
120 | CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ | |
121 | x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \ | |
122 | x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \ | |
123 | CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ | |
124 | x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \ | |
125 | x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \ | |
126 | x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \ | |
127 | CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ | |
128 | x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \ | |
129 | x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \ | |
130 | x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \ | |
131 | CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ | |
132 | x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \ | |
133 | x.pci_num = num; \ | |
134 | } | |
135 | ||
136 | #ifdef CONFIG_LS102XA | |
137 | #include <asm/arch/immap_ls102xa.h> | |
138 | ||
139 | /* PEX1/2 Misc Ports Status Register */ | |
140 | #define LTSSM_STATE_SHIFT 20 | |
e4e8cb71 ML |
141 | |
142 | static int ls_pcie_link_state(struct ls_pcie *pcie) | |
143 | { | |
144 | u32 state; | |
145 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; | |
146 | ||
147 | state = in_be32(&scfg->pexmscportsr[pcie->idx]); | |
148 | state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; | |
149 | if (state < LTSSM_PCIE_L0) { | |
150 | debug("....PCIe link error. LTSSM=0x%02x.\n", state); | |
151 | return 0; | |
152 | } | |
153 | ||
154 | return 1; | |
155 | } | |
156 | #else | |
e4e8cb71 ML |
157 | static int ls_pcie_link_state(struct ls_pcie *pcie) |
158 | { | |
159 | u32 state; | |
160 | ||
af523a0d | 161 | state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & |
00704590 ML |
162 | LTSSM_STATE_MASK; |
163 | if (state < LTSSM_PCIE_L0) { | |
164 | debug("....PCIe link error. LTSSM=0x%02x.\n", state); | |
165 | return 0; | |
166 | } | |
e4e8cb71 | 167 | |
00704590 | 168 | return 1; |
e4e8cb71 ML |
169 | } |
170 | #endif | |
171 | ||
172 | static int ls_pcie_link_up(struct ls_pcie *pcie) | |
173 | { | |
174 | int state; | |
175 | u32 cap; | |
176 | ||
177 | state = ls_pcie_link_state(pcie); | |
178 | if (state) | |
179 | return state; | |
180 | ||
181 | /* Try to download speed to gen1 */ | |
182 | cap = readl(pcie->dbi + PCIE_LINK_CAP); | |
183 | writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP); | |
00704590 ML |
184 | /* |
185 | * Notice: the following delay has critical impact on link training | |
186 | * if too short (<30ms) the link doesn't get up. | |
187 | */ | |
188 | mdelay(100); | |
e4e8cb71 ML |
189 | state = ls_pcie_link_state(pcie); |
190 | if (state) | |
191 | return state; | |
192 | ||
193 | writel(cap, pcie->dbi + PCIE_LINK_CAP); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
198 | static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev) | |
199 | { | |
200 | writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, | |
201 | pcie->dbi + PCIE_ATU_VIEWPORT); | |
202 | writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET); | |
203 | } | |
204 | ||
205 | static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev) | |
206 | { | |
207 | writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, | |
208 | pcie->dbi + PCIE_ATU_VIEWPORT); | |
209 | writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET); | |
210 | } | |
211 | ||
212 | static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type, | |
213 | u64 phys, u64 bus_addr, pci_size_t size) | |
214 | { | |
215 | writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT); | |
216 | writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE); | |
217 | writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE); | |
218 | writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT); | |
219 | writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET); | |
220 | writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET); | |
221 | writel(type, pcie->dbi + PCIE_ATU_CR1); | |
222 | writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2); | |
223 | } | |
224 | ||
01cafced ML |
225 | /* Use bar match mode and MEM type as default */ |
226 | static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx, | |
227 | int bar, u64 phys) | |
228 | { | |
229 | writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT); | |
230 | writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET); | |
231 | writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET); | |
232 | writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1); | |
233 | writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | | |
234 | PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2); | |
235 | } | |
236 | ||
e4e8cb71 ML |
237 | static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info) |
238 | { | |
239 | #ifdef DEBUG | |
240 | int i; | |
241 | #endif | |
242 | ||
243 | /* ATU 0 : OUTBOUND : CFG0 */ | |
244 | ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, | |
245 | PCIE_ATU_TYPE_CFG0, | |
246 | info->cfg0_phys, | |
247 | 0, | |
248 | info->cfg0_size); | |
249 | /* ATU 1 : OUTBOUND : CFG1 */ | |
250 | ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, | |
251 | PCIE_ATU_TYPE_CFG1, | |
252 | info->cfg1_phys, | |
253 | 0, | |
254 | info->cfg1_size); | |
255 | /* ATU 2 : OUTBOUND : MEM */ | |
256 | ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2, | |
257 | PCIE_ATU_TYPE_MEM, | |
258 | info->mem_phys, | |
259 | info->mem_bus, | |
260 | info->mem_size); | |
261 | /* ATU 3 : OUTBOUND : IO */ | |
262 | ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3, | |
263 | PCIE_ATU_TYPE_IO, | |
264 | info->io_phys, | |
265 | info->io_bus, | |
266 | info->io_size); | |
267 | ||
268 | #ifdef DEBUG | |
269 | for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) { | |
270 | writel(PCIE_ATU_REGION_OUTBOUND | i, | |
271 | pcie->dbi + PCIE_ATU_VIEWPORT); | |
272 | debug("iATU%d:\n", i); | |
273 | debug("\tLOWER PHYS 0x%08x\n", | |
274 | readl(pcie->dbi + PCIE_ATU_LOWER_BASE)); | |
275 | debug("\tUPPER PHYS 0x%08x\n", | |
276 | readl(pcie->dbi + PCIE_ATU_UPPER_BASE)); | |
277 | debug("\tLOWER BUS 0x%08x\n", | |
278 | readl(pcie->dbi + PCIE_ATU_LOWER_TARGET)); | |
279 | debug("\tUPPER BUS 0x%08x\n", | |
280 | readl(pcie->dbi + PCIE_ATU_UPPER_TARGET)); | |
281 | debug("\tLIMIT 0x%08x\n", | |
282 | readl(pcie->dbi + PCIE_ATU_LIMIT)); | |
283 | debug("\tCR1 0x%08x\n", | |
284 | readl(pcie->dbi + PCIE_ATU_CR1)); | |
285 | debug("\tCR2 0x%08x\n", | |
286 | readl(pcie->dbi + PCIE_ATU_CR2)); | |
287 | } | |
288 | #endif | |
289 | } | |
290 | ||
291 | int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) | |
292 | { | |
293 | /* Do not skip controller */ | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d) | |
298 | { | |
299 | if (PCI_DEV(d) > 0) | |
300 | return -EINVAL; | |
301 | ||
00704590 ML |
302 | /* Controller does not support multi-function in RC mode */ |
303 | if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0)) | |
304 | return -EINVAL; | |
305 | ||
e4e8cb71 ML |
306 | return 0; |
307 | } | |
308 | ||
309 | static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d, | |
310 | int where, u32 *val) | |
311 | { | |
312 | struct ls_pcie *pcie = hose->priv_data; | |
313 | u32 busdev, *addr; | |
314 | ||
315 | if (ls_pcie_addr_valid(hose, d)) { | |
316 | *val = 0xffffffff; | |
7ba34ff0 | 317 | return 0; |
e4e8cb71 ML |
318 | } |
319 | ||
320 | if (PCI_BUS(d) == hose->first_busno) { | |
321 | addr = pcie->dbi + (where & ~0x3); | |
322 | } else { | |
323 | busdev = PCIE_ATU_BUS(PCI_BUS(d)) | | |
324 | PCIE_ATU_DEV(PCI_DEV(d)) | | |
325 | PCIE_ATU_FUNC(PCI_FUNC(d)); | |
326 | ||
327 | if (PCI_BUS(d) == hose->first_busno + 1) { | |
328 | ls_pcie_cfg0_set_busdev(pcie, busdev); | |
329 | addr = pcie->va_cfg0 + (where & ~0x3); | |
330 | } else { | |
331 | ls_pcie_cfg1_set_busdev(pcie, busdev); | |
332 | addr = pcie->va_cfg1 + (where & ~0x3); | |
333 | } | |
334 | } | |
335 | ||
336 | *val = readl(addr); | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d, | |
342 | int where, u32 val) | |
343 | { | |
344 | struct ls_pcie *pcie = hose->priv_data; | |
345 | u32 busdev, *addr; | |
346 | ||
347 | if (ls_pcie_addr_valid(hose, d)) | |
348 | return -EINVAL; | |
349 | ||
350 | if (PCI_BUS(d) == hose->first_busno) { | |
351 | addr = pcie->dbi + (where & ~0x3); | |
352 | } else { | |
353 | busdev = PCIE_ATU_BUS(PCI_BUS(d)) | | |
354 | PCIE_ATU_DEV(PCI_DEV(d)) | | |
355 | PCIE_ATU_FUNC(PCI_FUNC(d)); | |
356 | ||
357 | if (PCI_BUS(d) == hose->first_busno + 1) { | |
358 | ls_pcie_cfg0_set_busdev(pcie, busdev); | |
359 | addr = pcie->va_cfg0 + (where & ~0x3); | |
360 | } else { | |
361 | ls_pcie_cfg1_set_busdev(pcie, busdev); | |
362 | addr = pcie->va_cfg1 + (where & ~0x3); | |
363 | } | |
364 | } | |
365 | ||
366 | writel(val, addr); | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
371 | static void ls_pcie_setup_ctrl(struct ls_pcie *pcie, | |
372 | struct ls_pcie_info *info) | |
373 | { | |
374 | struct pci_controller *hose = &pcie->hose; | |
375 | pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); | |
376 | ||
377 | ls_pcie_setup_atu(pcie, info); | |
378 | ||
379 | pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0); | |
380 | ||
381 | /* program correct class for RC */ | |
00704590 | 382 | writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN); |
e4e8cb71 ML |
383 | pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE, |
384 | PCI_CLASS_BRIDGE_PCI); | |
00704590 ML |
385 | #ifndef CONFIG_LS102XA |
386 | writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN); | |
387 | #endif | |
e4e8cb71 ML |
388 | } |
389 | ||
01cafced ML |
390 | static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie, |
391 | struct ls_pcie_info *info) | |
392 | { | |
393 | u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE; | |
394 | ||
395 | /* ATU 0 : INBOUND : map BAR0 */ | |
396 | ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys); | |
397 | /* ATU 1 : INBOUND : map BAR1 */ | |
398 | phys += PCIE_BAR1_SIZE; | |
399 | ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys); | |
400 | /* ATU 2 : INBOUND : map BAR2 */ | |
401 | phys += PCIE_BAR2_SIZE; | |
402 | ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys); | |
403 | /* ATU 3 : INBOUND : map BAR4 */ | |
404 | phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE; | |
405 | ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys); | |
406 | ||
407 | /* ATU 0 : OUTBOUND : map 4G MEM */ | |
408 | ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, | |
409 | PCIE_ATU_TYPE_MEM, | |
410 | info->phys_base, | |
411 | 0, | |
412 | 4 * 1024 * 1024 * 1024ULL); | |
413 | } | |
414 | ||
415 | /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ | |
416 | static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) | |
417 | { | |
418 | if (size < 4 * 1024) | |
419 | return; | |
420 | ||
421 | switch (bar) { | |
422 | case 0: | |
423 | writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); | |
424 | break; | |
425 | case 1: | |
426 | writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); | |
427 | break; | |
428 | case 2: | |
429 | writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); | |
430 | writel(0, bar_base + PCI_BASE_ADDRESS_3); | |
431 | break; | |
432 | case 4: | |
433 | writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); | |
434 | writel(0, bar_base + PCI_BASE_ADDRESS_5); | |
435 | break; | |
436 | default: | |
437 | break; | |
438 | } | |
439 | } | |
440 | ||
441 | static void ls_pcie_ep_setup_bars(void *bar_base) | |
442 | { | |
443 | /* BAR0 - 32bit - 4K configuration */ | |
444 | ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); | |
445 | /* BAR1 - 32bit - 8K MSIX*/ | |
446 | ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); | |
447 | /* BAR2 - 64bit - 4K MEM desciptor */ | |
448 | ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); | |
449 | /* BAR4 - 64bit - 1M MEM*/ | |
450 | ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); | |
451 | } | |
452 | ||
453 | static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) | |
454 | { | |
455 | struct pci_controller *hose = &pcie->hose; | |
456 | pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); | |
457 | int sriov; | |
458 | ||
459 | sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV); | |
460 | if (sriov) { | |
461 | int pf, vf; | |
462 | ||
463 | for (pf = 0; pf < PCIE_PF_NUM; pf++) { | |
464 | for (vf = 0; vf <= PCIE_VF_NUM; vf++) { | |
af523a0d | 465 | #ifndef CONFIG_LS102XA |
01cafced ML |
466 | writel(PCIE_LCTRL0_VAL(pf, vf), |
467 | pcie->dbi + PCIE_LUT_BASE + | |
468 | PCIE_LUT_LCTRL0); | |
af523a0d | 469 | #endif |
01cafced ML |
470 | ls_pcie_ep_setup_bars(pcie->dbi); |
471 | ls_pcie_ep_setup_atu(pcie, info); | |
472 | } | |
473 | } | |
474 | ||
475 | /* Disable CFG2 */ | |
af523a0d | 476 | #ifndef CONFIG_LS102XA |
01cafced | 477 | writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); |
af523a0d | 478 | #endif |
01cafced ML |
479 | } else { |
480 | ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); | |
481 | ls_pcie_ep_setup_atu(pcie, info); | |
482 | } | |
483 | } | |
484 | ||
e4e8cb71 ML |
485 | int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) |
486 | { | |
487 | struct ls_pcie *pcie; | |
488 | struct pci_controller *hose; | |
489 | int num = dev - PCIE1; | |
490 | pci_dev_t pdev = PCI_BDF(busno, 0, 0); | |
491 | int i, linkup, ep_mode; | |
492 | u8 header_type; | |
493 | u16 temp16; | |
494 | ||
495 | if (!is_serdes_configured(dev)) { | |
496 | printf("PCIe%d: disabled\n", num + 1); | |
497 | return busno; | |
498 | } | |
499 | ||
500 | pcie = malloc(sizeof(*pcie)); | |
501 | if (!pcie) | |
502 | return busno; | |
503 | memset(pcie, 0, sizeof(*pcie)); | |
504 | ||
505 | hose = &pcie->hose; | |
506 | hose->priv_data = pcie; | |
507 | hose->first_busno = busno; | |
508 | pcie->idx = num; | |
509 | pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE); | |
510 | pcie->va_cfg0 = map_physmem(info->cfg0_phys, | |
511 | info->cfg0_size, | |
512 | MAP_NOCACHE); | |
513 | pcie->va_cfg1 = map_physmem(info->cfg1_phys, | |
514 | info->cfg1_size, | |
515 | MAP_NOCACHE); | |
516 | ||
517 | /* outbound memory */ | |
518 | pci_set_region(&hose->regions[0], | |
519 | (pci_size_t)info->mem_bus, | |
520 | (phys_size_t)info->mem_phys, | |
521 | (pci_size_t)info->mem_size, | |
522 | PCI_REGION_MEM); | |
523 | ||
524 | /* outbound io */ | |
525 | pci_set_region(&hose->regions[1], | |
526 | (pci_size_t)info->io_bus, | |
527 | (phys_size_t)info->io_phys, | |
528 | (pci_size_t)info->io_size, | |
529 | PCI_REGION_IO); | |
530 | ||
531 | /* System memory space */ | |
532 | pci_set_region(&hose->regions[2], | |
533 | CONFIG_SYS_PCI_MEMORY_BUS, | |
534 | CONFIG_SYS_PCI_MEMORY_PHYS, | |
535 | CONFIG_SYS_PCI_MEMORY_SIZE, | |
536 | PCI_REGION_SYS_MEMORY); | |
537 | ||
538 | hose->region_count = 3; | |
539 | ||
540 | for (i = 0; i < hose->region_count; i++) | |
541 | debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", | |
542 | i, | |
543 | (u64)hose->regions[i].phys_start, | |
544 | (u64)hose->regions[i].bus_start, | |
545 | (u64)hose->regions[i].size, | |
546 | hose->regions[i].flags); | |
547 | ||
548 | pci_set_ops(hose, | |
549 | pci_hose_read_config_byte_via_dword, | |
550 | pci_hose_read_config_word_via_dword, | |
551 | ls_pcie_read_config, | |
552 | pci_hose_write_config_byte_via_dword, | |
553 | pci_hose_write_config_word_via_dword, | |
554 | ls_pcie_write_config); | |
555 | ||
556 | pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type); | |
557 | ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; | |
558 | printf("PCIe%u: %s ", info->pci_num, | |
559 | ep_mode ? "Endpoint" : "Root Complex"); | |
560 | ||
01cafced ML |
561 | if (ep_mode) |
562 | ls_pcie_setup_ep(pcie, info); | |
563 | else | |
564 | ls_pcie_setup_ctrl(pcie, info); | |
565 | ||
e4e8cb71 ML |
566 | linkup = ls_pcie_link_up(pcie); |
567 | ||
568 | if (!linkup) { | |
569 | /* Let the user know there's no PCIe link */ | |
570 | printf("no link, regs @ 0x%lx\n", info->regs); | |
571 | hose->last_busno = hose->first_busno; | |
572 | return busno; | |
573 | } | |
574 | ||
575 | /* Print the negotiated PCIe link width */ | |
00704590 ML |
576 | pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16); |
577 | printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, | |
578 | (temp16 & 0xf), info->regs); | |
e4e8cb71 ML |
579 | |
580 | if (ep_mode) | |
581 | return busno; | |
582 | ||
e4e8cb71 ML |
583 | pci_register_hose(hose); |
584 | ||
585 | hose->last_busno = pci_hose_scan(hose); | |
586 | ||
587 | printf("PCIe%x: Bus %02x - %02x\n", | |
588 | info->pci_num, hose->first_busno, hose->last_busno); | |
589 | ||
590 | return hose->last_busno + 1; | |
591 | } | |
592 | ||
593 | int ls_pcie_init_board(int busno) | |
594 | { | |
595 | struct ls_pcie_info info; | |
596 | ||
597 | #ifdef CONFIG_PCIE1 | |
598 | SET_LS_PCIE_INFO(info, 1); | |
599 | busno = ls_pcie_init_ctrl(busno, PCIE1, &info); | |
600 | #endif | |
601 | ||
602 | #ifdef CONFIG_PCIE2 | |
603 | SET_LS_PCIE_INFO(info, 2); | |
604 | busno = ls_pcie_init_ctrl(busno, PCIE2, &info); | |
605 | #endif | |
606 | ||
607 | #ifdef CONFIG_PCIE3 | |
608 | SET_LS_PCIE_INFO(info, 3); | |
609 | busno = ls_pcie_init_ctrl(busno, PCIE3, &info); | |
610 | #endif | |
611 | ||
612 | #ifdef CONFIG_PCIE4 | |
613 | SET_LS_PCIE_INFO(info, 4); | |
614 | busno = ls_pcie_init_ctrl(busno, PCIE4, &info); | |
615 | #endif | |
616 | ||
617 | return busno; | |
618 | } | |
619 | ||
620 | void pci_init_board(void) | |
621 | { | |
622 | ls_pcie_init_board(0); | |
623 | } | |
624 | ||
da419027 ML |
625 | #ifdef CONFIG_OF_BOARD_SETUP |
626 | #include <libfdt.h> | |
627 | #include <fdt_support.h> | |
628 | ||
629 | static void ft_pcie_ls_setup(void *blob, const char *pci_compat, | |
630 | unsigned long ctrl_addr, enum srds_prtcl dev) | |
631 | { | |
632 | int off; | |
633 | ||
634 | off = fdt_node_offset_by_compat_reg(blob, pci_compat, | |
635 | (phys_addr_t)ctrl_addr); | |
636 | if (off < 0) | |
637 | return; | |
638 | ||
639 | if (!is_serdes_configured(dev)) | |
640 | fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); | |
641 | } | |
642 | ||
d42bd345 | 643 | void ft_pci_setup(void *blob, bd_t *bd) |
da419027 ML |
644 | { |
645 | #ifdef CONFIG_PCIE1 | |
646 | ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); | |
647 | #endif | |
648 | ||
649 | #ifdef CONFIG_PCIE2 | |
650 | ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); | |
651 | #endif | |
e4e8cb71 ML |
652 | |
653 | #ifdef CONFIG_PCIE3 | |
654 | ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3); | |
655 | #endif | |
656 | ||
657 | #ifdef CONFIG_PCIE4 | |
658 | ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4); | |
659 | #endif | |
da419027 ML |
660 | } |
661 | ||
662 | #else | |
d42bd345 | 663 | void ft_pci_setup(void *blob, bd_t *bd) |
da419027 ML |
664 | { |
665 | } | |
666 | #endif | |
70e52d21 | 667 | |
06b53010 | 668 | #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) |
70e52d21 SY |
669 | |
670 | void pcie_set_available_streamids(void *blob, const char *pcie_path, | |
671 | u32 *stream_ids, int count) | |
672 | { | |
673 | int nodeoffset; | |
674 | int i; | |
675 | ||
676 | nodeoffset = fdt_path_offset(blob, pcie_path); | |
677 | if (nodeoffset < 0) { | |
678 | printf("\n%s: ERROR: unable to update PCIe node\n", __func__); | |
679 | return; | |
680 | } | |
681 | ||
682 | /* for each stream ID, append to mmu-masters */ | |
683 | for (i = 0; i < count; i++) { | |
684 | fdt_appendprop_u32(blob, nodeoffset, "available-stream-ids", | |
685 | stream_ids[i]); | |
686 | } | |
687 | } | |
688 | ||
689 | #define MAX_STREAM_IDS 4 | |
690 | void fdt_fixup_smmu_pcie(void *blob) | |
691 | { | |
692 | int count; | |
693 | u32 stream_ids[MAX_STREAM_IDS]; | |
6923b069 | 694 | u32 ctlr_streamid = 0x300; |
70e52d21 SY |
695 | |
696 | #ifdef CONFIG_PCIE1 | |
697 | /* PEX1 stream ID fixup */ | |
698 | count = FSL_PEX1_STREAM_ID_END - FSL_PEX1_STREAM_ID_START + 1; | |
699 | alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids, | |
700 | MAX_STREAM_IDS); | |
701 | pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count); | |
6923b069 VS |
702 | append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000", |
703 | &ctlr_streamid, 1); | |
70e52d21 SY |
704 | #endif |
705 | ||
706 | #ifdef CONFIG_PCIE2 | |
707 | /* PEX2 stream ID fixup */ | |
708 | count = FSL_PEX2_STREAM_ID_END - FSL_PEX2_STREAM_ID_START + 1; | |
709 | alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids, | |
710 | MAX_STREAM_IDS); | |
711 | pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count); | |
6923b069 VS |
712 | append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000", |
713 | &ctlr_streamid, 1); | |
70e52d21 SY |
714 | #endif |
715 | ||
716 | #ifdef CONFIG_PCIE3 | |
717 | /* PEX3 stream ID fixup */ | |
718 | count = FSL_PEX3_STREAM_ID_END - FSL_PEX3_STREAM_ID_START + 1; | |
719 | alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids, | |
720 | MAX_STREAM_IDS); | |
721 | pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count); | |
6923b069 VS |
722 | append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000", |
723 | &ctlr_streamid, 1); | |
70e52d21 SY |
724 | #endif |
725 | ||
726 | #ifdef CONFIG_PCIE4 | |
727 | /* PEX4 stream ID fixup */ | |
728 | count = FSL_PEX4_STREAM_ID_END - FSL_PEX4_STREAM_ID_START + 1; | |
729 | alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids, | |
730 | MAX_STREAM_IDS); | |
731 | pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count); | |
6923b069 VS |
732 | append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000", |
733 | &ctlr_streamid, 1); | |
70e52d21 SY |
734 | #endif |
735 | } | |
736 | #endif |