]>
Commit | Line | Data |
---|---|---|
e85390dc WD |
1 | /* |
2 | * COM1 NS16550 support | |
a47a12be | 3 | * originally from linux source (arch/powerpc/boot/ns16550.c) |
6d0f6bcf | 4 | * modified to use CONFIG_SYS_ISA_MEM and new defines |
e85390dc WD |
5 | */ |
6 | ||
fa54eb12 | 7 | #include <common.h> |
12e431b2 SG |
8 | #include <dm.h> |
9 | #include <errno.h> | |
10 | #include <fdtdec.h> | |
0eb25b61 | 11 | #include <mapmem.h> |
e85390dc | 12 | #include <ns16550.h> |
12e431b2 | 13 | #include <serial.h> |
a1b322a9 | 14 | #include <watchdog.h> |
167cdad1 GR |
15 | #include <linux/types.h> |
16 | #include <asm/io.h> | |
e85390dc | 17 | |
12e431b2 SG |
18 | DECLARE_GLOBAL_DATA_PTR; |
19 | ||
200779e3 DZ |
20 | #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ |
21 | #define UART_MCRVAL (UART_MCR_DTR | \ | |
22 | UART_MCR_RTS) /* RTS/DTR */ | |
23 | #define UART_FCRVAL (UART_FCR_FIFO_EN | \ | |
24 | UART_FCR_RXSR | \ | |
25 | UART_FCR_TXSR) /* Clear & enable FIFOs */ | |
12e431b2 SG |
26 | |
27 | #ifndef CONFIG_DM_SERIAL | |
167cdad1 | 28 | #ifdef CONFIG_SYS_NS16550_PORT_MAPPED |
f8df9d0d SG |
29 | #define serial_out(x, y) outb(x, (ulong)y) |
30 | #define serial_in(y) inb((ulong)y) | |
79df1208 | 31 | #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0) |
f8df9d0d SG |
32 | #define serial_out(x, y) out_be32(y, x) |
33 | #define serial_in(y) in_be32(y) | |
79df1208 | 34 | #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0) |
f8df9d0d SG |
35 | #define serial_out(x, y) out_le32(y, x) |
36 | #define serial_in(y) in_le32(y) | |
167cdad1 | 37 | #else |
f8df9d0d SG |
38 | #define serial_out(x, y) writeb(x, y) |
39 | #define serial_in(y) readb(y) | |
167cdad1 | 40 | #endif |
12e431b2 | 41 | #endif /* !CONFIG_DM_SERIAL */ |
e85390dc | 42 | |
7c387646 | 43 | #if defined(CONFIG_SOC_KEYSTONE) |
ef509b90 VA |
44 | #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 |
45 | #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) | |
d57dee57 KM |
46 | #undef UART_MCRVAL |
47 | #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL | |
48 | #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) | |
49 | #else | |
50 | #define UART_MCRVAL (UART_MCR_RTS) | |
51 | #endif | |
ef509b90 VA |
52 | #endif |
53 | ||
a160ea0b PW |
54 | #ifndef CONFIG_SYS_NS16550_IER |
55 | #define CONFIG_SYS_NS16550_IER 0x00 | |
56 | #endif /* CONFIG_SYS_NS16550_IER */ | |
57 | ||
12e431b2 | 58 | #ifdef CONFIG_DM_SERIAL |
12e431b2 | 59 | |
76571674 SG |
60 | static inline void serial_out_shift(unsigned char *addr, int shift, int value) |
61 | { | |
12e431b2 | 62 | #ifdef CONFIG_SYS_NS16550_PORT_MAPPED |
1f77690e | 63 | outb(value, (ulong)addr); |
12e431b2 SG |
64 | #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) |
65 | out_le32(addr, value); | |
66 | #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) | |
67 | out_be32(addr, value); | |
68 | #elif defined(CONFIG_SYS_BIG_ENDIAN) | |
76571674 | 69 | writeb(value, addr + (1 << shift) - 1); |
12e431b2 SG |
70 | #else |
71 | writeb(value, addr); | |
72 | #endif | |
73 | } | |
74 | ||
76571674 | 75 | static inline int serial_in_shift(unsigned char *addr, int shift) |
12e431b2 | 76 | { |
12e431b2 | 77 | #ifdef CONFIG_SYS_NS16550_PORT_MAPPED |
1f77690e | 78 | return inb((ulong)addr); |
12e431b2 SG |
79 | #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) |
80 | return in_le32(addr); | |
81 | #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) | |
82 | return in_be32(addr); | |
83 | #elif defined(CONFIG_SYS_BIG_ENDIAN) | |
20379c11 | 84 | return readb(addr + (1 << shift) - 1); |
12e431b2 SG |
85 | #else |
86 | return readb(addr); | |
87 | #endif | |
88 | } | |
89 | ||
76571674 SG |
90 | static void ns16550_writeb(NS16550_t port, int offset, int value) |
91 | { | |
92 | struct ns16550_platdata *plat = port->plat; | |
93 | unsigned char *addr; | |
94 | ||
95 | offset *= 1 << plat->reg_shift; | |
96 | addr = map_sysmem(plat->base, 0) + offset; | |
97 | /* | |
98 | * As far as we know it doesn't make sense to support selection of | |
99 | * these options at run-time, so use the existing CONFIG options. | |
100 | */ | |
101 | serial_out_shift(addr, plat->reg_shift, value); | |
102 | } | |
103 | ||
104 | static int ns16550_readb(NS16550_t port, int offset) | |
105 | { | |
106 | struct ns16550_platdata *plat = port->plat; | |
107 | unsigned char *addr; | |
108 | ||
109 | offset *= 1 << plat->reg_shift; | |
110 | addr = map_sysmem(plat->base, 0) + offset; | |
111 | ||
112 | return serial_in_shift(addr, plat->reg_shift); | |
113 | } | |
114 | ||
12e431b2 SG |
115 | /* We can clean these up once everything is moved to driver model */ |
116 | #define serial_out(value, addr) \ | |
117 | ns16550_writeb(com_port, addr - (unsigned char *)com_port, value) | |
118 | #define serial_in(addr) \ | |
119 | ns16550_readb(com_port, addr - (unsigned char *)com_port) | |
120 | #endif | |
121 | ||
21d00436 | 122 | static inline int calc_divisor(NS16550_t port, int clock, int baudrate) |
fa54eb12 SG |
123 | { |
124 | const unsigned int mode_x_div = 16; | |
125 | ||
21d00436 SG |
126 | return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); |
127 | } | |
128 | ||
129 | int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) | |
130 | { | |
fa54eb12 SG |
131 | #ifdef CONFIG_OMAP1510 |
132 | /* If can't cleanly clock 115200 set div to 1 */ | |
133 | if ((clock == 12000000) && (baudrate == 115200)) { | |
134 | port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ | |
135 | return 1; /* return 1 for base divisor */ | |
136 | } | |
137 | port->osc_12m_sel = 0; /* clear if previsouly set */ | |
138 | #endif | |
139 | ||
21d00436 | 140 | return calc_divisor(port, clock, baudrate); |
fa54eb12 SG |
141 | } |
142 | ||
8bbe33c8 SG |
143 | static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) |
144 | { | |
145 | serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); | |
146 | serial_out(baud_divisor & 0xff, &com_port->dll); | |
147 | serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); | |
148 | serial_out(UART_LCRVAL, &com_port->lcr); | |
149 | } | |
150 | ||
f8df9d0d | 151 | void NS16550_init(NS16550_t com_port, int baud_divisor) |
e85390dc | 152 | { |
956a8bae GG |
153 | #if (defined(CONFIG_SPL_BUILD) && \ |
154 | (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) | |
fd2aeac5 | 155 | /* |
956a8bae GG |
156 | * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode |
157 | * before SPL starts only THRE bit is set. We have to empty the | |
158 | * transmitter before initialization starts. | |
fd2aeac5 MH |
159 | */ |
160 | if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) | |
161 | == UART_LSR_THRE) { | |
12e431b2 SG |
162 | if (baud_divisor != -1) |
163 | NS16550_setbrg(com_port, baud_divisor); | |
fd2aeac5 MH |
164 | serial_out(0, &com_port->mdr1); |
165 | } | |
166 | #endif | |
167 | ||
cb55b332 SW |
168 | while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) |
169 | ; | |
170 | ||
a160ea0b | 171 | serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); |
456ccfdf TR |
172 | #if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \ |
173 | defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) | |
167cdad1 | 174 | serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ |
945af8d7 | 175 | #endif |
8bbe33c8 | 176 | NS16550_setbrg(com_port, 0); |
167cdad1 GR |
177 | serial_out(UART_MCRVAL, &com_port->mcr); |
178 | serial_out(UART_FCRVAL, &com_port->fcr); | |
12e431b2 SG |
179 | if (baud_divisor != -1) |
180 | NS16550_setbrg(com_port, baud_divisor); | |
8ac22a60 | 181 | #if defined(CONFIG_OMAP) || \ |
6213a68f | 182 | defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ |
9ed6e412 | 183 | defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) |
5289e83a | 184 | |
f8df9d0d SG |
185 | /* /16 is proper to hit 115200 with 48MHz */ |
186 | serial_out(0, &com_port->mdr1); | |
b4746d8b | 187 | #endif /* CONFIG_OMAP */ |
7c387646 | 188 | #if defined(CONFIG_SOC_KEYSTONE) |
ef509b90 VA |
189 | serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); |
190 | #endif | |
e85390dc WD |
191 | } |
192 | ||
f5675aa5 | 193 | #ifndef CONFIG_NS16550_MIN_FUNCTIONS |
f8df9d0d | 194 | void NS16550_reinit(NS16550_t com_port, int baud_divisor) |
e85390dc | 195 | { |
a160ea0b | 196 | serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); |
8bbe33c8 | 197 | NS16550_setbrg(com_port, 0); |
167cdad1 GR |
198 | serial_out(UART_MCRVAL, &com_port->mcr); |
199 | serial_out(UART_FCRVAL, &com_port->fcr); | |
8bbe33c8 | 200 | NS16550_setbrg(com_port, baud_divisor); |
e85390dc | 201 | } |
f5675aa5 | 202 | #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ |
e85390dc | 203 | |
f8df9d0d | 204 | void NS16550_putc(NS16550_t com_port, char c) |
e85390dc | 205 | { |
f8df9d0d SG |
206 | while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) |
207 | ; | |
167cdad1 | 208 | serial_out(c, &com_port->thr); |
1a2d9b30 SR |
209 | |
210 | /* | |
211 | * Call watchdog_reset() upon newline. This is done here in putc | |
212 | * since the environment code uses a single puts() to print the complete | |
213 | * environment upon "printenv". So we can't put this watchdog call | |
214 | * in puts(). | |
215 | */ | |
216 | if (c == '\n') | |
217 | WATCHDOG_RESET(); | |
e85390dc WD |
218 | } |
219 | ||
f5675aa5 | 220 | #ifndef CONFIG_NS16550_MIN_FUNCTIONS |
f8df9d0d | 221 | char NS16550_getc(NS16550_t com_port) |
e85390dc | 222 | { |
167cdad1 | 223 | while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { |
f2041388 | 224 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY) |
232c150a WD |
225 | extern void usbtty_poll(void); |
226 | usbtty_poll(); | |
227 | #endif | |
a1b322a9 | 228 | WATCHDOG_RESET(); |
232c150a | 229 | } |
167cdad1 | 230 | return serial_in(&com_port->rbr); |
e85390dc WD |
231 | } |
232 | ||
f8df9d0d | 233 | int NS16550_tstc(NS16550_t com_port) |
e85390dc | 234 | { |
f8df9d0d | 235 | return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; |
e85390dc WD |
236 | } |
237 | ||
f5675aa5 | 238 | #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ |
12e431b2 | 239 | |
21d00436 SG |
240 | #ifdef CONFIG_DEBUG_UART_NS16550 |
241 | ||
242 | #include <debug_uart.h> | |
243 | ||
244 | void debug_uart_init(void) | |
245 | { | |
246 | struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; | |
247 | int baud_divisor; | |
248 | ||
249 | /* | |
250 | * We copy the code from above because it is already horribly messy. | |
251 | * Trying to refactor to nicely remove the duplication doesn't seem | |
252 | * feasible. The better fix is to move all users of this driver to | |
253 | * driver model. | |
254 | */ | |
255 | baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, | |
256 | CONFIG_BAUDRATE); | |
257 | ||
258 | serial_out_shift(&com_port->ier, 0, CONFIG_SYS_NS16550_IER); | |
259 | serial_out_shift(&com_port->mcr, 0, UART_MCRVAL); | |
260 | serial_out_shift(&com_port->fcr, 0, UART_FCRVAL); | |
261 | ||
262 | serial_out_shift(&com_port->lcr, 0, UART_LCR_BKSE | UART_LCRVAL); | |
263 | serial_out_shift(&com_port->dll, 0, baud_divisor & 0xff); | |
264 | serial_out_shift(&com_port->dlm, 0, (baud_divisor >> 8) & 0xff); | |
265 | serial_out_shift(&com_port->lcr, 0, UART_LCRVAL); | |
266 | } | |
267 | ||
268 | static inline void _debug_uart_putc(int ch) | |
269 | { | |
270 | struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; | |
271 | ||
272 | while (!(serial_in_shift(&com_port->lsr, 0) & UART_LSR_THRE)) | |
273 | ; | |
274 | serial_out_shift(&com_port->thr, 0, ch); | |
275 | } | |
276 | ||
277 | DEBUG_UART_FUNCS | |
278 | ||
279 | #endif | |
280 | ||
12e431b2 SG |
281 | #ifdef CONFIG_DM_SERIAL |
282 | static int ns16550_serial_putc(struct udevice *dev, const char ch) | |
283 | { | |
284 | struct NS16550 *const com_port = dev_get_priv(dev); | |
285 | ||
286 | if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) | |
287 | return -EAGAIN; | |
288 | serial_out(ch, &com_port->thr); | |
289 | ||
290 | /* | |
291 | * Call watchdog_reset() upon newline. This is done here in putc | |
292 | * since the environment code uses a single puts() to print the complete | |
293 | * environment upon "printenv". So we can't put this watchdog call | |
294 | * in puts(). | |
295 | */ | |
296 | if (ch == '\n') | |
297 | WATCHDOG_RESET(); | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | static int ns16550_serial_pending(struct udevice *dev, bool input) | |
303 | { | |
304 | struct NS16550 *const com_port = dev_get_priv(dev); | |
305 | ||
306 | if (input) | |
307 | return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0; | |
308 | else | |
309 | return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1; | |
310 | } | |
311 | ||
312 | static int ns16550_serial_getc(struct udevice *dev) | |
313 | { | |
314 | struct NS16550 *const com_port = dev_get_priv(dev); | |
315 | ||
aea2be20 | 316 | if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) |
12e431b2 SG |
317 | return -EAGAIN; |
318 | ||
319 | return serial_in(&com_port->rbr); | |
320 | } | |
321 | ||
322 | static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) | |
323 | { | |
324 | struct NS16550 *const com_port = dev_get_priv(dev); | |
325 | struct ns16550_platdata *plat = com_port->plat; | |
326 | int clock_divisor; | |
327 | ||
328 | clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); | |
329 | ||
330 | NS16550_setbrg(com_port, clock_divisor); | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
335 | int ns16550_serial_probe(struct udevice *dev) | |
336 | { | |
337 | struct NS16550 *const com_port = dev_get_priv(dev); | |
338 | ||
11c1a878 | 339 | com_port->plat = dev_get_platdata(dev); |
12e431b2 SG |
340 | NS16550_init(com_port, -1); |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
11c1a878 | 345 | #ifdef CONFIG_OF_CONTROL |
12e431b2 SG |
346 | int ns16550_serial_ofdata_to_platdata(struct udevice *dev) |
347 | { | |
12e431b2 SG |
348 | struct ns16550_platdata *plat = dev->platdata; |
349 | fdt_addr_t addr; | |
350 | ||
3db886a5 | 351 | /* try Processor Local Bus device first */ |
12e431b2 | 352 | addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); |
3db886a5 BM |
353 | #ifdef CONFIG_PCI |
354 | if (addr == FDT_ADDR_T_NONE) { | |
355 | /* then try pci device */ | |
356 | struct fdt_pci_addr pci_addr; | |
357 | u32 bar; | |
358 | int ret; | |
359 | ||
360 | /* we prefer to use a memory-mapped register */ | |
361 | ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, | |
362 | FDT_PCI_SPACE_MEM32, "reg", | |
363 | &pci_addr); | |
364 | if (ret) { | |
365 | /* try if there is any i/o-mapped register */ | |
366 | ret = fdtdec_get_pci_addr(gd->fdt_blob, | |
367 | dev->of_offset, | |
368 | FDT_PCI_SPACE_IO, | |
369 | "reg", &pci_addr); | |
370 | if (ret) | |
371 | return ret; | |
372 | } | |
373 | ||
374 | ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset, | |
375 | &pci_addr, &bar); | |
376 | if (ret) | |
377 | return ret; | |
378 | ||
379 | addr = bar; | |
380 | } | |
381 | #endif | |
382 | ||
12e431b2 SG |
383 | if (addr == FDT_ADDR_T_NONE) |
384 | return -EINVAL; | |
385 | ||
167efe01 | 386 | plat->base = addr; |
12e431b2 SG |
387 | plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, |
388 | "reg-shift", 1); | |
12e431b2 SG |
389 | |
390 | return 0; | |
391 | } | |
11c1a878 | 392 | #endif |
12e431b2 SG |
393 | |
394 | const struct dm_serial_ops ns16550_serial_ops = { | |
395 | .putc = ns16550_serial_putc, | |
396 | .pending = ns16550_serial_pending, | |
397 | .getc = ns16550_serial_getc, | |
398 | .setbrg = ns16550_serial_setbrg, | |
399 | }; | |
400 | #endif /* CONFIG_DM_SERIAL */ |