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Commit | Line | Data |
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38254f45 GL |
1 | /* |
2 | * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
38254f45 GL |
5 | */ |
6 | ||
7 | #include <common.h> | |
d255bb0e | 8 | #include <malloc.h> |
38254f45 | 9 | #include <spi.h> |
1221ce45 | 10 | #include <linux/errno.h> |
38254f45 | 11 | #include <asm/io.h> |
d8e0ca85 | 12 | #include <asm/gpio.h> |
86271115 SB |
13 | #include <asm/arch/imx-regs.h> |
14 | #include <asm/arch/clock.h> | |
3acb011c | 15 | #include <asm/imx-common/spi.h> |
38254f45 GL |
16 | |
17 | #ifdef CONFIG_MX27 | |
18 | /* i.MX27 has a completely wrong register layout and register definitions in the | |
19 | * datasheet, the correct one is in the Freescale's Linux driver */ | |
20 | ||
61a58a16 | 21 | #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ |
38254f45 | 22 | "See linux mxc_spi driver from Freescale for details." |
08c61a58 | 23 | #endif |
c9d59c7f SB |
24 | |
25 | static unsigned long spi_bases[] = { | |
08c61a58 | 26 | MXC_SPI_BASE_ADDRESSES |
c9d59c7f SB |
27 | }; |
28 | ||
155fa9af NK |
29 | __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) |
30 | { | |
31 | return -1; | |
32 | } | |
33 | ||
c4ea1424 SB |
34 | #define OUT MXC_GPIO_DIRECTION_OUT |
35 | ||
ac87c17d SB |
36 | #define reg_read readl |
37 | #define reg_write(a, v) writel(v, a) | |
38 | ||
f659b573 HS |
39 | #if !defined(CONFIG_SYS_SPI_MXC_WAIT) |
40 | #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ | |
41 | #endif | |
42 | ||
d255bb0e HS |
43 | struct mxc_spi_slave { |
44 | struct spi_slave slave; | |
45 | unsigned long base; | |
46 | u32 ctrl_reg; | |
08c61a58 | 47 | #if defined(MXC_ECSPI) |
d205ddcf SB |
48 | u32 cfg_reg; |
49 | #endif | |
fc7a93c8 | 50 | int gpio; |
c4ea1424 | 51 | int ss_pol; |
027a9a00 MN |
52 | unsigned int max_hz; |
53 | unsigned int mode; | |
38254f45 | 54 | }; |
d255bb0e HS |
55 | |
56 | static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) | |
57 | { | |
58 | return container_of(slave, struct mxc_spi_slave, slave); | |
59 | } | |
38254f45 | 60 | |
d205ddcf SB |
61 | void spi_cs_activate(struct spi_slave *slave) |
62 | { | |
63 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); | |
64 | if (mxcs->gpio > 0) | |
d8e0ca85 | 65 | gpio_set_value(mxcs->gpio, mxcs->ss_pol); |
d205ddcf SB |
66 | } |
67 | ||
68 | void spi_cs_deactivate(struct spi_slave *slave) | |
69 | { | |
70 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); | |
71 | if (mxcs->gpio > 0) | |
d8e0ca85 | 72 | gpio_set_value(mxcs->gpio, |
c4ea1424 | 73 | !(mxcs->ss_pol)); |
d205ddcf SB |
74 | } |
75 | ||
afaa9f65 AG |
76 | u32 get_cspi_div(u32 div) |
77 | { | |
78 | int i; | |
79 | ||
80 | for (i = 0; i < 8; i++) { | |
81 | if (div <= (4 << i)) | |
82 | return i; | |
83 | } | |
84 | return i; | |
85 | } | |
86 | ||
08c61a58 | 87 | #ifdef MXC_CSPI |
027a9a00 | 88 | static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) |
c9d59c7f SB |
89 | { |
90 | unsigned int ctrl_reg; | |
afaa9f65 AG |
91 | u32 clk_src; |
92 | u32 div; | |
027a9a00 MN |
93 | unsigned int max_hz = mxcs->max_hz; |
94 | unsigned int mode = mxcs->mode; | |
afaa9f65 AG |
95 | |
96 | clk_src = mxc_get_clock(MXC_CSPI_CLK); | |
97 | ||
cd200403 | 98 | div = DIV_ROUND_UP(clk_src, max_hz); |
afaa9f65 AG |
99 | div = get_cspi_div(div); |
100 | ||
101 | debug("clk %d Hz, div %d, real clk %d Hz\n", | |
102 | max_hz, div, clk_src / (4 << div)); | |
c9d59c7f SB |
103 | |
104 | ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | | |
105 | MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | | |
afaa9f65 | 106 | MXC_CSPICTRL_DATARATE(div) | |
c9d59c7f SB |
107 | MXC_CSPICTRL_EN | |
108 | #ifdef CONFIG_MX35 | |
109 | MXC_CSPICTRL_SSCTL | | |
110 | #endif | |
111 | MXC_CSPICTRL_MODE; | |
112 | ||
113 | if (mode & SPI_CPHA) | |
114 | ctrl_reg |= MXC_CSPICTRL_PHA; | |
115 | if (mode & SPI_CPOL) | |
116 | ctrl_reg |= MXC_CSPICTRL_POL; | |
117 | if (mode & SPI_CS_HIGH) | |
118 | ctrl_reg |= MXC_CSPICTRL_SSPOL; | |
119 | mxcs->ctrl_reg = ctrl_reg; | |
120 | ||
121 | return 0; | |
122 | } | |
123 | #endif | |
124 | ||
08c61a58 | 125 | #ifdef MXC_ECSPI |
027a9a00 | 126 | static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) |
d205ddcf SB |
127 | { |
128 | u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); | |
9a30903b | 129 | s32 reg_ctrl, reg_config; |
5d584cce MN |
130 | u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; |
131 | u32 pre_div = 0, post_div = 0; | |
ac87c17d | 132 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
027a9a00 MN |
133 | unsigned int max_hz = mxcs->max_hz; |
134 | unsigned int mode = mxcs->mode; | |
d205ddcf | 135 | |
0f1411bc FE |
136 | /* |
137 | * Reset SPI and set all CSs to master mode, if toggling | |
138 | * between slave and master mode we might see a glitch | |
139 | * on the clock line | |
140 | */ | |
141 | reg_ctrl = MXC_CSPICTRL_MODE_MASK; | |
142 | reg_write(®s->ctrl, reg_ctrl); | |
143 | reg_ctrl |= MXC_CSPICTRL_EN; | |
144 | reg_write(®s->ctrl, reg_ctrl); | |
d205ddcf | 145 | |
d205ddcf | 146 | if (clk_src > max_hz) { |
9a30903b DB |
147 | pre_div = (clk_src - 1) / max_hz; |
148 | /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ | |
149 | post_div = fls(pre_div); | |
150 | if (post_div > 4) { | |
151 | post_div -= 4; | |
152 | if (post_div >= 16) { | |
d205ddcf SB |
153 | printf("Error: no divider for the freq: %d\n", |
154 | max_hz); | |
155 | return -1; | |
156 | } | |
9a30903b DB |
157 | pre_div >>= post_div; |
158 | } else { | |
159 | post_div = 0; | |
d205ddcf SB |
160 | } |
161 | } | |
162 | ||
163 | debug("pre_div = %d, post_div=%d\n", pre_div, post_div); | |
164 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | | |
165 | MXC_CSPICTRL_SELCHAN(cs); | |
166 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | | |
167 | MXC_CSPICTRL_PREDIV(pre_div); | |
168 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | | |
169 | MXC_CSPICTRL_POSTDIV(post_div); | |
170 | ||
d205ddcf SB |
171 | if (mode & SPI_CS_HIGH) |
172 | ss_pol = 1; | |
173 | ||
5d584cce | 174 | if (mode & SPI_CPOL) { |
d205ddcf | 175 | sclkpol = 1; |
5d584cce MN |
176 | sclkctl = 1; |
177 | } | |
d205ddcf SB |
178 | |
179 | if (mode & SPI_CPHA) | |
180 | sclkpha = 1; | |
181 | ||
ac87c17d | 182 | reg_config = reg_read(®s->cfg); |
d205ddcf SB |
183 | |
184 | /* | |
185 | * Configuration register setup | |
c9d59c7f | 186 | * The MX51 supports different setup for each SS |
d205ddcf SB |
187 | */ |
188 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | | |
189 | (ss_pol << (cs + MXC_CSPICON_SSPOL)); | |
190 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | | |
191 | (sclkpol << (cs + MXC_CSPICON_POL)); | |
5d584cce MN |
192 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | |
193 | (sclkctl << (cs + MXC_CSPICON_CTL)); | |
d205ddcf SB |
194 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | |
195 | (sclkpha << (cs + MXC_CSPICON_PHA)); | |
196 | ||
197 | debug("reg_ctrl = 0x%x\n", reg_ctrl); | |
ac87c17d | 198 | reg_write(®s->ctrl, reg_ctrl); |
d205ddcf | 199 | debug("reg_config = 0x%x\n", reg_config); |
ac87c17d | 200 | reg_write(®s->cfg, reg_config); |
d205ddcf SB |
201 | |
202 | /* save config register and control register */ | |
203 | mxcs->ctrl_reg = reg_ctrl; | |
204 | mxcs->cfg_reg = reg_config; | |
205 | ||
206 | /* clear interrupt reg */ | |
ac87c17d SB |
207 | reg_write(®s->intr, 0); |
208 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); | |
d205ddcf SB |
209 | |
210 | return 0; | |
211 | } | |
212 | #endif | |
213 | ||
2f721d17 SB |
214 | int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, |
215 | const u8 *dout, u8 *din, unsigned long flags) | |
38254f45 | 216 | { |
d255bb0e | 217 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
9675fed4 | 218 | int nbytes = DIV_ROUND_UP(bitlen, 8); |
2f721d17 | 219 | u32 data, cnt, i; |
ac87c17d | 220 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
f659b573 HS |
221 | u32 ts; |
222 | int status; | |
38254f45 | 223 | |
2f721d17 SB |
224 | debug("%s: bitlen %d dout 0x%x din 0x%x\n", |
225 | __func__, bitlen, (u32)dout, (u32)din); | |
d205ddcf SB |
226 | |
227 | mxcs->ctrl_reg = (mxcs->ctrl_reg & | |
228 | ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | | |
f9b6a157 | 229 | MXC_CSPICTRL_BITCOUNT(bitlen - 1); |
38254f45 | 230 | |
ac87c17d | 231 | reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); |
08c61a58 | 232 | #ifdef MXC_ECSPI |
ac87c17d | 233 | reg_write(®s->cfg, mxcs->cfg_reg); |
d205ddcf | 234 | #endif |
38254f45 | 235 | |
d205ddcf | 236 | /* Clear interrupt register */ |
ac87c17d | 237 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); |
fc7a93c8 | 238 | |
2f721d17 SB |
239 | /* |
240 | * The SPI controller works only with words, | |
241 | * check if less than a word is sent. | |
242 | * Access to the FIFO is only 32 bit | |
243 | */ | |
244 | if (bitlen % 32) { | |
245 | data = 0; | |
246 | cnt = (bitlen % 32) / 8; | |
247 | if (dout) { | |
248 | for (i = 0; i < cnt; i++) { | |
249 | data = (data << 8) | (*dout++ & 0xFF); | |
250 | } | |
251 | } | |
252 | debug("Sending SPI 0x%x\n", data); | |
253 | ||
ac87c17d | 254 | reg_write(®s->txdata, data); |
2f721d17 SB |
255 | nbytes -= cnt; |
256 | } | |
257 | ||
258 | data = 0; | |
259 | ||
260 | while (nbytes > 0) { | |
261 | data = 0; | |
262 | if (dout) { | |
263 | /* Buffer is not 32-bit aligned */ | |
264 | if ((unsigned long)dout & 0x03) { | |
265 | data = 0; | |
dff01094 | 266 | for (i = 0; i < 4; i++) |
2f721d17 | 267 | data = (data << 8) | (*dout++ & 0xFF); |
2f721d17 SB |
268 | } else { |
269 | data = *(u32 *)dout; | |
270 | data = cpu_to_be32(data); | |
6d5ce1bd | 271 | dout += 4; |
2f721d17 | 272 | } |
2f721d17 SB |
273 | } |
274 | debug("Sending SPI 0x%x\n", data); | |
ac87c17d | 275 | reg_write(®s->txdata, data); |
2f721d17 SB |
276 | nbytes -= 4; |
277 | } | |
38254f45 | 278 | |
d205ddcf | 279 | /* FIFO is written, now starts the transfer setting the XCH bit */ |
ac87c17d | 280 | reg_write(®s->ctrl, mxcs->ctrl_reg | |
d205ddcf | 281 | MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); |
38254f45 | 282 | |
f659b573 HS |
283 | ts = get_timer(0); |
284 | status = reg_read(®s->stat); | |
d205ddcf | 285 | /* Wait until the TC (Transfer completed) bit is set */ |
f659b573 HS |
286 | while ((status & MXC_CSPICTRL_TC) == 0) { |
287 | if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) { | |
288 | printf("spi_xchg_single: Timeout!\n"); | |
289 | return -1; | |
290 | } | |
291 | status = reg_read(®s->stat); | |
292 | } | |
38254f45 | 293 | |
d205ddcf | 294 | /* Transfer completed, clear any pending request */ |
ac87c17d | 295 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); |
d205ddcf | 296 | |
9675fed4 | 297 | nbytes = DIV_ROUND_UP(bitlen, 8); |
d205ddcf | 298 | |
2f721d17 | 299 | cnt = nbytes % 32; |
d205ddcf | 300 | |
2f721d17 | 301 | if (bitlen % 32) { |
ac87c17d | 302 | data = reg_read(®s->rxdata); |
2f721d17 | 303 | cnt = (bitlen % 32) / 8; |
dff01094 | 304 | data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); |
2f721d17 SB |
305 | debug("SPI Rx unaligned: 0x%x\n", data); |
306 | if (din) { | |
dff01094 AG |
307 | memcpy(din, &data, cnt); |
308 | din += cnt; | |
2f721d17 SB |
309 | } |
310 | nbytes -= cnt; | |
311 | } | |
312 | ||
313 | while (nbytes > 0) { | |
314 | u32 tmp; | |
ac87c17d | 315 | tmp = reg_read(®s->rxdata); |
2f721d17 SB |
316 | data = cpu_to_be32(tmp); |
317 | debug("SPI Rx: 0x%x 0x%x\n", tmp, data); | |
b4141195 | 318 | cnt = min_t(u32, nbytes, sizeof(data)); |
2f721d17 SB |
319 | if (din) { |
320 | memcpy(din, &data, cnt); | |
321 | din += cnt; | |
322 | } | |
323 | nbytes -= cnt; | |
324 | } | |
325 | ||
326 | return 0; | |
fc7a93c8 | 327 | |
38254f45 GL |
328 | } |
329 | ||
d255bb0e HS |
330 | int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
331 | void *din, unsigned long flags) | |
38254f45 | 332 | { |
9675fed4 | 333 | int n_bytes = DIV_ROUND_UP(bitlen, 8); |
2f721d17 SB |
334 | int n_bits; |
335 | int ret; | |
336 | u32 blk_size; | |
337 | u8 *p_outbuf = (u8 *)dout; | |
338 | u8 *p_inbuf = (u8 *)din; | |
38254f45 | 339 | |
2f721d17 SB |
340 | if (!slave) |
341 | return -1; | |
38254f45 | 342 | |
2f721d17 SB |
343 | if (flags & SPI_XFER_BEGIN) |
344 | spi_cs_activate(slave); | |
345 | ||
346 | while (n_bytes > 0) { | |
2f721d17 SB |
347 | if (n_bytes < MAX_SPI_BYTES) |
348 | blk_size = n_bytes; | |
349 | else | |
350 | blk_size = MAX_SPI_BYTES; | |
351 | ||
352 | n_bits = blk_size * 8; | |
353 | ||
354 | ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); | |
355 | ||
356 | if (ret) | |
357 | return ret; | |
358 | if (dout) | |
359 | p_outbuf += blk_size; | |
360 | if (din) | |
361 | p_inbuf += blk_size; | |
362 | n_bytes -= blk_size; | |
eff536be ML |
363 | } |
364 | ||
2f721d17 SB |
365 | if (flags & SPI_XFER_END) { |
366 | spi_cs_deactivate(slave); | |
f9b6a157 | 367 | } |
38254f45 GL |
368 | |
369 | return 0; | |
370 | } | |
371 | ||
372 | void spi_init(void) | |
373 | { | |
374 | } | |
375 | ||
155fa9af NK |
376 | /* |
377 | * Some SPI devices require active chip-select over multiple | |
378 | * transactions, we achieve this using a GPIO. Still, the SPI | |
379 | * controller has to be configured to use one of its own chipselects. | |
380 | * To use this feature you have to implement board_spi_cs_gpio() to assign | |
381 | * a gpio value for each cs (-1 if cs doesn't need to use gpio). | |
382 | * You must use some unused on this SPI controller cs between 0 and 3. | |
383 | */ | |
384 | static int setup_cs_gpio(struct mxc_spi_slave *mxcs, | |
385 | unsigned int bus, unsigned int cs) | |
fc7a93c8 GL |
386 | { |
387 | int ret; | |
388 | ||
155fa9af NK |
389 | mxcs->gpio = board_spi_cs_gpio(bus, cs); |
390 | if (mxcs->gpio == -1) | |
391 | return 0; | |
392 | ||
393 | ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); | |
394 | if (ret) { | |
395 | printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); | |
396 | return -EINVAL; | |
fc7a93c8 GL |
397 | } |
398 | ||
155fa9af | 399 | return 0; |
fc7a93c8 GL |
400 | } |
401 | ||
d255bb0e HS |
402 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
403 | unsigned int max_hz, unsigned int mode) | |
38254f45 | 404 | { |
d255bb0e | 405 | struct mxc_spi_slave *mxcs; |
fc7a93c8 GL |
406 | int ret; |
407 | ||
408 | if (bus >= ARRAY_SIZE(spi_bases)) | |
409 | return NULL; | |
410 | ||
027a9a00 MN |
411 | if (max_hz == 0) { |
412 | printf("Error: desired clock is 0\n"); | |
413 | return NULL; | |
414 | } | |
415 | ||
d3504fee | 416 | mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); |
2f721d17 SB |
417 | if (!mxcs) { |
418 | puts("mxc_spi: SPI Slave not allocated !\n"); | |
fc7a93c8 | 419 | return NULL; |
2f721d17 | 420 | } |
38254f45 | 421 | |
de5bf02c FE |
422 | mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; |
423 | ||
155fa9af | 424 | ret = setup_cs_gpio(mxcs, bus, cs); |
fc7a93c8 GL |
425 | if (ret < 0) { |
426 | free(mxcs); | |
d255bb0e | 427 | return NULL; |
fc7a93c8 GL |
428 | } |
429 | ||
d205ddcf | 430 | mxcs->base = spi_bases[bus]; |
027a9a00 MN |
431 | mxcs->max_hz = max_hz; |
432 | mxcs->mode = mode; | |
d205ddcf | 433 | |
d255bb0e HS |
434 | return &mxcs->slave; |
435 | } | |
436 | ||
437 | void spi_free_slave(struct spi_slave *slave) | |
438 | { | |
f9b6a157 GL |
439 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
440 | ||
441 | free(mxcs); | |
d255bb0e HS |
442 | } |
443 | ||
444 | int spi_claim_bus(struct spi_slave *slave) | |
445 | { | |
027a9a00 | 446 | int ret; |
d255bb0e | 447 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
ac87c17d | 448 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
d255bb0e | 449 | |
ac87c17d | 450 | reg_write(®s->rxdata, 1); |
38254f45 | 451 | udelay(1); |
027a9a00 MN |
452 | ret = spi_cfg_mxc(mxcs, slave->cs); |
453 | if (ret) { | |
454 | printf("mxc_spi: cannot setup SPI controller\n"); | |
455 | return ret; | |
456 | } | |
ac87c17d SB |
457 | reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); |
458 | reg_write(®s->intr, 0); | |
38254f45 GL |
459 | |
460 | return 0; | |
461 | } | |
d255bb0e HS |
462 | |
463 | void spi_release_bus(struct spi_slave *slave) | |
464 | { | |
465 | /* TODO: Shut the controller down */ | |
466 | } |