[people/ms/u-boot.git] / drivers / spi / mxc_spi.c

/*
 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/spi.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."
#endif

__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return -1;
}

#define OUT	MXC_GPIO_DIRECTION_OUT

#define reg_read readl
#define reg_write(a, v) writel(v, a)

#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
#define CONFIG_SYS_SPI_MXC_WAIT		(CONFIG_SYS_HZ/100)	/* 10 ms */
#endif

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
#if defined(MXC_ECSPI)
	u32		cfg_reg;
#endif
	int		gpio;
	int		ss_pol;
	unsigned int	max_hz;
	unsigned int	mode;
	struct gpio_desc ss;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
	if (CONFIG_IS_ENABLED(DM_SPI)) {
		dm_gpio_set_value(&mxcs->ss, mxcs->ss_pol);
	} else {
		if (mxcs->gpio > 0)
			gpio_set_value(mxcs->gpio, mxcs->ss_pol);
	}
}

static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
	if (CONFIG_IS_ENABLED(DM_SPI)) {
		dm_gpio_set_value(&mxcs->ss, !(mxcs->ss_pol));
	} else {
		if (mxcs->gpio > 0)
			gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
	}
}

u32 get_cspi_div(u32 div)
{
	int i;

	for (i = 0; i < 8; i++) {
		if (div <= (4 << i))
			return i;
	}
	return i;
}

#ifdef MXC_CSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	unsigned int ctrl_reg;
	u32 clk_src;
	u32 div;
	unsigned int max_hz = mxcs->max_hz;
	unsigned int mode = mxcs->mode;

	clk_src = mxc_get_clock(MXC_CSPI_CLK);

	div = DIV_ROUND_UP(clk_src, max_hz);
	div = get_cspi_div(div);

	debug("clk %d Hz, div %d, real clk %d Hz\n",
		max_hz, div, clk_src / (4 << div));

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
		MXC_CSPICTRL_DATARATE(div) |
		MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
		MXC_CSPICTRL_SSCTL |
#endif
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (mode & SPI_CPOL)
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;
	mxcs->ctrl_reg = ctrl_reg;

	return 0;
}
#endif

#ifdef MXC_ECSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	s32 reg_ctrl, reg_config;
	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
	u32 pre_div = 0, post_div = 0;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	unsigned int max_hz = mxcs->max_hz;
	unsigned int mode = mxcs->mode;

	/*
	 * Reset SPI and set all CSs to master mode, if toggling
	 * between slave and master mode we might see a glitch
	 * on the clock line
	 */
	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	reg_write(&regs->ctrl, reg_ctrl);
	reg_ctrl |=  MXC_CSPICTRL_EN;
	reg_write(&regs->ctrl, reg_ctrl);

	if (clk_src > max_hz) {
		pre_div = (clk_src - 1) / max_hz;
		/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
		post_div = fls(pre_div);
		if (post_div > 4) {
			post_div -= 4;
			if (post_div >= 16) {
				printf("Error: no divider for the freq: %d\n",
					max_hz);
				return -1;
			}
			pre_div >>= post_div;
		} else {
			post_div = 0;
		}
	}

	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
		MXC_CSPICTRL_SELCHAN(cs);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
		MXC_CSPICTRL_PREDIV(pre_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
		MXC_CSPICTRL_POSTDIV(post_div);

	if (mode & SPI_CS_HIGH)
		ss_pol = 1;

	if (mode & SPI_CPOL) {
		sclkpol = 1;
		sclkctl = 1;
	}

	if (mode & SPI_CPHA)
		sclkpha = 1;

	reg_config = reg_read(&regs->cfg);

	/*
	 * Configuration register setup
	 * The MX51 supports different setup for each SS
	 */
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
		(ss_pol << (cs + MXC_CSPICON_SSPOL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
		(sclkpol << (cs + MXC_CSPICON_POL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
		(sclkctl << (cs + MXC_CSPICON_CTL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
		(sclkpha << (cs + MXC_CSPICON_PHA));

	debug("reg_ctrl = 0x%x\n", reg_ctrl);
	reg_write(&regs->ctrl, reg_ctrl);
	debug("reg_config = 0x%x\n", reg_config);
	reg_write(&regs->cfg, reg_config);

	/* save config register and control register */
	mxcs->ctrl_reg = reg_ctrl;
	mxcs->cfg_reg = reg_config;

	/* clear interrupt reg */
	reg_write(&regs->intr, 0);
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	return 0;
}
#endif

int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
	const u8 *dout, u8 *din, unsigned long flags)
{
	int nbytes = DIV_ROUND_UP(bitlen, 8);
	u32 data, cnt, i;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	u32 ts;
	int status;

	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
		__func__, bitlen, (u32)dout, (u32)din);

	mxcs->ctrl_reg = (mxcs->ctrl_reg &
		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
		MXC_CSPICTRL_BITCOUNT(bitlen - 1);

	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
#ifdef MXC_ECSPI
	reg_write(&regs->cfg, mxcs->cfg_reg);
#endif

	/* Clear interrupt register */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	/*
	 * The SPI controller works only with words,
	 * check if less than a word is sent.
	 * Access to the FIFO is only 32 bit
	 */
	if (bitlen % 32) {
		data = 0;
		cnt = (bitlen % 32) / 8;
		if (dout) {
			for (i = 0; i < cnt; i++) {
				data = (data << 8) | (*dout++ & 0xFF);
			}
		}
		debug("Sending SPI 0x%x\n", data);

		reg_write(&regs->txdata, data);
		nbytes -= cnt;
	}

	data = 0;

	while (nbytes > 0) {
		data = 0;
		if (dout) {
			/* Buffer is not 32-bit aligned */
			if ((unsigned long)dout & 0x03) {
				data = 0;
				for (i = 0; i < 4; i++)
					data = (data << 8) | (*dout++ & 0xFF);
			} else {
				data = *(u32 *)dout;
				data = cpu_to_be32(data);
				dout += 4;
			}
		}
		debug("Sending SPI 0x%x\n", data);
		reg_write(&regs->txdata, data);
		nbytes -= 4;
	}

	/* FIFO is written, now starts the transfer setting the XCH bit */
	reg_write(&regs->ctrl, mxcs->ctrl_reg |
		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);

	ts = get_timer(0);
	status = reg_read(&regs->stat);
	/* Wait until the TC (Transfer completed) bit is set */
	while ((status & MXC_CSPICTRL_TC) == 0) {
		if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
			printf("spi_xchg_single: Timeout!\n");
			return -1;
		}
		status = reg_read(&regs->stat);
	}

	/* Transfer completed, clear any pending request */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	nbytes = DIV_ROUND_UP(bitlen, 8);

	cnt = nbytes % 32;

	if (bitlen % 32) {
		data = reg_read(&regs->rxdata);
		cnt = (bitlen % 32) / 8;
		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
		debug("SPI Rx unaligned: 0x%x\n", data);
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	while (nbytes > 0) {
		u32 tmp;
		tmp = reg_read(&regs->rxdata);
		data = cpu_to_be32(tmp);
		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
		cnt = min_t(u32, nbytes, sizeof(data));
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	return 0;

}

static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
				 unsigned int bitlen, const void *dout,
				 void *din, unsigned long flags)
{
	int n_bytes = DIV_ROUND_UP(bitlen, 8);
	int n_bits;
	int ret;
	u32 blk_size;
	u8 *p_outbuf = (u8 *)dout;
	u8 *p_inbuf = (u8 *)din;

	if (!mxcs)
		return -EINVAL;

	if (flags & SPI_XFER_BEGIN)
		mxc_spi_cs_activate(mxcs);

	while (n_bytes > 0) {
		if (n_bytes < MAX_SPI_BYTES)
			blk_size = n_bytes;
		else
			blk_size = MAX_SPI_BYTES;

		n_bits = blk_size * 8;

		ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);

		if (ret)
			return ret;
		if (dout)
			p_outbuf += blk_size;
		if (din)
			p_inbuf += blk_size;
		n_bytes -= blk_size;
	}

	if (flags & SPI_XFER_END) {
		mxc_spi_cs_deactivate(mxcs);
	}

	return 0;
}

static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
{
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
	int ret;

	reg_write(&regs->rxdata, 1);
	udelay(1);
	ret = spi_cfg_mxc(mxcs, cs);
	if (ret) {
		printf("mxc_spi: cannot setup SPI controller\n");
		return ret;
	}
	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	reg_write(&regs->intr, 0);

	return 0;
}

#ifndef CONFIG_DM_SPI
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}

void spi_init(void)
{
}

/*
 * Some SPI devices require active chip-select over multiple
 * transactions, we achieve this using a GPIO. Still, the SPI
 * controller has to be configured to use one of its own chipselects.
 * To use this feature you have to implement board_spi_cs_gpio() to assign
 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
 * You must use some unused on this SPI controller cs between 0 and 3.
 */
static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
			 unsigned int bus, unsigned int cs)
{
	int ret;

	mxcs->gpio = board_spi_cs_gpio(bus, cs);
	if (mxcs->gpio == -1)
		return 0;

	gpio_request(mxcs->gpio, "spi-cs");
	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
	if (ret) {
		printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
		return -EINVAL;
	}

	return 0;
}

static unsigned long spi_bases[] = {
	MXC_SPI_BASE_ADDRESSES
};

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	struct mxc_spi_slave *mxcs;
	int ret;

	if (bus >= ARRAY_SIZE(spi_bases))
		return NULL;

	if (max_hz == 0) {
		printf("Error: desired clock is 0\n");
		return NULL;
	}

	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
	if (!mxcs) {
		puts("mxc_spi: SPI Slave not allocated !\n");
		return NULL;
	}

	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	ret = setup_cs_gpio(mxcs, bus, cs);
	if (ret < 0) {
		free(mxcs);
		return NULL;
	}

	mxcs->base = spi_bases[bus];
	mxcs->max_hz = max_hz;
	mxcs->mode = mode;

	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	free(mxcs);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
#else

static int mxc_spi_probe(struct udevice *bus)
{
	struct mxc_spi_slave *plat = bus->platdata;
	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
	int node = dev_of_offset(bus);
	const void *blob = gd->fdt_blob;
	int ret;

	if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
				 GPIOD_IS_OUT)) {
		dev_err(bus, "No cs-gpios property\n");
		return -EINVAL;
	}

	plat->base = dev_get_addr(bus);
	if (plat->base == FDT_ADDR_T_NONE)
		return -ENODEV;

	ret = dm_gpio_set_value(&plat->ss, !(mxcs->ss_pol));
	if (ret) {
		dev_err(bus, "Setting cs error\n");
		return ret;
	}

	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
				      20000000);

	return 0;
}

static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);


	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}

static int mxc_spi_claim_bus(struct udevice *dev)
{
	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);

	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
}

static int mxc_spi_release_bus(struct udevice *dev)
{
	return 0;
}

static int mxc_spi_set_speed(struct udevice *bus, uint speed)
{
	/* Nothing to do */
	return 0;
}

static int mxc_spi_set_mode(struct udevice *bus, uint mode)
{
	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);

	mxcs->mode = mode;
	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	return 0;
}

static const struct dm_spi_ops mxc_spi_ops = {
	.claim_bus	= mxc_spi_claim_bus,
	.release_bus	= mxc_spi_release_bus,
	.xfer		= mxc_spi_xfer,
	.set_speed	= mxc_spi_set_speed,
	.set_mode	= mxc_spi_set_mode,
};

static const struct udevice_id mxc_spi_ids[] = {
	{ .compatible = "fsl,imx51-ecspi" },
	{ }
};

U_BOOT_DRIVER(mxc_spi) = {
	.name	= "mxc_spi",
	.id	= UCLASS_SPI,
	.of_match = mxc_spi_ids,
	.ops	= &mxc_spi_ops,
	.platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
	.probe	= mxc_spi_probe,
};
#endif
Commit	Line	Data
38254f45 GL	1	/*
	2	* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
38254f45 GL	5	*/
	6
	7	#include <common.h>
994266bd	8	#include <dm.h>
d255bb0e	9	#include <malloc.h>
38254f45	10	#include <spi.h>
1221ce45	11	#include <linux/errno.h>
38254f45	12	#include <asm/io.h>
d8e0ca85	13	#include <asm/gpio.h>
86271115 SB	14	#include <asm/arch/imx-regs.h>
86271115 SB	15	#include <asm/arch/clock.h>
552a848e	16	#include <asm/mach-imx/spi.h>
38254f45	17
994266bd PF	18	DECLARE_GLOBAL_DATA_PTR;
994266bd PF	19
38254f45 GL	20	#ifdef CONFIG_MX27
	21	/* i.MX27 has a completely wrong register layout and register definitions in the
	22	* datasheet, the correct one is in the Freescale's Linux driver */
	23
61a58a16	24	#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
38254f45	25	"See linux mxc_spi driver from Freescale for details."
08c61a58	26	#endif
c9d59c7f	27
155fa9af NK	28	__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
	29	{
	30	return -1;
	31	}
	32
c4ea1424 SB	33	#define OUT MXC_GPIO_DIRECTION_OUT
c4ea1424 SB	34
ac87c17d SB	35	#define reg_read readl
	36	#define reg_write(a, v) writel(v, a)
	37
f659b573 HS	38	#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
	39	#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
	40	#endif
	41
d255bb0e HS	42	struct mxc_spi_slave {
	43	struct spi_slave slave;
	44	unsigned long base;
	45	u32 ctrl_reg;
08c61a58	46	#if defined(MXC_ECSPI)
d205ddcf SB	47	u32 cfg_reg;
d205ddcf SB	48	#endif
fc7a93c8	49	int gpio;
c4ea1424	50	int ss_pol;
027a9a00 MN	51	unsigned int max_hz;
027a9a00 MN	52	unsigned int mode;
994266bd	53	struct gpio_desc ss;
38254f45	54	};
d255bb0e HS	55
	56	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	57	{
	58	return container_of(slave, struct mxc_spi_slave, slave);
	59	}
38254f45	60
994266bd	61	static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
d205ddcf	62	{
994266bd PF	63	if (CONFIG_IS_ENABLED(DM_SPI)) {
	64	dm_gpio_set_value(&mxcs->ss, mxcs->ss_pol);
	65	} else {
	66	if (mxcs->gpio > 0)
	67	gpio_set_value(mxcs->gpio, mxcs->ss_pol);
	68	}
d205ddcf SB	69	}
d205ddcf SB	70
994266bd	71	static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
d205ddcf	72	{
994266bd PF	73	if (CONFIG_IS_ENABLED(DM_SPI)) {
	74	dm_gpio_set_value(&mxcs->ss, !(mxcs->ss_pol));
	75	} else {
	76	if (mxcs->gpio > 0)
	77	gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
	78	}
d205ddcf SB	79	}
d205ddcf SB	80
afaa9f65 AG	81	u32 get_cspi_div(u32 div)
	82	{
	83	int i;
	84
	85	for (i = 0; i < 8; i++) {
	86	if (div <= (4 << i))
	87	return i;
	88	}
	89	return i;
	90	}
	91
08c61a58	92	#ifdef MXC_CSPI
027a9a00	93	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
c9d59c7f SB	94	{
c9d59c7f SB	95	unsigned int ctrl_reg;
afaa9f65 AG	96	u32 clk_src;
afaa9f65 AG	97	u32 div;
027a9a00 MN	98	unsigned int max_hz = mxcs->max_hz;
027a9a00 MN	99	unsigned int mode = mxcs->mode;
afaa9f65 AG	100
	101	clk_src = mxc_get_clock(MXC_CSPI_CLK);
	102
cd200403	103	div = DIV_ROUND_UP(clk_src, max_hz);
afaa9f65 AG	104	div = get_cspi_div(div);
	105
	106	debug("clk %d Hz, div %d, real clk %d Hz\n",
	107	max_hz, div, clk_src / (4 << div));
c9d59c7f SB	108
	109	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
	110	MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) \|
afaa9f65	111	MXC_CSPICTRL_DATARATE(div) \|
c9d59c7f SB	112	MXC_CSPICTRL_EN \|
	113	#ifdef CONFIG_MX35
	114	MXC_CSPICTRL_SSCTL \|
	115	#endif
	116	MXC_CSPICTRL_MODE;
	117
	118	if (mode & SPI_CPHA)
	119	ctrl_reg \|= MXC_CSPICTRL_PHA;
	120	if (mode & SPI_CPOL)
	121	ctrl_reg \|= MXC_CSPICTRL_POL;
	122	if (mode & SPI_CS_HIGH)
	123	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	124	mxcs->ctrl_reg = ctrl_reg;
	125
	126	return 0;
	127	}
	128	#endif
	129
08c61a58	130	#ifdef MXC_ECSPI
027a9a00	131	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
d205ddcf SB	132	{
d205ddcf SB	133	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
9a30903b	134	s32 reg_ctrl, reg_config;
5d584cce MN	135	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
5d584cce MN	136	u32 pre_div = 0, post_div = 0;
ac87c17d	137	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
027a9a00 MN	138	unsigned int max_hz = mxcs->max_hz;
027a9a00 MN	139	unsigned int mode = mxcs->mode;
d205ddcf	140
0f1411bc FE	141	/*
	142	* Reset SPI and set all CSs to master mode, if toggling
	143	* between slave and master mode we might see a glitch
	144	* on the clock line
	145	*/
	146	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	147	reg_write(&regs->ctrl, reg_ctrl);
	148	reg_ctrl \|= MXC_CSPICTRL_EN;
	149	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	150
d205ddcf	151	if (clk_src > max_hz) {
9a30903b DB	152	pre_div = (clk_src - 1) / max_hz;
	153	/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
	154	post_div = fls(pre_div);
	155	if (post_div > 4) {
	156	post_div -= 4;
	157	if (post_div >= 16) {
d205ddcf SB	158	printf("Error: no divider for the freq: %d\n",
	159	max_hz);
	160	return -1;
	161	}
9a30903b DB	162	pre_div >>= post_div;
	163	} else {
	164	post_div = 0;
d205ddcf SB	165	}
	166	}
	167
	168	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	169	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) \|
	170	MXC_CSPICTRL_SELCHAN(cs);
	171	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) \|
	172	MXC_CSPICTRL_PREDIV(pre_div);
	173	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) \|
	174	MXC_CSPICTRL_POSTDIV(post_div);
	175
d205ddcf SB	176	if (mode & SPI_CS_HIGH)
	177	ss_pol = 1;
	178
5d584cce	179	if (mode & SPI_CPOL) {
d205ddcf	180	sclkpol = 1;
5d584cce MN	181	sclkctl = 1;
5d584cce MN	182	}
d205ddcf SB	183
	184	if (mode & SPI_CPHA)
	185	sclkpha = 1;
	186
ac87c17d	187	reg_config = reg_read(&regs->cfg);
d205ddcf SB	188
	189	/*
	190	* Configuration register setup
c9d59c7f	191	* The MX51 supports different setup for each SS
d205ddcf SB	192	*/
	193	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) \|
	194	(ss_pol << (cs + MXC_CSPICON_SSPOL));
	195	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) \|
	196	(sclkpol << (cs + MXC_CSPICON_POL));
5d584cce MN	197	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) \|
5d584cce MN	198	(sclkctl << (cs + MXC_CSPICON_CTL));
d205ddcf SB	199	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) \|
	200	(sclkpha << (cs + MXC_CSPICON_PHA));
	201
	202	debug("reg_ctrl = 0x%x\n", reg_ctrl);
ac87c17d	203	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	204	debug("reg_config = 0x%x\n", reg_config);
ac87c17d	205	reg_write(&regs->cfg, reg_config);
d205ddcf SB	206
	207	/* save config register and control register */
	208	mxcs->ctrl_reg = reg_ctrl;
	209	mxcs->cfg_reg = reg_config;
	210
	211	/* clear interrupt reg */
ac87c17d SB	212	reg_write(&regs->intr, 0);
ac87c17d SB	213	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf SB	214
	215	return 0;
	216	}
	217	#endif
	218
994266bd	219	int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
2f721d17	220	const u8 dout, u8 din, unsigned long flags)
38254f45	221	{
9675fed4	222	int nbytes = DIV_ROUND_UP(bitlen, 8);
2f721d17	223	u32 data, cnt, i;
ac87c17d	224	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
f659b573 HS	225	u32 ts;
f659b573 HS	226	int status;
38254f45	227
2f721d17 SB	228	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
2f721d17 SB	229	__func__, bitlen, (u32)dout, (u32)din);
d205ddcf SB	230
	231	mxcs->ctrl_reg = (mxcs->ctrl_reg &
	232	~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) \|
f9b6a157	233	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
38254f45	234
ac87c17d	235	reg_write(&regs->ctrl, mxcs->ctrl_reg \| MXC_CSPICTRL_EN);
08c61a58	236	#ifdef MXC_ECSPI
ac87c17d	237	reg_write(&regs->cfg, mxcs->cfg_reg);
d205ddcf	238	#endif
38254f45	239
d205ddcf	240	/* Clear interrupt register */
ac87c17d	241	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
fc7a93c8	242
2f721d17 SB	243	/*
	244	* The SPI controller works only with words,
	245	* check if less than a word is sent.
	246	* Access to the FIFO is only 32 bit
	247	*/
	248	if (bitlen % 32) {
	249	data = 0;
	250	cnt = (bitlen % 32) / 8;
	251	if (dout) {
	252	for (i = 0; i < cnt; i++) {
	253	data = (data << 8) \| (*dout++ & 0xFF);
	254	}
	255	}
	256	debug("Sending SPI 0x%x\n", data);
	257
ac87c17d	258	reg_write(&regs->txdata, data);
2f721d17 SB	259	nbytes -= cnt;
	260	}
	261
	262	data = 0;
	263
	264	while (nbytes > 0) {
	265	data = 0;
	266	if (dout) {
	267	/* Buffer is not 32-bit aligned */
	268	if ((unsigned long)dout & 0x03) {
	269	data = 0;
dff01094	270	for (i = 0; i < 4; i++)
2f721d17	271	data = (data << 8) \| (*dout++ & 0xFF);
2f721d17 SB	272	} else {
	273	data = (u32 )dout;
	274	data = cpu_to_be32(data);
6d5ce1bd	275	dout += 4;
2f721d17	276	}
2f721d17 SB	277	}
2f721d17 SB	278	debug("Sending SPI 0x%x\n", data);
ac87c17d	279	reg_write(&regs->txdata, data);
2f721d17 SB	280	nbytes -= 4;
2f721d17 SB	281	}
38254f45	282
d205ddcf	283	/* FIFO is written, now starts the transfer setting the XCH bit */
ac87c17d	284	reg_write(&regs->ctrl, mxcs->ctrl_reg \|
d205ddcf	285	MXC_CSPICTRL_EN \| MXC_CSPICTRL_XCH);
38254f45	286
f659b573 HS	287	ts = get_timer(0);
f659b573 HS	288	status = reg_read(&regs->stat);
d205ddcf	289	/* Wait until the TC (Transfer completed) bit is set */
f659b573 HS	290	while ((status & MXC_CSPICTRL_TC) == 0) {
	291	if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
	292	printf("spi_xchg_single: Timeout!\n");
	293	return -1;
	294	}
	295	status = reg_read(&regs->stat);
	296	}
38254f45	297
d205ddcf	298	/* Transfer completed, clear any pending request */
ac87c17d	299	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf	300
9675fed4	301	nbytes = DIV_ROUND_UP(bitlen, 8);
d205ddcf	302
2f721d17	303	cnt = nbytes % 32;
d205ddcf	304
2f721d17	305	if (bitlen % 32) {
ac87c17d	306	data = reg_read(&regs->rxdata);
2f721d17	307	cnt = (bitlen % 32) / 8;
dff01094	308	data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
2f721d17 SB	309	debug("SPI Rx unaligned: 0x%x\n", data);
2f721d17 SB	310	if (din) {
dff01094 AG	311	memcpy(din, &data, cnt);
dff01094 AG	312	din += cnt;
2f721d17 SB	313	}
	314	nbytes -= cnt;
	315	}
	316
	317	while (nbytes > 0) {
	318	u32 tmp;
ac87c17d	319	tmp = reg_read(&regs->rxdata);
2f721d17 SB	320	data = cpu_to_be32(tmp);
2f721d17 SB	321	debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
b4141195	322	cnt = min_t(u32, nbytes, sizeof(data));
2f721d17 SB	323	if (din) {
	324	memcpy(din, &data, cnt);
	325	din += cnt;
	326	}
	327	nbytes -= cnt;
	328	}
	329
	330	return 0;
fc7a93c8	331
38254f45 GL	332	}
38254f45 GL	333
994266bd PF	334	static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
	335	unsigned int bitlen, const void *dout,
	336	void *din, unsigned long flags)
38254f45	337	{
9675fed4	338	int n_bytes = DIV_ROUND_UP(bitlen, 8);
2f721d17 SB	339	int n_bits;
	340	int ret;
	341	u32 blk_size;
	342	u8 p_outbuf = (u8 )dout;
	343	u8 p_inbuf = (u8 )din;
38254f45	344
994266bd PF	345	if (!mxcs)
994266bd PF	346	return -EINVAL;
38254f45	347
2f721d17	348	if (flags & SPI_XFER_BEGIN)
994266bd	349	mxc_spi_cs_activate(mxcs);
2f721d17 SB	350
2f721d17 SB	351	while (n_bytes > 0) {
2f721d17 SB	352	if (n_bytes < MAX_SPI_BYTES)
	353	blk_size = n_bytes;
	354	else
	355	blk_size = MAX_SPI_BYTES;
	356
	357	n_bits = blk_size * 8;
	358
994266bd	359	ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
2f721d17 SB	360
	361	if (ret)
	362	return ret;
	363	if (dout)
	364	p_outbuf += blk_size;
	365	if (din)
	366	p_inbuf += blk_size;
	367	n_bytes -= blk_size;
eff536be ML	368	}
eff536be ML	369
2f721d17	370	if (flags & SPI_XFER_END) {
994266bd	371	mxc_spi_cs_deactivate(mxcs);
f9b6a157	372	}
38254f45 GL	373
	374	return 0;
	375	}
	376
994266bd PF	377	static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
	378	{
	379	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
	380	int ret;
	381
	382	reg_write(&regs->rxdata, 1);
	383	udelay(1);
	384	ret = spi_cfg_mxc(mxcs, cs);
	385	if (ret) {
	386	printf("mxc_spi: cannot setup SPI controller\n");
	387	return ret;
	388	}
	389	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	390	reg_write(&regs->intr, 0);
	391
	392	return 0;
	393	}
	394
	395	#ifndef CONFIG_DM_SPI
	396	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
	397	void *din, unsigned long flags)
	398	{
	399	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	400
	401	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
	402	}
	403
38254f45 GL	404	void spi_init(void)
	405	{
	406	}
	407
155fa9af NK	408	/*
	409	* Some SPI devices require active chip-select over multiple
	410	* transactions, we achieve this using a GPIO. Still, the SPI
	411	* controller has to be configured to use one of its own chipselects.
	412	* To use this feature you have to implement board_spi_cs_gpio() to assign
	413	* a gpio value for each cs (-1 if cs doesn't need to use gpio).
	414	* You must use some unused on this SPI controller cs between 0 and 3.
	415	*/
	416	static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
	417	unsigned int bus, unsigned int cs)
fc7a93c8 GL	418	{
	419	int ret;
	420
155fa9af NK	421	mxcs->gpio = board_spi_cs_gpio(bus, cs);
	422	if (mxcs->gpio == -1)
	423	return 0;
	424
994266bd	425	gpio_request(mxcs->gpio, "spi-cs");
155fa9af NK	426	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
	427	if (ret) {
	428	printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
	429	return -EINVAL;
fc7a93c8 GL	430	}
fc7a93c8 GL	431
155fa9af	432	return 0;
fc7a93c8 GL	433	}
fc7a93c8 GL	434
994266bd PF	435	static unsigned long spi_bases[] = {
	436	MXC_SPI_BASE_ADDRESSES
	437	};
	438
d255bb0e HS	439	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	440	unsigned int max_hz, unsigned int mode)
38254f45	441	{
d255bb0e	442	struct mxc_spi_slave *mxcs;
fc7a93c8 GL	443	int ret;
	444
	445	if (bus >= ARRAY_SIZE(spi_bases))
	446	return NULL;
	447
027a9a00 MN	448	if (max_hz == 0) {
	449	printf("Error: desired clock is 0\n");
	450	return NULL;
	451	}
	452
d3504fee	453	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
2f721d17 SB	454	if (!mxcs) {
2f721d17 SB	455	puts("mxc_spi: SPI Slave not allocated !\n");
fc7a93c8	456	return NULL;
2f721d17	457	}
38254f45	458
de5bf02c FE	459	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
de5bf02c FE	460
155fa9af	461	ret = setup_cs_gpio(mxcs, bus, cs);
fc7a93c8 GL	462	if (ret < 0) {
fc7a93c8 GL	463	free(mxcs);
d255bb0e	464	return NULL;
fc7a93c8 GL	465	}
fc7a93c8 GL	466
d205ddcf	467	mxcs->base = spi_bases[bus];
027a9a00 MN	468	mxcs->max_hz = max_hz;
027a9a00 MN	469	mxcs->mode = mode;
d205ddcf	470
d255bb0e HS	471	return &mxcs->slave;
	472	}
	473
	474	void spi_free_slave(struct spi_slave *slave)
	475	{
f9b6a157 GL	476	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	477
	478	free(mxcs);
d255bb0e HS	479	}
	480
	481	int spi_claim_bus(struct spi_slave *slave)
	482	{
	483	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	484
994266bd PF	485	return mxc_spi_claim_bus_internal(mxcs, slave->cs);
	486	}
	487
	488	void spi_release_bus(struct spi_slave *slave)
	489	{
	490	/* TODO: Shut the controller down */
	491	}
	492	#else
	493
	494	static int mxc_spi_probe(struct udevice *bus)
	495	{
	496	struct mxc_spi_slave *plat = bus->platdata;
	497	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
	498	int node = dev_of_offset(bus);
	499	const void *blob = gd->fdt_blob;
	500	int ret;
	501
	502	if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
	503	GPIOD_IS_OUT)) {
	504	dev_err(bus, "No cs-gpios property\n");
	505	return -EINVAL;
	506	}
	507
	508	plat->base = dev_get_addr(bus);
	509	if (plat->base == FDT_ADDR_T_NONE)
	510	return -ENODEV;
	511
	512	ret = dm_gpio_set_value(&plat->ss, !(mxcs->ss_pol));
027a9a00	513	if (ret) {
994266bd	514	dev_err(bus, "Setting cs error\n");
027a9a00 MN	515	return ret;
027a9a00 MN	516	}
994266bd PF	517
	518	mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
	519	20000000);
38254f45 GL	520
	521	return 0;
	522	}
d255bb0e	523
994266bd PF	524	static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
994266bd PF	525	const void dout, void din, unsigned long flags)
d255bb0e	526	{
994266bd PF	527	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
	528
	529
	530	return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
	531	}
	532
	533	static int mxc_spi_claim_bus(struct udevice *dev)
	534	{
	535	struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
	536	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	537
	538	return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
d255bb0e	539	}
994266bd PF	540
	541	static int mxc_spi_release_bus(struct udevice *dev)
	542	{
	543	return 0;
	544	}
	545
	546	static int mxc_spi_set_speed(struct udevice *bus, uint speed)
	547	{
	548	/* Nothing to do */
	549	return 0;
	550	}
	551
	552	static int mxc_spi_set_mode(struct udevice *bus, uint mode)
	553	{
	554	struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
	555
	556	mxcs->mode = mode;
	557	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
	558
	559	return 0;
	560	}
	561
	562	static const struct dm_spi_ops mxc_spi_ops = {
	563	.claim_bus = mxc_spi_claim_bus,
	564	.release_bus = mxc_spi_release_bus,
	565	.xfer = mxc_spi_xfer,
	566	.set_speed = mxc_spi_set_speed,
	567	.set_mode = mxc_spi_set_mode,
	568	};
	569
	570	static const struct udevice_id mxc_spi_ids[] = {
	571	{ .compatible = "fsl,imx51-ecspi" },
	572	{ }
	573	};
	574
	575	U_BOOT_DRIVER(mxc_spi) = {
	576	.name = "mxc_spi",
	577	.id = UCLASS_SPI,
	578	.of_match = mxc_spi_ids,
	579	.ops = &mxc_spi_ops,
	580	.platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
	581	.probe = mxc_spi_probe,
	582	};
	583	#endif