]>
Commit | Line | Data |
---|---|---|
3e326ece | 1 | /* |
4dae14ce ZW |
2 | * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. |
3 | * | |
4 | * Interrupt support is added. Now, it has been tested | |
5 | * on ULI1575 chip and works well with USB keyboard. | |
6 | * | |
7 | * (C) Copyright 2007 | |
8 | * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> | |
3e326ece MK |
9 | * |
10 | * (C) Copyright 2003 | |
792a09eb | 11 | * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> |
3e326ece MK |
12 | * |
13 | * Note: Much of this code has been derived from Linux 2.4 | |
14 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
15 | * (C) Copyright 2000-2002 David Brownell | |
16 | * | |
17 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard | |
18 | * ebenard@eukrea.com - based on s3c24x0's driver | |
19 | * | |
20 | * See file CREDITS for list of people who contributed to this | |
21 | * project. | |
22 | * | |
23 | * This program is free software; you can redistribute it and/or | |
24 | * modify it under the terms of the GNU General Public License as | |
25 | * published by the Free Software Foundation; either version 2 of | |
26 | * the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
ae0b05df | 30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
3e326ece MK |
31 | * GNU General Public License for more details. |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
36 | * MA 02111-1307 USA | |
37 | * | |
38 | */ | |
39 | /* | |
40 | * IMPORTANT NOTES | |
fc43be47 | 41 | * 1 - Read doc/README.generic_usb_ohci |
3e326ece | 42 | * 2 - this driver is intended for use with USB Mass Storage Devices |
4dae14ce | 43 | * (BBB) and USB keyboard. There is NO support for Isochronous pipes! |
fc43be47 | 44 | * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG |
3e326ece MK |
45 | * to activate workaround for bug #41 or this driver will NOT work! |
46 | */ | |
47 | ||
48 | #include <common.h> | |
fc43be47 MK |
49 | #include <asm/byteorder.h> |
50 | ||
51 | #if defined(CONFIG_PCI_OHCI) | |
4dae14ce | 52 | # include <pci.h> |
477434c6 SP |
53 | #if !defined(CONFIG_PCI_OHCI_DEVNO) |
54 | #define CONFIG_PCI_OHCI_DEVNO 0 | |
55 | #endif | |
ddf83a2f | 56 | #endif |
3e326ece MK |
57 | |
58 | #include <malloc.h> | |
59 | #include <usb.h> | |
2731b9a8 JCPV |
60 | |
61 | #include "ohci.h" | |
3e326ece | 62 | |
e8da58f2 WD |
63 | #ifdef CONFIG_AT91RM9200 |
64 | #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ | |
65 | #endif | |
66 | ||
ddf83a2f MK |
67 | #if defined(CONFIG_ARM920T) || \ |
68 | defined(CONFIG_S3C2400) || \ | |
ae3b770e | 69 | defined(CONFIG_S3C2410) || \ |
8262813c | 70 | defined(CONFIG_S3C6400) || \ |
ae3b770e | 71 | defined(CONFIG_440EP) || \ |
4dae14ce | 72 | defined(CONFIG_PCI_OHCI) || \ |
2596f5b9 | 73 | defined(CONFIG_MPC5200) || \ |
6d0f6bcf | 74 | defined(CONFIG_SYS_OHCI_USE_NPS) |
24e37645 MK |
75 | # define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
76 | #endif | |
77 | ||
3e326ece | 78 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
ae3b770e MK |
79 | #undef DEBUG |
80 | #undef SHOW_INFO | |
81 | #undef OHCI_FILL_TRACE | |
3e326ece MK |
82 | |
83 | /* For initializing controller (mask in an HCFS mode too) */ | |
84 | #define OHCI_CONTROL_INIT \ | |
85 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
86 | ||
fc43be47 MK |
87 | /* |
88 | * e.g. PCI controllers need this | |
89 | */ | |
6d0f6bcf | 90 | #ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS |
f957576c MK |
91 | # define readl(a) __swap_32(*((volatile u32 *)(a))) |
92 | # define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a)) | |
fc43be47 | 93 | #else |
f957576c MK |
94 | # define readl(a) (*((volatile u32 *)(a))) |
95 | # define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) | |
6d0f6bcf | 96 | #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ |
3e326ece | 97 | |
6f5794a6 RB |
98 | #define min_t(type, x, y) \ |
99 | ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) | |
3e326ece | 100 | |
4dae14ce ZW |
101 | #ifdef CONFIG_PCI_OHCI |
102 | static struct pci_device_id ohci_pci_ids[] = { | |
103 | {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ | |
97213f32 | 104 | {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ |
3afac79e | 105 | {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ |
4dae14ce ZW |
106 | /* Please add supported PCI OHCI controller ids here */ |
107 | {0, 0} | |
108 | }; | |
109 | #endif | |
110 | ||
e90fb6af YT |
111 | #ifdef CONFIG_PCI_EHCI_DEVNO |
112 | static struct pci_device_id ehci_pci_ids[] = { | |
113 | {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ | |
114 | /* Please add supported PCI EHCI controller ids here */ | |
115 | {0, 0} | |
116 | }; | |
117 | #endif | |
118 | ||
3e326ece MK |
119 | #ifdef DEBUG |
120 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
121 | #else | |
6f5794a6 | 122 | #define dbg(format, arg...) do {} while (0) |
3e326ece MK |
123 | #endif /* DEBUG */ |
124 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) | |
3e326ece MK |
125 | #ifdef SHOW_INFO |
126 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
127 | #else | |
6f5794a6 | 128 | #define info(format, arg...) do {} while (0) |
3e326ece MK |
129 | #endif |
130 | ||
6d0f6bcf | 131 | #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER |
fc43be47 MK |
132 | # define m16_swap(x) cpu_to_be16(x) |
133 | # define m32_swap(x) cpu_to_be32(x) | |
ae3b770e | 134 | #else |
fc43be47 MK |
135 | # define m16_swap(x) cpu_to_le16(x) |
136 | # define m32_swap(x) cpu_to_le32(x) | |
6d0f6bcf | 137 | #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ |
3e326ece MK |
138 | |
139 | /* global ohci_t */ | |
140 | static ohci_t gohci; | |
141 | /* this must be aligned to a 256 byte boundary */ | |
142 | struct ohci_hcca ghcca[1]; | |
143 | /* a pointer to the aligned storage */ | |
144 | struct ohci_hcca *phcca; | |
145 | /* this allocates EDs for all possible endpoints */ | |
146 | struct ohci_device ohci_dev; | |
3e326ece MK |
147 | /* device which was disconnected */ |
148 | struct usb_device *devgone; | |
149 | ||
6f5794a6 RB |
150 | static inline u32 roothub_a(struct ohci *hc) |
151 | { return readl(&hc->regs->roothub.a); } | |
152 | static inline u32 roothub_b(struct ohci *hc) | |
153 | { return readl(&hc->regs->roothub.b); } | |
154 | static inline u32 roothub_status(struct ohci *hc) | |
155 | { return readl(&hc->regs->roothub.status); } | |
156 | static inline u32 roothub_portstatus(struct ohci *hc, int i) | |
157 | { return readl(&hc->regs->roothub.portstatus[i]); } | |
3e326ece | 158 | |
3e326ece | 159 | /* forward declaration */ |
6f5794a6 RB |
160 | static int hc_interrupt(void); |
161 | static void td_submit_job(struct usb_device *dev, unsigned long pipe, | |
162 | void *buffer, int transfer_len, | |
163 | struct devrequest *setup, urb_priv_t *urb, | |
164 | int interval); | |
3e326ece MK |
165 | |
166 | /*-------------------------------------------------------------------------* | |
167 | * URB support functions | |
168 | *-------------------------------------------------------------------------*/ | |
169 | ||
170 | /* free HCD-private data associated with this URB */ | |
171 | ||
6f5794a6 | 172 | static void urb_free_priv(urb_priv_t *urb) |
3e326ece MK |
173 | { |
174 | int i; | |
175 | int last; | |
6f5794a6 | 176 | struct td *td; |
3e326ece MK |
177 | |
178 | last = urb->length - 1; | |
179 | if (last >= 0) { | |
180 | for (i = 0; i <= last; i++) { | |
181 | td = urb->td[i]; | |
182 | if (td) { | |
183 | td->usb_dev = NULL; | |
184 | urb->td[i] = NULL; | |
185 | } | |
186 | } | |
187 | } | |
4dae14ce | 188 | free(urb); |
3e326ece MK |
189 | } |
190 | ||
191 | /*-------------------------------------------------------------------------*/ | |
192 | ||
193 | #ifdef DEBUG | |
6f5794a6 | 194 | static int sohci_get_current_frame_number(struct usb_device *dev); |
3e326ece MK |
195 | |
196 | /* debug| print the main components of an URB | |
197 | * small: 0) header + data packets 1) just header */ | |
198 | ||
6f5794a6 RB |
199 | static void pkt_print(urb_priv_t *purb, struct usb_device *dev, |
200 | unsigned long pipe, void *buffer, int transfer_len, | |
201 | struct devrequest *setup, char *str, int small) | |
3e326ece | 202 | { |
6f5794a6 | 203 | dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", |
3e326ece | 204 | str, |
6f5794a6 RB |
205 | sohci_get_current_frame_number(dev), |
206 | usb_pipedevice(pipe), | |
207 | usb_pipeendpoint(pipe), | |
208 | usb_pipeout(pipe)? 'O': 'I', | |
209 | usb_pipetype(pipe) < 2 ? \ | |
210 | (usb_pipeint(pipe)? "INTR": "ISOC"): \ | |
211 | (usb_pipecontrol(pipe)? "CTRL": "BULK"), | |
4dae14ce | 212 | (purb ? purb->actual_length : 0), |
3e326ece MK |
213 | transfer_len, dev->status); |
214 | #ifdef OHCI_VERBOSE_DEBUG | |
215 | if (!small) { | |
216 | int i, len; | |
217 | ||
6f5794a6 RB |
218 | if (usb_pipecontrol(pipe)) { |
219 | printf(__FILE__ ": cmd(8):"); | |
3e326ece | 220 | for (i = 0; i < 8 ; i++) |
6f5794a6 RB |
221 | printf(" %02x", ((__u8 *) setup) [i]); |
222 | printf("\n"); | |
3e326ece MK |
223 | } |
224 | if (transfer_len > 0 && buffer) { | |
6f5794a6 | 225 | printf(__FILE__ ": data(%d/%d):", |
4dae14ce | 226 | (purb ? purb->actual_length : 0), |
3e326ece | 227 | transfer_len); |
6f5794a6 | 228 | len = usb_pipeout(pipe)? transfer_len: |
4dae14ce | 229 | (purb ? purb->actual_length : 0); |
3e326ece | 230 | for (i = 0; i < 16 && i < len; i++) |
6f5794a6 RB |
231 | printf(" %02x", ((__u8 *) buffer) [i]); |
232 | printf("%s\n", i < len? "...": ""); | |
3e326ece MK |
233 | } |
234 | } | |
235 | #endif | |
236 | } | |
237 | ||
6f5794a6 RB |
238 | /* just for debugging; prints non-empty branches of the int ed tree |
239 | * inclusive iso eds */ | |
240 | void ep_print_int_eds(ohci_t *ohci, char *str) | |
241 | { | |
3e326ece | 242 | int i, j; |
6f5794a6 RB |
243 | __u32 *ed_p; |
244 | for (i = 0; i < 32; i++) { | |
3e326ece MK |
245 | j = 5; |
246 | ed_p = &(ohci->hcca->int_table [i]); | |
247 | if (*ed_p == 0) | |
248 | continue; | |
6f5794a6 | 249 | printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); |
3e326ece MK |
250 | while (*ed_p != 0 && j--) { |
251 | ed_t *ed = (ed_t *)m32_swap(ed_p); | |
6f5794a6 | 252 | printf(" ed: %4x;", ed->hwINFO); |
3e326ece MK |
253 | ed_p = &ed->hwNextED; |
254 | } | |
6f5794a6 | 255 | printf("\n"); |
3e326ece MK |
256 | } |
257 | } | |
258 | ||
6f5794a6 | 259 | static void ohci_dump_intr_mask(char *label, __u32 mask) |
3e326ece | 260 | { |
6f5794a6 | 261 | dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
3e326ece MK |
262 | label, |
263 | mask, | |
264 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
265 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
266 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
267 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
268 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
269 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
270 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
271 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
272 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
273 | ); | |
274 | } | |
275 | ||
6f5794a6 | 276 | static void maybe_print_eds(char *label, __u32 value) |
3e326ece MK |
277 | { |
278 | ed_t *edp = (ed_t *)value; | |
279 | ||
280 | if (value) { | |
6f5794a6 RB |
281 | dbg("%s %08x", label, value); |
282 | dbg("%08x", edp->hwINFO); | |
283 | dbg("%08x", edp->hwTailP); | |
284 | dbg("%08x", edp->hwHeadP); | |
285 | dbg("%08x", edp->hwNextED); | |
3e326ece MK |
286 | } |
287 | } | |
288 | ||
6f5794a6 | 289 | static char *hcfs2string(int state) |
3e326ece MK |
290 | { |
291 | switch (state) { | |
6f5794a6 RB |
292 | case OHCI_USB_RESET: return "reset"; |
293 | case OHCI_USB_RESUME: return "resume"; | |
294 | case OHCI_USB_OPER: return "operational"; | |
295 | case OHCI_USB_SUSPEND: return "suspend"; | |
3e326ece MK |
296 | } |
297 | return "?"; | |
298 | } | |
299 | ||
300 | /* dump control and status registers */ | |
6f5794a6 | 301 | static void ohci_dump_status(ohci_t *controller) |
3e326ece MK |
302 | { |
303 | struct ohci_regs *regs = controller->regs; | |
304 | __u32 temp; | |
305 | ||
6f5794a6 | 306 | temp = readl(®s->revision) & 0xff; |
3e326ece | 307 | if (temp != 0x10) |
6f5794a6 | 308 | dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
3e326ece | 309 | |
6f5794a6 RB |
310 | temp = readl(®s->control); |
311 | dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, | |
3e326ece MK |
312 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", |
313 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
314 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
6f5794a6 | 315 | hcfs2string(temp & OHCI_CTRL_HCFS), |
3e326ece MK |
316 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", |
317 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
318 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
319 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
320 | temp & OHCI_CTRL_CBSR | |
321 | ); | |
322 | ||
6f5794a6 RB |
323 | temp = readl(®s->cmdstatus); |
324 | dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, | |
3e326ece MK |
325 | (temp & OHCI_SOC) >> 16, |
326 | (temp & OHCI_OCR) ? " OCR" : "", | |
327 | (temp & OHCI_BLF) ? " BLF" : "", | |
328 | (temp & OHCI_CLF) ? " CLF" : "", | |
329 | (temp & OHCI_HCR) ? " HCR" : "" | |
330 | ); | |
331 | ||
6f5794a6 RB |
332 | ohci_dump_intr_mask("intrstatus", readl(®s->intrstatus)); |
333 | ohci_dump_intr_mask("intrenable", readl(®s->intrenable)); | |
3e326ece | 334 | |
6f5794a6 | 335 | maybe_print_eds("ed_periodcurrent", readl(®s->ed_periodcurrent)); |
3e326ece | 336 | |
6f5794a6 RB |
337 | maybe_print_eds("ed_controlhead", readl(®s->ed_controlhead)); |
338 | maybe_print_eds("ed_controlcurrent", readl(®s->ed_controlcurrent)); | |
3e326ece | 339 | |
6f5794a6 RB |
340 | maybe_print_eds("ed_bulkhead", readl(®s->ed_bulkhead)); |
341 | maybe_print_eds("ed_bulkcurrent", readl(®s->ed_bulkcurrent)); | |
3e326ece | 342 | |
6f5794a6 | 343 | maybe_print_eds("donehead", readl(®s->donehead)); |
3e326ece MK |
344 | } |
345 | ||
6f5794a6 | 346 | static void ohci_dump_roothub(ohci_t *controller, int verbose) |
3e326ece MK |
347 | { |
348 | __u32 temp, ndp, i; | |
349 | ||
6f5794a6 | 350 | temp = roothub_a(controller); |
3e326ece MK |
351 | ndp = (temp & RH_A_NDP); |
352 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
353 | ndp = (ndp == 2) ? 1:0; | |
3e326ece MK |
354 | #endif |
355 | if (verbose) { | |
6f5794a6 | 356 | dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
3e326ece MK |
357 | ((temp & RH_A_POTPGT) >> 24) & 0xff, |
358 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
359 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
360 | (temp & RH_A_DT) ? " DT" : "", | |
361 | (temp & RH_A_NPS) ? " NPS" : "", | |
362 | (temp & RH_A_PSM) ? " PSM" : "", | |
363 | ndp | |
364 | ); | |
6f5794a6 RB |
365 | temp = roothub_b(controller); |
366 | dbg("roothub.b: %08x PPCM=%04x DR=%04x", | |
3e326ece MK |
367 | temp, |
368 | (temp & RH_B_PPCM) >> 16, | |
369 | (temp & RH_B_DR) | |
370 | ); | |
6f5794a6 RB |
371 | temp = roothub_status(controller); |
372 | dbg("roothub.status: %08x%s%s%s%s%s%s", | |
3e326ece MK |
373 | temp, |
374 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
375 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
376 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
377 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
378 | (temp & RH_HS_OCI) ? " OCI" : "", | |
379 | (temp & RH_HS_LPS) ? " LPS" : "" | |
380 | ); | |
381 | } | |
382 | ||
383 | for (i = 0; i < ndp; i++) { | |
6f5794a6 RB |
384 | temp = roothub_portstatus(controller, i); |
385 | dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
3e326ece MK |
386 | i, |
387 | temp, | |
388 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
389 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
390 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
391 | (temp & RH_PS_PESC) ? " PESC" : "", | |
392 | (temp & RH_PS_CSC) ? " CSC" : "", | |
393 | ||
394 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
395 | (temp & RH_PS_PPS) ? " PPS" : "", | |
396 | (temp & RH_PS_PRS) ? " PRS" : "", | |
397 | (temp & RH_PS_POCI) ? " POCI" : "", | |
398 | (temp & RH_PS_PSS) ? " PSS" : "", | |
399 | ||
400 | (temp & RH_PS_PES) ? " PES" : "", | |
401 | (temp & RH_PS_CCS) ? " CCS" : "" | |
402 | ); | |
403 | } | |
404 | } | |
405 | ||
6f5794a6 | 406 | static void ohci_dump(ohci_t *controller, int verbose) |
3e326ece | 407 | { |
6f5794a6 | 408 | dbg("OHCI controller usb-%s state", controller->slot_name); |
3e326ece MK |
409 | |
410 | /* dumps some of the state we know about */ | |
6f5794a6 | 411 | ohci_dump_status(controller); |
3e326ece | 412 | if (verbose) |
6f5794a6 RB |
413 | ep_print_int_eds(controller, "hcca"); |
414 | dbg("hcca frame #%04x", controller->hcca->frame_no); | |
415 | ohci_dump_roothub(controller, 1); | |
2596f5b9 | 416 | } |
3e326ece MK |
417 | #endif /* DEBUG */ |
418 | ||
419 | /*-------------------------------------------------------------------------* | |
420 | * Interface functions (URB) | |
421 | *-------------------------------------------------------------------------*/ | |
422 | ||
423 | /* get a transfer request */ | |
424 | ||
4dae14ce | 425 | int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) |
3e326ece MK |
426 | { |
427 | ohci_t *ohci; | |
6f5794a6 | 428 | ed_t *ed; |
4dae14ce | 429 | urb_priv_t *purb_priv = urb; |
3e326ece | 430 | int i, size = 0; |
4dae14ce ZW |
431 | struct usb_device *dev = urb->dev; |
432 | unsigned long pipe = urb->pipe; | |
433 | void *buffer = urb->transfer_buffer; | |
434 | int transfer_len = urb->transfer_buffer_length; | |
435 | int interval = urb->interval; | |
3e326ece MK |
436 | |
437 | ohci = &gohci; | |
438 | ||
439 | /* when controller's hung, permit only roothub cleanup attempts | |
440 | * such as powering down ports */ | |
441 | if (ohci->disabled) { | |
442 | err("sohci_submit_job: EPIPE"); | |
443 | return -1; | |
444 | } | |
ae79f606 | 445 | |
6f5794a6 RB |
446 | /* we're about to begin a new transaction here so mark the |
447 | * URB unfinished */ | |
4dae14ce | 448 | urb->finished = 0; |
3e326ece MK |
449 | |
450 | /* every endpoint has a ed, locate and fill it */ | |
6f5794a6 RB |
451 | ed = ep_add_ed(dev, pipe, interval, 1); |
452 | if (!ed) { | |
3e326ece MK |
453 | err("sohci_submit_job: ENOMEM"); |
454 | return -1; | |
455 | } | |
456 | ||
457 | /* for the private part of the URB we need the number of TDs (size) */ | |
6f5794a6 RB |
458 | switch (usb_pipetype(pipe)) { |
459 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
460 | size = (transfer_len - 1) / 4096 + 1; | |
461 | break; | |
462 | case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
463 | size = (transfer_len == 0)? 2: | |
464 | (transfer_len - 1) / 4096 + 3; | |
465 | break; | |
466 | case PIPE_INTERRUPT: /* 1 TD */ | |
467 | size = 1; | |
468 | break; | |
3e326ece MK |
469 | } |
470 | ||
4dae14ce ZW |
471 | ed->purb = urb; |
472 | ||
3e326ece MK |
473 | if (size >= (N_URB_TD - 1)) { |
474 | err("need %d TDs, only have %d", size, N_URB_TD); | |
475 | return -1; | |
476 | } | |
3e326ece MK |
477 | purb_priv->pipe = pipe; |
478 | ||
479 | /* fill the private part of the URB */ | |
480 | purb_priv->length = size; | |
481 | purb_priv->ed = ed; | |
482 | purb_priv->actual_length = 0; | |
483 | ||
484 | /* allocate the TDs */ | |
485 | /* note that td[0] was allocated in ep_add_ed */ | |
486 | for (i = 0; i < size; i++) { | |
6f5794a6 | 487 | purb_priv->td[i] = td_alloc(dev); |
3e326ece MK |
488 | if (!purb_priv->td[i]) { |
489 | purb_priv->length = i; | |
6f5794a6 | 490 | urb_free_priv(purb_priv); |
3e326ece MK |
491 | err("sohci_submit_job: ENOMEM"); |
492 | return -1; | |
493 | } | |
494 | } | |
495 | ||
496 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
6f5794a6 | 497 | urb_free_priv(purb_priv); |
3e326ece MK |
498 | err("sohci_submit_job: EINVAL"); |
499 | return -1; | |
500 | } | |
501 | ||
502 | /* link the ed into a chain if is not already */ | |
503 | if (ed->state != ED_OPER) | |
6f5794a6 | 504 | ep_link(ohci, ed); |
3e326ece MK |
505 | |
506 | /* fill the TDs and link it to the ed */ | |
6f5794a6 RB |
507 | td_submit_job(dev, pipe, buffer, transfer_len, |
508 | setup, purb_priv, interval); | |
3e326ece MK |
509 | |
510 | return 0; | |
511 | } | |
512 | ||
4dae14ce ZW |
513 | static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) |
514 | { | |
515 | struct ohci_regs *regs = hc->regs; | |
516 | ||
6f5794a6 | 517 | switch (usb_pipetype(urb->pipe)) { |
4dae14ce ZW |
518 | case PIPE_INTERRUPT: |
519 | /* implicitly requeued */ | |
520 | if (urb->dev->irq_handle && | |
521 | (urb->dev->irq_act_len = urb->actual_length)) { | |
6f5794a6 RB |
522 | writel(OHCI_INTR_WDH, ®s->intrenable); |
523 | readl(®s->intrenable); /* PCI posting flush */ | |
4dae14ce | 524 | urb->dev->irq_handle(urb->dev); |
6f5794a6 RB |
525 | writel(OHCI_INTR_WDH, ®s->intrdisable); |
526 | readl(®s->intrdisable); /* PCI posting flush */ | |
4dae14ce ZW |
527 | } |
528 | urb->actual_length = 0; | |
6f5794a6 | 529 | td_submit_job( |
4dae14ce ZW |
530 | urb->dev, |
531 | urb->pipe, | |
532 | urb->transfer_buffer, | |
533 | urb->transfer_buffer_length, | |
534 | NULL, | |
535 | urb, | |
536 | urb->interval); | |
537 | break; | |
538 | case PIPE_CONTROL: | |
539 | case PIPE_BULK: | |
540 | break; | |
541 | default: | |
542 | return 0; | |
543 | } | |
544 | return 1; | |
545 | } | |
546 | ||
3e326ece MK |
547 | /*-------------------------------------------------------------------------*/ |
548 | ||
549 | #ifdef DEBUG | |
550 | /* tell us the current USB frame number */ | |
551 | ||
6f5794a6 | 552 | static int sohci_get_current_frame_number(struct usb_device *usb_dev) |
3e326ece MK |
553 | { |
554 | ohci_t *ohci = &gohci; | |
555 | ||
6f5794a6 | 556 | return m16_swap(ohci->hcca->frame_no); |
3e326ece MK |
557 | } |
558 | #endif | |
559 | ||
4dae14ce ZW |
560 | /*-------------------------------------------------------------------------* |
561 | * ED handling functions | |
562 | *-------------------------------------------------------------------------*/ | |
563 | ||
564 | /* search for the right branch to insert an interrupt ed into the int tree | |
565 | * do some load ballancing; | |
566 | * returns the branch and | |
567 | * sets the interval to interval = 2^integer (ld (interval)) */ | |
568 | ||
6f5794a6 | 569 | static int ep_int_ballance(ohci_t *ohci, int interval, int load) |
4dae14ce ZW |
570 | { |
571 | int i, branch = 0; | |
572 | ||
573 | /* search for the least loaded interrupt endpoint | |
574 | * branch of all 32 branches | |
575 | */ | |
576 | for (i = 0; i < 32; i++) | |
577 | if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) | |
578 | branch = i; | |
579 | ||
580 | branch = branch % interval; | |
581 | for (i = branch; i < 32; i += interval) | |
582 | ohci->ohci_int_load [i] += load; | |
583 | ||
584 | return branch; | |
585 | } | |
586 | ||
587 | /*-------------------------------------------------------------------------*/ | |
588 | ||
589 | /* 2^int( ld (inter)) */ | |
590 | ||
6f5794a6 | 591 | static int ep_2_n_interval(int inter) |
4dae14ce ZW |
592 | { |
593 | int i; | |
6f5794a6 | 594 | for (i = 0; ((inter >> i) > 1) && (i < 5); i++); |
4dae14ce ZW |
595 | return 1 << i; |
596 | } | |
597 | ||
598 | /*-------------------------------------------------------------------------*/ | |
599 | ||
600 | /* the int tree is a binary tree | |
6f5794a6 RB |
601 | * in order to process it sequentially the indexes of the branches have to |
602 | * be mapped the mapping reverses the bits of a word of num_bits length */ | |
603 | static int ep_rev(int num_bits, int word) | |
4dae14ce ZW |
604 | { |
605 | int i, wout = 0; | |
606 | ||
607 | for (i = 0; i < num_bits; i++) | |
608 | wout |= (((word >> i) & 1) << (num_bits - i - 1)); | |
609 | return wout; | |
610 | } | |
611 | ||
3e326ece MK |
612 | /*-------------------------------------------------------------------------* |
613 | * ED handling functions | |
614 | *-------------------------------------------------------------------------*/ | |
615 | ||
616 | /* link an ed into one of the HC chains */ | |
617 | ||
6f5794a6 | 618 | static int ep_link(ohci_t *ohci, ed_t *edi) |
3e326ece MK |
619 | { |
620 | volatile ed_t *ed = edi; | |
4dae14ce ZW |
621 | int int_branch; |
622 | int i; | |
623 | int inter; | |
624 | int interval; | |
625 | int load; | |
6f5794a6 | 626 | __u32 *ed_p; |
3e326ece MK |
627 | |
628 | ed->state = ED_OPER; | |
4dae14ce | 629 | ed->int_interval = 0; |
3e326ece MK |
630 | |
631 | switch (ed->type) { | |
632 | case PIPE_CONTROL: | |
633 | ed->hwNextED = 0; | |
6f5794a6 RB |
634 | if (ohci->ed_controltail == NULL) |
635 | writel(ed, &ohci->regs->ed_controlhead); | |
636 | else | |
637 | ohci->ed_controltail->hwNextED = | |
638 | m32_swap((unsigned long)ed); | |
639 | ||
3e326ece MK |
640 | ed->ed_prev = ohci->ed_controltail; |
641 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
642 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
643 | ohci->hc_control |= OHCI_CTRL_CLE; | |
6f5794a6 | 644 | writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
645 | } |
646 | ohci->ed_controltail = edi; | |
647 | break; | |
648 | ||
649 | case PIPE_BULK: | |
650 | ed->hwNextED = 0; | |
6f5794a6 RB |
651 | if (ohci->ed_bulktail == NULL) |
652 | writel(ed, &ohci->regs->ed_bulkhead); | |
653 | else | |
654 | ohci->ed_bulktail->hwNextED = | |
655 | m32_swap((unsigned long)ed); | |
656 | ||
3e326ece MK |
657 | ed->ed_prev = ohci->ed_bulktail; |
658 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
659 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
660 | ohci->hc_control |= OHCI_CTRL_BLE; | |
6f5794a6 | 661 | writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
662 | } |
663 | ohci->ed_bulktail = edi; | |
664 | break; | |
4dae14ce ZW |
665 | |
666 | case PIPE_INTERRUPT: | |
667 | load = ed->int_load; | |
6f5794a6 | 668 | interval = ep_2_n_interval(ed->int_period); |
4dae14ce | 669 | ed->int_interval = interval; |
6f5794a6 | 670 | int_branch = ep_int_ballance(ohci, interval, load); |
4dae14ce ZW |
671 | ed->int_branch = int_branch; |
672 | ||
6f5794a6 | 673 | for (i = 0; i < ep_rev(6, interval); i += inter) { |
4dae14ce | 674 | inter = 1; |
6f5794a6 RB |
675 | for (ed_p = &(ohci->hcca->int_table[\ |
676 | ep_rev(5, i) + int_branch]); | |
677 | (*ed_p != 0) && | |
678 | (((ed_t *)ed_p)->int_interval >= interval); | |
4dae14ce | 679 | ed_p = &(((ed_t *)ed_p)->hwNextED)) |
6f5794a6 RB |
680 | inter = ep_rev(6, |
681 | ((ed_t *)ed_p)->int_interval); | |
4dae14ce | 682 | ed->hwNextED = *ed_p; |
4a8527ef | 683 | *ed_p = m32_swap((unsigned long)ed); |
4dae14ce ZW |
684 | } |
685 | break; | |
3e326ece MK |
686 | } |
687 | return 0; | |
688 | } | |
689 | ||
690 | /*-------------------------------------------------------------------------*/ | |
691 | ||
4dae14ce | 692 | /* scan the periodic table to find and unlink this ED */ |
6f5794a6 RB |
693 | static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, |
694 | unsigned index, unsigned period) | |
4dae14ce ZW |
695 | { |
696 | for (; index < NUM_INTS; index += period) { | |
697 | __u32 *ed_p = &ohci->hcca->int_table [index]; | |
698 | ||
699 | /* ED might have been unlinked through another path */ | |
700 | while (*ed_p != 0) { | |
6f5794a6 RB |
701 | if (((struct ed *) |
702 | m32_swap((unsigned long)ed_p)) == ed) { | |
4dae14ce ZW |
703 | *ed_p = ed->hwNextED; |
704 | break; | |
705 | } | |
6f5794a6 RB |
706 | ed_p = &(((struct ed *) |
707 | m32_swap((unsigned long)ed_p))->hwNextED); | |
4dae14ce ZW |
708 | } |
709 | } | |
710 | } | |
711 | ||
3e326ece MK |
712 | /* unlink an ed from one of the HC chains. |
713 | * just the link to the ed is unlinked. | |
714 | * the link from the ed still points to another operational ed or 0 | |
715 | * so the HC can eventually finish the processing of the unlinked ed */ | |
716 | ||
6f5794a6 | 717 | static int ep_unlink(ohci_t *ohci, ed_t *edi) |
3e326ece | 718 | { |
53e336e9 | 719 | volatile ed_t *ed = edi; |
4dae14ce | 720 | int i; |
53e336e9 | 721 | |
6f5794a6 | 722 | ed->hwINFO |= m32_swap(OHCI_ED_SKIP); |
3e326ece MK |
723 | |
724 | switch (ed->type) { | |
725 | case PIPE_CONTROL: | |
726 | if (ed->ed_prev == NULL) { | |
727 | if (!ed->hwNextED) { | |
728 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
6f5794a6 | 729 | writel(ohci->hc_control, &ohci->regs->control); |
3e326ece | 730 | } |
6f5794a6 RB |
731 | writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
732 | &ohci->regs->ed_controlhead); | |
3e326ece MK |
733 | } else { |
734 | ed->ed_prev->hwNextED = ed->hwNextED; | |
735 | } | |
736 | if (ohci->ed_controltail == ed) { | |
737 | ohci->ed_controltail = ed->ed_prev; | |
738 | } else { | |
6f5794a6 RB |
739 | ((ed_t *)m32_swap( |
740 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
741 | } |
742 | break; | |
743 | ||
744 | case PIPE_BULK: | |
745 | if (ed->ed_prev == NULL) { | |
746 | if (!ed->hwNextED) { | |
747 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
6f5794a6 | 748 | writel(ohci->hc_control, &ohci->regs->control); |
3e326ece | 749 | } |
6f5794a6 RB |
750 | writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
751 | &ohci->regs->ed_bulkhead); | |
3e326ece MK |
752 | } else { |
753 | ed->ed_prev->hwNextED = ed->hwNextED; | |
754 | } | |
755 | if (ohci->ed_bulktail == ed) { | |
756 | ohci->ed_bulktail = ed->ed_prev; | |
757 | } else { | |
6f5794a6 RB |
758 | ((ed_t *)m32_swap( |
759 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
760 | } |
761 | break; | |
4dae14ce ZW |
762 | |
763 | case PIPE_INTERRUPT: | |
6f5794a6 | 764 | periodic_unlink(ohci, ed, 0, 1); |
4dae14ce ZW |
765 | for (i = ed->int_branch; i < 32; i += ed->int_interval) |
766 | ohci->ohci_int_load[i] -= ed->int_load; | |
767 | break; | |
3e326ece MK |
768 | } |
769 | ed->state = ED_UNLINK; | |
770 | return 0; | |
771 | } | |
772 | ||
3e326ece MK |
773 | /*-------------------------------------------------------------------------*/ |
774 | ||
ddf83a2f MK |
775 | /* add/reinit an endpoint; this should be done once at the |
776 | * usb_set_configuration command, but the USB stack is a little bit | |
777 | * stateless so we do it at every transaction if the state of the ed | |
778 | * is ED_NEW then a dummy td is added and the state is changed to | |
779 | * ED_UNLINK in all other cases the state is left unchanged the ed | |
780 | * info fields are setted anyway even though most of them should not | |
781 | * change | |
782 | */ | |
6f5794a6 RB |
783 | static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, |
784 | int interval, int load) | |
3e326ece MK |
785 | { |
786 | td_t *td; | |
787 | ed_t *ed_ret; | |
788 | volatile ed_t *ed; | |
789 | ||
6f5794a6 RB |
790 | ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | |
791 | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; | |
3e326ece MK |
792 | |
793 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
794 | err("ep_add_ed: pending delete"); | |
795 | /* pending delete request */ | |
796 | return NULL; | |
797 | } | |
798 | ||
799 | if (ed->state == ED_NEW) { | |
3e326ece | 800 | /* dummy td; end of td list for ed */ |
6f5794a6 RB |
801 | td = td_alloc(usb_dev); |
802 | ed->hwTailP = m32_swap((unsigned long)td); | |
3e326ece MK |
803 | ed->hwHeadP = ed->hwTailP; |
804 | ed->state = ED_UNLINK; | |
6f5794a6 | 805 | ed->type = usb_pipetype(pipe); |
3e326ece MK |
806 | ohci_dev.ed_cnt++; |
807 | } | |
808 | ||
6f5794a6 RB |
809 | ed->hwINFO = m32_swap(usb_pipedevice(pipe) |
810 | | usb_pipeendpoint(pipe) << 7 | |
811 | | (usb_pipeisoc(pipe)? 0x8000: 0) | |
812 | | (usb_pipecontrol(pipe)? 0: \ | |
813 | (usb_pipeout(pipe)? 0x800: 0x1000)) | |
814 | | usb_pipeslow(pipe) << 13 | |
815 | | usb_maxpacket(usb_dev, pipe) << 16); | |
3e326ece | 816 | |
4dae14ce ZW |
817 | if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { |
818 | ed->int_period = interval; | |
819 | ed->int_load = load; | |
820 | } | |
821 | ||
3e326ece MK |
822 | return ed_ret; |
823 | } | |
824 | ||
825 | /*-------------------------------------------------------------------------* | |
826 | * TD handling functions | |
827 | *-------------------------------------------------------------------------*/ | |
828 | ||
829 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
830 | ||
6f5794a6 | 831 | static void td_fill(ohci_t *ohci, unsigned int info, |
3e326ece MK |
832 | void *data, int len, |
833 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
834 | { | |
835 | volatile td_t *td, *td_pt; | |
836 | #ifdef OHCI_FILL_TRACE | |
837 | int i; | |
838 | #endif | |
839 | ||
840 | if (index > urb_priv->length) { | |
841 | err("index > length"); | |
842 | return; | |
843 | } | |
844 | /* use this td as the next dummy */ | |
845 | td_pt = urb_priv->td [index]; | |
846 | td_pt->hwNextTD = 0; | |
847 | ||
848 | /* fill the old dummy TD */ | |
6f5794a6 RB |
849 | td = urb_priv->td [index] = |
850 | (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); | |
3e326ece MK |
851 | |
852 | td->ed = urb_priv->ed; | |
853 | td->next_dl_td = NULL; | |
854 | td->index = index; | |
855 | td->data = (__u32)data; | |
856 | #ifdef OHCI_FILL_TRACE | |
48867208 | 857 | if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { |
3e326ece | 858 | for (i = 0; i < len; i++) |
6f5794a6 | 859 | printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); |
3e326ece MK |
860 | printf("\n"); |
861 | } | |
862 | #endif | |
863 | if (!len) | |
864 | data = 0; | |
865 | ||
6f5794a6 RB |
866 | td->hwINFO = m32_swap(info); |
867 | td->hwCBP = m32_swap((unsigned long)data); | |
3e326ece | 868 | if (data) |
6f5794a6 | 869 | td->hwBE = m32_swap((unsigned long)(data + len - 1)); |
3e326ece MK |
870 | else |
871 | td->hwBE = 0; | |
6f5794a6 RB |
872 | |
873 | td->hwNextTD = m32_swap((unsigned long)td_pt); | |
3e326ece MK |
874 | |
875 | /* append to queue */ | |
876 | td->ed->hwTailP = td->hwNextTD; | |
877 | } | |
878 | ||
879 | /*-------------------------------------------------------------------------*/ | |
880 | ||
881 | /* prepare all TDs of a transfer */ | |
882 | ||
6f5794a6 RB |
883 | static void td_submit_job(struct usb_device *dev, unsigned long pipe, |
884 | void *buffer, int transfer_len, | |
885 | struct devrequest *setup, urb_priv_t *urb, | |
886 | int interval) | |
3e326ece MK |
887 | { |
888 | ohci_t *ohci = &gohci; | |
889 | int data_len = transfer_len; | |
890 | void *data; | |
891 | int cnt = 0; | |
892 | __u32 info = 0; | |
893 | unsigned int toggle = 0; | |
894 | ||
6f5794a6 RB |
895 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle |
896 | * bits for reseting */ | |
897 | if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { | |
3e326ece MK |
898 | toggle = TD_T_TOGGLE; |
899 | } else { | |
900 | toggle = TD_T_DATA0; | |
6f5794a6 RB |
901 | usb_settoggle(dev, usb_pipeendpoint(pipe), |
902 | usb_pipeout(pipe), 1); | |
3e326ece MK |
903 | } |
904 | urb->td_cnt = 0; | |
905 | if (data_len) | |
906 | data = buffer; | |
907 | else | |
908 | data = 0; | |
909 | ||
6f5794a6 | 910 | switch (usb_pipetype(pipe)) { |
3e326ece | 911 | case PIPE_BULK: |
6f5794a6 | 912 | info = usb_pipeout(pipe)? |
3e326ece | 913 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; |
6f5794a6 RB |
914 | while (data_len > 4096) { |
915 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), | |
916 | data, 4096, dev, cnt, urb); | |
3e326ece MK |
917 | data += 4096; data_len -= 4096; cnt++; |
918 | } | |
6f5794a6 | 919 | info = usb_pipeout(pipe)? |
3e326ece | 920 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; |
6f5794a6 RB |
921 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, |
922 | data_len, dev, cnt, urb); | |
3e326ece MK |
923 | cnt++; |
924 | ||
6f5794a6 RB |
925 | if (!ohci->sleeping) { |
926 | /* start bulk list */ | |
927 | writel(OHCI_BLF, &ohci->regs->cmdstatus); | |
928 | } | |
3e326ece MK |
929 | break; |
930 | ||
931 | case PIPE_CONTROL: | |
6f5794a6 | 932 | /* Setup phase */ |
3e326ece | 933 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; |
6f5794a6 RB |
934 | td_fill(ohci, info, setup, 8, dev, cnt++, urb); |
935 | ||
936 | /* Optional Data phase */ | |
3e326ece | 937 | if (data_len > 0) { |
6f5794a6 RB |
938 | info = usb_pipeout(pipe)? |
939 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : | |
940 | TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
3e326ece | 941 | /* NOTE: mishandles transfers >8K, some >4K */ |
6f5794a6 RB |
942 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
943 | } | |
944 | ||
945 | /* Status phase */ | |
946 | info = usb_pipeout(pipe)? | |
947 | TD_CC | TD_DP_IN | TD_T_DATA1: | |
948 | TD_CC | TD_DP_OUT | TD_T_DATA1; | |
949 | td_fill(ohci, info, data, 0, dev, cnt++, urb); | |
950 | ||
951 | if (!ohci->sleeping) { | |
952 | /* start Control list */ | |
953 | writel(OHCI_CLF, &ohci->regs->cmdstatus); | |
3e326ece | 954 | } |
3e326ece | 955 | break; |
4dae14ce ZW |
956 | |
957 | case PIPE_INTERRUPT: | |
6f5794a6 | 958 | info = usb_pipeout(urb->pipe)? |
4dae14ce ZW |
959 | TD_CC | TD_DP_OUT | toggle: |
960 | TD_CC | TD_R | TD_DP_IN | toggle; | |
6f5794a6 | 961 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
4dae14ce | 962 | break; |
3e326ece MK |
963 | } |
964 | if (urb->length != cnt) | |
965 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
966 | } | |
967 | ||
968 | /*-------------------------------------------------------------------------* | |
969 | * Done List handling functions | |
970 | *-------------------------------------------------------------------------*/ | |
971 | ||
3e326ece MK |
972 | /* calculate the transfer length and update the urb */ |
973 | ||
6f5794a6 | 974 | static void dl_transfer_length(td_t *td) |
3e326ece MK |
975 | { |
976 | __u32 tdINFO, tdBE, tdCBP; | |
4dae14ce | 977 | urb_priv_t *lurb_priv = td->ed->purb; |
3e326ece | 978 | |
6f5794a6 RB |
979 | tdINFO = m32_swap(td->hwINFO); |
980 | tdBE = m32_swap(td->hwBE); | |
981 | tdCBP = m32_swap(td->hwCBP); | |
3e326ece | 982 | |
48867208 | 983 | if (!(usb_pipecontrol(lurb_priv->pipe) && |
3e326ece MK |
984 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { |
985 | if (tdBE != 0) { | |
986 | if (td->hwCBP == 0) | |
987 | lurb_priv->actual_length += tdBE - td->data + 1; | |
988 | else | |
989 | lurb_priv->actual_length += tdCBP - td->data; | |
990 | } | |
991 | } | |
992 | } | |
993 | ||
994 | /*-------------------------------------------------------------------------*/ | |
6f5794a6 RB |
995 | static void check_status(td_t *td_list) |
996 | { | |
997 | urb_priv_t *lurb_priv = td_list->ed->purb; | |
998 | int urb_len = lurb_priv->length; | |
999 | __u32 *phwHeadP = &td_list->ed->hwHeadP; | |
1000 | int cc; | |
1001 | ||
1002 | cc = TD_CC_GET(m32_swap(td_list->hwINFO)); | |
1003 | if (cc) { | |
1004 | err(" USB-error: %s (%x)", cc_to_string[cc], cc); | |
1005 | ||
1006 | if (*phwHeadP & m32_swap(0x1)) { | |
1007 | if (lurb_priv && | |
1008 | ((td_list->index + 1) < urb_len)) { | |
1009 | *phwHeadP = | |
1010 | (lurb_priv->td[urb_len - 1]->hwNextTD &\ | |
1011 | m32_swap(0xfffffff0)) | | |
1012 | (*phwHeadP & m32_swap(0x2)); | |
1013 | ||
1014 | lurb_priv->td_cnt += urb_len - | |
1015 | td_list->index - 1; | |
1016 | } else | |
1017 | *phwHeadP &= m32_swap(0xfffffff2); | |
1018 | } | |
1019 | #ifdef CONFIG_MPC5200 | |
1020 | td_list->hwNextTD = 0; | |
1021 | #endif | |
1022 | } | |
1023 | } | |
3e326ece MK |
1024 | |
1025 | /* replies to the request have to be on a FIFO basis so | |
1026 | * we reverse the reversed done-list */ | |
6f5794a6 | 1027 | static td_t *dl_reverse_done_list(ohci_t *ohci) |
3e326ece MK |
1028 | { |
1029 | __u32 td_list_hc; | |
1030 | td_t *td_rev = NULL; | |
1031 | td_t *td_list = NULL; | |
3e326ece | 1032 | |
6f5794a6 | 1033 | td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; |
3e326ece MK |
1034 | ohci->hcca->done_head = 0; |
1035 | ||
1036 | while (td_list_hc) { | |
1037 | td_list = (td_t *)td_list_hc; | |
6f5794a6 | 1038 | check_status(td_list); |
3e326ece MK |
1039 | td_list->next_dl_td = td_rev; |
1040 | td_rev = td_list; | |
6f5794a6 | 1041 | td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; |
3e326ece MK |
1042 | } |
1043 | return td_list; | |
1044 | } | |
1045 | ||
6f5794a6 | 1046 | /*-------------------------------------------------------------------------*/ |
3e326ece MK |
1047 | /*-------------------------------------------------------------------------*/ |
1048 | ||
6f5794a6 RB |
1049 | static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) |
1050 | { | |
1051 | if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) | |
1052 | urb->finished = sohci_return_job(ohci, urb); | |
1053 | else | |
1054 | dbg("finish_urb: strange.., ED state %x, \n", status); | |
1055 | } | |
1056 | ||
1057 | /* | |
1058 | * Used to take back a TD from the host controller. This would normally be | |
1059 | * called from within dl_done_list, however it may be called directly if the | |
1060 | * HC no longer sees the TD and it has not appeared on the donelist (after | |
1061 | * two frames). This bug has been observed on ZF Micro systems. | |
1062 | */ | |
1063 | static int takeback_td(ohci_t *ohci, td_t *td_list) | |
3e326ece | 1064 | { |
3e326ece | 1065 | ed_t *ed; |
6f5794a6 | 1066 | int cc; |
3e326ece MK |
1067 | int stat = 0; |
1068 | /* urb_t *urb; */ | |
1069 | urb_priv_t *lurb_priv; | |
1070 | __u32 tdINFO, edHeadP, edTailP; | |
1071 | ||
6f5794a6 | 1072 | tdINFO = m32_swap(td_list->hwINFO); |
3e326ece | 1073 | |
6f5794a6 RB |
1074 | ed = td_list->ed; |
1075 | lurb_priv = ed->purb; | |
3e326ece | 1076 | |
6f5794a6 | 1077 | dl_transfer_length(td_list); |
3e326ece | 1078 | |
6f5794a6 | 1079 | lurb_priv->td_cnt++; |
3e326ece | 1080 | |
6f5794a6 RB |
1081 | /* error code of transfer */ |
1082 | cc = TD_CC_GET(tdINFO); | |
1083 | if (cc) { | |
1084 | err("USB-error: %s (%x)", cc_to_string[cc], cc); | |
1085 | stat = cc_to_error[cc]; | |
1086 | } | |
ae79f606 | 1087 | |
6f5794a6 RB |
1088 | /* see if this done list makes for all TD's of current URB, |
1089 | * and mark the URB finished if so */ | |
1090 | if (lurb_priv->td_cnt == lurb_priv->length) | |
1091 | finish_urb(ohci, lurb_priv, ed->state); | |
1092 | ||
1093 | dbg("dl_done_list: processing TD %x, len %x\n", | |
1094 | lurb_priv->td_cnt, lurb_priv->length); | |
1095 | ||
48867208 | 1096 | if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { |
6f5794a6 RB |
1097 | edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; |
1098 | edTailP = m32_swap(ed->hwTailP); | |
1099 | ||
1100 | /* unlink eds if they are not busy */ | |
1101 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
1102 | ep_unlink(ohci, ed); | |
1103 | } | |
1104 | return stat; | |
1105 | } | |
3e326ece | 1106 | |
6f5794a6 RB |
1107 | static int dl_done_list(ohci_t *ohci) |
1108 | { | |
1109 | int stat = 0; | |
1110 | td_t *td_list = dl_reverse_done_list(ohci); | |
1111 | ||
1112 | while (td_list) { | |
1113 | td_t *td_next = td_list->next_dl_td; | |
1114 | stat = takeback_td(ohci, td_list); | |
1115 | td_list = td_next; | |
3e326ece MK |
1116 | } |
1117 | return stat; | |
1118 | } | |
1119 | ||
1120 | /*-------------------------------------------------------------------------* | |
1121 | * Virtual Root Hub | |
1122 | *-------------------------------------------------------------------------*/ | |
1123 | ||
1124 | /* Device descriptor */ | |
1125 | static __u8 root_hub_dev_des[] = | |
1126 | { | |
1127 | 0x12, /* __u8 bLength; */ | |
1128 | 0x01, /* __u8 bDescriptorType; Device */ | |
1129 | 0x10, /* __u16 bcdUSB; v1.1 */ | |
1130 | 0x01, | |
1131 | 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ | |
1132 | 0x00, /* __u8 bDeviceSubClass; */ | |
1133 | 0x00, /* __u8 bDeviceProtocol; */ | |
1134 | 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ | |
1135 | 0x00, /* __u16 idVendor; */ | |
1136 | 0x00, | |
1137 | 0x00, /* __u16 idProduct; */ | |
1138 | 0x00, | |
1139 | 0x00, /* __u16 bcdDevice; */ | |
1140 | 0x00, | |
1141 | 0x00, /* __u8 iManufacturer; */ | |
1142 | 0x01, /* __u8 iProduct; */ | |
1143 | 0x00, /* __u8 iSerialNumber; */ | |
1144 | 0x01 /* __u8 bNumConfigurations; */ | |
1145 | }; | |
1146 | ||
3e326ece MK |
1147 | /* Configuration descriptor */ |
1148 | static __u8 root_hub_config_des[] = | |
1149 | { | |
1150 | 0x09, /* __u8 bLength; */ | |
1151 | 0x02, /* __u8 bDescriptorType; Configuration */ | |
1152 | 0x19, /* __u16 wTotalLength; */ | |
1153 | 0x00, | |
1154 | 0x01, /* __u8 bNumInterfaces; */ | |
1155 | 0x01, /* __u8 bConfigurationValue; */ | |
1156 | 0x00, /* __u8 iConfiguration; */ | |
1157 | 0x40, /* __u8 bmAttributes; | |
6f5794a6 | 1158 | Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ |
3e326ece MK |
1159 | 0x00, /* __u8 MaxPower; */ |
1160 | ||
1161 | /* interface */ | |
1162 | 0x09, /* __u8 if_bLength; */ | |
1163 | 0x04, /* __u8 if_bDescriptorType; Interface */ | |
1164 | 0x00, /* __u8 if_bInterfaceNumber; */ | |
1165 | 0x00, /* __u8 if_bAlternateSetting; */ | |
1166 | 0x01, /* __u8 if_bNumEndpoints; */ | |
1167 | 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ | |
1168 | 0x00, /* __u8 if_bInterfaceSubClass; */ | |
1169 | 0x00, /* __u8 if_bInterfaceProtocol; */ | |
1170 | 0x00, /* __u8 if_iInterface; */ | |
1171 | ||
1172 | /* endpoint */ | |
1173 | 0x07, /* __u8 ep_bLength; */ | |
1174 | 0x05, /* __u8 ep_bDescriptorType; Endpoint */ | |
1175 | 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ | |
1176 | 0x03, /* __u8 ep_bmAttributes; Interrupt */ | |
1177 | 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ | |
1178 | 0x00, | |
1179 | 0xff /* __u8 ep_bInterval; 255 ms */ | |
1180 | }; | |
1181 | ||
1182 | static unsigned char root_hub_str_index0[] = | |
1183 | { | |
1184 | 0x04, /* __u8 bLength; */ | |
1185 | 0x03, /* __u8 bDescriptorType; String-descriptor */ | |
1186 | 0x09, /* __u8 lang ID */ | |
1187 | 0x04, /* __u8 lang ID */ | |
1188 | }; | |
1189 | ||
1190 | static unsigned char root_hub_str_index1[] = | |
1191 | { | |
1192 | 28, /* __u8 bLength; */ | |
1193 | 0x03, /* __u8 bDescriptorType; String-descriptor */ | |
1194 | 'O', /* __u8 Unicode */ | |
1195 | 0, /* __u8 Unicode */ | |
1196 | 'H', /* __u8 Unicode */ | |
1197 | 0, /* __u8 Unicode */ | |
1198 | 'C', /* __u8 Unicode */ | |
1199 | 0, /* __u8 Unicode */ | |
1200 | 'I', /* __u8 Unicode */ | |
1201 | 0, /* __u8 Unicode */ | |
1202 | ' ', /* __u8 Unicode */ | |
1203 | 0, /* __u8 Unicode */ | |
1204 | 'R', /* __u8 Unicode */ | |
1205 | 0, /* __u8 Unicode */ | |
1206 | 'o', /* __u8 Unicode */ | |
1207 | 0, /* __u8 Unicode */ | |
1208 | 'o', /* __u8 Unicode */ | |
1209 | 0, /* __u8 Unicode */ | |
1210 | 't', /* __u8 Unicode */ | |
1211 | 0, /* __u8 Unicode */ | |
1212 | ' ', /* __u8 Unicode */ | |
1213 | 0, /* __u8 Unicode */ | |
1214 | 'H', /* __u8 Unicode */ | |
1215 | 0, /* __u8 Unicode */ | |
1216 | 'u', /* __u8 Unicode */ | |
1217 | 0, /* __u8 Unicode */ | |
1218 | 'b', /* __u8 Unicode */ | |
1219 | 0, /* __u8 Unicode */ | |
1220 | }; | |
1221 | ||
1222 | /* Hub class-specific descriptor is constructed dynamically */ | |
1223 | ||
3e326ece MK |
1224 | /*-------------------------------------------------------------------------*/ |
1225 | ||
1226 | #define OK(x) len = (x); break | |
1227 | #ifdef DEBUG | |
6f5794a6 RB |
1228 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); writel((x), \ |
1229 | &gohci.regs->roothub.status); } | |
1230 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ | |
1231 | (x)); writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); } | |
3e326ece MK |
1232 | #else |
1233 | #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) | |
6f5794a6 RB |
1234 | #define WR_RH_PORTSTAT(x) writel((x), \ |
1235 | &gohci.regs->roothub.portstatus[wIndex-1]) | |
3e326ece MK |
1236 | #endif |
1237 | #define RD_RH_STAT roothub_status(&gohci) | |
6f5794a6 | 1238 | #define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) |
3e326ece MK |
1239 | |
1240 | /* request to virtual root hub */ | |
1241 | ||
1242 | int rh_check_port_status(ohci_t *controller) | |
1243 | { | |
1244 | __u32 temp, ndp, i; | |
1245 | int res; | |
1246 | ||
1247 | res = -1; | |
6f5794a6 | 1248 | temp = roothub_a(controller); |
3e326ece MK |
1249 | ndp = (temp & RH_A_NDP); |
1250 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1251 | ndp = (ndp == 2) ? 1:0; | |
1252 | #endif | |
1253 | for (i = 0; i < ndp; i++) { | |
6f5794a6 | 1254 | temp = roothub_portstatus(controller, i); |
3e326ece MK |
1255 | /* check for a device disconnect */ |
1256 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
1257 | (RH_PS_PESC | RH_PS_CSC)) && | |
1258 | ((temp & RH_PS_CCS) == 0)) { | |
1259 | res = i; | |
1260 | break; | |
1261 | } | |
1262 | } | |
1263 | return res; | |
1264 | } | |
1265 | ||
1266 | static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, | |
1267 | void *buffer, int transfer_len, struct devrequest *cmd) | |
1268 | { | |
6f5794a6 | 1269 | void *data = buffer; |
3e326ece MK |
1270 | int leni = transfer_len; |
1271 | int len = 0; | |
1272 | int stat = 0; | |
1273 | __u32 datab[4]; | |
1274 | __u8 *data_buf = (__u8 *)datab; | |
1275 | __u16 bmRType_bReq; | |
1276 | __u16 wValue; | |
1277 | __u16 wIndex; | |
1278 | __u16 wLength; | |
1279 | ||
1280 | #ifdef DEBUG | |
6f5794a6 RB |
1281 | pkt_print(NULL, dev, pipe, buffer, transfer_len, |
1282 | cmd, "SUB(rh)", usb_pipein(pipe)); | |
3e326ece MK |
1283 | #else |
1284 | wait_ms(1); | |
1285 | #endif | |
48867208 | 1286 | if (usb_pipeint(pipe)) { |
3e326ece MK |
1287 | info("Root-Hub submit IRQ: NOT implemented"); |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
6f5794a6 RB |
1292 | wValue = le16_to_cpu(cmd->value); |
1293 | wIndex = le16_to_cpu(cmd->index); | |
1294 | wLength = le16_to_cpu(cmd->length); | |
3e326ece MK |
1295 | |
1296 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
1297 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); | |
1298 | ||
1299 | switch (bmRType_bReq) { | |
1300 | /* Request Destination: | |
1301 | without flags: Device, | |
1302 | RH_INTERFACE: interface, | |
1303 | RH_ENDPOINT: endpoint, | |
1304 | RH_CLASS means HUB here, | |
1305 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1306 | */ | |
1307 | ||
1308 | case RH_GET_STATUS: | |
6f5794a6 RB |
1309 | *(__u16 *) data_buf = cpu_to_le16(1); |
1310 | OK(2); | |
3e326ece | 1311 | case RH_GET_STATUS | RH_INTERFACE: |
6f5794a6 RB |
1312 | *(__u16 *) data_buf = cpu_to_le16(0); |
1313 | OK(2); | |
3e326ece | 1314 | case RH_GET_STATUS | RH_ENDPOINT: |
6f5794a6 RB |
1315 | *(__u16 *) data_buf = cpu_to_le16(0); |
1316 | OK(2); | |
3e326ece | 1317 | case RH_GET_STATUS | RH_CLASS: |
6f5794a6 | 1318 | *(__u32 *) data_buf = cpu_to_le32( |
3e326ece | 1319 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); |
6f5794a6 | 1320 | OK(4); |
3e326ece | 1321 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
6f5794a6 RB |
1322 | *(__u32 *) data_buf = cpu_to_le32(RD_RH_PORTSTAT); |
1323 | OK(4); | |
3e326ece MK |
1324 | |
1325 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1326 | switch (wValue) { | |
6f5794a6 RB |
1327 | case (RH_ENDPOINT_STALL): |
1328 | OK(0); | |
3e326ece MK |
1329 | } |
1330 | break; | |
1331 | ||
1332 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1333 | switch (wValue) { | |
6f5794a6 RB |
1334 | case RH_C_HUB_LOCAL_POWER: |
1335 | OK(0); | |
1336 | case (RH_C_HUB_OVER_CURRENT): | |
1337 | WR_RH_STAT(RH_HS_OCIC); | |
1338 | OK(0); | |
3e326ece MK |
1339 | } |
1340 | break; | |
1341 | ||
1342 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1343 | switch (wValue) { | |
6f5794a6 RB |
1344 | case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); |
1345 | case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); | |
1346 | case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); | |
1347 | case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); | |
1348 | case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); | |
1349 | case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); | |
1350 | case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); | |
1351 | case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); | |
3e326ece MK |
1352 | } |
1353 | break; | |
1354 | ||
1355 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1356 | switch (wValue) { | |
6f5794a6 RB |
1357 | case (RH_PORT_SUSPEND): |
1358 | WR_RH_PORTSTAT(RH_PS_PSS); OK(0); | |
1359 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1360 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1361 | WR_RH_PORTSTAT(RH_PS_PRS); | |
1362 | OK(0); | |
1363 | case (RH_PORT_POWER): | |
1364 | WR_RH_PORTSTAT(RH_PS_PPS); | |
1365 | wait_ms(100); | |
1366 | OK(0); | |
1367 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
1368 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1369 | WR_RH_PORTSTAT(RH_PS_PES); | |
1370 | OK(0); | |
3e326ece MK |
1371 | } |
1372 | break; | |
1373 | ||
6f5794a6 RB |
1374 | case RH_SET_ADDRESS: |
1375 | gohci.rh.devnum = wValue; | |
1376 | OK(0); | |
3e326ece MK |
1377 | |
1378 | case RH_GET_DESCRIPTOR: | |
1379 | switch ((wValue & 0xff00) >> 8) { | |
6f5794a6 RB |
1380 | case (0x01): /* device descriptor */ |
1381 | len = min_t(unsigned int, | |
1382 | leni, | |
1383 | min_t(unsigned int, | |
1384 | sizeof(root_hub_dev_des), | |
1385 | wLength)); | |
1386 | data_buf = root_hub_dev_des; OK(len); | |
1387 | case (0x02): /* configuration descriptor */ | |
1388 | len = min_t(unsigned int, | |
1389 | leni, | |
1390 | min_t(unsigned int, | |
1391 | sizeof(root_hub_config_des), | |
1392 | wLength)); | |
1393 | data_buf = root_hub_config_des; OK(len); | |
1394 | case (0x03): /* string descriptors */ | |
1395 | if (wValue == 0x0300) { | |
3e326ece | 1396 | len = min_t(unsigned int, |
6f5794a6 RB |
1397 | leni, |
1398 | min_t(unsigned int, | |
1399 | sizeof(root_hub_str_index0), | |
1400 | wLength)); | |
1401 | data_buf = root_hub_str_index0; | |
1402 | OK(len); | |
3e326ece | 1403 | } |
6f5794a6 RB |
1404 | if (wValue == 0x0301) { |
1405 | len = min_t(unsigned int, | |
1406 | leni, | |
1407 | min_t(unsigned int, | |
1408 | sizeof(root_hub_str_index1), | |
1409 | wLength)); | |
1410 | data_buf = root_hub_str_index1; | |
1411 | OK(len); | |
1412 | } | |
1413 | default: | |
1414 | stat = USB_ST_STALLED; | |
3e326ece MK |
1415 | } |
1416 | break; | |
1417 | ||
1418 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
1419 | { | |
6f5794a6 | 1420 | __u32 temp = roothub_a(&gohci); |
3e326ece MK |
1421 | |
1422 | data_buf [0] = 9; /* min length; */ | |
1423 | data_buf [1] = 0x29; | |
1424 | data_buf [2] = temp & RH_A_NDP; | |
1425 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1426 | data_buf [2] = (data_buf [2] == 2) ? 1:0; | |
1427 | #endif | |
3e326ece MK |
1428 | data_buf [3] = 0; |
1429 | if (temp & RH_A_PSM) /* per-port power switching? */ | |
1430 | data_buf [3] |= 0x1; | |
1431 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ | |
1432 | data_buf [3] |= 0x10; | |
6f5794a6 | 1433 | else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ |
3e326ece | 1434 | data_buf [3] |= 0x8; |
3e326ece MK |
1435 | |
1436 | /* corresponds to data_buf[4-7] */ | |
1437 | datab [1] = 0; | |
1438 | data_buf [5] = (temp & RH_A_POTPGT) >> 24; | |
6f5794a6 | 1439 | temp = roothub_b(&gohci); |
3e326ece MK |
1440 | data_buf [7] = temp & RH_B_DR; |
1441 | if (data_buf [2] < 7) { | |
1442 | data_buf [8] = 0xff; | |
1443 | } else { | |
1444 | data_buf [0] += 2; | |
1445 | data_buf [8] = (temp & RH_B_DR) >> 8; | |
1446 | data_buf [10] = data_buf [9] = 0xff; | |
1447 | } | |
1448 | ||
1449 | len = min_t(unsigned int, leni, | |
ddf83a2f | 1450 | min_t(unsigned int, data_buf [0], wLength)); |
6f5794a6 | 1451 | OK(len); |
3e326ece MK |
1452 | } |
1453 | ||
6f5794a6 | 1454 | case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK(1); |
3e326ece | 1455 | |
6f5794a6 | 1456 | case RH_SET_CONFIGURATION: WR_RH_STAT(0x10000); OK(0); |
3e326ece MK |
1457 | |
1458 | default: | |
6f5794a6 | 1459 | dbg("unsupported root hub command"); |
3e326ece MK |
1460 | stat = USB_ST_STALLED; |
1461 | } | |
1462 | ||
1463 | #ifdef DEBUG | |
6f5794a6 | 1464 | ohci_dump_roothub(&gohci, 1); |
3e326ece MK |
1465 | #else |
1466 | wait_ms(1); | |
1467 | #endif | |
1468 | ||
1469 | len = min_t(int, len, leni); | |
1470 | if (data != data_buf) | |
6f5794a6 | 1471 | memcpy(data, data_buf, len); |
3e326ece MK |
1472 | dev->act_len = len; |
1473 | dev->status = stat; | |
1474 | ||
1475 | #ifdef DEBUG | |
6f5794a6 RB |
1476 | pkt_print(NULL, dev, pipe, buffer, |
1477 | transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); | |
3e326ece MK |
1478 | #else |
1479 | wait_ms(1); | |
1480 | #endif | |
1481 | ||
1482 | return stat; | |
1483 | } | |
1484 | ||
1485 | /*-------------------------------------------------------------------------*/ | |
1486 | ||
1487 | /* common code for handling submit messages - used for all but root hub */ | |
1488 | /* accesses. */ | |
1489 | int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1490 | int transfer_len, struct devrequest *setup, int interval) | |
1491 | { | |
1492 | int stat = 0; | |
1493 | int maxsize = usb_maxpacket(dev, pipe); | |
1494 | int timeout; | |
4dae14ce ZW |
1495 | urb_priv_t *urb; |
1496 | ||
1497 | urb = malloc(sizeof(urb_priv_t)); | |
1498 | memset(urb, 0, sizeof(urb_priv_t)); | |
1499 | ||
1500 | urb->dev = dev; | |
1501 | urb->pipe = pipe; | |
1502 | urb->transfer_buffer = buffer; | |
1503 | urb->transfer_buffer_length = transfer_len; | |
1504 | urb->interval = interval; | |
3e326ece MK |
1505 | |
1506 | /* device pulled? Shortcut the action. */ | |
1507 | if (devgone == dev) { | |
1508 | dev->status = USB_ST_CRC_ERR; | |
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | #ifdef DEBUG | |
4dae14ce | 1513 | urb->actual_length = 0; |
6f5794a6 RB |
1514 | pkt_print(urb, dev, pipe, buffer, transfer_len, |
1515 | setup, "SUB", usb_pipein(pipe)); | |
3e326ece MK |
1516 | #else |
1517 | wait_ms(1); | |
1518 | #endif | |
1519 | if (!maxsize) { | |
1520 | err("submit_common_message: pipesize for pipe %lx is zero", | |
1521 | pipe); | |
1522 | return -1; | |
1523 | } | |
1524 | ||
4dae14ce | 1525 | if (sohci_submit_job(urb, setup) < 0) { |
3e326ece MK |
1526 | err("sohci_submit_job failed"); |
1527 | return -1; | |
1528 | } | |
1529 | ||
ae3b770e | 1530 | #if 0 |
3e326ece MK |
1531 | wait_ms(10); |
1532 | /* ohci_dump_status(&gohci); */ | |
ae3b770e | 1533 | #endif |
3e326ece MK |
1534 | |
1535 | /* allow more time for a BULK device to react - some are slow */ | |
1536 | #define BULK_TO 5000 /* timeout in milliseconds */ | |
48867208 | 1537 | if (usb_pipebulk(pipe)) |
3e326ece MK |
1538 | timeout = BULK_TO; |
1539 | else | |
1540 | timeout = 100; | |
1541 | ||
1542 | /* wait for it to complete */ | |
1543 | for (;;) { | |
1544 | /* check whether the controller is done */ | |
1545 | stat = hc_interrupt(); | |
1546 | if (stat < 0) { | |
1547 | stat = USB_ST_CRC_ERR; | |
1548 | break; | |
1549 | } | |
ddf83a2f | 1550 | |
ddf83a2f MK |
1551 | /* NOTE: since we are not interrupt driven in U-Boot and always |
1552 | * handle only one URB at a time, we cannot assume the | |
1553 | * transaction finished on the first successful return from | |
1554 | * hc_interrupt().. unless the flag for current URB is set, | |
1555 | * meaning that all TD's to/from device got actually | |
1556 | * transferred and processed. If the current URB is not | |
1557 | * finished we need to re-iterate this loop so as | |
1558 | * hc_interrupt() gets called again as there needs to be some | |
1559 | * more TD's to process still */ | |
4dae14ce | 1560 | if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { |
3e326ece MK |
1561 | /* 0xff is returned for an SF-interrupt */ |
1562 | break; | |
1563 | } | |
ddf83a2f | 1564 | |
3e326ece MK |
1565 | if (--timeout) { |
1566 | wait_ms(1); | |
4dae14ce | 1567 | if (!urb->finished) |
6f5794a6 | 1568 | dbg("*"); |
4dae14ce | 1569 | |
3e326ece MK |
1570 | } else { |
1571 | err("CTL:TIMEOUT "); | |
ddf83a2f | 1572 | dbg("submit_common_msg: TO status %x\n", stat); |
4dae14ce | 1573 | urb->finished = 1; |
3e326ece MK |
1574 | stat = USB_ST_CRC_ERR; |
1575 | break; | |
1576 | } | |
1577 | } | |
3e326ece MK |
1578 | |
1579 | dev->status = stat; | |
1580 | dev->act_len = transfer_len; | |
1581 | ||
1582 | #ifdef DEBUG | |
6f5794a6 RB |
1583 | pkt_print(urb, dev, pipe, buffer, transfer_len, |
1584 | setup, "RET(ctlr)", usb_pipein(pipe)); | |
3e326ece MK |
1585 | #else |
1586 | wait_ms(1); | |
1587 | #endif | |
1588 | ||
1589 | /* free TDs in urb_priv */ | |
48867208 | 1590 | if (!usb_pipeint(pipe)) |
6f5794a6 | 1591 | urb_free_priv(urb); |
3e326ece MK |
1592 | return 0; |
1593 | } | |
1594 | ||
1595 | /* submit routines called from usb.c */ | |
1596 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1597 | int transfer_len) | |
1598 | { | |
1599 | info("submit_bulk_msg"); | |
1600 | return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); | |
1601 | } | |
1602 | ||
1603 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1604 | int transfer_len, struct devrequest *setup) | |
1605 | { | |
1606 | int maxsize = usb_maxpacket(dev, pipe); | |
1607 | ||
1608 | info("submit_control_msg"); | |
1609 | #ifdef DEBUG | |
6f5794a6 RB |
1610 | pkt_print(NULL, dev, pipe, buffer, transfer_len, |
1611 | setup, "SUB", usb_pipein(pipe)); | |
3e326ece MK |
1612 | #else |
1613 | wait_ms(1); | |
1614 | #endif | |
1615 | if (!maxsize) { | |
1616 | err("submit_control_message: pipesize for pipe %lx is zero", | |
1617 | pipe); | |
1618 | return -1; | |
1619 | } | |
1620 | if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { | |
1621 | gohci.rh.dev = dev; | |
1622 | /* root hub - redirect */ | |
1623 | return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, | |
1624 | setup); | |
1625 | } | |
1626 | ||
1627 | return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); | |
1628 | } | |
1629 | ||
1630 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1631 | int transfer_len, int interval) | |
1632 | { | |
1633 | info("submit_int_msg"); | |
4dae14ce ZW |
1634 | return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, |
1635 | interval); | |
3e326ece MK |
1636 | } |
1637 | ||
1638 | /*-------------------------------------------------------------------------* | |
1639 | * HC functions | |
1640 | *-------------------------------------------------------------------------*/ | |
1641 | ||
1642 | /* reset the HC and BUS */ | |
1643 | ||
6f5794a6 | 1644 | static int hc_reset(ohci_t *ohci) |
3e326ece | 1645 | { |
e90fb6af YT |
1646 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1647 | pci_dev_t pdev; | |
1648 | #endif | |
3e326ece MK |
1649 | int timeout = 30; |
1650 | int smm_timeout = 50; /* 0,5 sec */ | |
1651 | ||
1652 | dbg("%s\n", __FUNCTION__); | |
1653 | ||
e90fb6af YT |
1654 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1655 | /* | |
1656 | * Some multi-function controllers (e.g. ISP1562) allow root hub | |
1657 | * resetting via EHCI registers only. | |
1658 | */ | |
1659 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); | |
1660 | if (pdev != -1) { | |
1661 | u32 base; | |
1662 | int timeout = 1000; | |
1663 | ||
1664 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
6f5794a6 | 1665 | writel(readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET, |
e90fb6af YT |
1666 | base + EHCI_USBCMD_OFF); |
1667 | ||
1668 | while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) { | |
1669 | if (timeout-- <= 0) { | |
1670 | printf("USB RootHub reset timed out!"); | |
1671 | break; | |
1672 | } | |
1673 | udelay(1); | |
1674 | } | |
1675 | } else | |
1676 | printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); | |
1677 | #endif | |
6f5794a6 RB |
1678 | if (readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
1679 | /* SMM owns the HC */ | |
1680 | writel(OHCI_OCR, &ohci->regs->cmdstatus);/* request ownership */ | |
3e326ece | 1681 | info("USB HC TakeOver from SMM"); |
6f5794a6 RB |
1682 | while (readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
1683 | wait_ms(10); | |
3e326ece MK |
1684 | if (--smm_timeout == 0) { |
1685 | err("USB HC TakeOver failed!"); | |
1686 | return -1; | |
1687 | } | |
1688 | } | |
1689 | } | |
1690 | ||
1691 | /* Disable HC interrupts */ | |
6f5794a6 | 1692 | writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3e326ece MK |
1693 | |
1694 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", | |
1695 | ohci->slot_name, | |
1696 | readl(&ohci->regs->control)); | |
1697 | ||
1698 | /* Reset USB (needed by some controllers) */ | |
53e336e9 | 1699 | ohci->hc_control = 0; |
6f5794a6 | 1700 | writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1701 | |
1702 | /* HC Reset requires max 10 us delay */ | |
6f5794a6 RB |
1703 | writel(OHCI_HCR, &ohci->regs->cmdstatus); |
1704 | while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
3e326ece MK |
1705 | if (--timeout == 0) { |
1706 | err("USB HC reset timed out!"); | |
1707 | return -1; | |
1708 | } | |
6f5794a6 | 1709 | udelay(1); |
3e326ece MK |
1710 | } |
1711 | return 0; | |
1712 | } | |
1713 | ||
1714 | /*-------------------------------------------------------------------------*/ | |
1715 | ||
1716 | /* Start an OHCI controller, set the BUS operational | |
1717 | * enable interrupts | |
1718 | * connect the virtual root hub */ | |
1719 | ||
6f5794a6 | 1720 | static int hc_start(ohci_t *ohci) |
3e326ece MK |
1721 | { |
1722 | __u32 mask; | |
1723 | unsigned int fminterval; | |
1724 | ||
1725 | ohci->disabled = 1; | |
1726 | ||
1727 | /* Tell the controller where the control and bulk lists are | |
1728 | * The lists are empty now. */ | |
1729 | ||
6f5794a6 RB |
1730 | writel(0, &ohci->regs->ed_controlhead); |
1731 | writel(0, &ohci->regs->ed_bulkhead); | |
3e326ece | 1732 | |
6f5794a6 | 1733 | writel((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ |
3e326ece MK |
1734 | |
1735 | fminterval = 0x2edf; | |
6f5794a6 | 1736 | writel((fminterval * 9) / 10, &ohci->regs->periodicstart); |
3e326ece | 1737 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
6f5794a6 RB |
1738 | writel(fminterval, &ohci->regs->fminterval); |
1739 | writel(0x628, &ohci->regs->lsthresh); | |
3e326ece MK |
1740 | |
1741 | /* start controller operations */ | |
1742 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1743 | ohci->disabled = 0; | |
6f5794a6 | 1744 | writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1745 | |
1746 | /* disable all interrupts */ | |
1747 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
1748 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | | |
1749 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
6f5794a6 | 1750 | writel(mask, &ohci->regs->intrdisable); |
3e326ece MK |
1751 | /* clear all interrupts */ |
1752 | mask &= ~OHCI_INTR_MIE; | |
6f5794a6 | 1753 | writel(mask, &ohci->regs->intrstatus); |
3e326ece MK |
1754 | /* Choose the interrupts we care about now - but w/o MIE */ |
1755 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
6f5794a6 | 1756 | writel(mask, &ohci->regs->intrenable); |
3e326ece MK |
1757 | |
1758 | #ifdef OHCI_USE_NPS | |
1759 | /* required for AMD-756 and some Mac platforms */ | |
6f5794a6 | 1760 | writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, |
3e326ece | 1761 | &ohci->regs->roothub.a); |
6f5794a6 | 1762 | writel(RH_HS_LPSC, &ohci->regs->roothub.status); |
3e326ece MK |
1763 | #endif /* OHCI_USE_NPS */ |
1764 | ||
6f5794a6 | 1765 | #define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) |
3e326ece | 1766 | /* POTPGT delay is bits 24-31, in 2 ms units. */ |
6f5794a6 | 1767 | mdelay((roothub_a(ohci) >> 23) & 0x1fe); |
3e326ece MK |
1768 | |
1769 | /* connect the virtual root hub */ | |
1770 | ohci->rh.devnum = 0; | |
1771 | ||
1772 | return 0; | |
1773 | } | |
1774 | ||
1775 | /*-------------------------------------------------------------------------*/ | |
1776 | ||
4dae14ce ZW |
1777 | /* Poll USB interrupt. */ |
1778 | void usb_event_poll(void) | |
1779 | { | |
1780 | hc_interrupt(); | |
1781 | } | |
1782 | ||
3e326ece MK |
1783 | /* an interrupt happens */ |
1784 | ||
6f5794a6 | 1785 | static int hc_interrupt(void) |
3e326ece MK |
1786 | { |
1787 | ohci_t *ohci = &gohci; | |
1788 | struct ohci_regs *regs = ohci->regs; | |
1789 | int ints; | |
1790 | int stat = -1; | |
1791 | ||
ddf83a2f | 1792 | if ((ohci->hcca->done_head != 0) && |
6f5794a6 | 1793 | !(m32_swap(ohci->hcca->done_head) & 0x01)) { |
ddf83a2f | 1794 | ints = OHCI_INTR_WDH; |
6f5794a6 RB |
1795 | } else { |
1796 | ints = readl(®s->intrstatus); | |
1797 | if (ints == ~(u32)0) { | |
1798 | ohci->disabled++; | |
1799 | err("%s device removed!", ohci->slot_name); | |
1800 | return -1; | |
1801 | } else { | |
1802 | ints &= readl(®s->intrenable); | |
1803 | if (ints == 0) { | |
1804 | dbg("hc_interrupt: returning..\n"); | |
1805 | return 0xff; | |
1806 | } | |
1807 | } | |
ddf83a2f | 1808 | } |
ae79f606 | 1809 | |
6f5794a6 RB |
1810 | /* dbg("Interrupt: %x frame: %x", ints, |
1811 | le16_to_cpu(ohci->hcca->frame_no)); */ | |
3e326ece | 1812 | |
6f5794a6 | 1813 | if (ints & OHCI_INTR_RHSC) |
ddf83a2f | 1814 | stat = 0xff; |
3e326ece MK |
1815 | |
1816 | if (ints & OHCI_INTR_UE) { | |
1817 | ohci->disabled++; | |
6f5794a6 | 1818 | err("OHCI Unrecoverable Error, controller usb-%s disabled", |
3e326ece MK |
1819 | ohci->slot_name); |
1820 | /* e.g. due to PCI Master/Target Abort */ | |
1821 | ||
1822 | #ifdef DEBUG | |
6f5794a6 | 1823 | ohci_dump(ohci, 1); |
3e326ece | 1824 | #else |
6f5794a6 | 1825 | wait_ms(1); |
3e326ece MK |
1826 | #endif |
1827 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1828 | /* Make some non-interrupt context restart the controller. */ | |
1829 | /* Count and limit the retries though; either hardware or */ | |
1830 | /* software errors can go forever... */ | |
6f5794a6 | 1831 | hc_reset(ohci); |
3e326ece MK |
1832 | return -1; |
1833 | } | |
1834 | ||
1835 | if (ints & OHCI_INTR_WDH) { | |
1836 | wait_ms(1); | |
6f5794a6 RB |
1837 | writel(OHCI_INTR_WDH, ®s->intrdisable); |
1838 | (void)readl(®s->intrdisable); /* flush */ | |
1839 | stat = dl_done_list(&gohci); | |
1840 | writel(OHCI_INTR_WDH, ®s->intrenable); | |
1841 | (void)readl(®s->intrdisable); /* flush */ | |
3e326ece MK |
1842 | } |
1843 | ||
1844 | if (ints & OHCI_INTR_SO) { | |
1845 | dbg("USB Schedule overrun\n"); | |
6f5794a6 | 1846 | writel(OHCI_INTR_SO, ®s->intrenable); |
3e326ece MK |
1847 | stat = -1; |
1848 | } | |
1849 | ||
1850 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1851 | if (ints & OHCI_INTR_SF) { | |
6f5794a6 | 1852 | unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; |
3e326ece | 1853 | wait_ms(1); |
6f5794a6 | 1854 | writel(OHCI_INTR_SF, ®s->intrdisable); |
3e326ece | 1855 | if (ohci->ed_rm_list[frame] != NULL) |
6f5794a6 | 1856 | writel(OHCI_INTR_SF, ®s->intrenable); |
3e326ece MK |
1857 | stat = 0xff; |
1858 | } | |
1859 | ||
6f5794a6 | 1860 | writel(ints, ®s->intrstatus); |
3e326ece MK |
1861 | return stat; |
1862 | } | |
1863 | ||
1864 | /*-------------------------------------------------------------------------*/ | |
1865 | ||
1866 | /*-------------------------------------------------------------------------*/ | |
1867 | ||
1868 | /* De-allocate all resources.. */ | |
1869 | ||
6f5794a6 | 1870 | static void hc_release_ohci(ohci_t *ohci) |
3e326ece | 1871 | { |
6f5794a6 | 1872 | dbg("USB HC release ohci usb-%s", ohci->slot_name); |
3e326ece MK |
1873 | |
1874 | if (!ohci->disabled) | |
6f5794a6 | 1875 | hc_reset(ohci); |
3e326ece MK |
1876 | } |
1877 | ||
1878 | /*-------------------------------------------------------------------------*/ | |
1879 | ||
1880 | /* | |
1881 | * low level initalisation routine, called from usb.c | |
1882 | */ | |
1883 | static char ohci_inited = 0; | |
1884 | ||
1885 | int usb_lowlevel_init(void) | |
1886 | { | |
4dae14ce ZW |
1887 | #ifdef CONFIG_PCI_OHCI |
1888 | pci_dev_t pdev; | |
1889 | #endif | |
24e37645 | 1890 | |
6d0f6bcf | 1891 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1892 | /* cpu dependant init */ |
6f5794a6 | 1893 | if (usb_cpu_init()) |
3e326ece | 1894 | return -1; |
24e37645 | 1895 | #endif |
3e326ece | 1896 | |
6d0f6bcf | 1897 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1898 | /* board dependant init */ |
6f5794a6 | 1899 | if (usb_board_init()) |
24e37645 MK |
1900 | return -1; |
1901 | #endif | |
6f5794a6 | 1902 | memset(&gohci, 0, sizeof(ohci_t)); |
3e326ece MK |
1903 | |
1904 | /* align the storage */ | |
1905 | if ((__u32)&ghcca[0] & 0xff) { | |
1906 | err("HCCA not aligned!!"); | |
1907 | return -1; | |
1908 | } | |
1909 | phcca = &ghcca[0]; | |
1910 | info("aligned ghcca %p", phcca); | |
1911 | memset(&ohci_dev, 0, sizeof(struct ohci_device)); | |
1912 | if ((__u32)&ohci_dev.ed[0] & 0x7) { | |
1913 | err("EDs not aligned!!"); | |
1914 | return -1; | |
1915 | } | |
1916 | memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); | |
1917 | if ((__u32)gtd & 0x7) { | |
1918 | err("TDs not aligned!!"); | |
1919 | return -1; | |
1920 | } | |
1921 | ptd = gtd; | |
1922 | gohci.hcca = phcca; | |
6f5794a6 | 1923 | memset(phcca, 0, sizeof(struct ohci_hcca)); |
3e326ece MK |
1924 | |
1925 | gohci.disabled = 1; | |
1926 | gohci.sleeping = 0; | |
1927 | gohci.irq = -1; | |
4dae14ce | 1928 | #ifdef CONFIG_PCI_OHCI |
477434c6 | 1929 | pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); |
4dae14ce ZW |
1930 | |
1931 | if (pdev != -1) { | |
1932 | u16 vid, did; | |
1933 | u32 base; | |
1934 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); | |
1935 | pci_read_config_word(pdev, PCI_DEVICE_ID, &did); | |
1936 | printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", | |
1937 | vid, did, (pdev >> 16) & 0xff, | |
1938 | (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); | |
1939 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
1940 | printf("OHCI regs address 0x%08x\n", base); | |
1941 | gohci.regs = (struct ohci_regs *)base; | |
1942 | } else | |
1943 | return -1; | |
1944 | #else | |
6d0f6bcf | 1945 | gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; |
4dae14ce | 1946 | #endif |
3e326ece MK |
1947 | |
1948 | gohci.flags = 0; | |
6d0f6bcf | 1949 | gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; |
3e326ece MK |
1950 | |
1951 | if (hc_reset (&gohci) < 0) { | |
1952 | hc_release_ohci (&gohci); | |
1953 | err ("can't reset usb-%s", gohci.slot_name); | |
6d0f6bcf | 1954 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1955 | /* board dependant cleanup */ |
ddf83a2f | 1956 | usb_board_init_fail(); |
24e37645 MK |
1957 | #endif |
1958 | ||
6d0f6bcf | 1959 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1960 | /* cpu dependant cleanup */ |
ddf83a2f | 1961 | usb_cpu_init_fail(); |
24e37645 | 1962 | #endif |
3e326ece MK |
1963 | return -1; |
1964 | } | |
1965 | ||
6f5794a6 RB |
1966 | if (hc_start(&gohci) < 0) { |
1967 | err("can't start usb-%s", gohci.slot_name); | |
1968 | hc_release_ohci(&gohci); | |
3e326ece | 1969 | /* Initialization failed */ |
6d0f6bcf | 1970 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 MK |
1971 | /* board dependant cleanup */ |
1972 | usb_board_stop(); | |
1973 | #endif | |
1974 | ||
6d0f6bcf | 1975 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 MK |
1976 | /* cpu dependant cleanup */ |
1977 | usb_cpu_stop(); | |
1978 | #endif | |
3e326ece MK |
1979 | return -1; |
1980 | } | |
1981 | ||
1982 | #ifdef DEBUG | |
6f5794a6 | 1983 | ohci_dump(&gohci, 1); |
3e326ece MK |
1984 | #else |
1985 | wait_ms(1); | |
1986 | #endif | |
1987 | ohci_inited = 1; | |
1988 | return 0; | |
1989 | } | |
1990 | ||
1991 | int usb_lowlevel_stop(void) | |
1992 | { | |
1993 | /* this gets called really early - before the controller has */ | |
1994 | /* even been initialized! */ | |
1995 | if (!ohci_inited) | |
1996 | return 0; | |
1997 | /* TODO release any interrupts, etc. */ | |
1998 | /* call hc_release_ohci() here ? */ | |
6f5794a6 | 1999 | hc_reset(&gohci); |
3e326ece | 2000 | |
6d0f6bcf | 2001 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
3e326ece | 2002 | /* board dependant cleanup */ |
6f5794a6 | 2003 | if (usb_board_stop()) |
3e326ece | 2004 | return -1; |
24e37645 MK |
2005 | #endif |
2006 | ||
6d0f6bcf | 2007 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 2008 | /* cpu dependant cleanup */ |
6f5794a6 | 2009 | if (usb_cpu_stop()) |
24e37645 MK |
2010 | return -1; |
2011 | #endif | |
eba1f2fc RB |
2012 | /* This driver is no longer initialised. It needs a new low-level |
2013 | * init (board/cpu) before it can be used again. */ | |
2014 | ohci_inited = 0; | |
3e326ece MK |
2015 | return 0; |
2016 | } |