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3e326ece | 1 | /* |
4dae14ce ZW |
2 | * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. |
3 | * | |
4 | * Interrupt support is added. Now, it has been tested | |
5 | * on ULI1575 chip and works well with USB keyboard. | |
6 | * | |
7 | * (C) Copyright 2007 | |
8 | * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> | |
3e326ece MK |
9 | * |
10 | * (C) Copyright 2003 | |
11 | * Gary Jennejohn, DENX Software Engineering <gj@denx.de> | |
12 | * | |
13 | * Note: Much of this code has been derived from Linux 2.4 | |
14 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
15 | * (C) Copyright 2000-2002 David Brownell | |
16 | * | |
17 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard | |
18 | * ebenard@eukrea.com - based on s3c24x0's driver | |
19 | * | |
20 | * See file CREDITS for list of people who contributed to this | |
21 | * project. | |
22 | * | |
23 | * This program is free software; you can redistribute it and/or | |
24 | * modify it under the terms of the GNU General Public License as | |
25 | * published by the Free Software Foundation; either version 2 of | |
26 | * the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
ddf83a2f | 30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
3e326ece MK |
31 | * GNU General Public License for more details. |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
36 | * MA 02111-1307 USA | |
37 | * | |
38 | */ | |
39 | /* | |
40 | * IMPORTANT NOTES | |
41 | * 1 - you MUST define LITTLEENDIAN in the configuration file for the | |
42 | * board or this driver will NOT work! | |
43 | * 2 - this driver is intended for use with USB Mass Storage Devices | |
4dae14ce | 44 | * (BBB) and USB keyboard. There is NO support for Isochronous pipes! |
3e326ece MK |
45 | * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG |
46 | * to activate workaround for bug #41 or this driver will NOT work! | |
47 | */ | |
48 | ||
49 | #include <common.h> | |
50 | /* #include <pci.h> no PCI on the S3C24X0 */ | |
51 | ||
7b59b3c7 | 52 | #ifdef CONFIG_USB_OHCI_NEW |
3e326ece | 53 | |
53e336e9 | 54 | /* mk: are these really required? */ |
ddf83a2f MK |
55 | #if defined(CONFIG_S3C2400) |
56 | # include <s3c2400.h> | |
57 | #elif defined(CONFIG_S3C2410) | |
58 | # include <s3c2410.h> | |
59 | #elif defined(CONFIG_ARM920T) | |
60 | # include <asm/arch/hardware.h> | |
61 | #elif defined(CONFIG_CPU_MONAHANS) | |
62 | # include <asm/arch/pxa-regs.h> | |
53e336e9 MK |
63 | #elif defined(CONFIG_MPC5200) |
64 | # include <mpc5xxx.h> | |
4dae14ce ZW |
65 | #elif defined(CONFIG_PCI_OHCI) |
66 | # include <pci.h> | |
ddf83a2f | 67 | #endif |
3e326ece MK |
68 | |
69 | #include <malloc.h> | |
70 | #include <usb.h> | |
71 | #include "usb_ohci.h" | |
72 | ||
ddf83a2f MK |
73 | #if defined(CONFIG_ARM920T) || \ |
74 | defined(CONFIG_S3C2400) || \ | |
ae3b770e MK |
75 | defined(CONFIG_S3C2410) || \ |
76 | defined(CONFIG_440EP) || \ | |
4dae14ce | 77 | defined(CONFIG_PCI_OHCI) || \ |
ae3b770e | 78 | defined(CONFIG_MPC5200) |
24e37645 MK |
79 | # define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
80 | #endif | |
81 | ||
3e326ece | 82 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
ae3b770e MK |
83 | #undef DEBUG |
84 | #undef SHOW_INFO | |
85 | #undef OHCI_FILL_TRACE | |
3e326ece MK |
86 | |
87 | /* For initializing controller (mask in an HCFS mode too) */ | |
88 | #define OHCI_CONTROL_INIT \ | |
89 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
90 | ||
4dae14ce ZW |
91 | #define readl(a) m32_swap(*((vu_long *)(a))) |
92 | #define writel(a, b) (*((vu_long *)(b)) = m32_swap((vu_long)a)) | |
3e326ece MK |
93 | |
94 | #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) | |
95 | ||
4dae14ce ZW |
96 | #ifdef CONFIG_PCI_OHCI |
97 | static struct pci_device_id ohci_pci_ids[] = { | |
98 | {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ | |
99 | /* Please add supported PCI OHCI controller ids here */ | |
100 | {0, 0} | |
101 | }; | |
102 | #endif | |
103 | ||
3e326ece MK |
104 | #ifdef DEBUG |
105 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
106 | #else | |
107 | #define dbg(format, arg...) do {} while(0) | |
108 | #endif /* DEBUG */ | |
109 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) | |
110 | #undef SHOW_INFO | |
111 | #ifdef SHOW_INFO | |
112 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
113 | #else | |
114 | #define info(format, arg...) do {} while(0) | |
115 | #endif | |
116 | ||
ae3b770e MK |
117 | #if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) |
118 | # define m16_swap(x) (x) | |
119 | # define m32_swap(x) (x) | |
120 | #else | |
121 | # define m16_swap(x) swap_16(x) | |
122 | # define m32_swap(x) swap_32(x) | |
123 | #endif | |
3e326ece MK |
124 | |
125 | /* global ohci_t */ | |
126 | static ohci_t gohci; | |
127 | /* this must be aligned to a 256 byte boundary */ | |
128 | struct ohci_hcca ghcca[1]; | |
129 | /* a pointer to the aligned storage */ | |
130 | struct ohci_hcca *phcca; | |
131 | /* this allocates EDs for all possible endpoints */ | |
132 | struct ohci_device ohci_dev; | |
3e326ece MK |
133 | /* RHSC flag */ |
134 | int got_rhsc; | |
135 | /* device which was disconnected */ | |
136 | struct usb_device *devgone; | |
137 | ||
ddf83a2f MK |
138 | |
139 | ||
3e326ece MK |
140 | /*-------------------------------------------------------------------------*/ |
141 | ||
142 | /* AMD-756 (D2 rev) reports corrupt register contents in some cases. | |
143 | * The erratum (#4) description is incorrect. AMD's workaround waits | |
144 | * till some bits (mostly reserved) are clear; ok for all revs. | |
145 | */ | |
146 | #define OHCI_QUIRK_AMD756 0xabcd | |
147 | #define read_roothub(hc, register, mask) ({ \ | |
148 | u32 temp = readl (&hc->regs->roothub.register); \ | |
149 | if (hc->flags & OHCI_QUIRK_AMD756) \ | |
150 | while (temp & mask) \ | |
151 | temp = readl (&hc->regs->roothub.register); \ | |
152 | temp; }) | |
153 | ||
154 | static u32 roothub_a (struct ohci *hc) | |
155 | { return read_roothub (hc, a, 0xfc0fe000); } | |
156 | static inline u32 roothub_b (struct ohci *hc) | |
157 | { return readl (&hc->regs->roothub.b); } | |
158 | static inline u32 roothub_status (struct ohci *hc) | |
159 | { return readl (&hc->regs->roothub.status); } | |
160 | static u32 roothub_portstatus (struct ohci *hc, int i) | |
161 | { return read_roothub (hc, portstatus [i], 0xffe0fce0); } | |
162 | ||
163 | ||
164 | /* forward declaration */ | |
165 | static int hc_interrupt (void); | |
166 | static void | |
167 | td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, | |
168 | int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); | |
169 | ||
170 | /*-------------------------------------------------------------------------* | |
171 | * URB support functions | |
172 | *-------------------------------------------------------------------------*/ | |
173 | ||
174 | /* free HCD-private data associated with this URB */ | |
175 | ||
176 | static void urb_free_priv (urb_priv_t * urb) | |
177 | { | |
178 | int i; | |
179 | int last; | |
180 | struct td * td; | |
181 | ||
182 | last = urb->length - 1; | |
183 | if (last >= 0) { | |
184 | for (i = 0; i <= last; i++) { | |
185 | td = urb->td[i]; | |
186 | if (td) { | |
187 | td->usb_dev = NULL; | |
188 | urb->td[i] = NULL; | |
189 | } | |
190 | } | |
191 | } | |
4dae14ce | 192 | free(urb); |
3e326ece MK |
193 | } |
194 | ||
195 | /*-------------------------------------------------------------------------*/ | |
196 | ||
197 | #ifdef DEBUG | |
198 | static int sohci_get_current_frame_number (struct usb_device * dev); | |
199 | ||
200 | /* debug| print the main components of an URB | |
201 | * small: 0) header + data packets 1) just header */ | |
202 | ||
4dae14ce ZW |
203 | static void pkt_print (urb_priv_t *purb, struct usb_device * dev, |
204 | unsigned long pipe, void * buffer, | |
3e326ece MK |
205 | int transfer_len, struct devrequest * setup, char * str, int small) |
206 | { | |
3e326ece MK |
207 | dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", |
208 | str, | |
209 | sohci_get_current_frame_number (dev), | |
210 | usb_pipedevice (pipe), | |
211 | usb_pipeendpoint (pipe), | |
212 | usb_pipeout (pipe)? 'O': 'I', | |
213 | usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): | |
214 | (usb_pipecontrol (pipe)? "CTRL": "BULK"), | |
4dae14ce | 215 | (purb ? purb->actual_length : 0), |
3e326ece MK |
216 | transfer_len, dev->status); |
217 | #ifdef OHCI_VERBOSE_DEBUG | |
218 | if (!small) { | |
219 | int i, len; | |
220 | ||
221 | if (usb_pipecontrol (pipe)) { | |
222 | printf (__FILE__ ": cmd(8):"); | |
223 | for (i = 0; i < 8 ; i++) | |
224 | printf (" %02x", ((__u8 *) setup) [i]); | |
225 | printf ("\n"); | |
226 | } | |
227 | if (transfer_len > 0 && buffer) { | |
228 | printf (__FILE__ ": data(%d/%d):", | |
4dae14ce | 229 | (purb ? purb->actual_length : 0), |
3e326ece MK |
230 | transfer_len); |
231 | len = usb_pipeout (pipe)? | |
4dae14ce ZW |
232 | transfer_len: |
233 | (purb ? purb->actual_length : 0); | |
3e326ece MK |
234 | for (i = 0; i < 16 && i < len; i++) |
235 | printf (" %02x", ((__u8 *) buffer) [i]); | |
236 | printf ("%s\n", i < len? "...": ""); | |
237 | } | |
238 | } | |
239 | #endif | |
240 | } | |
241 | ||
242 | /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ | |
243 | void ep_print_int_eds (ohci_t *ohci, char * str) { | |
244 | int i, j; | |
245 | __u32 * ed_p; | |
246 | for (i= 0; i < 32; i++) { | |
247 | j = 5; | |
248 | ed_p = &(ohci->hcca->int_table [i]); | |
249 | if (*ed_p == 0) | |
250 | continue; | |
251 | printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); | |
252 | while (*ed_p != 0 && j--) { | |
253 | ed_t *ed = (ed_t *)m32_swap(ed_p); | |
254 | printf (" ed: %4x;", ed->hwINFO); | |
255 | ed_p = &ed->hwNextED; | |
256 | } | |
257 | printf ("\n"); | |
258 | } | |
259 | } | |
260 | ||
261 | static void ohci_dump_intr_mask (char *label, __u32 mask) | |
262 | { | |
263 | dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", | |
264 | label, | |
265 | mask, | |
266 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
267 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
268 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
269 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
270 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
271 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
272 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
273 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
274 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
275 | ); | |
276 | } | |
277 | ||
278 | static void maybe_print_eds (char *label, __u32 value) | |
279 | { | |
280 | ed_t *edp = (ed_t *)value; | |
281 | ||
282 | if (value) { | |
283 | dbg ("%s %08x", label, value); | |
284 | dbg ("%08x", edp->hwINFO); | |
285 | dbg ("%08x", edp->hwTailP); | |
286 | dbg ("%08x", edp->hwHeadP); | |
287 | dbg ("%08x", edp->hwNextED); | |
288 | } | |
289 | } | |
290 | ||
291 | static char * hcfs2string (int state) | |
292 | { | |
293 | switch (state) { | |
294 | case OHCI_USB_RESET: return "reset"; | |
295 | case OHCI_USB_RESUME: return "resume"; | |
296 | case OHCI_USB_OPER: return "operational"; | |
297 | case OHCI_USB_SUSPEND: return "suspend"; | |
298 | } | |
299 | return "?"; | |
300 | } | |
301 | ||
302 | /* dump control and status registers */ | |
303 | static void ohci_dump_status (ohci_t *controller) | |
304 | { | |
305 | struct ohci_regs *regs = controller->regs; | |
306 | __u32 temp; | |
307 | ||
308 | temp = readl (®s->revision) & 0xff; | |
309 | if (temp != 0x10) | |
310 | dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); | |
311 | ||
312 | temp = readl (®s->control); | |
313 | dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, | |
314 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", | |
315 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
316 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
317 | hcfs2string (temp & OHCI_CTRL_HCFS), | |
318 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", | |
319 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
320 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
321 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
322 | temp & OHCI_CTRL_CBSR | |
323 | ); | |
324 | ||
325 | temp = readl (®s->cmdstatus); | |
326 | dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, | |
327 | (temp & OHCI_SOC) >> 16, | |
328 | (temp & OHCI_OCR) ? " OCR" : "", | |
329 | (temp & OHCI_BLF) ? " BLF" : "", | |
330 | (temp & OHCI_CLF) ? " CLF" : "", | |
331 | (temp & OHCI_HCR) ? " HCR" : "" | |
332 | ); | |
333 | ||
334 | ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); | |
335 | ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); | |
336 | ||
337 | maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); | |
338 | ||
339 | maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); | |
340 | maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); | |
341 | ||
342 | maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); | |
343 | maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); | |
344 | ||
345 | maybe_print_eds ("donehead", readl (®s->donehead)); | |
346 | } | |
347 | ||
348 | static void ohci_dump_roothub (ohci_t *controller, int verbose) | |
349 | { | |
350 | __u32 temp, ndp, i; | |
351 | ||
352 | temp = roothub_a (controller); | |
353 | ndp = (temp & RH_A_NDP); | |
354 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
355 | ndp = (ndp == 2) ? 1:0; | |
3e326ece MK |
356 | #endif |
357 | if (verbose) { | |
358 | dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, | |
359 | ((temp & RH_A_POTPGT) >> 24) & 0xff, | |
360 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
361 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
362 | (temp & RH_A_DT) ? " DT" : "", | |
363 | (temp & RH_A_NPS) ? " NPS" : "", | |
364 | (temp & RH_A_PSM) ? " PSM" : "", | |
365 | ndp | |
366 | ); | |
367 | temp = roothub_b (controller); | |
368 | dbg ("roothub.b: %08x PPCM=%04x DR=%04x", | |
369 | temp, | |
370 | (temp & RH_B_PPCM) >> 16, | |
371 | (temp & RH_B_DR) | |
372 | ); | |
373 | temp = roothub_status (controller); | |
374 | dbg ("roothub.status: %08x%s%s%s%s%s%s", | |
375 | temp, | |
376 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
377 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
378 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
379 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
380 | (temp & RH_HS_OCI) ? " OCI" : "", | |
381 | (temp & RH_HS_LPS) ? " LPS" : "" | |
382 | ); | |
383 | } | |
384 | ||
385 | for (i = 0; i < ndp; i++) { | |
386 | temp = roothub_portstatus (controller, i); | |
387 | dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
388 | i, | |
389 | temp, | |
390 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
391 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
392 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
393 | (temp & RH_PS_PESC) ? " PESC" : "", | |
394 | (temp & RH_PS_CSC) ? " CSC" : "", | |
395 | ||
396 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
397 | (temp & RH_PS_PPS) ? " PPS" : "", | |
398 | (temp & RH_PS_PRS) ? " PRS" : "", | |
399 | (temp & RH_PS_POCI) ? " POCI" : "", | |
400 | (temp & RH_PS_PSS) ? " PSS" : "", | |
401 | ||
402 | (temp & RH_PS_PES) ? " PES" : "", | |
403 | (temp & RH_PS_CCS) ? " CCS" : "" | |
404 | ); | |
405 | } | |
406 | } | |
407 | ||
408 | static void ohci_dump (ohci_t *controller, int verbose) | |
409 | { | |
410 | dbg ("OHCI controller usb-%s state", controller->slot_name); | |
411 | ||
412 | /* dumps some of the state we know about */ | |
413 | ohci_dump_status (controller); | |
414 | if (verbose) | |
415 | ep_print_int_eds (controller, "hcca"); | |
416 | dbg ("hcca frame #%04x", controller->hcca->frame_no); | |
417 | ohci_dump_roothub (controller, 1); | |
418 | } | |
419 | ||
420 | ||
421 | #endif /* DEBUG */ | |
422 | ||
423 | /*-------------------------------------------------------------------------* | |
424 | * Interface functions (URB) | |
425 | *-------------------------------------------------------------------------*/ | |
426 | ||
427 | /* get a transfer request */ | |
428 | ||
4dae14ce | 429 | int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) |
3e326ece MK |
430 | { |
431 | ohci_t *ohci; | |
432 | ed_t * ed; | |
4dae14ce | 433 | urb_priv_t *purb_priv = urb; |
3e326ece | 434 | int i, size = 0; |
4dae14ce ZW |
435 | struct usb_device *dev = urb->dev; |
436 | unsigned long pipe = urb->pipe; | |
437 | void *buffer = urb->transfer_buffer; | |
438 | int transfer_len = urb->transfer_buffer_length; | |
439 | int interval = urb->interval; | |
3e326ece MK |
440 | |
441 | ohci = &gohci; | |
442 | ||
443 | /* when controller's hung, permit only roothub cleanup attempts | |
444 | * such as powering down ports */ | |
445 | if (ohci->disabled) { | |
446 | err("sohci_submit_job: EPIPE"); | |
447 | return -1; | |
448 | } | |
ae79f606 | 449 | |
ddf83a2f | 450 | /* we're about to begin a new transaction here so mark the URB unfinished */ |
4dae14ce | 451 | urb->finished = 0; |
3e326ece MK |
452 | |
453 | /* every endpoint has a ed, locate and fill it */ | |
4dae14ce | 454 | if (!(ed = ep_add_ed (dev, pipe, interval, 1))) { |
3e326ece MK |
455 | err("sohci_submit_job: ENOMEM"); |
456 | return -1; | |
457 | } | |
458 | ||
459 | /* for the private part of the URB we need the number of TDs (size) */ | |
460 | switch (usb_pipetype (pipe)) { | |
461 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
462 | size = (transfer_len - 1) / 4096 + 1; | |
463 | break; | |
464 | case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
465 | size = (transfer_len == 0)? 2: | |
466 | (transfer_len - 1) / 4096 + 3; | |
467 | break; | |
4dae14ce ZW |
468 | case PIPE_INTERRUPT: /* 1 TD */ |
469 | size = 1; | |
470 | break; | |
3e326ece MK |
471 | } |
472 | ||
4dae14ce ZW |
473 | ed->purb = urb; |
474 | ||
3e326ece MK |
475 | if (size >= (N_URB_TD - 1)) { |
476 | err("need %d TDs, only have %d", size, N_URB_TD); | |
477 | return -1; | |
478 | } | |
3e326ece MK |
479 | purb_priv->pipe = pipe; |
480 | ||
481 | /* fill the private part of the URB */ | |
482 | purb_priv->length = size; | |
483 | purb_priv->ed = ed; | |
484 | purb_priv->actual_length = 0; | |
485 | ||
486 | /* allocate the TDs */ | |
487 | /* note that td[0] was allocated in ep_add_ed */ | |
488 | for (i = 0; i < size; i++) { | |
489 | purb_priv->td[i] = td_alloc (dev); | |
490 | if (!purb_priv->td[i]) { | |
491 | purb_priv->length = i; | |
492 | urb_free_priv (purb_priv); | |
493 | err("sohci_submit_job: ENOMEM"); | |
494 | return -1; | |
495 | } | |
496 | } | |
497 | ||
498 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
499 | urb_free_priv (purb_priv); | |
500 | err("sohci_submit_job: EINVAL"); | |
501 | return -1; | |
502 | } | |
503 | ||
504 | /* link the ed into a chain if is not already */ | |
505 | if (ed->state != ED_OPER) | |
506 | ep_link (ohci, ed); | |
507 | ||
508 | /* fill the TDs and link it to the ed */ | |
509 | td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
4dae14ce ZW |
514 | static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) |
515 | { | |
516 | struct ohci_regs *regs = hc->regs; | |
517 | ||
518 | switch (usb_pipetype (urb->pipe)) { | |
519 | case PIPE_INTERRUPT: | |
520 | /* implicitly requeued */ | |
521 | if (urb->dev->irq_handle && | |
522 | (urb->dev->irq_act_len = urb->actual_length)) { | |
523 | writel (OHCI_INTR_WDH, ®s->intrenable); | |
524 | readl (®s->intrenable); /* PCI posting flush */ | |
525 | urb->dev->irq_handle(urb->dev); | |
526 | writel (OHCI_INTR_WDH, ®s->intrdisable); | |
527 | readl (®s->intrdisable); /* PCI posting flush */ | |
528 | } | |
529 | urb->actual_length = 0; | |
530 | td_submit_job ( | |
531 | urb->dev, | |
532 | urb->pipe, | |
533 | urb->transfer_buffer, | |
534 | urb->transfer_buffer_length, | |
535 | NULL, | |
536 | urb, | |
537 | urb->interval); | |
538 | break; | |
539 | case PIPE_CONTROL: | |
540 | case PIPE_BULK: | |
541 | break; | |
542 | default: | |
543 | return 0; | |
544 | } | |
545 | return 1; | |
546 | } | |
547 | ||
3e326ece MK |
548 | /*-------------------------------------------------------------------------*/ |
549 | ||
550 | #ifdef DEBUG | |
551 | /* tell us the current USB frame number */ | |
552 | ||
553 | static int sohci_get_current_frame_number (struct usb_device *usb_dev) | |
554 | { | |
555 | ohci_t *ohci = &gohci; | |
556 | ||
557 | return m16_swap (ohci->hcca->frame_no); | |
558 | } | |
559 | #endif | |
560 | ||
4dae14ce ZW |
561 | /*-------------------------------------------------------------------------* |
562 | * ED handling functions | |
563 | *-------------------------------------------------------------------------*/ | |
564 | ||
565 | /* search for the right branch to insert an interrupt ed into the int tree | |
566 | * do some load ballancing; | |
567 | * returns the branch and | |
568 | * sets the interval to interval = 2^integer (ld (interval)) */ | |
569 | ||
570 | static int ep_int_ballance (ohci_t * ohci, int interval, int load) | |
571 | { | |
572 | int i, branch = 0; | |
573 | ||
574 | /* search for the least loaded interrupt endpoint | |
575 | * branch of all 32 branches | |
576 | */ | |
577 | for (i = 0; i < 32; i++) | |
578 | if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) | |
579 | branch = i; | |
580 | ||
581 | branch = branch % interval; | |
582 | for (i = branch; i < 32; i += interval) | |
583 | ohci->ohci_int_load [i] += load; | |
584 | ||
585 | return branch; | |
586 | } | |
587 | ||
588 | /*-------------------------------------------------------------------------*/ | |
589 | ||
590 | /* 2^int( ld (inter)) */ | |
591 | ||
592 | static int ep_2_n_interval (int inter) | |
593 | { | |
594 | int i; | |
595 | for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++); | |
596 | return 1 << i; | |
597 | } | |
598 | ||
599 | /*-------------------------------------------------------------------------*/ | |
600 | ||
601 | /* the int tree is a binary tree | |
602 | * in order to process it sequentially the indexes of the branches have to be mapped | |
603 | * the mapping reverses the bits of a word of num_bits length */ | |
604 | ||
605 | static int ep_rev (int num_bits, int word) | |
606 | { | |
607 | int i, wout = 0; | |
608 | ||
609 | for (i = 0; i < num_bits; i++) | |
610 | wout |= (((word >> i) & 1) << (num_bits - i - 1)); | |
611 | return wout; | |
612 | } | |
613 | ||
3e326ece MK |
614 | /*-------------------------------------------------------------------------* |
615 | * ED handling functions | |
616 | *-------------------------------------------------------------------------*/ | |
617 | ||
618 | /* link an ed into one of the HC chains */ | |
619 | ||
620 | static int ep_link (ohci_t *ohci, ed_t *edi) | |
621 | { | |
622 | volatile ed_t *ed = edi; | |
4dae14ce ZW |
623 | int int_branch; |
624 | int i; | |
625 | int inter; | |
626 | int interval; | |
627 | int load; | |
628 | __u32 * ed_p; | |
3e326ece MK |
629 | |
630 | ed->state = ED_OPER; | |
4dae14ce | 631 | ed->int_interval = 0; |
3e326ece MK |
632 | |
633 | switch (ed->type) { | |
634 | case PIPE_CONTROL: | |
635 | ed->hwNextED = 0; | |
636 | if (ohci->ed_controltail == NULL) { | |
637 | writel (ed, &ohci->regs->ed_controlhead); | |
638 | } else { | |
ae3b770e | 639 | ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed); |
3e326ece MK |
640 | } |
641 | ed->ed_prev = ohci->ed_controltail; | |
642 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
643 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
644 | ohci->hc_control |= OHCI_CTRL_CLE; | |
645 | writel (ohci->hc_control, &ohci->regs->control); | |
646 | } | |
647 | ohci->ed_controltail = edi; | |
648 | break; | |
649 | ||
650 | case PIPE_BULK: | |
651 | ed->hwNextED = 0; | |
652 | if (ohci->ed_bulktail == NULL) { | |
653 | writel (ed, &ohci->regs->ed_bulkhead); | |
654 | } else { | |
ae3b770e | 655 | ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed); |
3e326ece MK |
656 | } |
657 | ed->ed_prev = ohci->ed_bulktail; | |
658 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
659 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
660 | ohci->hc_control |= OHCI_CTRL_BLE; | |
661 | writel (ohci->hc_control, &ohci->regs->control); | |
662 | } | |
663 | ohci->ed_bulktail = edi; | |
664 | break; | |
4dae14ce ZW |
665 | |
666 | case PIPE_INTERRUPT: | |
667 | load = ed->int_load; | |
668 | interval = ep_2_n_interval (ed->int_period); | |
669 | ed->int_interval = interval; | |
670 | int_branch = ep_int_ballance (ohci, interval, load); | |
671 | ed->int_branch = int_branch; | |
672 | ||
673 | for (i = 0; i < ep_rev (6, interval); i += inter) { | |
674 | inter = 1; | |
675 | for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]); | |
676 | (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval); | |
677 | ed_p = &(((ed_t *)ed_p)->hwNextED)) | |
678 | inter = ep_rev (6, ((ed_t *)ed_p)->int_interval); | |
679 | ed->hwNextED = *ed_p; | |
680 | *ed_p = m32_swap(ed); | |
681 | } | |
682 | break; | |
3e326ece MK |
683 | } |
684 | return 0; | |
685 | } | |
686 | ||
687 | /*-------------------------------------------------------------------------*/ | |
688 | ||
4dae14ce ZW |
689 | /* scan the periodic table to find and unlink this ED */ |
690 | static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed, | |
691 | unsigned index, unsigned period) | |
692 | { | |
693 | for (; index < NUM_INTS; index += period) { | |
694 | __u32 *ed_p = &ohci->hcca->int_table [index]; | |
695 | ||
696 | /* ED might have been unlinked through another path */ | |
697 | while (*ed_p != 0) { | |
698 | if (((struct ed *)m32_swap (ed_p)) == ed) { | |
699 | *ed_p = ed->hwNextED; | |
700 | break; | |
701 | } | |
702 | ed_p = & (((struct ed *)m32_swap (ed_p))->hwNextED); | |
703 | } | |
704 | } | |
705 | } | |
706 | ||
707 | ||
3e326ece MK |
708 | /* unlink an ed from one of the HC chains. |
709 | * just the link to the ed is unlinked. | |
710 | * the link from the ed still points to another operational ed or 0 | |
711 | * so the HC can eventually finish the processing of the unlinked ed */ | |
712 | ||
53e336e9 | 713 | static int ep_unlink (ohci_t *ohci, ed_t *edi) |
3e326ece | 714 | { |
53e336e9 | 715 | volatile ed_t *ed = edi; |
4dae14ce | 716 | int i; |
53e336e9 | 717 | |
3e326ece MK |
718 | ed->hwINFO |= m32_swap (OHCI_ED_SKIP); |
719 | ||
720 | switch (ed->type) { | |
721 | case PIPE_CONTROL: | |
722 | if (ed->ed_prev == NULL) { | |
723 | if (!ed->hwNextED) { | |
724 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
725 | writel (ohci->hc_control, &ohci->regs->control); | |
726 | } | |
727 | writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); | |
728 | } else { | |
729 | ed->ed_prev->hwNextED = ed->hwNextED; | |
730 | } | |
731 | if (ohci->ed_controltail == ed) { | |
732 | ohci->ed_controltail = ed->ed_prev; | |
733 | } else { | |
734 | ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
735 | } | |
736 | break; | |
737 | ||
738 | case PIPE_BULK: | |
739 | if (ed->ed_prev == NULL) { | |
740 | if (!ed->hwNextED) { | |
741 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
742 | writel (ohci->hc_control, &ohci->regs->control); | |
743 | } | |
744 | writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); | |
745 | } else { | |
746 | ed->ed_prev->hwNextED = ed->hwNextED; | |
747 | } | |
748 | if (ohci->ed_bulktail == ed) { | |
749 | ohci->ed_bulktail = ed->ed_prev; | |
750 | } else { | |
751 | ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
752 | } | |
753 | break; | |
4dae14ce ZW |
754 | |
755 | case PIPE_INTERRUPT: | |
756 | periodic_unlink (ohci, ed, 0, 1); | |
757 | for (i = ed->int_branch; i < 32; i += ed->int_interval) | |
758 | ohci->ohci_int_load[i] -= ed->int_load; | |
759 | break; | |
3e326ece MK |
760 | } |
761 | ed->state = ED_UNLINK; | |
762 | return 0; | |
763 | } | |
764 | ||
765 | ||
766 | /*-------------------------------------------------------------------------*/ | |
767 | ||
ddf83a2f MK |
768 | /* add/reinit an endpoint; this should be done once at the |
769 | * usb_set_configuration command, but the USB stack is a little bit | |
770 | * stateless so we do it at every transaction if the state of the ed | |
771 | * is ED_NEW then a dummy td is added and the state is changed to | |
772 | * ED_UNLINK in all other cases the state is left unchanged the ed | |
773 | * info fields are setted anyway even though most of them should not | |
774 | * change | |
775 | */ | |
4dae14ce ZW |
776 | static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe, |
777 | int interval, int load) | |
3e326ece MK |
778 | { |
779 | td_t *td; | |
780 | ed_t *ed_ret; | |
781 | volatile ed_t *ed; | |
782 | ||
783 | ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | | |
784 | (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; | |
785 | ||
786 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
787 | err("ep_add_ed: pending delete"); | |
788 | /* pending delete request */ | |
789 | return NULL; | |
790 | } | |
791 | ||
792 | if (ed->state == ED_NEW) { | |
793 | ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ | |
794 | /* dummy td; end of td list for ed */ | |
795 | td = td_alloc (usb_dev); | |
ae3b770e | 796 | ed->hwTailP = m32_swap ((unsigned long)td); |
3e326ece MK |
797 | ed->hwHeadP = ed->hwTailP; |
798 | ed->state = ED_UNLINK; | |
799 | ed->type = usb_pipetype (pipe); | |
800 | ohci_dev.ed_cnt++; | |
801 | } | |
802 | ||
803 | ed->hwINFO = m32_swap (usb_pipedevice (pipe) | |
804 | | usb_pipeendpoint (pipe) << 7 | |
805 | | (usb_pipeisoc (pipe)? 0x8000: 0) | |
806 | | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) | |
807 | | usb_pipeslow (pipe) << 13 | |
808 | | usb_maxpacket (usb_dev, pipe) << 16); | |
809 | ||
4dae14ce ZW |
810 | if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { |
811 | ed->int_period = interval; | |
812 | ed->int_load = load; | |
813 | } | |
814 | ||
3e326ece MK |
815 | return ed_ret; |
816 | } | |
817 | ||
818 | /*-------------------------------------------------------------------------* | |
819 | * TD handling functions | |
820 | *-------------------------------------------------------------------------*/ | |
821 | ||
822 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
823 | ||
824 | static void td_fill (ohci_t *ohci, unsigned int info, | |
825 | void *data, int len, | |
826 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
827 | { | |
828 | volatile td_t *td, *td_pt; | |
829 | #ifdef OHCI_FILL_TRACE | |
830 | int i; | |
831 | #endif | |
832 | ||
833 | if (index > urb_priv->length) { | |
834 | err("index > length"); | |
835 | return; | |
836 | } | |
837 | /* use this td as the next dummy */ | |
838 | td_pt = urb_priv->td [index]; | |
839 | td_pt->hwNextTD = 0; | |
840 | ||
841 | /* fill the old dummy TD */ | |
842 | td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); | |
843 | ||
844 | td->ed = urb_priv->ed; | |
845 | td->next_dl_td = NULL; | |
846 | td->index = index; | |
847 | td->data = (__u32)data; | |
848 | #ifdef OHCI_FILL_TRACE | |
849 | if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { | |
850 | for (i = 0; i < len; i++) | |
851 | printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); | |
852 | printf("\n"); | |
853 | } | |
854 | #endif | |
855 | if (!len) | |
856 | data = 0; | |
857 | ||
858 | td->hwINFO = m32_swap (info); | |
ae3b770e | 859 | td->hwCBP = m32_swap ((unsigned long)data); |
3e326ece | 860 | if (data) |
ae3b770e | 861 | td->hwBE = m32_swap ((unsigned long)(data + len - 1)); |
3e326ece MK |
862 | else |
863 | td->hwBE = 0; | |
ae3b770e | 864 | td->hwNextTD = m32_swap ((unsigned long)td_pt); |
3e326ece MK |
865 | |
866 | /* append to queue */ | |
867 | td->ed->hwTailP = td->hwNextTD; | |
868 | } | |
869 | ||
870 | /*-------------------------------------------------------------------------*/ | |
871 | ||
872 | /* prepare all TDs of a transfer */ | |
873 | ||
874 | static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, | |
875 | int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) | |
876 | { | |
877 | ohci_t *ohci = &gohci; | |
878 | int data_len = transfer_len; | |
879 | void *data; | |
880 | int cnt = 0; | |
881 | __u32 info = 0; | |
882 | unsigned int toggle = 0; | |
883 | ||
884 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ | |
885 | if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { | |
886 | toggle = TD_T_TOGGLE; | |
887 | } else { | |
888 | toggle = TD_T_DATA0; | |
889 | usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); | |
890 | } | |
891 | urb->td_cnt = 0; | |
892 | if (data_len) | |
893 | data = buffer; | |
894 | else | |
895 | data = 0; | |
896 | ||
897 | switch (usb_pipetype (pipe)) { | |
898 | case PIPE_BULK: | |
899 | info = usb_pipeout (pipe)? | |
900 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; | |
901 | while(data_len > 4096) { | |
902 | td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); | |
903 | data += 4096; data_len -= 4096; cnt++; | |
904 | } | |
905 | info = usb_pipeout (pipe)? | |
906 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; | |
907 | td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); | |
908 | cnt++; | |
909 | ||
910 | if (!ohci->sleeping) | |
911 | writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ | |
912 | break; | |
913 | ||
914 | case PIPE_CONTROL: | |
915 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; | |
916 | td_fill (ohci, info, setup, 8, dev, cnt++, urb); | |
917 | if (data_len > 0) { | |
918 | info = usb_pipeout (pipe)? | |
919 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
920 | /* NOTE: mishandles transfers >8K, some >4K */ | |
921 | td_fill (ohci, info, data, data_len, dev, cnt++, urb); | |
922 | } | |
923 | info = usb_pipeout (pipe)? | |
924 | TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; | |
925 | td_fill (ohci, info, data, 0, dev, cnt++, urb); | |
926 | if (!ohci->sleeping) | |
927 | writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ | |
928 | break; | |
4dae14ce ZW |
929 | |
930 | case PIPE_INTERRUPT: | |
931 | info = usb_pipeout (urb->pipe)? | |
932 | TD_CC | TD_DP_OUT | toggle: | |
933 | TD_CC | TD_R | TD_DP_IN | toggle; | |
934 | td_fill (ohci, info, data, data_len, dev, cnt++, urb); | |
935 | break; | |
3e326ece MK |
936 | } |
937 | if (urb->length != cnt) | |
938 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
939 | } | |
940 | ||
941 | /*-------------------------------------------------------------------------* | |
942 | * Done List handling functions | |
943 | *-------------------------------------------------------------------------*/ | |
944 | ||
945 | ||
946 | /* calculate the transfer length and update the urb */ | |
947 | ||
948 | static void dl_transfer_length(td_t * td) | |
949 | { | |
950 | __u32 tdINFO, tdBE, tdCBP; | |
4dae14ce | 951 | urb_priv_t *lurb_priv = td->ed->purb; |
3e326ece MK |
952 | |
953 | tdINFO = m32_swap (td->hwINFO); | |
954 | tdBE = m32_swap (td->hwBE); | |
955 | tdCBP = m32_swap (td->hwCBP); | |
956 | ||
957 | ||
958 | if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && | |
959 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { | |
960 | if (tdBE != 0) { | |
961 | if (td->hwCBP == 0) | |
962 | lurb_priv->actual_length += tdBE - td->data + 1; | |
963 | else | |
964 | lurb_priv->actual_length += tdCBP - td->data; | |
965 | } | |
966 | } | |
967 | } | |
968 | ||
969 | /*-------------------------------------------------------------------------*/ | |
970 | ||
971 | /* replies to the request have to be on a FIFO basis so | |
972 | * we reverse the reversed done-list */ | |
973 | ||
974 | static td_t * dl_reverse_done_list (ohci_t *ohci) | |
975 | { | |
976 | __u32 td_list_hc; | |
977 | td_t *td_rev = NULL; | |
978 | td_t *td_list = NULL; | |
979 | urb_priv_t *lurb_priv = NULL; | |
980 | ||
981 | td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; | |
982 | ohci->hcca->done_head = 0; | |
983 | ||
984 | while (td_list_hc) { | |
985 | td_list = (td_t *)td_list_hc; | |
986 | ||
987 | if (TD_CC_GET (m32_swap (td_list->hwINFO))) { | |
4dae14ce | 988 | lurb_priv = td_list->ed->purb; |
3e326ece MK |
989 | dbg(" USB-error/status: %x : %p", |
990 | TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); | |
991 | if (td_list->ed->hwHeadP & m32_swap (0x1)) { | |
992 | if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { | |
993 | td_list->ed->hwHeadP = | |
994 | (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | | |
995 | (td_list->ed->hwHeadP & m32_swap (0x2)); | |
996 | lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; | |
997 | } else | |
998 | td_list->ed->hwHeadP &= m32_swap (0xfffffff2); | |
999 | } | |
53e336e9 MK |
1000 | #ifdef CONFIG_MPC5200 |
1001 | td_list->hwNextTD = 0; | |
1002 | #endif | |
3e326ece MK |
1003 | } |
1004 | ||
1005 | td_list->next_dl_td = td_rev; | |
1006 | td_rev = td_list; | |
1007 | td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; | |
1008 | } | |
1009 | return td_list; | |
1010 | } | |
1011 | ||
1012 | /*-------------------------------------------------------------------------*/ | |
1013 | ||
1014 | /* td done list */ | |
1015 | static int dl_done_list (ohci_t *ohci, td_t *td_list) | |
1016 | { | |
1017 | td_t *td_list_next = NULL; | |
1018 | ed_t *ed; | |
1019 | int cc = 0; | |
1020 | int stat = 0; | |
1021 | /* urb_t *urb; */ | |
1022 | urb_priv_t *lurb_priv; | |
1023 | __u32 tdINFO, edHeadP, edTailP; | |
1024 | ||
1025 | while (td_list) { | |
1026 | td_list_next = td_list->next_dl_td; | |
1027 | ||
3e326ece MK |
1028 | tdINFO = m32_swap (td_list->hwINFO); |
1029 | ||
1030 | ed = td_list->ed; | |
4dae14ce | 1031 | lurb_priv = ed->purb; |
3e326ece MK |
1032 | |
1033 | dl_transfer_length(td_list); | |
1034 | ||
1035 | /* error code of transfer */ | |
1036 | cc = TD_CC_GET (tdINFO); | |
1037 | if (cc != 0) { | |
1038 | dbg("ConditionCode %#x", cc); | |
1039 | stat = cc_to_error[cc]; | |
1040 | } | |
ae79f606 | 1041 | |
ddf83a2f MK |
1042 | /* see if this done list makes for all TD's of current URB, |
1043 | * and mark the URB finished if so */ | |
1044 | if (++(lurb_priv->td_cnt) == lurb_priv->length) { | |
ae3b770e MK |
1045 | #if 1 |
1046 | if ((ed->state & (ED_OPER | ED_UNLINK)) && | |
1047 | (lurb_priv->state != URB_DEL)) | |
1048 | #else | |
ddf83a2f | 1049 | if ((ed->state & (ED_OPER | ED_UNLINK))) |
4dae14ce ZW |
1050 | #endif |
1051 | lurb_priv->finished = sohci_return_job(ohci, | |
1052 | lurb_priv); | |
ddf83a2f MK |
1053 | else |
1054 | dbg("dl_done_list: strange.., ED state %x, ed->state\n"); | |
1055 | } else | |
1056 | dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt, | |
1057 | lurb_priv->length); | |
4dae14ce ZW |
1058 | if (ed->state != ED_NEW && |
1059 | (usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) { | |
3e326ece MK |
1060 | edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; |
1061 | edTailP = m32_swap (ed->hwTailP); | |
1062 | ||
1063 | /* unlink eds if they are not busy */ | |
1064 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
1065 | ep_unlink (ohci, ed); | |
1066 | } | |
1067 | ||
1068 | td_list = td_list_next; | |
1069 | } | |
1070 | return stat; | |
1071 | } | |
1072 | ||
1073 | /*-------------------------------------------------------------------------* | |
1074 | * Virtual Root Hub | |
1075 | *-------------------------------------------------------------------------*/ | |
1076 | ||
1077 | /* Device descriptor */ | |
1078 | static __u8 root_hub_dev_des[] = | |
1079 | { | |
1080 | 0x12, /* __u8 bLength; */ | |
1081 | 0x01, /* __u8 bDescriptorType; Device */ | |
1082 | 0x10, /* __u16 bcdUSB; v1.1 */ | |
1083 | 0x01, | |
1084 | 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ | |
1085 | 0x00, /* __u8 bDeviceSubClass; */ | |
1086 | 0x00, /* __u8 bDeviceProtocol; */ | |
1087 | 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ | |
1088 | 0x00, /* __u16 idVendor; */ | |
1089 | 0x00, | |
1090 | 0x00, /* __u16 idProduct; */ | |
1091 | 0x00, | |
1092 | 0x00, /* __u16 bcdDevice; */ | |
1093 | 0x00, | |
1094 | 0x00, /* __u8 iManufacturer; */ | |
1095 | 0x01, /* __u8 iProduct; */ | |
1096 | 0x00, /* __u8 iSerialNumber; */ | |
1097 | 0x01 /* __u8 bNumConfigurations; */ | |
1098 | }; | |
1099 | ||
1100 | ||
1101 | /* Configuration descriptor */ | |
1102 | static __u8 root_hub_config_des[] = | |
1103 | { | |
1104 | 0x09, /* __u8 bLength; */ | |
1105 | 0x02, /* __u8 bDescriptorType; Configuration */ | |
1106 | 0x19, /* __u16 wTotalLength; */ | |
1107 | 0x00, | |
1108 | 0x01, /* __u8 bNumInterfaces; */ | |
1109 | 0x01, /* __u8 bConfigurationValue; */ | |
1110 | 0x00, /* __u8 iConfiguration; */ | |
1111 | 0x40, /* __u8 bmAttributes; | |
1112 | Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ | |
1113 | 0x00, /* __u8 MaxPower; */ | |
1114 | ||
1115 | /* interface */ | |
1116 | 0x09, /* __u8 if_bLength; */ | |
1117 | 0x04, /* __u8 if_bDescriptorType; Interface */ | |
1118 | 0x00, /* __u8 if_bInterfaceNumber; */ | |
1119 | 0x00, /* __u8 if_bAlternateSetting; */ | |
1120 | 0x01, /* __u8 if_bNumEndpoints; */ | |
1121 | 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ | |
1122 | 0x00, /* __u8 if_bInterfaceSubClass; */ | |
1123 | 0x00, /* __u8 if_bInterfaceProtocol; */ | |
1124 | 0x00, /* __u8 if_iInterface; */ | |
1125 | ||
1126 | /* endpoint */ | |
1127 | 0x07, /* __u8 ep_bLength; */ | |
1128 | 0x05, /* __u8 ep_bDescriptorType; Endpoint */ | |
1129 | 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ | |
1130 | 0x03, /* __u8 ep_bmAttributes; Interrupt */ | |
1131 | 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ | |
1132 | 0x00, | |
1133 | 0xff /* __u8 ep_bInterval; 255 ms */ | |
1134 | }; | |
1135 | ||
1136 | static unsigned char root_hub_str_index0[] = | |
1137 | { | |
1138 | 0x04, /* __u8 bLength; */ | |
1139 | 0x03, /* __u8 bDescriptorType; String-descriptor */ | |
1140 | 0x09, /* __u8 lang ID */ | |
1141 | 0x04, /* __u8 lang ID */ | |
1142 | }; | |
1143 | ||
1144 | static unsigned char root_hub_str_index1[] = | |
1145 | { | |
1146 | 28, /* __u8 bLength; */ | |
1147 | 0x03, /* __u8 bDescriptorType; String-descriptor */ | |
1148 | 'O', /* __u8 Unicode */ | |
1149 | 0, /* __u8 Unicode */ | |
1150 | 'H', /* __u8 Unicode */ | |
1151 | 0, /* __u8 Unicode */ | |
1152 | 'C', /* __u8 Unicode */ | |
1153 | 0, /* __u8 Unicode */ | |
1154 | 'I', /* __u8 Unicode */ | |
1155 | 0, /* __u8 Unicode */ | |
1156 | ' ', /* __u8 Unicode */ | |
1157 | 0, /* __u8 Unicode */ | |
1158 | 'R', /* __u8 Unicode */ | |
1159 | 0, /* __u8 Unicode */ | |
1160 | 'o', /* __u8 Unicode */ | |
1161 | 0, /* __u8 Unicode */ | |
1162 | 'o', /* __u8 Unicode */ | |
1163 | 0, /* __u8 Unicode */ | |
1164 | 't', /* __u8 Unicode */ | |
1165 | 0, /* __u8 Unicode */ | |
1166 | ' ', /* __u8 Unicode */ | |
1167 | 0, /* __u8 Unicode */ | |
1168 | 'H', /* __u8 Unicode */ | |
1169 | 0, /* __u8 Unicode */ | |
1170 | 'u', /* __u8 Unicode */ | |
1171 | 0, /* __u8 Unicode */ | |
1172 | 'b', /* __u8 Unicode */ | |
1173 | 0, /* __u8 Unicode */ | |
1174 | }; | |
1175 | ||
1176 | /* Hub class-specific descriptor is constructed dynamically */ | |
1177 | ||
1178 | ||
1179 | /*-------------------------------------------------------------------------*/ | |
1180 | ||
1181 | #define OK(x) len = (x); break | |
1182 | #ifdef DEBUG | |
1183 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} | |
1184 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} | |
1185 | #else | |
1186 | #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) | |
1187 | #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) | |
1188 | #endif | |
1189 | #define RD_RH_STAT roothub_status(&gohci) | |
1190 | #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) | |
1191 | ||
1192 | /* request to virtual root hub */ | |
1193 | ||
1194 | int rh_check_port_status(ohci_t *controller) | |
1195 | { | |
1196 | __u32 temp, ndp, i; | |
1197 | int res; | |
1198 | ||
1199 | res = -1; | |
1200 | temp = roothub_a (controller); | |
1201 | ndp = (temp & RH_A_NDP); | |
1202 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1203 | ndp = (ndp == 2) ? 1:0; | |
1204 | #endif | |
1205 | for (i = 0; i < ndp; i++) { | |
1206 | temp = roothub_portstatus (controller, i); | |
1207 | /* check for a device disconnect */ | |
1208 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
1209 | (RH_PS_PESC | RH_PS_CSC)) && | |
1210 | ((temp & RH_PS_CCS) == 0)) { | |
1211 | res = i; | |
1212 | break; | |
1213 | } | |
1214 | } | |
1215 | return res; | |
1216 | } | |
1217 | ||
1218 | static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, | |
1219 | void *buffer, int transfer_len, struct devrequest *cmd) | |
1220 | { | |
1221 | void * data = buffer; | |
1222 | int leni = transfer_len; | |
1223 | int len = 0; | |
1224 | int stat = 0; | |
1225 | __u32 datab[4]; | |
1226 | __u8 *data_buf = (__u8 *)datab; | |
1227 | __u16 bmRType_bReq; | |
1228 | __u16 wValue; | |
1229 | __u16 wIndex; | |
1230 | __u16 wLength; | |
1231 | ||
1232 | #ifdef DEBUG | |
4dae14ce | 1233 | pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); |
3e326ece MK |
1234 | #else |
1235 | wait_ms(1); | |
1236 | #endif | |
1237 | if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { | |
1238 | info("Root-Hub submit IRQ: NOT implemented"); | |
1239 | return 0; | |
1240 | } | |
1241 | ||
1242 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
ae3b770e MK |
1243 | #if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) |
1244 | wValue = __swap_16(cmd->value); | |
1245 | wIndex = __swap_16(cmd->index); | |
1246 | wLength = __swap_16(cmd->length); | |
1247 | #else | |
3e326ece MK |
1248 | wValue = m16_swap (cmd->value); |
1249 | wIndex = m16_swap (cmd->index); | |
1250 | wLength = m16_swap (cmd->length); | |
ae3b770e | 1251 | #endif /* CONFIG_440EP || CONFIG_MPC5200 */ |
3e326ece MK |
1252 | |
1253 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
1254 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); | |
1255 | ||
1256 | switch (bmRType_bReq) { | |
1257 | /* Request Destination: | |
1258 | without flags: Device, | |
1259 | RH_INTERFACE: interface, | |
1260 | RH_ENDPOINT: endpoint, | |
1261 | RH_CLASS means HUB here, | |
1262 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1263 | */ | |
1264 | ||
ae3b770e MK |
1265 | #if defined(CONFIG_440EP) || defined(CONFIG_MPC5200) |
1266 | case RH_GET_STATUS: | |
1267 | *(__u16 *) data_buf = __swap_16(1); OK (2); | |
1268 | case RH_GET_STATUS | RH_INTERFACE: | |
1269 | *(__u16 *) data_buf = __swap_16(0); OK (2); | |
1270 | case RH_GET_STATUS | RH_ENDPOINT: | |
1271 | *(__u16 *) data_buf = __swap_16(0); OK (2); | |
1272 | case RH_GET_STATUS | RH_CLASS: | |
1273 | *(__u32 *) data_buf = __swap_32( | |
1274 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); | |
1275 | OK (4); | |
1276 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: | |
1277 | *(__u32 *) data_buf = __swap_32(RD_RH_PORTSTAT); OK (4); | |
1278 | #else | |
3e326ece MK |
1279 | case RH_GET_STATUS: |
1280 | *(__u16 *) data_buf = m16_swap (1); OK (2); | |
1281 | case RH_GET_STATUS | RH_INTERFACE: | |
1282 | *(__u16 *) data_buf = m16_swap (0); OK (2); | |
1283 | case RH_GET_STATUS | RH_ENDPOINT: | |
1284 | *(__u16 *) data_buf = m16_swap (0); OK (2); | |
1285 | case RH_GET_STATUS | RH_CLASS: | |
1286 | *(__u32 *) data_buf = m32_swap ( | |
1287 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); | |
1288 | OK (4); | |
1289 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: | |
1290 | *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); | |
ae3b770e | 1291 | #endif /* CONFIG_440EP || CONFIG_MPC5200 */ |
3e326ece MK |
1292 | |
1293 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1294 | switch (wValue) { | |
1295 | case (RH_ENDPOINT_STALL): OK (0); | |
1296 | } | |
1297 | break; | |
1298 | ||
1299 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1300 | switch (wValue) { | |
1301 | case RH_C_HUB_LOCAL_POWER: | |
1302 | OK(0); | |
1303 | case (RH_C_HUB_OVER_CURRENT): | |
1304 | WR_RH_STAT(RH_HS_OCIC); OK (0); | |
1305 | } | |
1306 | break; | |
1307 | ||
1308 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1309 | switch (wValue) { | |
1310 | case (RH_PORT_ENABLE): | |
1311 | WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); | |
1312 | case (RH_PORT_SUSPEND): | |
1313 | WR_RH_PORTSTAT (RH_PS_POCI); OK (0); | |
1314 | case (RH_PORT_POWER): | |
1315 | WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); | |
1316 | case (RH_C_PORT_CONNECTION): | |
1317 | WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); | |
1318 | case (RH_C_PORT_ENABLE): | |
1319 | WR_RH_PORTSTAT (RH_PS_PESC); OK (0); | |
1320 | case (RH_C_PORT_SUSPEND): | |
1321 | WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); | |
1322 | case (RH_C_PORT_OVER_CURRENT): | |
1323 | WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); | |
1324 | case (RH_C_PORT_RESET): | |
1325 | WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); | |
1326 | } | |
1327 | break; | |
1328 | ||
1329 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1330 | switch (wValue) { | |
1331 | case (RH_PORT_SUSPEND): | |
1332 | WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); | |
1333 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1334 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1335 | WR_RH_PORTSTAT (RH_PS_PRS); | |
1336 | OK (0); | |
1337 | case (RH_PORT_POWER): | |
d98c0885 RG |
1338 | WR_RH_PORTSTAT (RH_PS_PPS ); |
1339 | wait_ms(100); | |
1340 | OK (0); | |
3e326ece MK |
1341 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ |
1342 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1343 | WR_RH_PORTSTAT (RH_PS_PES ); | |
1344 | OK (0); | |
1345 | } | |
1346 | break; | |
1347 | ||
1348 | case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); | |
1349 | ||
1350 | case RH_GET_DESCRIPTOR: | |
1351 | switch ((wValue & 0xff00) >> 8) { | |
1352 | case (0x01): /* device descriptor */ | |
1353 | len = min_t(unsigned int, | |
1354 | leni, | |
1355 | min_t(unsigned int, | |
1356 | sizeof (root_hub_dev_des), | |
1357 | wLength)); | |
1358 | data_buf = root_hub_dev_des; OK(len); | |
1359 | case (0x02): /* configuration descriptor */ | |
1360 | len = min_t(unsigned int, | |
1361 | leni, | |
1362 | min_t(unsigned int, | |
1363 | sizeof (root_hub_config_des), | |
1364 | wLength)); | |
1365 | data_buf = root_hub_config_des; OK(len); | |
1366 | case (0x03): /* string descriptors */ | |
1367 | if(wValue==0x0300) { | |
1368 | len = min_t(unsigned int, | |
1369 | leni, | |
1370 | min_t(unsigned int, | |
1371 | sizeof (root_hub_str_index0), | |
1372 | wLength)); | |
1373 | data_buf = root_hub_str_index0; | |
1374 | OK(len); | |
1375 | } | |
1376 | if(wValue==0x0301) { | |
1377 | len = min_t(unsigned int, | |
1378 | leni, | |
1379 | min_t(unsigned int, | |
1380 | sizeof (root_hub_str_index1), | |
1381 | wLength)); | |
1382 | data_buf = root_hub_str_index1; | |
1383 | OK(len); | |
1384 | } | |
1385 | default: | |
1386 | stat = USB_ST_STALLED; | |
1387 | } | |
1388 | break; | |
1389 | ||
1390 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
1391 | { | |
1392 | __u32 temp = roothub_a (&gohci); | |
1393 | ||
1394 | data_buf [0] = 9; /* min length; */ | |
1395 | data_buf [1] = 0x29; | |
1396 | data_buf [2] = temp & RH_A_NDP; | |
1397 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1398 | data_buf [2] = (data_buf [2] == 2) ? 1:0; | |
1399 | #endif | |
3e326ece MK |
1400 | data_buf [3] = 0; |
1401 | if (temp & RH_A_PSM) /* per-port power switching? */ | |
1402 | data_buf [3] |= 0x1; | |
1403 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ | |
1404 | data_buf [3] |= 0x10; | |
3e326ece MK |
1405 | else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ |
1406 | data_buf [3] |= 0x8; | |
3e326ece MK |
1407 | |
1408 | /* corresponds to data_buf[4-7] */ | |
1409 | datab [1] = 0; | |
1410 | data_buf [5] = (temp & RH_A_POTPGT) >> 24; | |
1411 | temp = roothub_b (&gohci); | |
1412 | data_buf [7] = temp & RH_B_DR; | |
1413 | if (data_buf [2] < 7) { | |
1414 | data_buf [8] = 0xff; | |
1415 | } else { | |
1416 | data_buf [0] += 2; | |
1417 | data_buf [8] = (temp & RH_B_DR) >> 8; | |
1418 | data_buf [10] = data_buf [9] = 0xff; | |
1419 | } | |
1420 | ||
1421 | len = min_t(unsigned int, leni, | |
ddf83a2f | 1422 | min_t(unsigned int, data_buf [0], wLength)); |
3e326ece MK |
1423 | OK (len); |
1424 | } | |
1425 | ||
1426 | case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); | |
1427 | ||
1428 | case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); | |
1429 | ||
1430 | default: | |
1431 | dbg ("unsupported root hub command"); | |
1432 | stat = USB_ST_STALLED; | |
1433 | } | |
1434 | ||
1435 | #ifdef DEBUG | |
1436 | ohci_dump_roothub (&gohci, 1); | |
1437 | #else | |
1438 | wait_ms(1); | |
1439 | #endif | |
1440 | ||
1441 | len = min_t(int, len, leni); | |
1442 | if (data != data_buf) | |
1443 | memcpy (data, data_buf, len); | |
1444 | dev->act_len = len; | |
1445 | dev->status = stat; | |
1446 | ||
1447 | #ifdef DEBUG | |
4dae14ce | 1448 | pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); |
3e326ece MK |
1449 | #else |
1450 | wait_ms(1); | |
1451 | #endif | |
1452 | ||
1453 | return stat; | |
1454 | } | |
1455 | ||
1456 | /*-------------------------------------------------------------------------*/ | |
1457 | ||
1458 | /* common code for handling submit messages - used for all but root hub */ | |
1459 | /* accesses. */ | |
1460 | int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1461 | int transfer_len, struct devrequest *setup, int interval) | |
1462 | { | |
1463 | int stat = 0; | |
1464 | int maxsize = usb_maxpacket(dev, pipe); | |
1465 | int timeout; | |
4dae14ce ZW |
1466 | urb_priv_t *urb; |
1467 | ||
1468 | urb = malloc(sizeof(urb_priv_t)); | |
1469 | memset(urb, 0, sizeof(urb_priv_t)); | |
1470 | ||
1471 | urb->dev = dev; | |
1472 | urb->pipe = pipe; | |
1473 | urb->transfer_buffer = buffer; | |
1474 | urb->transfer_buffer_length = transfer_len; | |
1475 | urb->interval = interval; | |
3e326ece MK |
1476 | |
1477 | /* device pulled? Shortcut the action. */ | |
1478 | if (devgone == dev) { | |
1479 | dev->status = USB_ST_CRC_ERR; | |
1480 | return 0; | |
1481 | } | |
1482 | ||
1483 | #ifdef DEBUG | |
4dae14ce ZW |
1484 | urb->actual_length = 0; |
1485 | pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); | |
3e326ece MK |
1486 | #else |
1487 | wait_ms(1); | |
1488 | #endif | |
1489 | if (!maxsize) { | |
1490 | err("submit_common_message: pipesize for pipe %lx is zero", | |
1491 | pipe); | |
1492 | return -1; | |
1493 | } | |
1494 | ||
4dae14ce | 1495 | if (sohci_submit_job(urb, setup) < 0) { |
3e326ece MK |
1496 | err("sohci_submit_job failed"); |
1497 | return -1; | |
1498 | } | |
1499 | ||
ae3b770e | 1500 | #if 0 |
3e326ece MK |
1501 | wait_ms(10); |
1502 | /* ohci_dump_status(&gohci); */ | |
ae3b770e | 1503 | #endif |
3e326ece MK |
1504 | |
1505 | /* allow more time for a BULK device to react - some are slow */ | |
1506 | #define BULK_TO 5000 /* timeout in milliseconds */ | |
1507 | if (usb_pipetype (pipe) == PIPE_BULK) | |
1508 | timeout = BULK_TO; | |
1509 | else | |
1510 | timeout = 100; | |
1511 | ||
1512 | /* wait for it to complete */ | |
1513 | for (;;) { | |
1514 | /* check whether the controller is done */ | |
1515 | stat = hc_interrupt(); | |
1516 | if (stat < 0) { | |
1517 | stat = USB_ST_CRC_ERR; | |
1518 | break; | |
1519 | } | |
ddf83a2f | 1520 | |
ddf83a2f MK |
1521 | /* NOTE: since we are not interrupt driven in U-Boot and always |
1522 | * handle only one URB at a time, we cannot assume the | |
1523 | * transaction finished on the first successful return from | |
1524 | * hc_interrupt().. unless the flag for current URB is set, | |
1525 | * meaning that all TD's to/from device got actually | |
1526 | * transferred and processed. If the current URB is not | |
1527 | * finished we need to re-iterate this loop so as | |
1528 | * hc_interrupt() gets called again as there needs to be some | |
1529 | * more TD's to process still */ | |
4dae14ce | 1530 | if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { |
3e326ece MK |
1531 | /* 0xff is returned for an SF-interrupt */ |
1532 | break; | |
1533 | } | |
ddf83a2f | 1534 | |
3e326ece MK |
1535 | if (--timeout) { |
1536 | wait_ms(1); | |
4dae14ce ZW |
1537 | if (!urb->finished) |
1538 | dbg("\%"); | |
1539 | ||
3e326ece MK |
1540 | } else { |
1541 | err("CTL:TIMEOUT "); | |
ddf83a2f | 1542 | dbg("submit_common_msg: TO status %x\n", stat); |
4dae14ce | 1543 | urb->finished = 1; |
3e326ece MK |
1544 | stat = USB_ST_CRC_ERR; |
1545 | break; | |
1546 | } | |
1547 | } | |
3e326ece MK |
1548 | |
1549 | dev->status = stat; | |
1550 | dev->act_len = transfer_len; | |
1551 | ||
1552 | #ifdef DEBUG | |
4dae14ce | 1553 | pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); |
3e326ece MK |
1554 | #else |
1555 | wait_ms(1); | |
1556 | #endif | |
1557 | ||
1558 | /* free TDs in urb_priv */ | |
4dae14ce ZW |
1559 | if (usb_pipetype (pipe) != PIPE_INTERRUPT) |
1560 | urb_free_priv (urb); | |
3e326ece MK |
1561 | return 0; |
1562 | } | |
1563 | ||
1564 | /* submit routines called from usb.c */ | |
1565 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1566 | int transfer_len) | |
1567 | { | |
1568 | info("submit_bulk_msg"); | |
1569 | return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); | |
1570 | } | |
1571 | ||
1572 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1573 | int transfer_len, struct devrequest *setup) | |
1574 | { | |
1575 | int maxsize = usb_maxpacket(dev, pipe); | |
1576 | ||
1577 | info("submit_control_msg"); | |
1578 | #ifdef DEBUG | |
4dae14ce | 1579 | pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); |
3e326ece MK |
1580 | #else |
1581 | wait_ms(1); | |
1582 | #endif | |
1583 | if (!maxsize) { | |
1584 | err("submit_control_message: pipesize for pipe %lx is zero", | |
1585 | pipe); | |
1586 | return -1; | |
1587 | } | |
1588 | if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { | |
1589 | gohci.rh.dev = dev; | |
1590 | /* root hub - redirect */ | |
1591 | return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, | |
1592 | setup); | |
1593 | } | |
1594 | ||
1595 | return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); | |
1596 | } | |
1597 | ||
1598 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1599 | int transfer_len, int interval) | |
1600 | { | |
1601 | info("submit_int_msg"); | |
4dae14ce ZW |
1602 | return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, |
1603 | interval); | |
3e326ece MK |
1604 | } |
1605 | ||
1606 | /*-------------------------------------------------------------------------* | |
1607 | * HC functions | |
1608 | *-------------------------------------------------------------------------*/ | |
1609 | ||
1610 | /* reset the HC and BUS */ | |
1611 | ||
1612 | static int hc_reset (ohci_t *ohci) | |
1613 | { | |
1614 | int timeout = 30; | |
1615 | int smm_timeout = 50; /* 0,5 sec */ | |
1616 | ||
1617 | dbg("%s\n", __FUNCTION__); | |
1618 | ||
1619 | if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ | |
1620 | writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ | |
1621 | info("USB HC TakeOver from SMM"); | |
1622 | while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { | |
1623 | wait_ms (10); | |
1624 | if (--smm_timeout == 0) { | |
1625 | err("USB HC TakeOver failed!"); | |
1626 | return -1; | |
1627 | } | |
1628 | } | |
1629 | } | |
1630 | ||
1631 | /* Disable HC interrupts */ | |
1632 | writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
1633 | ||
1634 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", | |
1635 | ohci->slot_name, | |
1636 | readl(&ohci->regs->control)); | |
1637 | ||
1638 | /* Reset USB (needed by some controllers) */ | |
53e336e9 MK |
1639 | ohci->hc_control = 0; |
1640 | writel (ohci->hc_control, &ohci->regs->control); | |
3e326ece MK |
1641 | |
1642 | /* HC Reset requires max 10 us delay */ | |
1643 | writel (OHCI_HCR, &ohci->regs->cmdstatus); | |
1644 | while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
1645 | if (--timeout == 0) { | |
1646 | err("USB HC reset timed out!"); | |
1647 | return -1; | |
1648 | } | |
1649 | udelay (1); | |
1650 | } | |
1651 | return 0; | |
1652 | } | |
1653 | ||
1654 | /*-------------------------------------------------------------------------*/ | |
1655 | ||
1656 | /* Start an OHCI controller, set the BUS operational | |
1657 | * enable interrupts | |
1658 | * connect the virtual root hub */ | |
1659 | ||
1660 | static int hc_start (ohci_t * ohci) | |
1661 | { | |
1662 | __u32 mask; | |
1663 | unsigned int fminterval; | |
1664 | ||
1665 | ohci->disabled = 1; | |
1666 | ||
1667 | /* Tell the controller where the control and bulk lists are | |
1668 | * The lists are empty now. */ | |
1669 | ||
1670 | writel (0, &ohci->regs->ed_controlhead); | |
1671 | writel (0, &ohci->regs->ed_bulkhead); | |
1672 | ||
1673 | writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ | |
1674 | ||
1675 | fminterval = 0x2edf; | |
1676 | writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); | |
1677 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); | |
1678 | writel (fminterval, &ohci->regs->fminterval); | |
1679 | writel (0x628, &ohci->regs->lsthresh); | |
1680 | ||
1681 | /* start controller operations */ | |
1682 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1683 | ohci->disabled = 0; | |
1684 | writel (ohci->hc_control, &ohci->regs->control); | |
1685 | ||
1686 | /* disable all interrupts */ | |
1687 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
1688 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | | |
1689 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
1690 | writel (mask, &ohci->regs->intrdisable); | |
1691 | /* clear all interrupts */ | |
1692 | mask &= ~OHCI_INTR_MIE; | |
1693 | writel (mask, &ohci->regs->intrstatus); | |
1694 | /* Choose the interrupts we care about now - but w/o MIE */ | |
1695 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
1696 | writel (mask, &ohci->regs->intrenable); | |
1697 | ||
1698 | #ifdef OHCI_USE_NPS | |
1699 | /* required for AMD-756 and some Mac platforms */ | |
1700 | writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, | |
1701 | &ohci->regs->roothub.a); | |
1702 | writel (RH_HS_LPSC, &ohci->regs->roothub.status); | |
1703 | #endif /* OHCI_USE_NPS */ | |
1704 | ||
1705 | #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) | |
1706 | /* POTPGT delay is bits 24-31, in 2 ms units. */ | |
1707 | mdelay ((roothub_a (ohci) >> 23) & 0x1fe); | |
1708 | ||
1709 | /* connect the virtual root hub */ | |
1710 | ohci->rh.devnum = 0; | |
1711 | ||
1712 | return 0; | |
1713 | } | |
1714 | ||
1715 | /*-------------------------------------------------------------------------*/ | |
1716 | ||
4dae14ce ZW |
1717 | /* Poll USB interrupt. */ |
1718 | void usb_event_poll(void) | |
1719 | { | |
1720 | hc_interrupt(); | |
1721 | } | |
1722 | ||
3e326ece MK |
1723 | /* an interrupt happens */ |
1724 | ||
ddf83a2f | 1725 | static int hc_interrupt (void) |
3e326ece MK |
1726 | { |
1727 | ohci_t *ohci = &gohci; | |
1728 | struct ohci_regs *regs = ohci->regs; | |
1729 | int ints; | |
1730 | int stat = -1; | |
1731 | ||
ddf83a2f MK |
1732 | if ((ohci->hcca->done_head != 0) && |
1733 | !(m32_swap (ohci->hcca->done_head) & 0x01)) { | |
1734 | ints = OHCI_INTR_WDH; | |
1735 | } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { | |
1736 | ohci->disabled++; | |
1737 | err ("%s device removed!", ohci->slot_name); | |
1738 | return -1; | |
1739 | } else if ((ints &= readl (®s->intrenable)) == 0) { | |
1740 | dbg("hc_interrupt: returning..\n"); | |
1741 | return 0xff; | |
1742 | } | |
ae79f606 | 1743 | |
3e326ece MK |
1744 | /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ |
1745 | ||
1746 | if (ints & OHCI_INTR_RHSC) { | |
1747 | got_rhsc = 1; | |
ddf83a2f | 1748 | stat = 0xff; |
3e326ece MK |
1749 | } |
1750 | ||
1751 | if (ints & OHCI_INTR_UE) { | |
1752 | ohci->disabled++; | |
1753 | err ("OHCI Unrecoverable Error, controller usb-%s disabled", | |
1754 | ohci->slot_name); | |
1755 | /* e.g. due to PCI Master/Target Abort */ | |
1756 | ||
1757 | #ifdef DEBUG | |
1758 | ohci_dump (ohci, 1); | |
1759 | #else | |
1760 | wait_ms(1); | |
1761 | #endif | |
1762 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1763 | /* Make some non-interrupt context restart the controller. */ | |
1764 | /* Count and limit the retries though; either hardware or */ | |
1765 | /* software errors can go forever... */ | |
1766 | hc_reset (ohci); | |
1767 | return -1; | |
1768 | } | |
1769 | ||
1770 | if (ints & OHCI_INTR_WDH) { | |
1771 | wait_ms(1); | |
1772 | writel (OHCI_INTR_WDH, ®s->intrdisable); | |
4dae14ce | 1773 | (void)readl (®s->intrdisable); /* flush */ |
3e326ece MK |
1774 | stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); |
1775 | writel (OHCI_INTR_WDH, ®s->intrenable); | |
4dae14ce | 1776 | (void)readl (®s->intrdisable); /* flush */ |
3e326ece MK |
1777 | } |
1778 | ||
1779 | if (ints & OHCI_INTR_SO) { | |
1780 | dbg("USB Schedule overrun\n"); | |
1781 | writel (OHCI_INTR_SO, ®s->intrenable); | |
1782 | stat = -1; | |
1783 | } | |
1784 | ||
1785 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1786 | if (ints & OHCI_INTR_SF) { | |
1787 | unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; | |
1788 | wait_ms(1); | |
1789 | writel (OHCI_INTR_SF, ®s->intrdisable); | |
1790 | if (ohci->ed_rm_list[frame] != NULL) | |
1791 | writel (OHCI_INTR_SF, ®s->intrenable); | |
1792 | stat = 0xff; | |
1793 | } | |
1794 | ||
1795 | writel (ints, ®s->intrstatus); | |
1796 | return stat; | |
1797 | } | |
1798 | ||
1799 | /*-------------------------------------------------------------------------*/ | |
1800 | ||
1801 | /*-------------------------------------------------------------------------*/ | |
1802 | ||
1803 | /* De-allocate all resources.. */ | |
1804 | ||
1805 | static void hc_release_ohci (ohci_t *ohci) | |
1806 | { | |
1807 | dbg ("USB HC release ohci usb-%s", ohci->slot_name); | |
1808 | ||
1809 | if (!ohci->disabled) | |
1810 | hc_reset (ohci); | |
1811 | } | |
1812 | ||
1813 | /*-------------------------------------------------------------------------*/ | |
1814 | ||
1815 | /* | |
1816 | * low level initalisation routine, called from usb.c | |
1817 | */ | |
1818 | static char ohci_inited = 0; | |
1819 | ||
1820 | int usb_lowlevel_init(void) | |
1821 | { | |
4dae14ce ZW |
1822 | #ifdef CONFIG_PCI_OHCI |
1823 | pci_dev_t pdev; | |
1824 | #endif | |
24e37645 | 1825 | |
ddf83a2f | 1826 | #ifdef CFG_USB_OHCI_CPU_INIT |
24e37645 MK |
1827 | /* cpu dependant init */ |
1828 | if(usb_cpu_init()) | |
3e326ece | 1829 | return -1; |
24e37645 | 1830 | #endif |
3e326ece | 1831 | |
ddf83a2f | 1832 | #ifdef CFG_USB_OHCI_BOARD_INIT |
24e37645 MK |
1833 | /* board dependant init */ |
1834 | if(usb_board_init()) | |
1835 | return -1; | |
1836 | #endif | |
3e326ece | 1837 | memset (&gohci, 0, sizeof (ohci_t)); |
3e326ece MK |
1838 | |
1839 | /* align the storage */ | |
1840 | if ((__u32)&ghcca[0] & 0xff) { | |
1841 | err("HCCA not aligned!!"); | |
1842 | return -1; | |
1843 | } | |
1844 | phcca = &ghcca[0]; | |
1845 | info("aligned ghcca %p", phcca); | |
1846 | memset(&ohci_dev, 0, sizeof(struct ohci_device)); | |
1847 | if ((__u32)&ohci_dev.ed[0] & 0x7) { | |
1848 | err("EDs not aligned!!"); | |
1849 | return -1; | |
1850 | } | |
1851 | memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); | |
1852 | if ((__u32)gtd & 0x7) { | |
1853 | err("TDs not aligned!!"); | |
1854 | return -1; | |
1855 | } | |
1856 | ptd = gtd; | |
1857 | gohci.hcca = phcca; | |
1858 | memset (phcca, 0, sizeof (struct ohci_hcca)); | |
1859 | ||
1860 | gohci.disabled = 1; | |
1861 | gohci.sleeping = 0; | |
1862 | gohci.irq = -1; | |
4dae14ce ZW |
1863 | #ifdef CONFIG_PCI_OHCI |
1864 | pdev = pci_find_devices(ohci_pci_ids, 0); | |
1865 | ||
1866 | if (pdev != -1) { | |
1867 | u16 vid, did; | |
1868 | u32 base; | |
1869 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); | |
1870 | pci_read_config_word(pdev, PCI_DEVICE_ID, &did); | |
1871 | printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", | |
1872 | vid, did, (pdev >> 16) & 0xff, | |
1873 | (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); | |
1874 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
1875 | printf("OHCI regs address 0x%08x\n", base); | |
1876 | gohci.regs = (struct ohci_regs *)base; | |
1877 | } else | |
1878 | return -1; | |
1879 | #else | |
24e37645 | 1880 | gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE; |
4dae14ce | 1881 | #endif |
3e326ece MK |
1882 | |
1883 | gohci.flags = 0; | |
301f1aa3 | 1884 | gohci.slot_name = CFG_USB_OHCI_SLOT_NAME; |
3e326ece MK |
1885 | |
1886 | if (hc_reset (&gohci) < 0) { | |
1887 | hc_release_ohci (&gohci); | |
1888 | err ("can't reset usb-%s", gohci.slot_name); | |
ddf83a2f | 1889 | #ifdef CFG_USB_OHCI_BOARD_INIT |
24e37645 | 1890 | /* board dependant cleanup */ |
ddf83a2f | 1891 | usb_board_init_fail(); |
24e37645 MK |
1892 | #endif |
1893 | ||
ddf83a2f | 1894 | #ifdef CFG_USB_OHCI_CPU_INIT |
24e37645 | 1895 | /* cpu dependant cleanup */ |
ddf83a2f | 1896 | usb_cpu_init_fail(); |
24e37645 | 1897 | #endif |
3e326ece MK |
1898 | return -1; |
1899 | } | |
1900 | ||
1901 | /* FIXME this is a second HC reset; why?? */ | |
1902 | /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); | |
1903 | wait_ms(10); */ | |
3e326ece MK |
1904 | if (hc_start (&gohci) < 0) { |
1905 | err ("can't start usb-%s", gohci.slot_name); | |
1906 | hc_release_ohci (&gohci); | |
1907 | /* Initialization failed */ | |
ddf83a2f | 1908 | #ifdef CFG_USB_OHCI_BOARD_INIT |
24e37645 MK |
1909 | /* board dependant cleanup */ |
1910 | usb_board_stop(); | |
1911 | #endif | |
1912 | ||
ddf83a2f | 1913 | #ifdef CFG_USB_OHCI_CPU_INIT |
24e37645 MK |
1914 | /* cpu dependant cleanup */ |
1915 | usb_cpu_stop(); | |
1916 | #endif | |
3e326ece MK |
1917 | return -1; |
1918 | } | |
1919 | ||
1920 | #ifdef DEBUG | |
1921 | ohci_dump (&gohci, 1); | |
1922 | #else | |
1923 | wait_ms(1); | |
1924 | #endif | |
1925 | ohci_inited = 1; | |
1926 | return 0; | |
1927 | } | |
1928 | ||
1929 | int usb_lowlevel_stop(void) | |
1930 | { | |
1931 | /* this gets called really early - before the controller has */ | |
1932 | /* even been initialized! */ | |
1933 | if (!ohci_inited) | |
1934 | return 0; | |
1935 | /* TODO release any interrupts, etc. */ | |
1936 | /* call hc_release_ohci() here ? */ | |
1937 | hc_reset (&gohci); | |
1938 | ||
ddf83a2f | 1939 | #ifdef CFG_USB_OHCI_BOARD_INIT |
3e326ece MK |
1940 | /* board dependant cleanup */ |
1941 | if(usb_board_stop()) | |
1942 | return -1; | |
24e37645 MK |
1943 | #endif |
1944 | ||
ddf83a2f | 1945 | #ifdef CFG_USB_OHCI_CPU_INIT |
24e37645 MK |
1946 | /* cpu dependant cleanup */ |
1947 | if(usb_cpu_stop()) | |
1948 | return -1; | |
1949 | #endif | |
3e326ece MK |
1950 | |
1951 | return 0; | |
1952 | } | |
7b59b3c7 | 1953 | #endif /* CONFIG_USB_OHCI_NEW */ |