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3072d30e | 1 | /* Discovery of auto-inc and auto-dec instructions. |
8e8f6434 | 2 | Copyright (C) 2006-2018 Free Software Foundation, Inc. |
3072d30e | 3 | Contributed by Kenneth Zadeck <zadeck@naturalbridge.com> |
48e1416a | 4 | |
3072d30e | 5 | This file is part of GCC. |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 9 | Software Foundation; either version 3, or (at your option) any later |
3072d30e | 10 | version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
3072d30e | 20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
9ef16211 | 24 | #include "backend.h" |
7c29e30e | 25 | #include "target.h" |
3072d30e | 26 | #include "rtl.h" |
7c29e30e | 27 | #include "tree.h" |
28 | #include "predict.h" | |
9ef16211 | 29 | #include "df.h" |
94ea8568 | 30 | #include "insn-config.h" |
ad7b10a2 | 31 | #include "memmodel.h" |
7c29e30e | 32 | #include "emit-rtl.h" |
33 | #include "recog.h" | |
7c29e30e | 34 | #include "cfgrtl.h" |
3072d30e | 35 | #include "expr.h" |
3072d30e | 36 | #include "tree-pass.h" |
3072d30e | 37 | #include "dbgcnt.h" |
397881d3 | 38 | #include "print-rtl.h" |
f21023fe | 39 | #include "valtrack.h" |
3072d30e | 40 | |
41 | /* This pass was originally removed from flow.c. However there is | |
42 | almost nothing that remains of that code. | |
43 | ||
44 | There are (4) basic forms that are matched: | |
45 | ||
ca4bb7ac | 46 | (1) FORM_PRE_ADD |
3072d30e | 47 | a <- b + c |
48 | ... | |
49 | *a | |
50 | ||
51 | becomes | |
52 | ||
53 | a <- b | |
54 | ... | |
55 | *(a += c) pre | |
ca4bb7ac | 56 | |
f21023fe | 57 | or, alternately, |
58 | ||
59 | a <- b + c | |
60 | ... | |
61 | *b | |
62 | ||
63 | becomes | |
64 | ||
65 | a <- b | |
66 | ... | |
67 | *(a += c) post | |
68 | ||
69 | This uses a post-add, but it's handled as FORM_PRE_ADD because | |
70 | the "increment" insn appears before the memory access. | |
71 | ||
ca4bb7ac | 72 | |
73 | (2) FORM_PRE_INC | |
3072d30e | 74 | a += c |
75 | ... | |
76 | *a | |
77 | ||
78 | becomes | |
79 | ||
f21023fe | 80 | ... |
3072d30e | 81 | *(a += c) pre |
ca4bb7ac | 82 | |
83 | ||
84 | (3) FORM_POST_ADD | |
3072d30e | 85 | *a |
86 | ... | |
87 | b <- a + c | |
88 | ||
48e1416a | 89 | (For this case to be true, b must not be assigned or used between |
ca4bb7ac | 90 | the *a and the assignment to b. B must also be a Pmode reg.) |
3072d30e | 91 | |
92 | becomes | |
93 | ||
94 | b <- a | |
3072d30e | 95 | *(b += c) post |
f21023fe | 96 | ... |
ca4bb7ac | 97 | |
98 | ||
99 | (4) FORM_POST_INC | |
3072d30e | 100 | *a |
101 | ... | |
102 | a <- a + c | |
103 | ||
104 | becomes | |
105 | ||
106 | *(a += c) post | |
f21023fe | 107 | ... |
108 | ||
3072d30e | 109 | |
110 | There are three types of values of c. | |
111 | ||
112 | 1) c is a constant equal to the width of the value being accessed by | |
113 | the pointer. This is useful for machines that have | |
114 | HAVE_PRE_INCREMENT, HAVE_POST_INCREMENT, HAVE_PRE_DECREMENT or | |
115 | HAVE_POST_DECREMENT defined. | |
116 | ||
bef304b8 | 117 | 2) c is a constant not equal to the width of the value being accessed |
3072d30e | 118 | by the pointer. This is useful for machines that have |
119 | HAVE_PRE_MODIFY_DISP, HAVE_POST_MODIFY_DISP defined. | |
120 | ||
48e1416a | 121 | 3) c is a register. This is useful for machines that have |
122 | HAVE_PRE_MODIFY_REG, HAVE_POST_MODIFY_REG | |
123 | ||
3072d30e | 124 | The is one special case: if a already had an offset equal to it +- |
125 | its width and that offset is equal to -c when the increment was | |
126 | before the ref or +c if the increment was after the ref, then if we | |
ca4bb7ac | 127 | can do the combination but switch the pre/post bit. */ |
3072d30e | 128 | |
3072d30e | 129 | |
130 | enum form | |
131 | { | |
132 | FORM_PRE_ADD, | |
133 | FORM_PRE_INC, | |
134 | FORM_POST_ADD, | |
135 | FORM_POST_INC, | |
136 | FORM_last | |
137 | }; | |
138 | ||
139 | /* The states of the second operands of mem refs and inc insns. If no | |
140 | second operand of the mem_ref was found, it is assumed to just be | |
141 | ZERO. SIZE is the size of the mode accessed in the memref. The | |
142 | ANY is used for constants that are not +-size or 0. REG is used if | |
143 | the forms are reg1 + reg2. */ | |
144 | ||
48e1416a | 145 | enum inc_state |
3072d30e | 146 | { |
147 | INC_ZERO, /* == 0 */ | |
148 | INC_NEG_SIZE, /* == +size */ | |
149 | INC_POS_SIZE, /* == -size */ | |
150 | INC_NEG_ANY, /* == some -constant */ | |
151 | INC_POS_ANY, /* == some +constant */ | |
152 | INC_REG, /* == some register */ | |
153 | INC_last | |
154 | }; | |
155 | ||
156 | /* The eight forms that pre/post inc/dec can take. */ | |
157 | enum gen_form | |
158 | { | |
159 | NOTHING, | |
160 | SIMPLE_PRE_INC, /* ++size */ | |
161 | SIMPLE_POST_INC, /* size++ */ | |
162 | SIMPLE_PRE_DEC, /* --size */ | |
163 | SIMPLE_POST_DEC, /* size-- */ | |
164 | DISP_PRE, /* ++con */ | |
165 | DISP_POST, /* con++ */ | |
166 | REG_PRE, /* ++reg */ | |
167 | REG_POST /* reg++ */ | |
168 | }; | |
169 | ||
170 | /* Tmp mem rtx for use in cost modeling. */ | |
171 | static rtx mem_tmp; | |
172 | ||
173 | static enum inc_state | |
7f4685e5 | 174 | set_inc_state (HOST_WIDE_INT val, poly_int64 size) |
3072d30e | 175 | { |
176 | if (val == 0) | |
177 | return INC_ZERO; | |
178 | if (val < 0) | |
7f4685e5 | 179 | return known_eq (val, -size) ? INC_NEG_SIZE : INC_NEG_ANY; |
3072d30e | 180 | else |
7f4685e5 | 181 | return known_eq (val, size) ? INC_POS_SIZE : INC_POS_ANY; |
3072d30e | 182 | } |
183 | ||
184 | /* The DECISION_TABLE that describes what form, if any, the increment | |
185 | or decrement will take. It is a three dimensional table. The first | |
186 | index is the type of constant or register found as the second | |
187 | operand of the inc insn. The second index is the type of constant | |
188 | or register found as the second operand of the memory reference (if | |
189 | no second operand exists, 0 is used). The third index is the form | |
190 | and location (relative to the mem reference) of inc insn. */ | |
191 | ||
192 | static bool initialized = false; | |
193 | static enum gen_form decision_table[INC_last][INC_last][FORM_last]; | |
194 | ||
195 | static void | |
196 | init_decision_table (void) | |
197 | { | |
198 | enum gen_form value; | |
199 | ||
200 | if (HAVE_PRE_INCREMENT || HAVE_PRE_MODIFY_DISP) | |
201 | { | |
202 | /* Prefer the simple form if both are available. */ | |
203 | value = (HAVE_PRE_INCREMENT) ? SIMPLE_PRE_INC : DISP_PRE; | |
204 | ||
205 | decision_table[INC_POS_SIZE][INC_ZERO][FORM_PRE_ADD] = value; | |
206 | decision_table[INC_POS_SIZE][INC_ZERO][FORM_PRE_INC] = value; | |
207 | ||
208 | decision_table[INC_POS_SIZE][INC_POS_SIZE][FORM_POST_ADD] = value; | |
209 | decision_table[INC_POS_SIZE][INC_POS_SIZE][FORM_POST_INC] = value; | |
210 | } | |
211 | ||
212 | if (HAVE_POST_INCREMENT || HAVE_POST_MODIFY_DISP) | |
213 | { | |
214 | /* Prefer the simple form if both are available. */ | |
215 | value = (HAVE_POST_INCREMENT) ? SIMPLE_POST_INC : DISP_POST; | |
216 | ||
217 | decision_table[INC_POS_SIZE][INC_ZERO][FORM_POST_ADD] = value; | |
218 | decision_table[INC_POS_SIZE][INC_ZERO][FORM_POST_INC] = value; | |
219 | ||
220 | decision_table[INC_POS_SIZE][INC_NEG_SIZE][FORM_PRE_ADD] = value; | |
221 | decision_table[INC_POS_SIZE][INC_NEG_SIZE][FORM_PRE_INC] = value; | |
222 | } | |
223 | ||
224 | if (HAVE_PRE_DECREMENT || HAVE_PRE_MODIFY_DISP) | |
225 | { | |
226 | /* Prefer the simple form if both are available. */ | |
227 | value = (HAVE_PRE_DECREMENT) ? SIMPLE_PRE_DEC : DISP_PRE; | |
228 | ||
229 | decision_table[INC_NEG_SIZE][INC_ZERO][FORM_PRE_ADD] = value; | |
230 | decision_table[INC_NEG_SIZE][INC_ZERO][FORM_PRE_INC] = value; | |
231 | ||
232 | decision_table[INC_NEG_SIZE][INC_NEG_SIZE][FORM_POST_ADD] = value; | |
233 | decision_table[INC_NEG_SIZE][INC_NEG_SIZE][FORM_POST_INC] = value; | |
234 | } | |
235 | ||
236 | if (HAVE_POST_DECREMENT || HAVE_POST_MODIFY_DISP) | |
237 | { | |
238 | /* Prefer the simple form if both are available. */ | |
239 | value = (HAVE_POST_DECREMENT) ? SIMPLE_POST_DEC : DISP_POST; | |
240 | ||
241 | decision_table[INC_NEG_SIZE][INC_ZERO][FORM_POST_ADD] = value; | |
242 | decision_table[INC_NEG_SIZE][INC_ZERO][FORM_POST_INC] = value; | |
243 | ||
244 | decision_table[INC_NEG_SIZE][INC_POS_SIZE][FORM_PRE_ADD] = value; | |
245 | decision_table[INC_NEG_SIZE][INC_POS_SIZE][FORM_PRE_INC] = value; | |
246 | } | |
247 | ||
248 | if (HAVE_PRE_MODIFY_DISP) | |
249 | { | |
250 | decision_table[INC_POS_ANY][INC_ZERO][FORM_PRE_ADD] = DISP_PRE; | |
251 | decision_table[INC_POS_ANY][INC_ZERO][FORM_PRE_INC] = DISP_PRE; | |
252 | ||
253 | decision_table[INC_POS_ANY][INC_POS_ANY][FORM_POST_ADD] = DISP_PRE; | |
254 | decision_table[INC_POS_ANY][INC_POS_ANY][FORM_POST_INC] = DISP_PRE; | |
255 | ||
256 | decision_table[INC_NEG_ANY][INC_ZERO][FORM_PRE_ADD] = DISP_PRE; | |
257 | decision_table[INC_NEG_ANY][INC_ZERO][FORM_PRE_INC] = DISP_PRE; | |
258 | ||
259 | decision_table[INC_NEG_ANY][INC_NEG_ANY][FORM_POST_ADD] = DISP_PRE; | |
260 | decision_table[INC_NEG_ANY][INC_NEG_ANY][FORM_POST_INC] = DISP_PRE; | |
261 | } | |
262 | ||
263 | if (HAVE_POST_MODIFY_DISP) | |
264 | { | |
265 | decision_table[INC_POS_ANY][INC_ZERO][FORM_POST_ADD] = DISP_POST; | |
266 | decision_table[INC_POS_ANY][INC_ZERO][FORM_POST_INC] = DISP_POST; | |
267 | ||
268 | decision_table[INC_POS_ANY][INC_NEG_ANY][FORM_PRE_ADD] = DISP_POST; | |
269 | decision_table[INC_POS_ANY][INC_NEG_ANY][FORM_PRE_INC] = DISP_POST; | |
270 | ||
271 | decision_table[INC_NEG_ANY][INC_ZERO][FORM_POST_ADD] = DISP_POST; | |
272 | decision_table[INC_NEG_ANY][INC_ZERO][FORM_POST_INC] = DISP_POST; | |
273 | ||
274 | decision_table[INC_NEG_ANY][INC_POS_ANY][FORM_PRE_ADD] = DISP_POST; | |
275 | decision_table[INC_NEG_ANY][INC_POS_ANY][FORM_PRE_INC] = DISP_POST; | |
276 | } | |
277 | ||
278 | /* This is much simpler than the other cases because we do not look | |
279 | for the reg1-reg2 case. Note that we do not have a INC_POS_REG | |
280 | and INC_NEG_REG states. Most of the use of such states would be | |
281 | on a target that had an R1 - R2 update address form. | |
282 | ||
283 | There is the remote possibility that you could also catch a = a + | |
284 | b; *(a - b) as a postdecrement of (a + b). However, it is | |
285 | unclear if *(a - b) would ever be generated on a machine that did | |
286 | not have that kind of addressing mode. The IA-64 and RS6000 will | |
287 | not do this, and I cannot speak for any other. If any | |
288 | architecture does have an a-b update for, these cases should be | |
289 | added. */ | |
290 | if (HAVE_PRE_MODIFY_REG) | |
291 | { | |
292 | decision_table[INC_REG][INC_ZERO][FORM_PRE_ADD] = REG_PRE; | |
293 | decision_table[INC_REG][INC_ZERO][FORM_PRE_INC] = REG_PRE; | |
294 | ||
295 | decision_table[INC_REG][INC_REG][FORM_POST_ADD] = REG_PRE; | |
296 | decision_table[INC_REG][INC_REG][FORM_POST_INC] = REG_PRE; | |
297 | } | |
298 | ||
299 | if (HAVE_POST_MODIFY_REG) | |
300 | { | |
301 | decision_table[INC_REG][INC_ZERO][FORM_POST_ADD] = REG_POST; | |
302 | decision_table[INC_REG][INC_ZERO][FORM_POST_INC] = REG_POST; | |
303 | } | |
304 | ||
305 | initialized = true; | |
306 | } | |
307 | ||
308 | /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or | |
309 | "reg_res = reg0+c". */ | |
310 | ||
48e1416a | 311 | static struct inc_insn |
3072d30e | 312 | { |
4db65708 | 313 | rtx_insn *insn; /* The insn being parsed. */ |
3072d30e | 314 | rtx pat; /* The pattern of the insn. */ |
315 | bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */ | |
316 | enum form form; | |
317 | rtx reg_res; | |
318 | rtx reg0; | |
319 | rtx reg1; | |
320 | enum inc_state reg1_state;/* The form of the const if reg1 is a const. */ | |
321 | HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */ | |
322 | } inc_insn; | |
323 | ||
324 | ||
325 | /* Dump the parsed inc insn to FILE. */ | |
326 | ||
48e1416a | 327 | static void |
3072d30e | 328 | dump_inc_insn (FILE *file) |
329 | { | |
48e1416a | 330 | const char *f = ((inc_insn.form == FORM_PRE_ADD) |
3072d30e | 331 | || (inc_insn.form == FORM_PRE_INC)) ? "pre" : "post"; |
332 | ||
333 | dump_insn_slim (file, inc_insn.insn); | |
334 | ||
335 | switch (inc_insn.form) | |
336 | { | |
337 | case FORM_PRE_ADD: | |
338 | case FORM_POST_ADD: | |
339 | if (inc_insn.reg1_is_const) | |
48e1416a | 340 | fprintf (file, "found %s add(%d) r[%d]=r[%d]+%d\n", |
341 | f, INSN_UID (inc_insn.insn), | |
342 | REGNO (inc_insn.reg_res), | |
3072d30e | 343 | REGNO (inc_insn.reg0), (int) inc_insn.reg1_val); |
344 | else | |
48e1416a | 345 | fprintf (file, "found %s add(%d) r[%d]=r[%d]+r[%d]\n", |
346 | f, INSN_UID (inc_insn.insn), | |
347 | REGNO (inc_insn.reg_res), | |
3072d30e | 348 | REGNO (inc_insn.reg0), REGNO (inc_insn.reg1)); |
349 | break; | |
48e1416a | 350 | |
3072d30e | 351 | case FORM_PRE_INC: |
352 | case FORM_POST_INC: | |
353 | if (inc_insn.reg1_is_const) | |
48e1416a | 354 | fprintf (file, "found %s inc(%d) r[%d]+=%d\n", |
355 | f, INSN_UID (inc_insn.insn), | |
3072d30e | 356 | REGNO (inc_insn.reg_res), (int) inc_insn.reg1_val); |
357 | else | |
48e1416a | 358 | fprintf (file, "found %s inc(%d) r[%d]+=r[%d]\n", |
359 | f, INSN_UID (inc_insn.insn), | |
3072d30e | 360 | REGNO (inc_insn.reg_res), REGNO (inc_insn.reg1)); |
361 | break; | |
362 | ||
363 | default: | |
364 | break; | |
365 | } | |
366 | } | |
367 | ||
368 | ||
369 | /* Parsed fields of a mem ref of the form "*(reg0+reg1)" or "*(reg0+c)". */ | |
370 | ||
371 | static struct mem_insn | |
372 | { | |
4db65708 | 373 | rtx_insn *insn; /* The insn being parsed. */ |
3072d30e | 374 | rtx pat; /* The pattern of the insn. */ |
375 | rtx *mem_loc; /* The address of the field that holds the mem */ | |
376 | /* that is to be replaced. */ | |
377 | bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */ | |
378 | rtx reg0; | |
379 | rtx reg1; /* This is either a reg or a const depending on | |
380 | reg1_is_const. */ | |
381 | enum inc_state reg1_state;/* The form of the const if reg1 is a const. */ | |
382 | HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */ | |
383 | } mem_insn; | |
384 | ||
385 | ||
386 | /* Dump the parsed mem insn to FILE. */ | |
387 | ||
48e1416a | 388 | static void |
3072d30e | 389 | dump_mem_insn (FILE *file) |
390 | { | |
391 | dump_insn_slim (file, mem_insn.insn); | |
392 | ||
393 | if (mem_insn.reg1_is_const) | |
48e1416a | 394 | fprintf (file, "found mem(%d) *(r[%d]+%d)\n", |
395 | INSN_UID (mem_insn.insn), | |
3072d30e | 396 | REGNO (mem_insn.reg0), (int) mem_insn.reg1_val); |
397 | else | |
48e1416a | 398 | fprintf (file, "found mem(%d) *(r[%d]+r[%d])\n", |
399 | INSN_UID (mem_insn.insn), | |
3072d30e | 400 | REGNO (mem_insn.reg0), REGNO (mem_insn.reg1)); |
401 | } | |
402 | ||
403 | ||
404 | /* The following three arrays contain pointers to instructions. They | |
405 | are indexed by REGNO. At any point in the basic block where we are | |
406 | looking these three arrays contain, respectively, the next insn | |
407 | that uses REGNO, the next inc or add insn that uses REGNO and the | |
408 | next insn that sets REGNO. | |
409 | ||
410 | The arrays are not cleared when we move from block to block so | |
411 | whenever an insn is retrieved from these arrays, it's block number | |
412 | must be compared with the current block. | |
413 | */ | |
414 | ||
f21023fe | 415 | static rtx_insn **reg_next_debug_use = NULL; |
4db65708 | 416 | static rtx_insn **reg_next_use = NULL; |
417 | static rtx_insn **reg_next_inc_use = NULL; | |
418 | static rtx_insn **reg_next_def = NULL; | |
3072d30e | 419 | |
420 | ||
421 | /* Move dead note that match PATTERN to TO_INSN from FROM_INSN. We do | |
422 | not really care about moving any other notes from the inc or add | |
423 | insn. Moving the REG_EQUAL and REG_EQUIV is clearly wrong and it | |
bef304b8 | 424 | does not appear that there are any other kinds of relevant notes. */ |
3072d30e | 425 | |
48e1416a | 426 | static void |
4db65708 | 427 | move_dead_notes (rtx_insn *to_insn, rtx_insn *from_insn, rtx pattern) |
3072d30e | 428 | { |
48e1416a | 429 | rtx note; |
3072d30e | 430 | rtx next_note; |
431 | rtx prev_note = NULL; | |
432 | ||
433 | for (note = REG_NOTES (from_insn); note; note = next_note) | |
434 | { | |
435 | next_note = XEXP (note, 1); | |
48e1416a | 436 | |
3072d30e | 437 | if ((REG_NOTE_KIND (note) == REG_DEAD) |
438 | && pattern == XEXP (note, 0)) | |
439 | { | |
440 | XEXP (note, 1) = REG_NOTES (to_insn); | |
441 | REG_NOTES (to_insn) = note; | |
442 | if (prev_note) | |
443 | XEXP (prev_note, 1) = next_note; | |
444 | else | |
445 | REG_NOTES (from_insn) = next_note; | |
446 | } | |
447 | else prev_note = note; | |
448 | } | |
449 | } | |
450 | ||
3072d30e | 451 | /* Change mem_insn.mem_loc so that uses NEW_ADDR which has an |
452 | increment of INC_REG. To have reached this point, the change is a | |
453 | legitimate one from a dataflow point of view. The only questions | |
454 | are is this a valid change to the instruction and is this a | |
455 | profitable change to the instruction. */ | |
456 | ||
457 | static bool | |
458 | attempt_change (rtx new_addr, rtx inc_reg) | |
459 | { | |
460 | /* There are four cases: For the two cases that involve an add | |
461 | instruction, we are going to have to delete the add and insert a | |
462 | mov. We are going to assume that the mov is free. This is | |
463 | fairly early in the backend and there are a lot of opportunities | |
464 | for removing that move later. In particular, there is the case | |
465 | where the move may be dead, this is what dead code elimination | |
466 | passes are for. The two cases where we have an inc insn will be | |
467 | handled mov free. */ | |
468 | ||
90bd219d | 469 | basic_block bb = BLOCK_FOR_INSN (mem_insn.insn); |
4db65708 | 470 | rtx_insn *mov_insn = NULL; |
3072d30e | 471 | int regno; |
472 | rtx mem = *mem_insn.mem_loc; | |
3754d046 | 473 | machine_mode mode = GET_MODE (mem); |
3072d30e | 474 | rtx new_mem; |
475 | int old_cost = 0; | |
476 | int new_cost = 0; | |
f529eb25 | 477 | bool speed = optimize_bb_for_speed_p (bb); |
3072d30e | 478 | |
479 | PUT_MODE (mem_tmp, mode); | |
480 | XEXP (mem_tmp, 0) = new_addr; | |
481 | ||
5ae4887d | 482 | old_cost = (set_src_cost (mem, mode, speed) |
b72d459f | 483 | + set_rtx_cost (PATTERN (inc_insn.insn), speed)); |
48924509 | 484 | |
5ae4887d | 485 | new_cost = set_src_cost (mem_tmp, mode, speed); |
b9c74b4d | 486 | |
48924509 | 487 | /* In the FORM_PRE_ADD and FORM_POST_ADD cases we emit an extra move |
488 | whose cost we should account for. */ | |
489 | if (inc_insn.form == FORM_PRE_ADD | |
490 | || inc_insn.form == FORM_POST_ADD) | |
491 | { | |
492 | start_sequence (); | |
493 | emit_move_insn (inc_insn.reg_res, inc_insn.reg0); | |
494 | mov_insn = get_insns (); | |
495 | end_sequence (); | |
496 | new_cost += seq_cost (mov_insn, speed); | |
497 | } | |
498 | ||
3072d30e | 499 | /* The first item of business is to see if this is profitable. */ |
500 | if (old_cost < new_cost) | |
501 | { | |
502 | if (dump_file) | |
503 | fprintf (dump_file, "cost failure old=%d new=%d\n", old_cost, new_cost); | |
504 | return false; | |
505 | } | |
506 | ||
9d75589a | 507 | /* Jump through a lot of hoops to keep the attributes up to date. We |
3072d30e | 508 | do not want to call one of the change address variants that take |
509 | an offset even though we know the offset in many cases. These | |
510 | assume you are changing where the address is pointing by the | |
511 | offset. */ | |
512 | new_mem = replace_equiv_address_nv (mem, new_addr); | |
513 | if (! validate_change (mem_insn.insn, mem_insn.mem_loc, new_mem, 0)) | |
514 | { | |
515 | if (dump_file) | |
48e1416a | 516 | fprintf (dump_file, "validation failure\n"); |
3072d30e | 517 | return false; |
518 | } | |
519 | ||
520 | /* From here to the end of the function we are committed to the | |
521 | change, i.e. nothing fails. Generate any necessary movs, move | |
522 | any regnotes, and fix up the reg_next_{use,inc_use,def}. */ | |
523 | switch (inc_insn.form) | |
524 | { | |
525 | case FORM_PRE_ADD: | |
a6879b1d | 526 | /* Replace the addition with a move. Do it at the location of |
527 | the addition since the operand of the addition may change | |
528 | before the memory reference. */ | |
48924509 | 529 | gcc_assert (mov_insn); |
530 | emit_insn_before (mov_insn, inc_insn.insn); | |
d4ce94c1 | 531 | regno = REGNO (inc_insn.reg0); |
f21023fe | 532 | /* ??? Could REGNO possibly be used in MEM_INSN other than in |
533 | the MEM address, and still die there, so that move_dead_notes | |
534 | would incorrectly move the note? */ | |
d4ce94c1 | 535 | if (reg_next_use[regno] == mem_insn.insn) |
536 | move_dead_notes (mov_insn, mem_insn.insn, inc_insn.reg0); | |
537 | else | |
538 | move_dead_notes (mov_insn, inc_insn.insn, inc_insn.reg0); | |
3072d30e | 539 | |
540 | regno = REGNO (inc_insn.reg_res); | |
f21023fe | 541 | if (reg_next_debug_use && reg_next_debug_use[regno] |
542 | && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb) | |
543 | { | |
544 | rtx adjres = gen_rtx_PLUS (GET_MODE (inc_insn.reg_res), | |
545 | inc_insn.reg_res, inc_insn.reg1); | |
546 | if (dump_file) | |
547 | fprintf (dump_file, "adjusting debug insns\n"); | |
548 | propagate_for_debug (PREV_INSN (reg_next_debug_use[regno]), | |
549 | mem_insn.insn, | |
550 | inc_insn.reg_res, adjres, bb); | |
551 | reg_next_debug_use[regno] = NULL; | |
552 | } | |
3072d30e | 553 | reg_next_def[regno] = mov_insn; |
554 | reg_next_use[regno] = NULL; | |
f21023fe | 555 | |
3072d30e | 556 | regno = REGNO (inc_insn.reg0); |
f21023fe | 557 | if (reg_next_debug_use && reg_next_debug_use[regno] |
558 | && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb | |
559 | && find_reg_note (mov_insn, REG_DEAD, inc_insn.reg0)) | |
560 | { | |
561 | if (dump_file) | |
562 | fprintf (dump_file, "remapping debug insns\n"); | |
563 | propagate_for_debug (PREV_INSN (reg_next_debug_use[regno]), | |
564 | mem_insn.insn, | |
565 | inc_insn.reg0, inc_insn.reg_res, bb); | |
566 | reg_next_debug_use[regno] = NULL; | |
567 | } | |
3072d30e | 568 | reg_next_use[regno] = mov_insn; |
569 | df_recompute_luids (bb); | |
570 | break; | |
571 | ||
572 | case FORM_POST_INC: | |
573 | regno = REGNO (inc_insn.reg_res); | |
f21023fe | 574 | if (reg_next_debug_use && reg_next_debug_use[regno] |
575 | && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb) | |
576 | { | |
577 | rtx adjres = gen_rtx_MINUS (GET_MODE (inc_insn.reg_res), | |
578 | inc_insn.reg_res, inc_insn.reg1); | |
579 | if (dump_file) | |
580 | fprintf (dump_file, "adjusting debug insns\n"); | |
581 | propagate_for_debug (PREV_INSN (reg_next_debug_use[regno]), | |
582 | inc_insn.insn, | |
583 | inc_insn.reg_res, adjres, bb); | |
584 | reg_next_debug_use[regno] = NULL; | |
585 | } | |
3072d30e | 586 | if (reg_next_use[regno] == reg_next_inc_use[regno]) |
587 | reg_next_inc_use[regno] = NULL; | |
588 | ||
589 | /* Fallthru. */ | |
590 | case FORM_PRE_INC: | |
591 | regno = REGNO (inc_insn.reg_res); | |
f21023fe | 592 | /* Despite the fall-through, we won't run this twice: we'll have |
593 | already cleared reg_next_debug_use[regno] before falling | |
594 | through. */ | |
595 | if (reg_next_debug_use && reg_next_debug_use[regno] | |
596 | && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb) | |
597 | { | |
598 | rtx adjres = gen_rtx_PLUS (GET_MODE (inc_insn.reg_res), | |
599 | inc_insn.reg_res, inc_insn.reg1); | |
600 | if (dump_file) | |
601 | fprintf (dump_file, "adjusting debug insns\n"); | |
602 | propagate_for_debug (PREV_INSN (reg_next_debug_use[regno]), | |
603 | mem_insn.insn, | |
604 | inc_insn.reg_res, adjres, bb); | |
605 | if (DF_INSN_LUID (mem_insn.insn) | |
606 | < DF_INSN_LUID (reg_next_debug_use[regno])) | |
607 | reg_next_debug_use[regno] = NULL; | |
608 | } | |
3072d30e | 609 | reg_next_def[regno] = mem_insn.insn; |
610 | reg_next_use[regno] = NULL; | |
611 | ||
612 | break; | |
613 | ||
614 | case FORM_POST_ADD: | |
48924509 | 615 | gcc_assert (mov_insn); |
616 | emit_insn_before (mov_insn, mem_insn.insn); | |
3072d30e | 617 | move_dead_notes (mov_insn, inc_insn.insn, inc_insn.reg0); |
618 | ||
619 | /* Do not move anything to the mov insn because the instruction | |
620 | pointer for the main iteration has not yet hit that. It is | |
621 | still pointing to the mem insn. */ | |
622 | regno = REGNO (inc_insn.reg_res); | |
f21023fe | 623 | /* The pseudo is now set earlier, so it must have been dead in |
624 | that range, and dead registers cannot be referenced in debug | |
625 | insns. */ | |
626 | gcc_assert (!(reg_next_debug_use && reg_next_debug_use[regno] | |
627 | && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb)); | |
3072d30e | 628 | reg_next_def[regno] = mem_insn.insn; |
629 | reg_next_use[regno] = NULL; | |
630 | ||
631 | regno = REGNO (inc_insn.reg0); | |
f21023fe | 632 | if (reg_next_debug_use && reg_next_debug_use[regno] |
633 | && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb | |
634 | && find_reg_note (mov_insn, REG_DEAD, inc_insn.reg0)) | |
635 | { | |
636 | if (dump_file) | |
637 | fprintf (dump_file, "remapping debug insns\n"); | |
638 | propagate_for_debug (PREV_INSN (reg_next_debug_use[regno]), | |
639 | inc_insn.insn, | |
640 | inc_insn.reg0, inc_insn.reg_res, bb); | |
641 | reg_next_debug_use[regno] = NULL; | |
642 | } | |
3072d30e | 643 | reg_next_use[regno] = mem_insn.insn; |
644 | if ((reg_next_use[regno] == reg_next_inc_use[regno]) | |
645 | || (reg_next_inc_use[regno] == inc_insn.insn)) | |
646 | reg_next_inc_use[regno] = NULL; | |
647 | df_recompute_luids (bb); | |
648 | break; | |
649 | ||
650 | case FORM_last: | |
651 | default: | |
652 | gcc_unreachable (); | |
653 | } | |
654 | ||
655 | if (!inc_insn.reg1_is_const) | |
656 | { | |
657 | regno = REGNO (inc_insn.reg1); | |
658 | reg_next_use[regno] = mem_insn.insn; | |
659 | if ((reg_next_use[regno] == reg_next_inc_use[regno]) | |
660 | || (reg_next_inc_use[regno] == inc_insn.insn)) | |
661 | reg_next_inc_use[regno] = NULL; | |
662 | } | |
663 | ||
664 | delete_insn (inc_insn.insn); | |
665 | ||
666 | if (dump_file && mov_insn) | |
667 | { | |
668 | fprintf (dump_file, "inserting mov "); | |
669 | dump_insn_slim (dump_file, mov_insn); | |
670 | } | |
671 | ||
672 | /* Record that this insn has an implicit side effect. */ | |
a1ddb869 | 673 | add_reg_note (mem_insn.insn, REG_INC, inc_reg); |
3072d30e | 674 | |
675 | if (dump_file) | |
676 | { | |
677 | fprintf (dump_file, "****success "); | |
678 | dump_insn_slim (dump_file, mem_insn.insn); | |
679 | } | |
680 | ||
681 | return true; | |
682 | } | |
683 | ||
684 | ||
685 | /* Try to combine the instruction in INC_INSN with the instruction in | |
686 | MEM_INSN. First the form is determined using the DECISION_TABLE | |
f0b5f617 | 687 | and the results of parsing the INC_INSN and the MEM_INSN. |
3072d30e | 688 | Assuming the form is ok, a prototype new address is built which is |
689 | passed to ATTEMPT_CHANGE for final processing. */ | |
690 | ||
48e1416a | 691 | static bool |
3072d30e | 692 | try_merge (void) |
693 | { | |
694 | enum gen_form gen_form; | |
695 | rtx mem = *mem_insn.mem_loc; | |
696 | rtx inc_reg = inc_insn.form == FORM_POST_ADD ? | |
697 | inc_insn.reg_res : mem_insn.reg0; | |
698 | ||
699 | /* The width of the mem being accessed. */ | |
52acb7ae | 700 | poly_int64 size = GET_MODE_SIZE (GET_MODE (mem)); |
4db65708 | 701 | rtx_insn *last_insn = NULL; |
3754d046 | 702 | machine_mode reg_mode = GET_MODE (inc_reg); |
3072d30e | 703 | |
704 | switch (inc_insn.form) | |
705 | { | |
706 | case FORM_PRE_ADD: | |
707 | case FORM_PRE_INC: | |
708 | last_insn = mem_insn.insn; | |
709 | break; | |
710 | case FORM_POST_INC: | |
711 | case FORM_POST_ADD: | |
712 | last_insn = inc_insn.insn; | |
713 | break; | |
714 | case FORM_last: | |
715 | default: | |
716 | gcc_unreachable (); | |
717 | } | |
718 | ||
719 | /* Cannot handle auto inc of the stack. */ | |
720 | if (inc_reg == stack_pointer_rtx) | |
721 | { | |
722 | if (dump_file) | |
723 | fprintf (dump_file, "cannot inc stack %d failure\n", REGNO (inc_reg)); | |
724 | return false; | |
725 | } | |
726 | ||
727 | /* Look to see if the inc register is dead after the memory | |
a6879b1d | 728 | reference. If it is, do not do the combination. */ |
3072d30e | 729 | if (find_regno_note (last_insn, REG_DEAD, REGNO (inc_reg))) |
730 | { | |
731 | if (dump_file) | |
732 | fprintf (dump_file, "dead failure %d\n", REGNO (inc_reg)); | |
733 | return false; | |
734 | } | |
735 | ||
48e1416a | 736 | mem_insn.reg1_state = (mem_insn.reg1_is_const) |
3072d30e | 737 | ? set_inc_state (mem_insn.reg1_val, size) : INC_REG; |
738 | inc_insn.reg1_state = (inc_insn.reg1_is_const) | |
739 | ? set_inc_state (inc_insn.reg1_val, size) : INC_REG; | |
740 | ||
741 | /* Now get the form that we are generating. */ | |
48e1416a | 742 | gen_form = decision_table |
3072d30e | 743 | [inc_insn.reg1_state][mem_insn.reg1_state][inc_insn.form]; |
744 | ||
745 | if (dbg_cnt (auto_inc_dec) == false) | |
746 | return false; | |
747 | ||
748 | switch (gen_form) | |
749 | { | |
750 | default: | |
751 | case NOTHING: | |
752 | return false; | |
753 | ||
754 | case SIMPLE_PRE_INC: /* ++size */ | |
755 | if (dump_file) | |
756 | fprintf (dump_file, "trying SIMPLE_PRE_INC\n"); | |
98155838 | 757 | return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg); |
48e1416a | 758 | |
3072d30e | 759 | case SIMPLE_POST_INC: /* size++ */ |
760 | if (dump_file) | |
761 | fprintf (dump_file, "trying SIMPLE_POST_INC\n"); | |
98155838 | 762 | return attempt_change (gen_rtx_POST_INC (reg_mode, inc_reg), inc_reg); |
48e1416a | 763 | |
3072d30e | 764 | case SIMPLE_PRE_DEC: /* --size */ |
765 | if (dump_file) | |
766 | fprintf (dump_file, "trying SIMPLE_PRE_DEC\n"); | |
98155838 | 767 | return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg); |
48e1416a | 768 | |
3072d30e | 769 | case SIMPLE_POST_DEC: /* size-- */ |
770 | if (dump_file) | |
771 | fprintf (dump_file, "trying SIMPLE_POST_DEC\n"); | |
98155838 | 772 | return attempt_change (gen_rtx_POST_DEC (reg_mode, inc_reg), inc_reg); |
48e1416a | 773 | |
3072d30e | 774 | case DISP_PRE: /* ++con */ |
775 | if (dump_file) | |
776 | fprintf (dump_file, "trying DISP_PRE\n"); | |
98155838 | 777 | return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, |
3072d30e | 778 | inc_reg, |
98155838 | 779 | gen_rtx_PLUS (reg_mode, |
3072d30e | 780 | inc_reg, |
781 | inc_insn.reg1)), | |
782 | inc_reg); | |
48e1416a | 783 | |
3072d30e | 784 | case DISP_POST: /* con++ */ |
785 | if (dump_file) | |
786 | fprintf (dump_file, "trying POST_DISP\n"); | |
98155838 | 787 | return attempt_change (gen_rtx_POST_MODIFY (reg_mode, |
3072d30e | 788 | inc_reg, |
98155838 | 789 | gen_rtx_PLUS (reg_mode, |
3072d30e | 790 | inc_reg, |
791 | inc_insn.reg1)), | |
792 | inc_reg); | |
48e1416a | 793 | |
3072d30e | 794 | case REG_PRE: /* ++reg */ |
795 | if (dump_file) | |
796 | fprintf (dump_file, "trying PRE_REG\n"); | |
98155838 | 797 | return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, |
3072d30e | 798 | inc_reg, |
98155838 | 799 | gen_rtx_PLUS (reg_mode, |
3072d30e | 800 | inc_reg, |
801 | inc_insn.reg1)), | |
802 | inc_reg); | |
48e1416a | 803 | |
3072d30e | 804 | case REG_POST: /* reg++ */ |
805 | if (dump_file) | |
806 | fprintf (dump_file, "trying POST_REG\n"); | |
98155838 | 807 | return attempt_change (gen_rtx_POST_MODIFY (reg_mode, |
3072d30e | 808 | inc_reg, |
98155838 | 809 | gen_rtx_PLUS (reg_mode, |
3072d30e | 810 | inc_reg, |
811 | inc_insn.reg1)), | |
812 | inc_reg); | |
3072d30e | 813 | } |
814 | } | |
815 | ||
816 | /* Return the next insn that uses (if reg_next_use is passed in | |
817 | NEXT_ARRAY) or defines (if reg_next_def is passed in NEXT_ARRAY) | |
818 | REGNO in BB. */ | |
819 | ||
4db65708 | 820 | static rtx_insn * |
821 | get_next_ref (int regno, basic_block bb, rtx_insn **next_array) | |
3072d30e | 822 | { |
4db65708 | 823 | rtx_insn *insn = next_array[regno]; |
3072d30e | 824 | |
825 | /* Lazy about cleaning out the next_arrays. */ | |
90bd219d | 826 | if (insn && BLOCK_FOR_INSN (insn) != bb) |
3072d30e | 827 | { |
828 | next_array[regno] = NULL; | |
829 | insn = NULL; | |
830 | } | |
831 | ||
832 | return insn; | |
833 | } | |
834 | ||
835 | ||
3072d30e | 836 | /* Return true if INSN is of a form "a = b op c" where a and b are |
837 | regs. op is + if c is a reg and +|- if c is a const. Fill in | |
48e1416a | 838 | INC_INSN with what is found. |
839 | ||
3072d30e | 840 | This function is called in two contexts, if BEFORE_MEM is true, |
841 | this is called for each insn in the basic block. If BEFORE_MEM is | |
842 | false, it is called for the instruction in the block that uses the | |
843 | index register for some memory reference that is currently being | |
844 | processed. */ | |
845 | ||
846 | static bool | |
4db65708 | 847 | parse_add_or_inc (rtx_insn *insn, bool before_mem) |
3072d30e | 848 | { |
849 | rtx pat = single_set (insn); | |
850 | if (!pat) | |
851 | return false; | |
852 | ||
853 | /* Result must be single reg. */ | |
854 | if (!REG_P (SET_DEST (pat))) | |
855 | return false; | |
856 | ||
857 | if ((GET_CODE (SET_SRC (pat)) != PLUS) | |
858 | && (GET_CODE (SET_SRC (pat)) != MINUS)) | |
859 | return false; | |
860 | ||
861 | if (!REG_P (XEXP (SET_SRC (pat), 0))) | |
862 | return false; | |
863 | ||
864 | inc_insn.insn = insn; | |
865 | inc_insn.pat = pat; | |
866 | inc_insn.reg_res = SET_DEST (pat); | |
867 | inc_insn.reg0 = XEXP (SET_SRC (pat), 0); | |
5c31bc69 | 868 | |
869 | /* Block any auto increment of the frame pointer since it expands into | |
870 | an addition and cannot be removed by copy propagation. */ | |
871 | if (inc_insn.reg0 == frame_pointer_rtx) | |
872 | return false; | |
873 | ||
3072d30e | 874 | if (rtx_equal_p (inc_insn.reg_res, inc_insn.reg0)) |
875 | inc_insn.form = before_mem ? FORM_PRE_INC : FORM_POST_INC; | |
48e1416a | 876 | else |
3072d30e | 877 | inc_insn.form = before_mem ? FORM_PRE_ADD : FORM_POST_ADD; |
878 | ||
971ba038 | 879 | if (CONST_INT_P (XEXP (SET_SRC (pat), 1))) |
3072d30e | 880 | { |
881 | /* Process a = b + c where c is a const. */ | |
882 | inc_insn.reg1_is_const = true; | |
883 | if (GET_CODE (SET_SRC (pat)) == PLUS) | |
884 | { | |
885 | inc_insn.reg1 = XEXP (SET_SRC (pat), 1); | |
886 | inc_insn.reg1_val = INTVAL (inc_insn.reg1); | |
887 | } | |
888 | else | |
889 | { | |
890 | inc_insn.reg1_val = -INTVAL (XEXP (SET_SRC (pat), 1)); | |
891 | inc_insn.reg1 = GEN_INT (inc_insn.reg1_val); | |
892 | } | |
893 | return true; | |
894 | } | |
895 | else if ((HAVE_PRE_MODIFY_REG || HAVE_POST_MODIFY_REG) | |
896 | && (REG_P (XEXP (SET_SRC (pat), 1))) | |
897 | && GET_CODE (SET_SRC (pat)) == PLUS) | |
898 | { | |
899 | /* Process a = b + c where c is a reg. */ | |
900 | inc_insn.reg1 = XEXP (SET_SRC (pat), 1); | |
901 | inc_insn.reg1_is_const = false; | |
48e1416a | 902 | |
903 | if (inc_insn.form == FORM_PRE_INC | |
3072d30e | 904 | || inc_insn.form == FORM_POST_INC) |
905 | return true; | |
906 | else if (rtx_equal_p (inc_insn.reg_res, inc_insn.reg1)) | |
907 | { | |
908 | /* Reverse the two operands and turn *_ADD into *_INC since | |
909 | a = c + a. */ | |
a4f59596 | 910 | std::swap (inc_insn.reg0, inc_insn.reg1); |
3072d30e | 911 | inc_insn.form = before_mem ? FORM_PRE_INC : FORM_POST_INC; |
912 | return true; | |
913 | } | |
48e1416a | 914 | else |
3072d30e | 915 | return true; |
916 | } | |
917 | ||
918 | return false; | |
919 | } | |
920 | ||
921 | ||
922 | /* A recursive function that checks all of the mem uses in | |
923 | ADDRESS_OF_X to see if any single one of them is compatible with | |
d4ce94c1 | 924 | what has been found in inc_insn. To avoid accidental matches, we |
925 | will only find MEMs with FINDREG, be it inc_insn.reg_res, be it | |
926 | inc_insn.reg0. | |
3072d30e | 927 | |
48e1416a | 928 | -1 is returned for success. 0 is returned if nothing was found and |
3072d30e | 929 | 1 is returned for failure. */ |
930 | ||
931 | static int | |
d4ce94c1 | 932 | find_address (rtx *address_of_x, rtx findreg) |
3072d30e | 933 | { |
934 | rtx x = *address_of_x; | |
935 | enum rtx_code code = GET_CODE (x); | |
936 | const char *const fmt = GET_RTX_FORMAT (code); | |
937 | int i; | |
938 | int value = 0; | |
939 | int tem; | |
940 | ||
d4ce94c1 | 941 | if (code == MEM && findreg == inc_insn.reg_res |
942 | && rtx_equal_p (XEXP (x, 0), inc_insn.reg_res)) | |
3072d30e | 943 | { |
d4ce94c1 | 944 | /* Match with *reg_res. */ |
3072d30e | 945 | mem_insn.mem_loc = address_of_x; |
946 | mem_insn.reg0 = inc_insn.reg_res; | |
947 | mem_insn.reg1_is_const = true; | |
948 | mem_insn.reg1_val = 0; | |
949 | mem_insn.reg1 = GEN_INT (0); | |
950 | return -1; | |
951 | } | |
d4ce94c1 | 952 | if (code == MEM && inc_insn.reg1_is_const && inc_insn.reg0 |
953 | && findreg == inc_insn.reg0 | |
954 | && rtx_equal_p (XEXP (x, 0), inc_insn.reg0)) | |
955 | { | |
956 | /* Match with *reg0, assumed to be equivalent to | |
957 | *(reg_res - reg1_val); callers must check whether this is the case. */ | |
958 | mem_insn.mem_loc = address_of_x; | |
959 | mem_insn.reg0 = inc_insn.reg_res; | |
960 | mem_insn.reg1_is_const = true; | |
961 | mem_insn.reg1_val = -inc_insn.reg1_val; | |
962 | mem_insn.reg1 = GEN_INT (mem_insn.reg1_val); | |
963 | return -1; | |
964 | } | |
965 | if (code == MEM && findreg == inc_insn.reg_res | |
966 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3072d30e | 967 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), inc_insn.reg_res)) |
968 | { | |
969 | rtx b = XEXP (XEXP (x, 0), 1); | |
970 | mem_insn.mem_loc = address_of_x; | |
971 | mem_insn.reg0 = inc_insn.reg_res; | |
972 | mem_insn.reg1 = b; | |
973 | mem_insn.reg1_is_const = inc_insn.reg1_is_const; | |
971ba038 | 974 | if (CONST_INT_P (b)) |
3072d30e | 975 | { |
976 | /* Match with *(reg0 + reg1) where reg1 is a const. */ | |
977 | HOST_WIDE_INT val = INTVAL (b); | |
48e1416a | 978 | if (inc_insn.reg1_is_const |
3072d30e | 979 | && (inc_insn.reg1_val == val || inc_insn.reg1_val == -val)) |
980 | { | |
981 | mem_insn.reg1_val = val; | |
982 | return -1; | |
983 | } | |
984 | } | |
48e1416a | 985 | else if (!inc_insn.reg1_is_const |
986 | && rtx_equal_p (inc_insn.reg1, b)) | |
3072d30e | 987 | /* Match with *(reg0 + reg1). */ |
988 | return -1; | |
989 | } | |
990 | ||
991 | if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) | |
992 | { | |
993 | /* If REG occurs inside a MEM used in a bit-field reference, | |
994 | that is unacceptable. */ | |
d4ce94c1 | 995 | if (find_address (&XEXP (x, 0), findreg)) |
3072d30e | 996 | return 1; |
997 | } | |
998 | ||
999 | if (x == inc_insn.reg_res) | |
1000 | return 1; | |
1001 | ||
1002 | /* Time for some deep diving. */ | |
1003 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1004 | { | |
1005 | if (fmt[i] == 'e') | |
1006 | { | |
d4ce94c1 | 1007 | tem = find_address (&XEXP (x, i), findreg); |
3072d30e | 1008 | /* If this is the first use, let it go so the rest of the |
1009 | insn can be checked. */ | |
1010 | if (value == 0) | |
1011 | value = tem; | |
1012 | else if (tem != 0) | |
1013 | /* More than one match was found. */ | |
1014 | return 1; | |
1015 | } | |
1016 | else if (fmt[i] == 'E') | |
1017 | { | |
1018 | int j; | |
1019 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1020 | { | |
d4ce94c1 | 1021 | tem = find_address (&XVECEXP (x, i, j), findreg); |
3072d30e | 1022 | /* If this is the first use, let it go so the rest of |
1023 | the insn can be checked. */ | |
1024 | if (value == 0) | |
1025 | value = tem; | |
1026 | else if (tem != 0) | |
1027 | /* More than one match was found. */ | |
1028 | return 1; | |
1029 | } | |
1030 | } | |
1031 | } | |
1032 | return value; | |
1033 | } | |
1034 | ||
1035 | /* Once a suitable mem reference has been found and the MEM_INSN | |
1036 | structure has been filled in, FIND_INC is called to see if there is | |
1037 | a suitable add or inc insn that follows the mem reference and | |
1038 | determine if it is suitable to merge. | |
1039 | ||
1040 | In the case where the MEM_INSN has two registers in the reference, | |
1041 | this function may be called recursively. The first time looking | |
1042 | for an add of the first register, and if that fails, looking for an | |
1043 | add of the second register. The FIRST_TRY parameter is used to | |
1044 | only allow the parameters to be reversed once. */ | |
1045 | ||
48e1416a | 1046 | static bool |
3072d30e | 1047 | find_inc (bool first_try) |
1048 | { | |
4db65708 | 1049 | rtx_insn *insn; |
90bd219d | 1050 | basic_block bb = BLOCK_FOR_INSN (mem_insn.insn); |
4db65708 | 1051 | rtx_insn *other_insn; |
be10bb5a | 1052 | df_ref def; |
3072d30e | 1053 | |
1054 | /* Make sure this reg appears only once in this insn. */ | |
1055 | if (count_occurrences (PATTERN (mem_insn.insn), mem_insn.reg0, 1) != 1) | |
1056 | { | |
1057 | if (dump_file) | |
48e1416a | 1058 | fprintf (dump_file, "mem count failure\n"); |
3072d30e | 1059 | return false; |
1060 | } | |
1061 | ||
1062 | if (dump_file) | |
1063 | dump_mem_insn (dump_file); | |
1064 | ||
1065 | /* Find the next use that is an inc. */ | |
48e1416a | 1066 | insn = get_next_ref (REGNO (mem_insn.reg0), |
90bd219d | 1067 | BLOCK_FOR_INSN (mem_insn.insn), |
3072d30e | 1068 | reg_next_inc_use); |
1069 | if (!insn) | |
1070 | return false; | |
1071 | ||
1072 | /* Even though we know the next use is an add or inc because it came | |
1073 | from the reg_next_inc_use, we must still reparse. */ | |
1074 | if (!parse_add_or_inc (insn, false)) | |
1075 | { | |
1076 | /* Next use was not an add. Look for one extra case. It could be | |
1077 | that we have: | |
48e1416a | 1078 | |
3072d30e | 1079 | *(a + b) |
1080 | ...= a; | |
1081 | ...= b + a | |
48e1416a | 1082 | |
3072d30e | 1083 | if we reverse the operands in the mem ref we would |
1084 | find this. Only try it once though. */ | |
1085 | if (first_try && !mem_insn.reg1_is_const) | |
1086 | { | |
a4f59596 | 1087 | std::swap (mem_insn.reg0, mem_insn.reg1); |
3072d30e | 1088 | return find_inc (false); |
1089 | } | |
1090 | else | |
1091 | return false; | |
1092 | } | |
1093 | ||
48e1416a | 1094 | /* Need to assure that none of the operands of the inc instruction are |
3072d30e | 1095 | assigned to by the mem insn. */ |
be10bb5a | 1096 | FOR_EACH_INSN_DEF (def, mem_insn.insn) |
3072d30e | 1097 | { |
3072d30e | 1098 | unsigned int regno = DF_REF_REGNO (def); |
48e1416a | 1099 | if ((regno == REGNO (inc_insn.reg0)) |
3072d30e | 1100 | || (regno == REGNO (inc_insn.reg_res))) |
1101 | { | |
1102 | if (dump_file) | |
1103 | fprintf (dump_file, "inc conflicts with store failure.\n"); | |
1104 | return false; | |
1105 | } | |
1106 | if (!inc_insn.reg1_is_const && (regno == REGNO (inc_insn.reg1))) | |
1107 | { | |
1108 | if (dump_file) | |
1109 | fprintf (dump_file, "inc conflicts with store failure.\n"); | |
1110 | return false; | |
1111 | } | |
1112 | } | |
1113 | ||
1114 | if (dump_file) | |
1115 | dump_inc_insn (dump_file); | |
1116 | ||
1117 | if (inc_insn.form == FORM_POST_ADD) | |
1118 | { | |
1119 | /* Make sure that there is no insn that assigns to inc_insn.res | |
1120 | between the mem_insn and the inc_insn. */ | |
4db65708 | 1121 | rtx_insn *other_insn = get_next_ref (REGNO (inc_insn.reg_res), |
1122 | BLOCK_FOR_INSN (mem_insn.insn), | |
1123 | reg_next_def); | |
3072d30e | 1124 | if (other_insn != inc_insn.insn) |
1125 | { | |
1126 | if (dump_file) | |
48e1416a | 1127 | fprintf (dump_file, |
3072d30e | 1128 | "result of add is assigned to between mem and inc insns.\n"); |
1129 | return false; | |
1130 | } | |
1131 | ||
48e1416a | 1132 | other_insn = get_next_ref (REGNO (inc_insn.reg_res), |
90bd219d | 1133 | BLOCK_FOR_INSN (mem_insn.insn), |
3072d30e | 1134 | reg_next_use); |
48e1416a | 1135 | if (other_insn |
3072d30e | 1136 | && (other_insn != inc_insn.insn) |
1137 | && (DF_INSN_LUID (inc_insn.insn) > DF_INSN_LUID (other_insn))) | |
1138 | { | |
1139 | if (dump_file) | |
48e1416a | 1140 | fprintf (dump_file, |
3072d30e | 1141 | "result of add is used between mem and inc insns.\n"); |
1142 | return false; | |
1143 | } | |
1144 | ||
1145 | /* For the post_add to work, the result_reg of the inc must not be | |
1146 | used in the mem insn since this will become the new index | |
1147 | register. */ | |
6416852c | 1148 | if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn))) |
3072d30e | 1149 | { |
1150 | if (dump_file) | |
1151 | fprintf (dump_file, "base reg replacement failure.\n"); | |
1152 | return false; | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | if (mem_insn.reg1_is_const) | |
1157 | { | |
1158 | if (mem_insn.reg1_val == 0) | |
1159 | { | |
1160 | if (!inc_insn.reg1_is_const) | |
1161 | { | |
1162 | /* The mem looks like *r0 and the rhs of the add has two | |
1163 | registers. */ | |
1164 | int luid = DF_INSN_LUID (inc_insn.insn); | |
1165 | if (inc_insn.form == FORM_POST_ADD) | |
1166 | { | |
48e1416a | 1167 | /* The trick is that we are not going to increment r0, |
3072d30e | 1168 | we are going to increment the result of the add insn. |
1169 | For this trick to be correct, the result reg of | |
1170 | the inc must be a valid addressing reg. */ | |
98155838 | 1171 | addr_space_t as = MEM_ADDR_SPACE (*mem_insn.mem_loc); |
1172 | if (GET_MODE (inc_insn.reg_res) | |
1173 | != targetm.addr_space.address_mode (as)) | |
3072d30e | 1174 | { |
1175 | if (dump_file) | |
1176 | fprintf (dump_file, "base reg mode failure.\n"); | |
1177 | return false; | |
1178 | } | |
1179 | ||
1180 | /* We also need to make sure that the next use of | |
1181 | inc result is after the inc. */ | |
48e1416a | 1182 | other_insn |
3072d30e | 1183 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_use); |
1184 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1185 | return false; | |
1186 | ||
1187 | if (!rtx_equal_p (mem_insn.reg0, inc_insn.reg0)) | |
a4f59596 | 1188 | std::swap (inc_insn.reg0, inc_insn.reg1); |
3072d30e | 1189 | } |
1190 | ||
48e1416a | 1191 | other_insn |
3072d30e | 1192 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def); |
1193 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1194 | return false; | |
1195 | } | |
1196 | } | |
1197 | /* Both the inc/add and the mem have a constant. Need to check | |
1198 | that the constants are ok. */ | |
1199 | else if ((mem_insn.reg1_val != inc_insn.reg1_val) | |
1200 | && (mem_insn.reg1_val != -inc_insn.reg1_val)) | |
1201 | return false; | |
1202 | } | |
1203 | else | |
1204 | { | |
1205 | /* The mem insn is of the form *(a + b) where a and b are both | |
1206 | regs. It may be that in order to match the add or inc we | |
1207 | need to treat it as if it was *(b + a). It may also be that | |
1208 | the add is of the form a + c where c does not match b and | |
1209 | then we just abandon this. */ | |
48e1416a | 1210 | |
3072d30e | 1211 | int luid = DF_INSN_LUID (inc_insn.insn); |
4db65708 | 1212 | rtx_insn *other_insn; |
48e1416a | 1213 | |
3072d30e | 1214 | /* Make sure this reg appears only once in this insn. */ |
1215 | if (count_occurrences (PATTERN (mem_insn.insn), mem_insn.reg1, 1) != 1) | |
1216 | return false; | |
48e1416a | 1217 | |
3072d30e | 1218 | if (inc_insn.form == FORM_POST_ADD) |
1219 | { | |
1220 | /* For this trick to be correct, the result reg of the inc | |
1221 | must be a valid addressing reg. */ | |
98155838 | 1222 | addr_space_t as = MEM_ADDR_SPACE (*mem_insn.mem_loc); |
1223 | if (GET_MODE (inc_insn.reg_res) | |
1224 | != targetm.addr_space.address_mode (as)) | |
3072d30e | 1225 | { |
1226 | if (dump_file) | |
1227 | fprintf (dump_file, "base reg mode failure.\n"); | |
1228 | return false; | |
1229 | } | |
1230 | ||
1231 | if (rtx_equal_p (mem_insn.reg0, inc_insn.reg0)) | |
1232 | { | |
1233 | if (!rtx_equal_p (mem_insn.reg1, inc_insn.reg1)) | |
1234 | { | |
1235 | /* See comment above on find_inc (false) call. */ | |
1236 | if (first_try) | |
1237 | { | |
a4f59596 | 1238 | std::swap (mem_insn.reg0, mem_insn.reg1); |
3072d30e | 1239 | return find_inc (false); |
1240 | } | |
1241 | else | |
1242 | return false; | |
1243 | } | |
1244 | ||
bef304b8 | 1245 | /* Need to check that there are no assignments to b |
3072d30e | 1246 | before the add insn. */ |
48e1416a | 1247 | other_insn |
3072d30e | 1248 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def); |
1249 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1250 | return false; | |
1251 | /* All ok for the next step. */ | |
1252 | } | |
1253 | else | |
1254 | { | |
1255 | /* We know that mem_insn.reg0 must equal inc_insn.reg1 | |
1256 | or else we would not have found the inc insn. */ | |
a4f59596 | 1257 | std::swap (mem_insn.reg0, mem_insn.reg1); |
3072d30e | 1258 | if (!rtx_equal_p (mem_insn.reg0, inc_insn.reg0)) |
1259 | { | |
1260 | /* See comment above on find_inc (false) call. */ | |
1261 | if (first_try) | |
1262 | return find_inc (false); | |
1263 | else | |
1264 | return false; | |
1265 | } | |
1266 | /* To have gotten here know that. | |
1267 | *(b + a) | |
48e1416a | 1268 | |
3072d30e | 1269 | ... = (b + a) |
48e1416a | 1270 | |
3072d30e | 1271 | We also know that the lhs of the inc is not b or a. We |
1272 | need to make sure that there are no assignments to b | |
48e1416a | 1273 | between the mem ref and the inc. */ |
1274 | ||
1275 | other_insn | |
3072d30e | 1276 | = get_next_ref (REGNO (inc_insn.reg0), bb, reg_next_def); |
1277 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1278 | return false; | |
1279 | } | |
1280 | ||
1281 | /* Need to check that the next use of the add result is later than | |
1282 | add insn since this will be the reg incremented. */ | |
48e1416a | 1283 | other_insn |
3072d30e | 1284 | = get_next_ref (REGNO (inc_insn.reg_res), bb, reg_next_use); |
1285 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1286 | return false; | |
1287 | } | |
1288 | else /* FORM_POST_INC. There is less to check here because we | |
48e1416a | 1289 | know that operands must line up. */ |
3072d30e | 1290 | { |
1291 | if (!rtx_equal_p (mem_insn.reg1, inc_insn.reg1)) | |
1292 | /* See comment above on find_inc (false) call. */ | |
1293 | { | |
1294 | if (first_try) | |
1295 | { | |
a4f59596 | 1296 | std::swap (mem_insn.reg0, mem_insn.reg1); |
3072d30e | 1297 | return find_inc (false); |
1298 | } | |
48e1416a | 1299 | else |
3072d30e | 1300 | return false; |
1301 | } | |
48e1416a | 1302 | |
3072d30e | 1303 | /* To have gotten here know that. |
1304 | *(a + b) | |
48e1416a | 1305 | |
3072d30e | 1306 | ... = (a + b) |
48e1416a | 1307 | |
3072d30e | 1308 | We also know that the lhs of the inc is not b. We need to make |
1309 | sure that there are no assignments to b between the mem ref and | |
1310 | the inc. */ | |
48e1416a | 1311 | other_insn |
3072d30e | 1312 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def); |
1313 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1314 | return false; | |
1315 | } | |
1316 | } | |
1317 | ||
1318 | if (inc_insn.form == FORM_POST_INC) | |
1319 | { | |
48e1416a | 1320 | other_insn |
3072d30e | 1321 | = get_next_ref (REGNO (inc_insn.reg0), bb, reg_next_use); |
1322 | /* When we found inc_insn, we were looking for the | |
1323 | next add or inc, not the next insn that used the | |
1324 | reg. Because we are going to increment the reg | |
1325 | in this form, we need to make sure that there | |
6dfdc153 | 1326 | were no intervening uses of reg. */ |
3072d30e | 1327 | if (inc_insn.insn != other_insn) |
1328 | return false; | |
1329 | } | |
1330 | ||
1331 | return try_merge (); | |
1332 | } | |
1333 | ||
1334 | ||
1335 | /* A recursive function that walks ADDRESS_OF_X to find all of the mem | |
1336 | uses in pat that could be used as an auto inc or dec. It then | |
1337 | calls FIND_INC for each one. */ | |
1338 | ||
1339 | static bool | |
1340 | find_mem (rtx *address_of_x) | |
1341 | { | |
1342 | rtx x = *address_of_x; | |
1343 | enum rtx_code code = GET_CODE (x); | |
1344 | const char *const fmt = GET_RTX_FORMAT (code); | |
1345 | int i; | |
1346 | ||
1347 | if (code == MEM && REG_P (XEXP (x, 0))) | |
1348 | { | |
1349 | /* Match with *reg0. */ | |
1350 | mem_insn.mem_loc = address_of_x; | |
1351 | mem_insn.reg0 = XEXP (x, 0); | |
1352 | mem_insn.reg1_is_const = true; | |
1353 | mem_insn.reg1_val = 0; | |
1354 | mem_insn.reg1 = GEN_INT (0); | |
1355 | if (find_inc (true)) | |
1356 | return true; | |
1357 | } | |
1358 | if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS | |
1359 | && REG_P (XEXP (XEXP (x, 0), 0))) | |
1360 | { | |
1361 | rtx reg1 = XEXP (XEXP (x, 0), 1); | |
1362 | mem_insn.mem_loc = address_of_x; | |
1363 | mem_insn.reg0 = XEXP (XEXP (x, 0), 0); | |
1364 | mem_insn.reg1 = reg1; | |
971ba038 | 1365 | if (CONST_INT_P (reg1)) |
3072d30e | 1366 | { |
1367 | mem_insn.reg1_is_const = true; | |
1368 | /* Match with *(reg0 + c) where c is a const. */ | |
1369 | mem_insn.reg1_val = INTVAL (reg1); | |
1370 | if (find_inc (true)) | |
1371 | return true; | |
1372 | } | |
1373 | else if (REG_P (reg1)) | |
1374 | { | |
1375 | /* Match with *(reg0 + reg1). */ | |
1376 | mem_insn.reg1_is_const = false; | |
1377 | if (find_inc (true)) | |
1378 | return true; | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) | |
1383 | { | |
1384 | /* If REG occurs inside a MEM used in a bit-field reference, | |
1385 | that is unacceptable. */ | |
1386 | return false; | |
1387 | } | |
1388 | ||
1389 | /* Time for some deep diving. */ | |
1390 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1391 | { | |
1392 | if (fmt[i] == 'e') | |
1393 | { | |
1394 | if (find_mem (&XEXP (x, i))) | |
1395 | return true; | |
1396 | } | |
1397 | else if (fmt[i] == 'E') | |
1398 | { | |
1399 | int j; | |
1400 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1401 | if (find_mem (&XVECEXP (x, i, j))) | |
1402 | return true; | |
1403 | } | |
1404 | } | |
1405 | return false; | |
1406 | } | |
1407 | ||
1408 | ||
1409 | /* Try to combine all incs and decs by constant values with memory | |
1410 | references in BB. */ | |
1411 | ||
1412 | static void | |
1413 | merge_in_block (int max_reg, basic_block bb) | |
1414 | { | |
4db65708 | 1415 | rtx_insn *insn; |
1416 | rtx_insn *curr; | |
3072d30e | 1417 | int success_in_block = 0; |
1418 | ||
1419 | if (dump_file) | |
1420 | fprintf (dump_file, "\n\nstarting bb %d\n", bb->index); | |
1421 | ||
1422 | FOR_BB_INSNS_REVERSE_SAFE (bb, insn, curr) | |
1423 | { | |
3072d30e | 1424 | bool insn_is_add_or_inc = true; |
1425 | ||
9845d120 | 1426 | if (!NONDEBUG_INSN_P (insn)) |
f21023fe | 1427 | { |
1428 | if (DEBUG_BIND_INSN_P (insn)) | |
1429 | { | |
1430 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); | |
1431 | df_ref use; | |
1432 | ||
1433 | if (dump_file) | |
1434 | dump_insn_slim (dump_file, insn); | |
1435 | ||
1436 | FOR_EACH_INSN_INFO_USE (use, insn_info) | |
1437 | reg_next_debug_use[DF_REF_REGNO (use)] = insn; | |
1438 | } | |
1439 | continue; | |
1440 | } | |
3072d30e | 1441 | |
1442 | /* This continue is deliberate. We do not want the uses of the | |
48e1416a | 1443 | jump put into reg_next_use because it is not considered safe to |
3072d30e | 1444 | combine a preincrement with a jump. */ |
1445 | if (JUMP_P (insn)) | |
1446 | continue; | |
1447 | ||
1448 | if (dump_file) | |
1449 | dump_insn_slim (dump_file, insn); | |
1450 | ||
1451 | /* Does this instruction increment or decrement a register? */ | |
1452 | if (parse_add_or_inc (insn, true)) | |
1453 | { | |
1454 | int regno = REGNO (inc_insn.reg_res); | |
1455 | /* Cannot handle case where there are three separate regs | |
1456 | before a mem ref. Too many moves would be needed to be | |
1457 | profitable. */ | |
1458 | if ((inc_insn.form == FORM_PRE_INC) || inc_insn.reg1_is_const) | |
1459 | { | |
1460 | mem_insn.insn = get_next_ref (regno, bb, reg_next_use); | |
1461 | if (mem_insn.insn) | |
1462 | { | |
1463 | bool ok = true; | |
1464 | if (!inc_insn.reg1_is_const) | |
1465 | { | |
1466 | /* We are only here if we are going to try a | |
1467 | HAVE_*_MODIFY_REG type transformation. c is a | |
1468 | reg and we must sure that the path from the | |
1469 | inc_insn to the mem_insn.insn is both def and use | |
1470 | clear of c because the inc insn is going to move | |
1471 | into the mem_insn.insn. */ | |
1472 | int luid = DF_INSN_LUID (mem_insn.insn); | |
4db65708 | 1473 | rtx_insn *other_insn |
3072d30e | 1474 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_use); |
48e1416a | 1475 | |
3072d30e | 1476 | if (other_insn && luid > DF_INSN_LUID (other_insn)) |
1477 | ok = false; | |
48e1416a | 1478 | |
1479 | other_insn | |
3072d30e | 1480 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def); |
48e1416a | 1481 | |
3072d30e | 1482 | if (other_insn && luid > DF_INSN_LUID (other_insn)) |
1483 | ok = false; | |
1484 | } | |
48e1416a | 1485 | |
3072d30e | 1486 | if (dump_file) |
1487 | dump_inc_insn (dump_file); | |
48e1416a | 1488 | |
d4ce94c1 | 1489 | if (ok && find_address (&PATTERN (mem_insn.insn), |
1490 | inc_insn.reg_res) == -1) | |
1491 | { | |
1492 | if (dump_file) | |
1493 | dump_mem_insn (dump_file); | |
1494 | if (try_merge ()) | |
1495 | { | |
1496 | success_in_block++; | |
1497 | insn_is_add_or_inc = false; | |
1498 | } | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | if (insn_is_add_or_inc | |
1503 | /* find_address will only recognize an address | |
1504 | with a reg0 that's not reg_res when | |
1505 | reg1_is_const, so cut it off early if we | |
1506 | already know it won't match. */ | |
1507 | && inc_insn.reg1_is_const | |
1508 | && inc_insn.reg0 | |
1509 | && inc_insn.reg0 != inc_insn.reg_res) | |
1510 | { | |
1511 | /* If we identified an inc_insn that uses two | |
1512 | different pseudos, it's of the form | |
1513 | ||
1514 | (set reg_res (plus reg0 reg1)) | |
1515 | ||
1516 | where reg1 is a constant (*). | |
1517 | ||
f21023fe | 1518 | The next use of reg_res was not identified by |
d4ce94c1 | 1519 | find_address as a mem_insn that we could turn |
1520 | into auto-inc, so see if we find a suitable | |
1521 | MEM in the next use of reg0, as long as it's | |
1522 | before any subsequent use of reg_res: | |
1523 | ||
1524 | ... (mem (... reg0 ...)) ... | |
1525 | ||
1526 | ... reg_res ... | |
1527 | ||
1528 | In this case, we can turn the plus into a | |
1529 | copy, and the reg0 in the MEM address into a | |
1530 | post_inc of reg_res: | |
1531 | ||
1532 | (set reg_res reg0) | |
1533 | ||
1534 | ... (mem (... (post_add reg_res reg1) ...)) ... | |
1535 | ||
1536 | reg_res will then have the correct value at | |
1537 | subsequent uses, and reg0 will remain | |
1538 | unchanged. | |
1539 | ||
1540 | (*) We could support non-const reg1, but then | |
1541 | we'd have to check that reg1 remains | |
1542 | unchanged all the way to the modified MEM, | |
1543 | and we'd have to extend find_address to | |
1544 | represent a non-const negated reg1. */ | |
1545 | regno = REGNO (inc_insn.reg0); | |
1546 | rtx_insn *reg0_use = get_next_ref (regno, bb, | |
1547 | reg_next_use); | |
1548 | ||
1549 | /* Give up if the next use of reg0 is after the next | |
1550 | use of reg_res (same insn is ok; we might have | |
1551 | found a MEM with reg_res before, and that failed, | |
1552 | but now we try reg0, which might work), or defs | |
1553 | of reg_res (same insn is not ok, we'd introduce | |
1554 | another def in the same insn) or reg0. */ | |
1555 | if (reg0_use) | |
1556 | { | |
1557 | int luid = DF_INSN_LUID (reg0_use); | |
1558 | ||
1559 | /* It might seem pointless to introduce an | |
1560 | auto-inc if there's no subsequent use of | |
1561 | reg_res (i.e., mem_insn.insn == NULL), but | |
1562 | the next use might be in the next iteration | |
1563 | of a loop, and it won't hurt if we make the | |
1564 | change even if it's not needed. */ | |
1565 | if (mem_insn.insn | |
1566 | && luid > DF_INSN_LUID (mem_insn.insn)) | |
1567 | reg0_use = NULL; | |
1568 | ||
1569 | rtx_insn *other_insn | |
1570 | = get_next_ref (REGNO (inc_insn.reg_res), bb, | |
1571 | reg_next_def); | |
1572 | ||
1573 | if (other_insn && luid >= DF_INSN_LUID (other_insn)) | |
1574 | reg0_use = NULL; | |
1575 | ||
1576 | other_insn | |
1577 | = get_next_ref (REGNO (inc_insn.reg0), bb, | |
1578 | reg_next_def); | |
1579 | ||
1580 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1581 | reg0_use = NULL; | |
1582 | } | |
1583 | ||
1584 | mem_insn.insn = reg0_use; | |
1585 | ||
1586 | if (mem_insn.insn | |
1587 | && find_address (&PATTERN (mem_insn.insn), | |
1588 | inc_insn.reg0) == -1) | |
3072d30e | 1589 | { |
1590 | if (dump_file) | |
1591 | dump_mem_insn (dump_file); | |
1592 | if (try_merge ()) | |
1593 | { | |
1594 | success_in_block++; | |
1595 | insn_is_add_or_inc = false; | |
1596 | } | |
1597 | } | |
1598 | } | |
1599 | } | |
1600 | } | |
1601 | else | |
1602 | { | |
1603 | insn_is_add_or_inc = false; | |
1604 | mem_insn.insn = insn; | |
1605 | if (find_mem (&PATTERN (insn))) | |
1606 | success_in_block++; | |
1607 | } | |
48e1416a | 1608 | |
3072d30e | 1609 | /* If the inc insn was merged with a mem, the inc insn is gone |
1610 | and there is noting to update. */ | |
e8403abd | 1611 | if (df_insn_info *insn_info = DF_INSN_INFO_GET (insn)) |
3072d30e | 1612 | { |
be10bb5a | 1613 | df_ref def, use; |
1614 | ||
3072d30e | 1615 | /* Need to update next use. */ |
be10bb5a | 1616 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
3072d30e | 1617 | { |
f21023fe | 1618 | if (reg_next_debug_use) |
1619 | reg_next_debug_use[DF_REF_REGNO (def)] = NULL; | |
3072d30e | 1620 | reg_next_use[DF_REF_REGNO (def)] = NULL; |
1621 | reg_next_inc_use[DF_REF_REGNO (def)] = NULL; | |
1622 | reg_next_def[DF_REF_REGNO (def)] = insn; | |
1623 | } | |
48e1416a | 1624 | |
be10bb5a | 1625 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
3072d30e | 1626 | { |
f21023fe | 1627 | if (reg_next_debug_use) |
1628 | /* This may seem surprising, but we know we may only | |
1629 | modify the value of a REG between an insn and the | |
1630 | next nondebug use thereof. Any debug uses after | |
1631 | the next nondebug use can be left alone, the REG | |
1632 | will hold the expected value there. */ | |
1633 | reg_next_debug_use[DF_REF_REGNO (use)] = NULL; | |
3072d30e | 1634 | reg_next_use[DF_REF_REGNO (use)] = insn; |
1635 | if (insn_is_add_or_inc) | |
1636 | reg_next_inc_use[DF_REF_REGNO (use)] = insn; | |
1637 | else | |
1638 | reg_next_inc_use[DF_REF_REGNO (use)] = NULL; | |
48e1416a | 1639 | } |
3072d30e | 1640 | } |
1641 | else if (dump_file) | |
e8403abd | 1642 | fprintf (dump_file, "skipping update of deleted insn %d\n", |
1643 | INSN_UID (insn)); | |
3072d30e | 1644 | } |
1645 | ||
1646 | /* If we were successful, try again. There may have been several | |
1647 | opportunities that were interleaved. This is rare but | |
1648 | gcc.c-torture/compile/pr17273.c actually exhibits this. */ | |
1649 | if (success_in_block) | |
1650 | { | |
1651 | /* In this case, we must clear these vectors since the trick of | |
1652 | testing if the stale insn in the block will not work. */ | |
f21023fe | 1653 | if (reg_next_debug_use) |
1654 | memset (reg_next_debug_use, 0, max_reg * sizeof (rtx)); | |
9af5ce0c | 1655 | memset (reg_next_use, 0, max_reg * sizeof (rtx)); |
1656 | memset (reg_next_inc_use, 0, max_reg * sizeof (rtx)); | |
1657 | memset (reg_next_def, 0, max_reg * sizeof (rtx)); | |
3072d30e | 1658 | df_recompute_luids (bb); |
1659 | merge_in_block (max_reg, bb); | |
1660 | } | |
1661 | } | |
1662 | ||
3072d30e | 1663 | /* Discover auto-inc auto-dec instructions. */ |
1664 | ||
cbe8bda8 | 1665 | namespace { |
1666 | ||
1667 | const pass_data pass_data_inc_dec = | |
3072d30e | 1668 | { |
cbe8bda8 | 1669 | RTL_PASS, /* type */ |
1670 | "auto_inc_dec", /* name */ | |
1671 | OPTGROUP_NONE, /* optinfo_flags */ | |
cbe8bda8 | 1672 | TV_AUTO_INC_DEC, /* tv_id */ |
1673 | 0, /* properties_required */ | |
1674 | 0, /* properties_provided */ | |
1675 | 0, /* properties_destroyed */ | |
1676 | 0, /* todo_flags_start */ | |
1677 | TODO_df_finish, /* todo_flags_finish */ | |
3072d30e | 1678 | }; |
cbe8bda8 | 1679 | |
1680 | class pass_inc_dec : public rtl_opt_pass | |
1681 | { | |
1682 | public: | |
9af5ce0c | 1683 | pass_inc_dec (gcc::context *ctxt) |
1684 | : rtl_opt_pass (pass_data_inc_dec, ctxt) | |
cbe8bda8 | 1685 | {} |
1686 | ||
1687 | /* opt_pass methods: */ | |
31315c24 | 1688 | virtual bool gate (function *) |
1689 | { | |
32aa77d9 | 1690 | if (!AUTO_INC_DEC) |
1691 | return false; | |
1692 | ||
31315c24 | 1693 | return (optimize > 0 && flag_auto_inc_dec); |
31315c24 | 1694 | } |
1695 | ||
1696 | ||
65b0537f | 1697 | unsigned int execute (function *); |
cbe8bda8 | 1698 | |
1699 | }; // class pass_inc_dec | |
1700 | ||
65b0537f | 1701 | unsigned int |
1702 | pass_inc_dec::execute (function *fun ATTRIBUTE_UNUSED) | |
1703 | { | |
32aa77d9 | 1704 | if (!AUTO_INC_DEC) |
1705 | return 0; | |
1706 | ||
65b0537f | 1707 | basic_block bb; |
1708 | int max_reg = max_reg_num (); | |
1709 | ||
1710 | if (!initialized) | |
1711 | init_decision_table (); | |
1712 | ||
1713 | mem_tmp = gen_rtx_MEM (Pmode, NULL_RTX); | |
1714 | ||
1715 | df_note_add_problem (); | |
1716 | df_analyze (); | |
1717 | ||
f21023fe | 1718 | if (MAY_HAVE_DEBUG_BIND_INSNS) |
1719 | reg_next_debug_use = XCNEWVEC (rtx_insn *, max_reg); | |
1720 | else | |
1721 | /* An earlier function may have had debug binds. */ | |
1722 | reg_next_debug_use = NULL; | |
4db65708 | 1723 | reg_next_use = XCNEWVEC (rtx_insn *, max_reg); |
1724 | reg_next_inc_use = XCNEWVEC (rtx_insn *, max_reg); | |
1725 | reg_next_def = XCNEWVEC (rtx_insn *, max_reg); | |
65b0537f | 1726 | FOR_EACH_BB_FN (bb, fun) |
1727 | merge_in_block (max_reg, bb); | |
1728 | ||
f21023fe | 1729 | free (reg_next_debug_use); |
65b0537f | 1730 | free (reg_next_use); |
1731 | free (reg_next_inc_use); | |
1732 | free (reg_next_def); | |
1733 | ||
1734 | mem_tmp = NULL; | |
32aa77d9 | 1735 | |
65b0537f | 1736 | return 0; |
1737 | } | |
1738 | ||
cbe8bda8 | 1739 | } // anon namespace |
1740 | ||
1741 | rtl_opt_pass * | |
1742 | make_pass_inc_dec (gcc::context *ctxt) | |
1743 | { | |
1744 | return new pass_inc_dec (ctxt); | |
1745 | } |