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6fb5fa3c | 1 | /* Discovery of auto-inc and auto-dec instructions. |
23a5b65a | 2 | Copyright (C) 2006-2014 Free Software Foundation, Inc. |
6fb5fa3c | 3 | Contributed by Kenneth Zadeck <zadeck@naturalbridge.com> |
b8698a0f | 4 | |
6fb5fa3c DB |
5 | This file is part of GCC. |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 9 | Software Foundation; either version 3, or (at your option) any later |
6fb5fa3c DB |
10 | version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
6fb5fa3c DB |
20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
25 | #include "tree.h" | |
26 | #include "rtl.h" | |
27 | #include "tm_p.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "basic-block.h" | |
30 | #include "insn-config.h" | |
31 | #include "regs.h" | |
32 | #include "flags.h" | |
83685514 AM |
33 | #include "hashtab.h" |
34 | #include "hash-set.h" | |
35 | #include "vec.h" | |
36 | #include "machmode.h" | |
37 | #include "input.h" | |
6fb5fa3c DB |
38 | #include "function.h" |
39 | #include "except.h" | |
718f9c0f | 40 | #include "diagnostic-core.h" |
6fb5fa3c DB |
41 | #include "recog.h" |
42 | #include "expr.h" | |
6fb5fa3c DB |
43 | #include "tree-pass.h" |
44 | #include "df.h" | |
45 | #include "dbgcnt.h" | |
d4ebfa65 | 46 | #include "target.h" |
6fb5fa3c DB |
47 | |
48 | /* This pass was originally removed from flow.c. However there is | |
49 | almost nothing that remains of that code. | |
50 | ||
51 | There are (4) basic forms that are matched: | |
52 | ||
1154c4fa | 53 | (1) FORM_PRE_ADD |
6fb5fa3c DB |
54 | a <- b + c |
55 | ... | |
56 | *a | |
57 | ||
58 | becomes | |
59 | ||
60 | a <- b | |
61 | ... | |
62 | *(a += c) pre | |
1154c4fa SB |
63 | |
64 | ||
65 | (2) FORM_PRE_INC | |
6fb5fa3c DB |
66 | a += c |
67 | ... | |
68 | *a | |
69 | ||
70 | becomes | |
71 | ||
72 | *(a += c) pre | |
1154c4fa SB |
73 | |
74 | ||
75 | (3) FORM_POST_ADD | |
6fb5fa3c DB |
76 | *a |
77 | ... | |
78 | b <- a + c | |
79 | ||
b8698a0f | 80 | (For this case to be true, b must not be assigned or used between |
1154c4fa | 81 | the *a and the assignment to b. B must also be a Pmode reg.) |
6fb5fa3c DB |
82 | |
83 | becomes | |
84 | ||
85 | b <- a | |
86 | ... | |
87 | *(b += c) post | |
1154c4fa SB |
88 | |
89 | ||
90 | (4) FORM_POST_INC | |
6fb5fa3c DB |
91 | *a |
92 | ... | |
93 | a <- a + c | |
94 | ||
95 | becomes | |
96 | ||
97 | *(a += c) post | |
98 | ||
99 | There are three types of values of c. | |
100 | ||
101 | 1) c is a constant equal to the width of the value being accessed by | |
102 | the pointer. This is useful for machines that have | |
103 | HAVE_PRE_INCREMENT, HAVE_POST_INCREMENT, HAVE_PRE_DECREMENT or | |
104 | HAVE_POST_DECREMENT defined. | |
105 | ||
0d52bcc1 | 106 | 2) c is a constant not equal to the width of the value being accessed |
6fb5fa3c DB |
107 | by the pointer. This is useful for machines that have |
108 | HAVE_PRE_MODIFY_DISP, HAVE_POST_MODIFY_DISP defined. | |
109 | ||
b8698a0f L |
110 | 3) c is a register. This is useful for machines that have |
111 | HAVE_PRE_MODIFY_REG, HAVE_POST_MODIFY_REG | |
112 | ||
6fb5fa3c DB |
113 | The is one special case: if a already had an offset equal to it +- |
114 | its width and that offset is equal to -c when the increment was | |
115 | before the ref or +c if the increment was after the ref, then if we | |
1154c4fa | 116 | can do the combination but switch the pre/post bit. */ |
6fb5fa3c | 117 | |
6fb5fa3c DB |
118 | #ifdef AUTO_INC_DEC |
119 | ||
120 | enum form | |
121 | { | |
122 | FORM_PRE_ADD, | |
123 | FORM_PRE_INC, | |
124 | FORM_POST_ADD, | |
125 | FORM_POST_INC, | |
126 | FORM_last | |
127 | }; | |
128 | ||
129 | /* The states of the second operands of mem refs and inc insns. If no | |
130 | second operand of the mem_ref was found, it is assumed to just be | |
131 | ZERO. SIZE is the size of the mode accessed in the memref. The | |
132 | ANY is used for constants that are not +-size or 0. REG is used if | |
133 | the forms are reg1 + reg2. */ | |
134 | ||
b8698a0f | 135 | enum inc_state |
6fb5fa3c DB |
136 | { |
137 | INC_ZERO, /* == 0 */ | |
138 | INC_NEG_SIZE, /* == +size */ | |
139 | INC_POS_SIZE, /* == -size */ | |
140 | INC_NEG_ANY, /* == some -constant */ | |
141 | INC_POS_ANY, /* == some +constant */ | |
142 | INC_REG, /* == some register */ | |
143 | INC_last | |
144 | }; | |
145 | ||
146 | /* The eight forms that pre/post inc/dec can take. */ | |
147 | enum gen_form | |
148 | { | |
149 | NOTHING, | |
150 | SIMPLE_PRE_INC, /* ++size */ | |
151 | SIMPLE_POST_INC, /* size++ */ | |
152 | SIMPLE_PRE_DEC, /* --size */ | |
153 | SIMPLE_POST_DEC, /* size-- */ | |
154 | DISP_PRE, /* ++con */ | |
155 | DISP_POST, /* con++ */ | |
156 | REG_PRE, /* ++reg */ | |
157 | REG_POST /* reg++ */ | |
158 | }; | |
159 | ||
160 | /* Tmp mem rtx for use in cost modeling. */ | |
161 | static rtx mem_tmp; | |
162 | ||
163 | static enum inc_state | |
164 | set_inc_state (HOST_WIDE_INT val, int size) | |
165 | { | |
166 | if (val == 0) | |
167 | return INC_ZERO; | |
168 | if (val < 0) | |
169 | return (val == -size) ? INC_NEG_SIZE : INC_NEG_ANY; | |
170 | else | |
171 | return (val == size) ? INC_POS_SIZE : INC_POS_ANY; | |
172 | } | |
173 | ||
174 | /* The DECISION_TABLE that describes what form, if any, the increment | |
175 | or decrement will take. It is a three dimensional table. The first | |
176 | index is the type of constant or register found as the second | |
177 | operand of the inc insn. The second index is the type of constant | |
178 | or register found as the second operand of the memory reference (if | |
179 | no second operand exists, 0 is used). The third index is the form | |
180 | and location (relative to the mem reference) of inc insn. */ | |
181 | ||
182 | static bool initialized = false; | |
183 | static enum gen_form decision_table[INC_last][INC_last][FORM_last]; | |
184 | ||
185 | static void | |
186 | init_decision_table (void) | |
187 | { | |
188 | enum gen_form value; | |
189 | ||
190 | if (HAVE_PRE_INCREMENT || HAVE_PRE_MODIFY_DISP) | |
191 | { | |
192 | /* Prefer the simple form if both are available. */ | |
193 | value = (HAVE_PRE_INCREMENT) ? SIMPLE_PRE_INC : DISP_PRE; | |
194 | ||
195 | decision_table[INC_POS_SIZE][INC_ZERO][FORM_PRE_ADD] = value; | |
196 | decision_table[INC_POS_SIZE][INC_ZERO][FORM_PRE_INC] = value; | |
197 | ||
198 | decision_table[INC_POS_SIZE][INC_POS_SIZE][FORM_POST_ADD] = value; | |
199 | decision_table[INC_POS_SIZE][INC_POS_SIZE][FORM_POST_INC] = value; | |
200 | } | |
201 | ||
202 | if (HAVE_POST_INCREMENT || HAVE_POST_MODIFY_DISP) | |
203 | { | |
204 | /* Prefer the simple form if both are available. */ | |
205 | value = (HAVE_POST_INCREMENT) ? SIMPLE_POST_INC : DISP_POST; | |
206 | ||
207 | decision_table[INC_POS_SIZE][INC_ZERO][FORM_POST_ADD] = value; | |
208 | decision_table[INC_POS_SIZE][INC_ZERO][FORM_POST_INC] = value; | |
209 | ||
210 | decision_table[INC_POS_SIZE][INC_NEG_SIZE][FORM_PRE_ADD] = value; | |
211 | decision_table[INC_POS_SIZE][INC_NEG_SIZE][FORM_PRE_INC] = value; | |
212 | } | |
213 | ||
214 | if (HAVE_PRE_DECREMENT || HAVE_PRE_MODIFY_DISP) | |
215 | { | |
216 | /* Prefer the simple form if both are available. */ | |
217 | value = (HAVE_PRE_DECREMENT) ? SIMPLE_PRE_DEC : DISP_PRE; | |
218 | ||
219 | decision_table[INC_NEG_SIZE][INC_ZERO][FORM_PRE_ADD] = value; | |
220 | decision_table[INC_NEG_SIZE][INC_ZERO][FORM_PRE_INC] = value; | |
221 | ||
222 | decision_table[INC_NEG_SIZE][INC_NEG_SIZE][FORM_POST_ADD] = value; | |
223 | decision_table[INC_NEG_SIZE][INC_NEG_SIZE][FORM_POST_INC] = value; | |
224 | } | |
225 | ||
226 | if (HAVE_POST_DECREMENT || HAVE_POST_MODIFY_DISP) | |
227 | { | |
228 | /* Prefer the simple form if both are available. */ | |
229 | value = (HAVE_POST_DECREMENT) ? SIMPLE_POST_DEC : DISP_POST; | |
230 | ||
231 | decision_table[INC_NEG_SIZE][INC_ZERO][FORM_POST_ADD] = value; | |
232 | decision_table[INC_NEG_SIZE][INC_ZERO][FORM_POST_INC] = value; | |
233 | ||
234 | decision_table[INC_NEG_SIZE][INC_POS_SIZE][FORM_PRE_ADD] = value; | |
235 | decision_table[INC_NEG_SIZE][INC_POS_SIZE][FORM_PRE_INC] = value; | |
236 | } | |
237 | ||
238 | if (HAVE_PRE_MODIFY_DISP) | |
239 | { | |
240 | decision_table[INC_POS_ANY][INC_ZERO][FORM_PRE_ADD] = DISP_PRE; | |
241 | decision_table[INC_POS_ANY][INC_ZERO][FORM_PRE_INC] = DISP_PRE; | |
242 | ||
243 | decision_table[INC_POS_ANY][INC_POS_ANY][FORM_POST_ADD] = DISP_PRE; | |
244 | decision_table[INC_POS_ANY][INC_POS_ANY][FORM_POST_INC] = DISP_PRE; | |
245 | ||
246 | decision_table[INC_NEG_ANY][INC_ZERO][FORM_PRE_ADD] = DISP_PRE; | |
247 | decision_table[INC_NEG_ANY][INC_ZERO][FORM_PRE_INC] = DISP_PRE; | |
248 | ||
249 | decision_table[INC_NEG_ANY][INC_NEG_ANY][FORM_POST_ADD] = DISP_PRE; | |
250 | decision_table[INC_NEG_ANY][INC_NEG_ANY][FORM_POST_INC] = DISP_PRE; | |
251 | } | |
252 | ||
253 | if (HAVE_POST_MODIFY_DISP) | |
254 | { | |
255 | decision_table[INC_POS_ANY][INC_ZERO][FORM_POST_ADD] = DISP_POST; | |
256 | decision_table[INC_POS_ANY][INC_ZERO][FORM_POST_INC] = DISP_POST; | |
257 | ||
258 | decision_table[INC_POS_ANY][INC_NEG_ANY][FORM_PRE_ADD] = DISP_POST; | |
259 | decision_table[INC_POS_ANY][INC_NEG_ANY][FORM_PRE_INC] = DISP_POST; | |
260 | ||
261 | decision_table[INC_NEG_ANY][INC_ZERO][FORM_POST_ADD] = DISP_POST; | |
262 | decision_table[INC_NEG_ANY][INC_ZERO][FORM_POST_INC] = DISP_POST; | |
263 | ||
264 | decision_table[INC_NEG_ANY][INC_POS_ANY][FORM_PRE_ADD] = DISP_POST; | |
265 | decision_table[INC_NEG_ANY][INC_POS_ANY][FORM_PRE_INC] = DISP_POST; | |
266 | } | |
267 | ||
268 | /* This is much simpler than the other cases because we do not look | |
269 | for the reg1-reg2 case. Note that we do not have a INC_POS_REG | |
270 | and INC_NEG_REG states. Most of the use of such states would be | |
271 | on a target that had an R1 - R2 update address form. | |
272 | ||
273 | There is the remote possibility that you could also catch a = a + | |
274 | b; *(a - b) as a postdecrement of (a + b). However, it is | |
275 | unclear if *(a - b) would ever be generated on a machine that did | |
276 | not have that kind of addressing mode. The IA-64 and RS6000 will | |
277 | not do this, and I cannot speak for any other. If any | |
278 | architecture does have an a-b update for, these cases should be | |
279 | added. */ | |
280 | if (HAVE_PRE_MODIFY_REG) | |
281 | { | |
282 | decision_table[INC_REG][INC_ZERO][FORM_PRE_ADD] = REG_PRE; | |
283 | decision_table[INC_REG][INC_ZERO][FORM_PRE_INC] = REG_PRE; | |
284 | ||
285 | decision_table[INC_REG][INC_REG][FORM_POST_ADD] = REG_PRE; | |
286 | decision_table[INC_REG][INC_REG][FORM_POST_INC] = REG_PRE; | |
287 | } | |
288 | ||
289 | if (HAVE_POST_MODIFY_REG) | |
290 | { | |
291 | decision_table[INC_REG][INC_ZERO][FORM_POST_ADD] = REG_POST; | |
292 | decision_table[INC_REG][INC_ZERO][FORM_POST_INC] = REG_POST; | |
293 | } | |
294 | ||
295 | initialized = true; | |
296 | } | |
297 | ||
298 | /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or | |
299 | "reg_res = reg0+c". */ | |
300 | ||
b8698a0f | 301 | static struct inc_insn |
6fb5fa3c | 302 | { |
3dfa938f | 303 | rtx_insn *insn; /* The insn being parsed. */ |
6fb5fa3c DB |
304 | rtx pat; /* The pattern of the insn. */ |
305 | bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */ | |
306 | enum form form; | |
307 | rtx reg_res; | |
308 | rtx reg0; | |
309 | rtx reg1; | |
310 | enum inc_state reg1_state;/* The form of the const if reg1 is a const. */ | |
311 | HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */ | |
312 | } inc_insn; | |
313 | ||
314 | ||
315 | /* Dump the parsed inc insn to FILE. */ | |
316 | ||
b8698a0f | 317 | static void |
6fb5fa3c DB |
318 | dump_inc_insn (FILE *file) |
319 | { | |
b8698a0f | 320 | const char *f = ((inc_insn.form == FORM_PRE_ADD) |
6fb5fa3c DB |
321 | || (inc_insn.form == FORM_PRE_INC)) ? "pre" : "post"; |
322 | ||
323 | dump_insn_slim (file, inc_insn.insn); | |
324 | ||
325 | switch (inc_insn.form) | |
326 | { | |
327 | case FORM_PRE_ADD: | |
328 | case FORM_POST_ADD: | |
329 | if (inc_insn.reg1_is_const) | |
b8698a0f L |
330 | fprintf (file, "found %s add(%d) r[%d]=r[%d]+%d\n", |
331 | f, INSN_UID (inc_insn.insn), | |
332 | REGNO (inc_insn.reg_res), | |
6fb5fa3c DB |
333 | REGNO (inc_insn.reg0), (int) inc_insn.reg1_val); |
334 | else | |
b8698a0f L |
335 | fprintf (file, "found %s add(%d) r[%d]=r[%d]+r[%d]\n", |
336 | f, INSN_UID (inc_insn.insn), | |
337 | REGNO (inc_insn.reg_res), | |
6fb5fa3c DB |
338 | REGNO (inc_insn.reg0), REGNO (inc_insn.reg1)); |
339 | break; | |
b8698a0f | 340 | |
6fb5fa3c DB |
341 | case FORM_PRE_INC: |
342 | case FORM_POST_INC: | |
343 | if (inc_insn.reg1_is_const) | |
b8698a0f L |
344 | fprintf (file, "found %s inc(%d) r[%d]+=%d\n", |
345 | f, INSN_UID (inc_insn.insn), | |
6fb5fa3c DB |
346 | REGNO (inc_insn.reg_res), (int) inc_insn.reg1_val); |
347 | else | |
b8698a0f L |
348 | fprintf (file, "found %s inc(%d) r[%d]+=r[%d]\n", |
349 | f, INSN_UID (inc_insn.insn), | |
6fb5fa3c DB |
350 | REGNO (inc_insn.reg_res), REGNO (inc_insn.reg1)); |
351 | break; | |
352 | ||
353 | default: | |
354 | break; | |
355 | } | |
356 | } | |
357 | ||
358 | ||
359 | /* Parsed fields of a mem ref of the form "*(reg0+reg1)" or "*(reg0+c)". */ | |
360 | ||
361 | static struct mem_insn | |
362 | { | |
3dfa938f | 363 | rtx_insn *insn; /* The insn being parsed. */ |
6fb5fa3c DB |
364 | rtx pat; /* The pattern of the insn. */ |
365 | rtx *mem_loc; /* The address of the field that holds the mem */ | |
366 | /* that is to be replaced. */ | |
367 | bool reg1_is_const; /* True if reg1 is const, false if reg1 is a reg. */ | |
368 | rtx reg0; | |
369 | rtx reg1; /* This is either a reg or a const depending on | |
370 | reg1_is_const. */ | |
371 | enum inc_state reg1_state;/* The form of the const if reg1 is a const. */ | |
372 | HOST_WIDE_INT reg1_val;/* Value if reg1 is const. */ | |
373 | } mem_insn; | |
374 | ||
375 | ||
376 | /* Dump the parsed mem insn to FILE. */ | |
377 | ||
b8698a0f | 378 | static void |
6fb5fa3c DB |
379 | dump_mem_insn (FILE *file) |
380 | { | |
381 | dump_insn_slim (file, mem_insn.insn); | |
382 | ||
383 | if (mem_insn.reg1_is_const) | |
b8698a0f L |
384 | fprintf (file, "found mem(%d) *(r[%d]+%d)\n", |
385 | INSN_UID (mem_insn.insn), | |
6fb5fa3c DB |
386 | REGNO (mem_insn.reg0), (int) mem_insn.reg1_val); |
387 | else | |
b8698a0f L |
388 | fprintf (file, "found mem(%d) *(r[%d]+r[%d])\n", |
389 | INSN_UID (mem_insn.insn), | |
6fb5fa3c DB |
390 | REGNO (mem_insn.reg0), REGNO (mem_insn.reg1)); |
391 | } | |
392 | ||
393 | ||
394 | /* The following three arrays contain pointers to instructions. They | |
395 | are indexed by REGNO. At any point in the basic block where we are | |
396 | looking these three arrays contain, respectively, the next insn | |
397 | that uses REGNO, the next inc or add insn that uses REGNO and the | |
398 | next insn that sets REGNO. | |
399 | ||
400 | The arrays are not cleared when we move from block to block so | |
401 | whenever an insn is retrieved from these arrays, it's block number | |
402 | must be compared with the current block. | |
403 | */ | |
404 | ||
3dfa938f DM |
405 | static rtx_insn **reg_next_use = NULL; |
406 | static rtx_insn **reg_next_inc_use = NULL; | |
407 | static rtx_insn **reg_next_def = NULL; | |
6fb5fa3c DB |
408 | |
409 | ||
410 | /* Move dead note that match PATTERN to TO_INSN from FROM_INSN. We do | |
411 | not really care about moving any other notes from the inc or add | |
412 | insn. Moving the REG_EQUAL and REG_EQUIV is clearly wrong and it | |
0d52bcc1 | 413 | does not appear that there are any other kinds of relevant notes. */ |
6fb5fa3c | 414 | |
b8698a0f | 415 | static void |
3dfa938f | 416 | move_dead_notes (rtx_insn *to_insn, rtx_insn *from_insn, rtx pattern) |
6fb5fa3c | 417 | { |
b8698a0f | 418 | rtx note; |
6fb5fa3c DB |
419 | rtx next_note; |
420 | rtx prev_note = NULL; | |
421 | ||
422 | for (note = REG_NOTES (from_insn); note; note = next_note) | |
423 | { | |
424 | next_note = XEXP (note, 1); | |
b8698a0f | 425 | |
6fb5fa3c DB |
426 | if ((REG_NOTE_KIND (note) == REG_DEAD) |
427 | && pattern == XEXP (note, 0)) | |
428 | { | |
429 | XEXP (note, 1) = REG_NOTES (to_insn); | |
430 | REG_NOTES (to_insn) = note; | |
431 | if (prev_note) | |
432 | XEXP (prev_note, 1) = next_note; | |
433 | else | |
434 | REG_NOTES (from_insn) = next_note; | |
435 | } | |
436 | else prev_note = note; | |
437 | } | |
438 | } | |
439 | ||
440 | ||
441 | /* Create a mov insn DEST_REG <- SRC_REG and insert it before | |
442 | NEXT_INSN. */ | |
443 | ||
3dfa938f DM |
444 | static rtx_insn * |
445 | insert_move_insn_before (rtx_insn *next_insn, rtx dest_reg, rtx src_reg) | |
6fb5fa3c | 446 | { |
3dfa938f | 447 | rtx_insn *insns; |
6fb5fa3c DB |
448 | |
449 | start_sequence (); | |
450 | emit_move_insn (dest_reg, src_reg); | |
451 | insns = get_insns (); | |
452 | end_sequence (); | |
453 | emit_insn_before (insns, next_insn); | |
454 | return insns; | |
455 | } | |
456 | ||
b8698a0f | 457 | |
6fb5fa3c DB |
458 | /* Change mem_insn.mem_loc so that uses NEW_ADDR which has an |
459 | increment of INC_REG. To have reached this point, the change is a | |
460 | legitimate one from a dataflow point of view. The only questions | |
461 | are is this a valid change to the instruction and is this a | |
462 | profitable change to the instruction. */ | |
463 | ||
464 | static bool | |
465 | attempt_change (rtx new_addr, rtx inc_reg) | |
466 | { | |
467 | /* There are four cases: For the two cases that involve an add | |
468 | instruction, we are going to have to delete the add and insert a | |
469 | mov. We are going to assume that the mov is free. This is | |
470 | fairly early in the backend and there are a lot of opportunities | |
471 | for removing that move later. In particular, there is the case | |
472 | where the move may be dead, this is what dead code elimination | |
473 | passes are for. The two cases where we have an inc insn will be | |
474 | handled mov free. */ | |
475 | ||
b0de17ef | 476 | basic_block bb = BLOCK_FOR_INSN (mem_insn.insn); |
3dfa938f | 477 | rtx_insn *mov_insn = NULL; |
6fb5fa3c DB |
478 | int regno; |
479 | rtx mem = *mem_insn.mem_loc; | |
480 | enum machine_mode mode = GET_MODE (mem); | |
481 | rtx new_mem; | |
482 | int old_cost = 0; | |
483 | int new_cost = 0; | |
f40751dd | 484 | bool speed = optimize_bb_for_speed_p (bb); |
6fb5fa3c DB |
485 | |
486 | PUT_MODE (mem_tmp, mode); | |
487 | XEXP (mem_tmp, 0) = new_addr; | |
488 | ||
5e8f01f4 | 489 | old_cost = (set_src_cost (mem, speed) |
d51102f3 | 490 | + set_rtx_cost (PATTERN (inc_insn.insn), speed)); |
5e8f01f4 | 491 | new_cost = set_src_cost (mem_tmp, speed); |
bbbbb16a | 492 | |
6fb5fa3c DB |
493 | /* The first item of business is to see if this is profitable. */ |
494 | if (old_cost < new_cost) | |
495 | { | |
496 | if (dump_file) | |
497 | fprintf (dump_file, "cost failure old=%d new=%d\n", old_cost, new_cost); | |
498 | return false; | |
499 | } | |
500 | ||
073a8998 | 501 | /* Jump through a lot of hoops to keep the attributes up to date. We |
6fb5fa3c DB |
502 | do not want to call one of the change address variants that take |
503 | an offset even though we know the offset in many cases. These | |
504 | assume you are changing where the address is pointing by the | |
505 | offset. */ | |
506 | new_mem = replace_equiv_address_nv (mem, new_addr); | |
507 | if (! validate_change (mem_insn.insn, mem_insn.mem_loc, new_mem, 0)) | |
508 | { | |
509 | if (dump_file) | |
b8698a0f | 510 | fprintf (dump_file, "validation failure\n"); |
6fb5fa3c DB |
511 | return false; |
512 | } | |
513 | ||
514 | /* From here to the end of the function we are committed to the | |
515 | change, i.e. nothing fails. Generate any necessary movs, move | |
516 | any regnotes, and fix up the reg_next_{use,inc_use,def}. */ | |
517 | switch (inc_insn.form) | |
518 | { | |
519 | case FORM_PRE_ADD: | |
c8305c98 KZ |
520 | /* Replace the addition with a move. Do it at the location of |
521 | the addition since the operand of the addition may change | |
522 | before the memory reference. */ | |
b8698a0f | 523 | mov_insn = insert_move_insn_before (inc_insn.insn, |
6fb5fa3c DB |
524 | inc_insn.reg_res, inc_insn.reg0); |
525 | move_dead_notes (mov_insn, inc_insn.insn, inc_insn.reg0); | |
526 | ||
527 | regno = REGNO (inc_insn.reg_res); | |
528 | reg_next_def[regno] = mov_insn; | |
529 | reg_next_use[regno] = NULL; | |
530 | regno = REGNO (inc_insn.reg0); | |
531 | reg_next_use[regno] = mov_insn; | |
532 | df_recompute_luids (bb); | |
533 | break; | |
534 | ||
535 | case FORM_POST_INC: | |
536 | regno = REGNO (inc_insn.reg_res); | |
537 | if (reg_next_use[regno] == reg_next_inc_use[regno]) | |
538 | reg_next_inc_use[regno] = NULL; | |
539 | ||
540 | /* Fallthru. */ | |
541 | case FORM_PRE_INC: | |
542 | regno = REGNO (inc_insn.reg_res); | |
543 | reg_next_def[regno] = mem_insn.insn; | |
544 | reg_next_use[regno] = NULL; | |
545 | ||
546 | break; | |
547 | ||
548 | case FORM_POST_ADD: | |
b8698a0f | 549 | mov_insn = insert_move_insn_before (mem_insn.insn, |
6fb5fa3c DB |
550 | inc_insn.reg_res, inc_insn.reg0); |
551 | move_dead_notes (mov_insn, inc_insn.insn, inc_insn.reg0); | |
552 | ||
553 | /* Do not move anything to the mov insn because the instruction | |
554 | pointer for the main iteration has not yet hit that. It is | |
555 | still pointing to the mem insn. */ | |
556 | regno = REGNO (inc_insn.reg_res); | |
557 | reg_next_def[regno] = mem_insn.insn; | |
558 | reg_next_use[regno] = NULL; | |
559 | ||
560 | regno = REGNO (inc_insn.reg0); | |
561 | reg_next_use[regno] = mem_insn.insn; | |
562 | if ((reg_next_use[regno] == reg_next_inc_use[regno]) | |
563 | || (reg_next_inc_use[regno] == inc_insn.insn)) | |
564 | reg_next_inc_use[regno] = NULL; | |
565 | df_recompute_luids (bb); | |
566 | break; | |
567 | ||
568 | case FORM_last: | |
569 | default: | |
570 | gcc_unreachable (); | |
571 | } | |
572 | ||
573 | if (!inc_insn.reg1_is_const) | |
574 | { | |
575 | regno = REGNO (inc_insn.reg1); | |
576 | reg_next_use[regno] = mem_insn.insn; | |
577 | if ((reg_next_use[regno] == reg_next_inc_use[regno]) | |
578 | || (reg_next_inc_use[regno] == inc_insn.insn)) | |
579 | reg_next_inc_use[regno] = NULL; | |
580 | } | |
581 | ||
582 | delete_insn (inc_insn.insn); | |
583 | ||
584 | if (dump_file && mov_insn) | |
585 | { | |
586 | fprintf (dump_file, "inserting mov "); | |
587 | dump_insn_slim (dump_file, mov_insn); | |
588 | } | |
589 | ||
590 | /* Record that this insn has an implicit side effect. */ | |
65c5f2a6 | 591 | add_reg_note (mem_insn.insn, REG_INC, inc_reg); |
6fb5fa3c DB |
592 | |
593 | if (dump_file) | |
594 | { | |
595 | fprintf (dump_file, "****success "); | |
596 | dump_insn_slim (dump_file, mem_insn.insn); | |
597 | } | |
598 | ||
599 | return true; | |
600 | } | |
601 | ||
602 | ||
603 | /* Try to combine the instruction in INC_INSN with the instruction in | |
604 | MEM_INSN. First the form is determined using the DECISION_TABLE | |
fa10beec | 605 | and the results of parsing the INC_INSN and the MEM_INSN. |
6fb5fa3c DB |
606 | Assuming the form is ok, a prototype new address is built which is |
607 | passed to ATTEMPT_CHANGE for final processing. */ | |
608 | ||
b8698a0f | 609 | static bool |
6fb5fa3c DB |
610 | try_merge (void) |
611 | { | |
612 | enum gen_form gen_form; | |
613 | rtx mem = *mem_insn.mem_loc; | |
614 | rtx inc_reg = inc_insn.form == FORM_POST_ADD ? | |
615 | inc_insn.reg_res : mem_insn.reg0; | |
616 | ||
617 | /* The width of the mem being accessed. */ | |
618 | int size = GET_MODE_SIZE (GET_MODE (mem)); | |
3dfa938f | 619 | rtx_insn *last_insn = NULL; |
d4ebfa65 | 620 | enum machine_mode reg_mode = GET_MODE (inc_reg); |
6fb5fa3c DB |
621 | |
622 | switch (inc_insn.form) | |
623 | { | |
624 | case FORM_PRE_ADD: | |
625 | case FORM_PRE_INC: | |
626 | last_insn = mem_insn.insn; | |
627 | break; | |
628 | case FORM_POST_INC: | |
629 | case FORM_POST_ADD: | |
630 | last_insn = inc_insn.insn; | |
631 | break; | |
632 | case FORM_last: | |
633 | default: | |
634 | gcc_unreachable (); | |
635 | } | |
636 | ||
637 | /* Cannot handle auto inc of the stack. */ | |
638 | if (inc_reg == stack_pointer_rtx) | |
639 | { | |
640 | if (dump_file) | |
641 | fprintf (dump_file, "cannot inc stack %d failure\n", REGNO (inc_reg)); | |
642 | return false; | |
643 | } | |
644 | ||
645 | /* Look to see if the inc register is dead after the memory | |
c8305c98 | 646 | reference. If it is, do not do the combination. */ |
6fb5fa3c DB |
647 | if (find_regno_note (last_insn, REG_DEAD, REGNO (inc_reg))) |
648 | { | |
649 | if (dump_file) | |
650 | fprintf (dump_file, "dead failure %d\n", REGNO (inc_reg)); | |
651 | return false; | |
652 | } | |
653 | ||
b8698a0f | 654 | mem_insn.reg1_state = (mem_insn.reg1_is_const) |
6fb5fa3c DB |
655 | ? set_inc_state (mem_insn.reg1_val, size) : INC_REG; |
656 | inc_insn.reg1_state = (inc_insn.reg1_is_const) | |
657 | ? set_inc_state (inc_insn.reg1_val, size) : INC_REG; | |
658 | ||
659 | /* Now get the form that we are generating. */ | |
b8698a0f | 660 | gen_form = decision_table |
6fb5fa3c DB |
661 | [inc_insn.reg1_state][mem_insn.reg1_state][inc_insn.form]; |
662 | ||
663 | if (dbg_cnt (auto_inc_dec) == false) | |
664 | return false; | |
665 | ||
666 | switch (gen_form) | |
667 | { | |
668 | default: | |
669 | case NOTHING: | |
670 | return false; | |
671 | ||
672 | case SIMPLE_PRE_INC: /* ++size */ | |
673 | if (dump_file) | |
674 | fprintf (dump_file, "trying SIMPLE_PRE_INC\n"); | |
d4ebfa65 | 675 | return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg); |
6fb5fa3c | 676 | break; |
b8698a0f | 677 | |
6fb5fa3c DB |
678 | case SIMPLE_POST_INC: /* size++ */ |
679 | if (dump_file) | |
680 | fprintf (dump_file, "trying SIMPLE_POST_INC\n"); | |
d4ebfa65 | 681 | return attempt_change (gen_rtx_POST_INC (reg_mode, inc_reg), inc_reg); |
6fb5fa3c | 682 | break; |
b8698a0f | 683 | |
6fb5fa3c DB |
684 | case SIMPLE_PRE_DEC: /* --size */ |
685 | if (dump_file) | |
686 | fprintf (dump_file, "trying SIMPLE_PRE_DEC\n"); | |
d4ebfa65 | 687 | return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg); |
6fb5fa3c | 688 | break; |
b8698a0f | 689 | |
6fb5fa3c DB |
690 | case SIMPLE_POST_DEC: /* size-- */ |
691 | if (dump_file) | |
692 | fprintf (dump_file, "trying SIMPLE_POST_DEC\n"); | |
d4ebfa65 | 693 | return attempt_change (gen_rtx_POST_DEC (reg_mode, inc_reg), inc_reg); |
6fb5fa3c | 694 | break; |
b8698a0f | 695 | |
6fb5fa3c DB |
696 | case DISP_PRE: /* ++con */ |
697 | if (dump_file) | |
698 | fprintf (dump_file, "trying DISP_PRE\n"); | |
d4ebfa65 | 699 | return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, |
6fb5fa3c | 700 | inc_reg, |
d4ebfa65 | 701 | gen_rtx_PLUS (reg_mode, |
6fb5fa3c DB |
702 | inc_reg, |
703 | inc_insn.reg1)), | |
704 | inc_reg); | |
705 | break; | |
b8698a0f | 706 | |
6fb5fa3c DB |
707 | case DISP_POST: /* con++ */ |
708 | if (dump_file) | |
709 | fprintf (dump_file, "trying POST_DISP\n"); | |
d4ebfa65 | 710 | return attempt_change (gen_rtx_POST_MODIFY (reg_mode, |
6fb5fa3c | 711 | inc_reg, |
d4ebfa65 | 712 | gen_rtx_PLUS (reg_mode, |
6fb5fa3c DB |
713 | inc_reg, |
714 | inc_insn.reg1)), | |
715 | inc_reg); | |
716 | break; | |
b8698a0f | 717 | |
6fb5fa3c DB |
718 | case REG_PRE: /* ++reg */ |
719 | if (dump_file) | |
720 | fprintf (dump_file, "trying PRE_REG\n"); | |
d4ebfa65 | 721 | return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, |
6fb5fa3c | 722 | inc_reg, |
d4ebfa65 | 723 | gen_rtx_PLUS (reg_mode, |
6fb5fa3c DB |
724 | inc_reg, |
725 | inc_insn.reg1)), | |
726 | inc_reg); | |
727 | break; | |
b8698a0f | 728 | |
6fb5fa3c DB |
729 | case REG_POST: /* reg++ */ |
730 | if (dump_file) | |
731 | fprintf (dump_file, "trying POST_REG\n"); | |
d4ebfa65 | 732 | return attempt_change (gen_rtx_POST_MODIFY (reg_mode, |
6fb5fa3c | 733 | inc_reg, |
d4ebfa65 | 734 | gen_rtx_PLUS (reg_mode, |
6fb5fa3c DB |
735 | inc_reg, |
736 | inc_insn.reg1)), | |
737 | inc_reg); | |
738 | break; | |
739 | } | |
740 | } | |
741 | ||
742 | /* Return the next insn that uses (if reg_next_use is passed in | |
743 | NEXT_ARRAY) or defines (if reg_next_def is passed in NEXT_ARRAY) | |
744 | REGNO in BB. */ | |
745 | ||
3dfa938f DM |
746 | static rtx_insn * |
747 | get_next_ref (int regno, basic_block bb, rtx_insn **next_array) | |
6fb5fa3c | 748 | { |
3dfa938f | 749 | rtx_insn *insn = next_array[regno]; |
6fb5fa3c DB |
750 | |
751 | /* Lazy about cleaning out the next_arrays. */ | |
b0de17ef | 752 | if (insn && BLOCK_FOR_INSN (insn) != bb) |
6fb5fa3c DB |
753 | { |
754 | next_array[regno] = NULL; | |
755 | insn = NULL; | |
756 | } | |
757 | ||
758 | return insn; | |
759 | } | |
760 | ||
761 | ||
762 | /* Reverse the operands in a mem insn. */ | |
763 | ||
b8698a0f | 764 | static void |
6fb5fa3c DB |
765 | reverse_mem (void) |
766 | { | |
b8698a0f | 767 | rtx tmp = mem_insn.reg1; |
6fb5fa3c DB |
768 | mem_insn.reg1 = mem_insn.reg0; |
769 | mem_insn.reg0 = tmp; | |
770 | } | |
771 | ||
772 | ||
773 | /* Reverse the operands in a inc insn. */ | |
774 | ||
b8698a0f | 775 | static void |
6fb5fa3c DB |
776 | reverse_inc (void) |
777 | { | |
b8698a0f | 778 | rtx tmp = inc_insn.reg1; |
6fb5fa3c DB |
779 | inc_insn.reg1 = inc_insn.reg0; |
780 | inc_insn.reg0 = tmp; | |
781 | } | |
782 | ||
783 | ||
784 | /* Return true if INSN is of a form "a = b op c" where a and b are | |
785 | regs. op is + if c is a reg and +|- if c is a const. Fill in | |
b8698a0f L |
786 | INC_INSN with what is found. |
787 | ||
6fb5fa3c DB |
788 | This function is called in two contexts, if BEFORE_MEM is true, |
789 | this is called for each insn in the basic block. If BEFORE_MEM is | |
790 | false, it is called for the instruction in the block that uses the | |
791 | index register for some memory reference that is currently being | |
792 | processed. */ | |
793 | ||
794 | static bool | |
3dfa938f | 795 | parse_add_or_inc (rtx_insn *insn, bool before_mem) |
6fb5fa3c DB |
796 | { |
797 | rtx pat = single_set (insn); | |
798 | if (!pat) | |
799 | return false; | |
800 | ||
801 | /* Result must be single reg. */ | |
802 | if (!REG_P (SET_DEST (pat))) | |
803 | return false; | |
804 | ||
805 | if ((GET_CODE (SET_SRC (pat)) != PLUS) | |
806 | && (GET_CODE (SET_SRC (pat)) != MINUS)) | |
807 | return false; | |
808 | ||
809 | if (!REG_P (XEXP (SET_SRC (pat), 0))) | |
810 | return false; | |
811 | ||
812 | inc_insn.insn = insn; | |
813 | inc_insn.pat = pat; | |
814 | inc_insn.reg_res = SET_DEST (pat); | |
815 | inc_insn.reg0 = XEXP (SET_SRC (pat), 0); | |
816 | if (rtx_equal_p (inc_insn.reg_res, inc_insn.reg0)) | |
817 | inc_insn.form = before_mem ? FORM_PRE_INC : FORM_POST_INC; | |
b8698a0f | 818 | else |
6fb5fa3c DB |
819 | inc_insn.form = before_mem ? FORM_PRE_ADD : FORM_POST_ADD; |
820 | ||
481683e1 | 821 | if (CONST_INT_P (XEXP (SET_SRC (pat), 1))) |
6fb5fa3c DB |
822 | { |
823 | /* Process a = b + c where c is a const. */ | |
824 | inc_insn.reg1_is_const = true; | |
825 | if (GET_CODE (SET_SRC (pat)) == PLUS) | |
826 | { | |
827 | inc_insn.reg1 = XEXP (SET_SRC (pat), 1); | |
828 | inc_insn.reg1_val = INTVAL (inc_insn.reg1); | |
829 | } | |
830 | else | |
831 | { | |
832 | inc_insn.reg1_val = -INTVAL (XEXP (SET_SRC (pat), 1)); | |
833 | inc_insn.reg1 = GEN_INT (inc_insn.reg1_val); | |
834 | } | |
835 | return true; | |
836 | } | |
837 | else if ((HAVE_PRE_MODIFY_REG || HAVE_POST_MODIFY_REG) | |
838 | && (REG_P (XEXP (SET_SRC (pat), 1))) | |
839 | && GET_CODE (SET_SRC (pat)) == PLUS) | |
840 | { | |
841 | /* Process a = b + c where c is a reg. */ | |
842 | inc_insn.reg1 = XEXP (SET_SRC (pat), 1); | |
843 | inc_insn.reg1_is_const = false; | |
b8698a0f L |
844 | |
845 | if (inc_insn.form == FORM_PRE_INC | |
6fb5fa3c DB |
846 | || inc_insn.form == FORM_POST_INC) |
847 | return true; | |
848 | else if (rtx_equal_p (inc_insn.reg_res, inc_insn.reg1)) | |
849 | { | |
850 | /* Reverse the two operands and turn *_ADD into *_INC since | |
851 | a = c + a. */ | |
852 | reverse_inc (); | |
853 | inc_insn.form = before_mem ? FORM_PRE_INC : FORM_POST_INC; | |
854 | return true; | |
855 | } | |
b8698a0f | 856 | else |
6fb5fa3c DB |
857 | return true; |
858 | } | |
859 | ||
860 | return false; | |
861 | } | |
862 | ||
863 | ||
864 | /* A recursive function that checks all of the mem uses in | |
865 | ADDRESS_OF_X to see if any single one of them is compatible with | |
866 | what has been found in inc_insn. | |
867 | ||
b8698a0f | 868 | -1 is returned for success. 0 is returned if nothing was found and |
6fb5fa3c DB |
869 | 1 is returned for failure. */ |
870 | ||
871 | static int | |
872 | find_address (rtx *address_of_x) | |
873 | { | |
874 | rtx x = *address_of_x; | |
875 | enum rtx_code code = GET_CODE (x); | |
876 | const char *const fmt = GET_RTX_FORMAT (code); | |
877 | int i; | |
878 | int value = 0; | |
879 | int tem; | |
880 | ||
881 | if (code == MEM && rtx_equal_p (XEXP (x, 0), inc_insn.reg_res)) | |
882 | { | |
883 | /* Match with *reg0. */ | |
884 | mem_insn.mem_loc = address_of_x; | |
885 | mem_insn.reg0 = inc_insn.reg_res; | |
886 | mem_insn.reg1_is_const = true; | |
887 | mem_insn.reg1_val = 0; | |
888 | mem_insn.reg1 = GEN_INT (0); | |
889 | return -1; | |
890 | } | |
891 | if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS | |
892 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), inc_insn.reg_res)) | |
893 | { | |
894 | rtx b = XEXP (XEXP (x, 0), 1); | |
895 | mem_insn.mem_loc = address_of_x; | |
896 | mem_insn.reg0 = inc_insn.reg_res; | |
897 | mem_insn.reg1 = b; | |
898 | mem_insn.reg1_is_const = inc_insn.reg1_is_const; | |
481683e1 | 899 | if (CONST_INT_P (b)) |
6fb5fa3c DB |
900 | { |
901 | /* Match with *(reg0 + reg1) where reg1 is a const. */ | |
902 | HOST_WIDE_INT val = INTVAL (b); | |
b8698a0f | 903 | if (inc_insn.reg1_is_const |
6fb5fa3c DB |
904 | && (inc_insn.reg1_val == val || inc_insn.reg1_val == -val)) |
905 | { | |
906 | mem_insn.reg1_val = val; | |
907 | return -1; | |
908 | } | |
909 | } | |
b8698a0f L |
910 | else if (!inc_insn.reg1_is_const |
911 | && rtx_equal_p (inc_insn.reg1, b)) | |
6fb5fa3c DB |
912 | /* Match with *(reg0 + reg1). */ |
913 | return -1; | |
914 | } | |
915 | ||
916 | if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) | |
917 | { | |
918 | /* If REG occurs inside a MEM used in a bit-field reference, | |
919 | that is unacceptable. */ | |
920 | if (find_address (&XEXP (x, 0))) | |
921 | return 1; | |
922 | } | |
923 | ||
924 | if (x == inc_insn.reg_res) | |
925 | return 1; | |
926 | ||
927 | /* Time for some deep diving. */ | |
928 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
929 | { | |
930 | if (fmt[i] == 'e') | |
931 | { | |
932 | tem = find_address (&XEXP (x, i)); | |
933 | /* If this is the first use, let it go so the rest of the | |
934 | insn can be checked. */ | |
935 | if (value == 0) | |
936 | value = tem; | |
937 | else if (tem != 0) | |
938 | /* More than one match was found. */ | |
939 | return 1; | |
940 | } | |
941 | else if (fmt[i] == 'E') | |
942 | { | |
943 | int j; | |
944 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
945 | { | |
946 | tem = find_address (&XVECEXP (x, i, j)); | |
947 | /* If this is the first use, let it go so the rest of | |
948 | the insn can be checked. */ | |
949 | if (value == 0) | |
950 | value = tem; | |
951 | else if (tem != 0) | |
952 | /* More than one match was found. */ | |
953 | return 1; | |
954 | } | |
955 | } | |
956 | } | |
957 | return value; | |
958 | } | |
959 | ||
960 | /* Once a suitable mem reference has been found and the MEM_INSN | |
961 | structure has been filled in, FIND_INC is called to see if there is | |
962 | a suitable add or inc insn that follows the mem reference and | |
963 | determine if it is suitable to merge. | |
964 | ||
965 | In the case where the MEM_INSN has two registers in the reference, | |
966 | this function may be called recursively. The first time looking | |
967 | for an add of the first register, and if that fails, looking for an | |
968 | add of the second register. The FIRST_TRY parameter is used to | |
969 | only allow the parameters to be reversed once. */ | |
970 | ||
b8698a0f | 971 | static bool |
6fb5fa3c DB |
972 | find_inc (bool first_try) |
973 | { | |
3dfa938f | 974 | rtx_insn *insn; |
b0de17ef | 975 | basic_block bb = BLOCK_FOR_INSN (mem_insn.insn); |
3dfa938f | 976 | rtx_insn *other_insn; |
bfac633a | 977 | df_ref def; |
6fb5fa3c DB |
978 | |
979 | /* Make sure this reg appears only once in this insn. */ | |
980 | if (count_occurrences (PATTERN (mem_insn.insn), mem_insn.reg0, 1) != 1) | |
981 | { | |
982 | if (dump_file) | |
b8698a0f | 983 | fprintf (dump_file, "mem count failure\n"); |
6fb5fa3c DB |
984 | return false; |
985 | } | |
986 | ||
987 | if (dump_file) | |
988 | dump_mem_insn (dump_file); | |
989 | ||
990 | /* Find the next use that is an inc. */ | |
b8698a0f | 991 | insn = get_next_ref (REGNO (mem_insn.reg0), |
b0de17ef | 992 | BLOCK_FOR_INSN (mem_insn.insn), |
6fb5fa3c DB |
993 | reg_next_inc_use); |
994 | if (!insn) | |
995 | return false; | |
996 | ||
997 | /* Even though we know the next use is an add or inc because it came | |
998 | from the reg_next_inc_use, we must still reparse. */ | |
999 | if (!parse_add_or_inc (insn, false)) | |
1000 | { | |
1001 | /* Next use was not an add. Look for one extra case. It could be | |
1002 | that we have: | |
b8698a0f | 1003 | |
6fb5fa3c DB |
1004 | *(a + b) |
1005 | ...= a; | |
1006 | ...= b + a | |
b8698a0f | 1007 | |
6fb5fa3c DB |
1008 | if we reverse the operands in the mem ref we would |
1009 | find this. Only try it once though. */ | |
1010 | if (first_try && !mem_insn.reg1_is_const) | |
1011 | { | |
1012 | reverse_mem (); | |
1013 | return find_inc (false); | |
1014 | } | |
1015 | else | |
1016 | return false; | |
1017 | } | |
1018 | ||
b8698a0f | 1019 | /* Need to assure that none of the operands of the inc instruction are |
6fb5fa3c | 1020 | assigned to by the mem insn. */ |
bfac633a | 1021 | FOR_EACH_INSN_DEF (def, mem_insn.insn) |
6fb5fa3c | 1022 | { |
6fb5fa3c | 1023 | unsigned int regno = DF_REF_REGNO (def); |
b8698a0f | 1024 | if ((regno == REGNO (inc_insn.reg0)) |
6fb5fa3c DB |
1025 | || (regno == REGNO (inc_insn.reg_res))) |
1026 | { | |
1027 | if (dump_file) | |
1028 | fprintf (dump_file, "inc conflicts with store failure.\n"); | |
1029 | return false; | |
1030 | } | |
1031 | if (!inc_insn.reg1_is_const && (regno == REGNO (inc_insn.reg1))) | |
1032 | { | |
1033 | if (dump_file) | |
1034 | fprintf (dump_file, "inc conflicts with store failure.\n"); | |
1035 | return false; | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | if (dump_file) | |
1040 | dump_inc_insn (dump_file); | |
1041 | ||
1042 | if (inc_insn.form == FORM_POST_ADD) | |
1043 | { | |
1044 | /* Make sure that there is no insn that assigns to inc_insn.res | |
1045 | between the mem_insn and the inc_insn. */ | |
3dfa938f DM |
1046 | rtx_insn *other_insn = get_next_ref (REGNO (inc_insn.reg_res), |
1047 | BLOCK_FOR_INSN (mem_insn.insn), | |
1048 | reg_next_def); | |
6fb5fa3c DB |
1049 | if (other_insn != inc_insn.insn) |
1050 | { | |
1051 | if (dump_file) | |
b8698a0f | 1052 | fprintf (dump_file, |
6fb5fa3c DB |
1053 | "result of add is assigned to between mem and inc insns.\n"); |
1054 | return false; | |
1055 | } | |
1056 | ||
b8698a0f | 1057 | other_insn = get_next_ref (REGNO (inc_insn.reg_res), |
b0de17ef | 1058 | BLOCK_FOR_INSN (mem_insn.insn), |
6fb5fa3c | 1059 | reg_next_use); |
b8698a0f | 1060 | if (other_insn |
6fb5fa3c DB |
1061 | && (other_insn != inc_insn.insn) |
1062 | && (DF_INSN_LUID (inc_insn.insn) > DF_INSN_LUID (other_insn))) | |
1063 | { | |
1064 | if (dump_file) | |
b8698a0f | 1065 | fprintf (dump_file, |
6fb5fa3c DB |
1066 | "result of add is used between mem and inc insns.\n"); |
1067 | return false; | |
1068 | } | |
1069 | ||
1070 | /* For the post_add to work, the result_reg of the inc must not be | |
1071 | used in the mem insn since this will become the new index | |
1072 | register. */ | |
71df5a7e | 1073 | if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn))) |
6fb5fa3c DB |
1074 | { |
1075 | if (dump_file) | |
1076 | fprintf (dump_file, "base reg replacement failure.\n"); | |
1077 | return false; | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | if (mem_insn.reg1_is_const) | |
1082 | { | |
1083 | if (mem_insn.reg1_val == 0) | |
1084 | { | |
1085 | if (!inc_insn.reg1_is_const) | |
1086 | { | |
1087 | /* The mem looks like *r0 and the rhs of the add has two | |
1088 | registers. */ | |
1089 | int luid = DF_INSN_LUID (inc_insn.insn); | |
1090 | if (inc_insn.form == FORM_POST_ADD) | |
1091 | { | |
b8698a0f | 1092 | /* The trick is that we are not going to increment r0, |
6fb5fa3c DB |
1093 | we are going to increment the result of the add insn. |
1094 | For this trick to be correct, the result reg of | |
1095 | the inc must be a valid addressing reg. */ | |
d4ebfa65 BE |
1096 | addr_space_t as = MEM_ADDR_SPACE (*mem_insn.mem_loc); |
1097 | if (GET_MODE (inc_insn.reg_res) | |
1098 | != targetm.addr_space.address_mode (as)) | |
6fb5fa3c DB |
1099 | { |
1100 | if (dump_file) | |
1101 | fprintf (dump_file, "base reg mode failure.\n"); | |
1102 | return false; | |
1103 | } | |
1104 | ||
1105 | /* We also need to make sure that the next use of | |
1106 | inc result is after the inc. */ | |
b8698a0f | 1107 | other_insn |
6fb5fa3c DB |
1108 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_use); |
1109 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1110 | return false; | |
1111 | ||
1112 | if (!rtx_equal_p (mem_insn.reg0, inc_insn.reg0)) | |
b8698a0f | 1113 | reverse_inc (); |
6fb5fa3c DB |
1114 | } |
1115 | ||
b8698a0f | 1116 | other_insn |
6fb5fa3c DB |
1117 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def); |
1118 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1119 | return false; | |
1120 | } | |
1121 | } | |
1122 | /* Both the inc/add and the mem have a constant. Need to check | |
1123 | that the constants are ok. */ | |
1124 | else if ((mem_insn.reg1_val != inc_insn.reg1_val) | |
1125 | && (mem_insn.reg1_val != -inc_insn.reg1_val)) | |
1126 | return false; | |
1127 | } | |
1128 | else | |
1129 | { | |
1130 | /* The mem insn is of the form *(a + b) where a and b are both | |
1131 | regs. It may be that in order to match the add or inc we | |
1132 | need to treat it as if it was *(b + a). It may also be that | |
1133 | the add is of the form a + c where c does not match b and | |
1134 | then we just abandon this. */ | |
b8698a0f | 1135 | |
6fb5fa3c | 1136 | int luid = DF_INSN_LUID (inc_insn.insn); |
3dfa938f | 1137 | rtx_insn *other_insn; |
b8698a0f | 1138 | |
6fb5fa3c DB |
1139 | /* Make sure this reg appears only once in this insn. */ |
1140 | if (count_occurrences (PATTERN (mem_insn.insn), mem_insn.reg1, 1) != 1) | |
1141 | return false; | |
b8698a0f | 1142 | |
6fb5fa3c DB |
1143 | if (inc_insn.form == FORM_POST_ADD) |
1144 | { | |
1145 | /* For this trick to be correct, the result reg of the inc | |
1146 | must be a valid addressing reg. */ | |
d4ebfa65 BE |
1147 | addr_space_t as = MEM_ADDR_SPACE (*mem_insn.mem_loc); |
1148 | if (GET_MODE (inc_insn.reg_res) | |
1149 | != targetm.addr_space.address_mode (as)) | |
6fb5fa3c DB |
1150 | { |
1151 | if (dump_file) | |
1152 | fprintf (dump_file, "base reg mode failure.\n"); | |
1153 | return false; | |
1154 | } | |
1155 | ||
1156 | if (rtx_equal_p (mem_insn.reg0, inc_insn.reg0)) | |
1157 | { | |
1158 | if (!rtx_equal_p (mem_insn.reg1, inc_insn.reg1)) | |
1159 | { | |
1160 | /* See comment above on find_inc (false) call. */ | |
1161 | if (first_try) | |
1162 | { | |
1163 | reverse_mem (); | |
1164 | return find_inc (false); | |
1165 | } | |
1166 | else | |
1167 | return false; | |
1168 | } | |
1169 | ||
0d52bcc1 | 1170 | /* Need to check that there are no assignments to b |
6fb5fa3c | 1171 | before the add insn. */ |
b8698a0f | 1172 | other_insn |
6fb5fa3c DB |
1173 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def); |
1174 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1175 | return false; | |
1176 | /* All ok for the next step. */ | |
1177 | } | |
1178 | else | |
1179 | { | |
1180 | /* We know that mem_insn.reg0 must equal inc_insn.reg1 | |
1181 | or else we would not have found the inc insn. */ | |
1182 | reverse_mem (); | |
1183 | if (!rtx_equal_p (mem_insn.reg0, inc_insn.reg0)) | |
1184 | { | |
1185 | /* See comment above on find_inc (false) call. */ | |
1186 | if (first_try) | |
1187 | return find_inc (false); | |
1188 | else | |
1189 | return false; | |
1190 | } | |
1191 | /* To have gotten here know that. | |
1192 | *(b + a) | |
b8698a0f | 1193 | |
6fb5fa3c | 1194 | ... = (b + a) |
b8698a0f | 1195 | |
6fb5fa3c DB |
1196 | We also know that the lhs of the inc is not b or a. We |
1197 | need to make sure that there are no assignments to b | |
b8698a0f L |
1198 | between the mem ref and the inc. */ |
1199 | ||
1200 | other_insn | |
6fb5fa3c DB |
1201 | = get_next_ref (REGNO (inc_insn.reg0), bb, reg_next_def); |
1202 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1203 | return false; | |
1204 | } | |
1205 | ||
1206 | /* Need to check that the next use of the add result is later than | |
1207 | add insn since this will be the reg incremented. */ | |
b8698a0f | 1208 | other_insn |
6fb5fa3c DB |
1209 | = get_next_ref (REGNO (inc_insn.reg_res), bb, reg_next_use); |
1210 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1211 | return false; | |
1212 | } | |
1213 | else /* FORM_POST_INC. There is less to check here because we | |
b8698a0f | 1214 | know that operands must line up. */ |
6fb5fa3c DB |
1215 | { |
1216 | if (!rtx_equal_p (mem_insn.reg1, inc_insn.reg1)) | |
1217 | /* See comment above on find_inc (false) call. */ | |
1218 | { | |
1219 | if (first_try) | |
1220 | { | |
1221 | reverse_mem (); | |
1222 | return find_inc (false); | |
1223 | } | |
b8698a0f | 1224 | else |
6fb5fa3c DB |
1225 | return false; |
1226 | } | |
b8698a0f | 1227 | |
6fb5fa3c DB |
1228 | /* To have gotten here know that. |
1229 | *(a + b) | |
b8698a0f | 1230 | |
6fb5fa3c | 1231 | ... = (a + b) |
b8698a0f | 1232 | |
6fb5fa3c DB |
1233 | We also know that the lhs of the inc is not b. We need to make |
1234 | sure that there are no assignments to b between the mem ref and | |
1235 | the inc. */ | |
b8698a0f | 1236 | other_insn |
6fb5fa3c DB |
1237 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def); |
1238 | if (other_insn && luid > DF_INSN_LUID (other_insn)) | |
1239 | return false; | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | if (inc_insn.form == FORM_POST_INC) | |
1244 | { | |
b8698a0f | 1245 | other_insn |
6fb5fa3c DB |
1246 | = get_next_ref (REGNO (inc_insn.reg0), bb, reg_next_use); |
1247 | /* When we found inc_insn, we were looking for the | |
1248 | next add or inc, not the next insn that used the | |
1249 | reg. Because we are going to increment the reg | |
1250 | in this form, we need to make sure that there | |
6ed3da00 | 1251 | were no intervening uses of reg. */ |
6fb5fa3c DB |
1252 | if (inc_insn.insn != other_insn) |
1253 | return false; | |
1254 | } | |
1255 | ||
1256 | return try_merge (); | |
1257 | } | |
1258 | ||
1259 | ||
1260 | /* A recursive function that walks ADDRESS_OF_X to find all of the mem | |
1261 | uses in pat that could be used as an auto inc or dec. It then | |
1262 | calls FIND_INC for each one. */ | |
1263 | ||
1264 | static bool | |
1265 | find_mem (rtx *address_of_x) | |
1266 | { | |
1267 | rtx x = *address_of_x; | |
1268 | enum rtx_code code = GET_CODE (x); | |
1269 | const char *const fmt = GET_RTX_FORMAT (code); | |
1270 | int i; | |
1271 | ||
1272 | if (code == MEM && REG_P (XEXP (x, 0))) | |
1273 | { | |
1274 | /* Match with *reg0. */ | |
1275 | mem_insn.mem_loc = address_of_x; | |
1276 | mem_insn.reg0 = XEXP (x, 0); | |
1277 | mem_insn.reg1_is_const = true; | |
1278 | mem_insn.reg1_val = 0; | |
1279 | mem_insn.reg1 = GEN_INT (0); | |
1280 | if (find_inc (true)) | |
1281 | return true; | |
1282 | } | |
1283 | if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS | |
1284 | && REG_P (XEXP (XEXP (x, 0), 0))) | |
1285 | { | |
1286 | rtx reg1 = XEXP (XEXP (x, 0), 1); | |
1287 | mem_insn.mem_loc = address_of_x; | |
1288 | mem_insn.reg0 = XEXP (XEXP (x, 0), 0); | |
1289 | mem_insn.reg1 = reg1; | |
481683e1 | 1290 | if (CONST_INT_P (reg1)) |
6fb5fa3c DB |
1291 | { |
1292 | mem_insn.reg1_is_const = true; | |
1293 | /* Match with *(reg0 + c) where c is a const. */ | |
1294 | mem_insn.reg1_val = INTVAL (reg1); | |
1295 | if (find_inc (true)) | |
1296 | return true; | |
1297 | } | |
1298 | else if (REG_P (reg1)) | |
1299 | { | |
1300 | /* Match with *(reg0 + reg1). */ | |
1301 | mem_insn.reg1_is_const = false; | |
1302 | if (find_inc (true)) | |
1303 | return true; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | if (code == SIGN_EXTRACT || code == ZERO_EXTRACT) | |
1308 | { | |
1309 | /* If REG occurs inside a MEM used in a bit-field reference, | |
1310 | that is unacceptable. */ | |
1311 | return false; | |
1312 | } | |
1313 | ||
1314 | /* Time for some deep diving. */ | |
1315 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1316 | { | |
1317 | if (fmt[i] == 'e') | |
1318 | { | |
1319 | if (find_mem (&XEXP (x, i))) | |
1320 | return true; | |
1321 | } | |
1322 | else if (fmt[i] == 'E') | |
1323 | { | |
1324 | int j; | |
1325 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1326 | if (find_mem (&XVECEXP (x, i, j))) | |
1327 | return true; | |
1328 | } | |
1329 | } | |
1330 | return false; | |
1331 | } | |
1332 | ||
1333 | ||
1334 | /* Try to combine all incs and decs by constant values with memory | |
1335 | references in BB. */ | |
1336 | ||
1337 | static void | |
1338 | merge_in_block (int max_reg, basic_block bb) | |
1339 | { | |
3dfa938f DM |
1340 | rtx_insn *insn; |
1341 | rtx_insn *curr; | |
6fb5fa3c DB |
1342 | int success_in_block = 0; |
1343 | ||
1344 | if (dump_file) | |
1345 | fprintf (dump_file, "\n\nstarting bb %d\n", bb->index); | |
1346 | ||
1347 | FOR_BB_INSNS_REVERSE_SAFE (bb, insn, curr) | |
1348 | { | |
6fb5fa3c DB |
1349 | bool insn_is_add_or_inc = true; |
1350 | ||
b5b8b0ac | 1351 | if (!NONDEBUG_INSN_P (insn)) |
b8698a0f | 1352 | continue; |
6fb5fa3c DB |
1353 | |
1354 | /* This continue is deliberate. We do not want the uses of the | |
b8698a0f | 1355 | jump put into reg_next_use because it is not considered safe to |
6fb5fa3c DB |
1356 | combine a preincrement with a jump. */ |
1357 | if (JUMP_P (insn)) | |
1358 | continue; | |
1359 | ||
1360 | if (dump_file) | |
1361 | dump_insn_slim (dump_file, insn); | |
1362 | ||
1363 | /* Does this instruction increment or decrement a register? */ | |
1364 | if (parse_add_or_inc (insn, true)) | |
1365 | { | |
1366 | int regno = REGNO (inc_insn.reg_res); | |
1367 | /* Cannot handle case where there are three separate regs | |
1368 | before a mem ref. Too many moves would be needed to be | |
1369 | profitable. */ | |
1370 | if ((inc_insn.form == FORM_PRE_INC) || inc_insn.reg1_is_const) | |
1371 | { | |
1372 | mem_insn.insn = get_next_ref (regno, bb, reg_next_use); | |
1373 | if (mem_insn.insn) | |
1374 | { | |
1375 | bool ok = true; | |
1376 | if (!inc_insn.reg1_is_const) | |
1377 | { | |
1378 | /* We are only here if we are going to try a | |
1379 | HAVE_*_MODIFY_REG type transformation. c is a | |
1380 | reg and we must sure that the path from the | |
1381 | inc_insn to the mem_insn.insn is both def and use | |
1382 | clear of c because the inc insn is going to move | |
1383 | into the mem_insn.insn. */ | |
1384 | int luid = DF_INSN_LUID (mem_insn.insn); | |
3dfa938f | 1385 | rtx_insn *other_insn |
6fb5fa3c | 1386 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_use); |
b8698a0f | 1387 | |
6fb5fa3c DB |
1388 | if (other_insn && luid > DF_INSN_LUID (other_insn)) |
1389 | ok = false; | |
b8698a0f L |
1390 | |
1391 | other_insn | |
6fb5fa3c | 1392 | = get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def); |
b8698a0f | 1393 | |
6fb5fa3c DB |
1394 | if (other_insn && luid > DF_INSN_LUID (other_insn)) |
1395 | ok = false; | |
1396 | } | |
b8698a0f | 1397 | |
6fb5fa3c DB |
1398 | if (dump_file) |
1399 | dump_inc_insn (dump_file); | |
b8698a0f | 1400 | |
6fb5fa3c DB |
1401 | if (ok && find_address (&PATTERN (mem_insn.insn)) == -1) |
1402 | { | |
1403 | if (dump_file) | |
1404 | dump_mem_insn (dump_file); | |
1405 | if (try_merge ()) | |
1406 | { | |
1407 | success_in_block++; | |
1408 | insn_is_add_or_inc = false; | |
1409 | } | |
1410 | } | |
1411 | } | |
1412 | } | |
1413 | } | |
1414 | else | |
1415 | { | |
1416 | insn_is_add_or_inc = false; | |
1417 | mem_insn.insn = insn; | |
1418 | if (find_mem (&PATTERN (insn))) | |
1419 | success_in_block++; | |
1420 | } | |
b8698a0f | 1421 | |
6fb5fa3c DB |
1422 | /* If the inc insn was merged with a mem, the inc insn is gone |
1423 | and there is noting to update. */ | |
737c262e | 1424 | if (df_insn_info *insn_info = DF_INSN_INFO_GET (insn)) |
6fb5fa3c | 1425 | { |
bfac633a RS |
1426 | df_ref def, use; |
1427 | ||
6fb5fa3c | 1428 | /* Need to update next use. */ |
bfac633a | 1429 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
6fb5fa3c | 1430 | { |
6fb5fa3c DB |
1431 | reg_next_use[DF_REF_REGNO (def)] = NULL; |
1432 | reg_next_inc_use[DF_REF_REGNO (def)] = NULL; | |
1433 | reg_next_def[DF_REF_REGNO (def)] = insn; | |
1434 | } | |
b8698a0f | 1435 | |
bfac633a | 1436 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
6fb5fa3c | 1437 | { |
6fb5fa3c DB |
1438 | reg_next_use[DF_REF_REGNO (use)] = insn; |
1439 | if (insn_is_add_or_inc) | |
1440 | reg_next_inc_use[DF_REF_REGNO (use)] = insn; | |
1441 | else | |
1442 | reg_next_inc_use[DF_REF_REGNO (use)] = NULL; | |
b8698a0f | 1443 | } |
6fb5fa3c DB |
1444 | } |
1445 | else if (dump_file) | |
737c262e RS |
1446 | fprintf (dump_file, "skipping update of deleted insn %d\n", |
1447 | INSN_UID (insn)); | |
6fb5fa3c DB |
1448 | } |
1449 | ||
1450 | /* If we were successful, try again. There may have been several | |
1451 | opportunities that were interleaved. This is rare but | |
1452 | gcc.c-torture/compile/pr17273.c actually exhibits this. */ | |
1453 | if (success_in_block) | |
1454 | { | |
1455 | /* In this case, we must clear these vectors since the trick of | |
1456 | testing if the stale insn in the block will not work. */ | |
c3284718 RS |
1457 | memset (reg_next_use, 0, max_reg * sizeof (rtx)); |
1458 | memset (reg_next_inc_use, 0, max_reg * sizeof (rtx)); | |
1459 | memset (reg_next_def, 0, max_reg * sizeof (rtx)); | |
6fb5fa3c DB |
1460 | df_recompute_luids (bb); |
1461 | merge_in_block (max_reg, bb); | |
1462 | } | |
1463 | } | |
1464 | ||
1465 | #endif | |
1466 | ||
6fb5fa3c DB |
1467 | /* Discover auto-inc auto-dec instructions. */ |
1468 | ||
27a4cd48 DM |
1469 | namespace { |
1470 | ||
1471 | const pass_data pass_data_inc_dec = | |
6fb5fa3c | 1472 | { |
27a4cd48 DM |
1473 | RTL_PASS, /* type */ |
1474 | "auto_inc_dec", /* name */ | |
1475 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
1476 | TV_AUTO_INC_DEC, /* tv_id */ |
1477 | 0, /* properties_required */ | |
1478 | 0, /* properties_provided */ | |
1479 | 0, /* properties_destroyed */ | |
1480 | 0, /* todo_flags_start */ | |
1481 | TODO_df_finish, /* todo_flags_finish */ | |
6fb5fa3c | 1482 | }; |
27a4cd48 DM |
1483 | |
1484 | class pass_inc_dec : public rtl_opt_pass | |
1485 | { | |
1486 | public: | |
c3284718 RS |
1487 | pass_inc_dec (gcc::context *ctxt) |
1488 | : rtl_opt_pass (pass_data_inc_dec, ctxt) | |
27a4cd48 DM |
1489 | {} |
1490 | ||
1491 | /* opt_pass methods: */ | |
1a3d085c TS |
1492 | virtual bool gate (function *) |
1493 | { | |
1494 | #ifdef AUTO_INC_DEC | |
1495 | return (optimize > 0 && flag_auto_inc_dec); | |
1496 | #else | |
1497 | return false; | |
1498 | #endif | |
1499 | } | |
1500 | ||
1501 | ||
be55bfe6 | 1502 | unsigned int execute (function *); |
27a4cd48 DM |
1503 | |
1504 | }; // class pass_inc_dec | |
1505 | ||
be55bfe6 TS |
1506 | unsigned int |
1507 | pass_inc_dec::execute (function *fun ATTRIBUTE_UNUSED) | |
1508 | { | |
1509 | #ifdef AUTO_INC_DEC | |
1510 | basic_block bb; | |
1511 | int max_reg = max_reg_num (); | |
1512 | ||
1513 | if (!initialized) | |
1514 | init_decision_table (); | |
1515 | ||
1516 | mem_tmp = gen_rtx_MEM (Pmode, NULL_RTX); | |
1517 | ||
1518 | df_note_add_problem (); | |
1519 | df_analyze (); | |
1520 | ||
3dfa938f DM |
1521 | reg_next_use = XCNEWVEC (rtx_insn *, max_reg); |
1522 | reg_next_inc_use = XCNEWVEC (rtx_insn *, max_reg); | |
1523 | reg_next_def = XCNEWVEC (rtx_insn *, max_reg); | |
be55bfe6 TS |
1524 | FOR_EACH_BB_FN (bb, fun) |
1525 | merge_in_block (max_reg, bb); | |
1526 | ||
1527 | free (reg_next_use); | |
1528 | free (reg_next_inc_use); | |
1529 | free (reg_next_def); | |
1530 | ||
1531 | mem_tmp = NULL; | |
1532 | #endif | |
1533 | return 0; | |
1534 | } | |
1535 | ||
27a4cd48 DM |
1536 | } // anon namespace |
1537 | ||
1538 | rtl_opt_pass * | |
1539 | make_pass_inc_dec (gcc::context *ctxt) | |
1540 | { | |
1541 | return new pass_inc_dec (ctxt); | |
1542 | } |