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fe3ad572 SC |
1 | /* Perform branch target register load optimizations. |
2 | Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
8 | Software Foundation; either version 2, or (at your option) any later | |
9 | version. | |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GCC; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
19 | 02111-1307, USA. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
25 | #include "bitmap.h" | |
26 | #include "sbitmap.h" | |
27 | #include "rtl.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "basic-block.h" | |
30 | #include "regs.h" | |
31 | #include "obstack.h" | |
32 | #include "fibheap.h" | |
33 | #include "output.h" | |
34 | #include "target.h" | |
35 | #include "expr.h" | |
36 | #include "flags.h" | |
37 | #include "insn-attr.h" | |
38 | #include "function.h" | |
8f7193b8 | 39 | #include "tm_p.h" |
fe3ad572 SC |
40 | |
41 | /* Target register optimizations - these are performed after reload. */ | |
42 | ||
43 | typedef struct btr_def_group_s | |
44 | { | |
45 | struct btr_def_group_s *next; | |
46 | rtx src; | |
47 | struct btr_def_s *members; | |
48 | } *btr_def_group; | |
49 | ||
50 | typedef struct btr_user_s | |
51 | { | |
52 | struct btr_user_s *next; | |
53 | basic_block bb; | |
54 | int luid; | |
55 | rtx insn; | |
56 | /* If INSN has a single use of a single branch register, then | |
57 | USE points to it within INSN. If there is more than | |
58 | one branch register use, or the use is in some way ambiguous, | |
59 | then USE is NULL. */ | |
60 | rtx use; | |
61 | int n_reaching_defs; | |
62 | int first_reaching_def; | |
63 | char other_use_this_block; | |
64 | } *btr_user; | |
65 | ||
66 | /* btr_def structs appear on three lists: | |
67 | 1. A list of all btr_def structures (head is | |
68 | ALL_BTR_DEFS, linked by the NEXT field). | |
69 | 2. A list of branch reg definitions per basic block (head is | |
70 | BB_BTR_DEFS[i], linked by the NEXT_THIS_BB field). | |
71 | 3. A list of all branch reg definitions belonging to the same | |
72 | group (head is in a BTR_DEF_GROUP struct, linked by | |
73 | NEXT_THIS_GROUP field). */ | |
74 | ||
75 | typedef struct btr_def_s | |
76 | { | |
77 | struct btr_def_s *next_this_bb; | |
78 | struct btr_def_s *next_this_group; | |
79 | basic_block bb; | |
80 | int luid; | |
81 | rtx insn; | |
82 | int btr; | |
83 | int cost; | |
84 | /* For a branch register setting insn that has a constant | |
85 | source (i.e. a label), group links together all the | |
86 | insns with the same source. For other branch register | |
87 | setting insns, group is NULL. */ | |
88 | btr_def_group group; | |
89 | btr_user uses; | |
90 | /* If this def has a reaching use which is not a simple use | |
91 | in a branch instruction, then has_ambiguous_use will be true, | |
f9da5064 | 92 | and we will not attempt to migrate this definition. */ |
fe3ad572 SC |
93 | char has_ambiguous_use; |
94 | /* live_range is an approximation to the true live range for this | |
95 | def/use web, because it records the set of blocks that contain | |
96 | the live range. There could be other live ranges for the same | |
97 | branch register in that set of blocks, either in the block | |
98 | containing the def (before the def), or in a block containing | |
99 | a use (after the use). If there are such other live ranges, then | |
100 | other_btr_uses_before_def or other_btr_uses_after_use must be set true | |
71c0e7fc | 101 | as appropriate. */ |
fe3ad572 SC |
102 | char other_btr_uses_before_def; |
103 | char other_btr_uses_after_use; | |
104 | bitmap live_range; | |
105 | } *btr_def; | |
106 | ||
107 | static int issue_rate; | |
108 | ||
109 | static int basic_block_freq (basic_block); | |
110 | static int insn_sets_btr_p (rtx, int, int *); | |
111 | static rtx *find_btr_use (rtx); | |
112 | static int btr_referenced_p (rtx, rtx *); | |
113 | static int find_btr_reference (rtx *, void *); | |
114 | static void find_btr_def_group (btr_def_group *, btr_def); | |
115 | static btr_def add_btr_def (fibheap_t, basic_block, int, rtx, | |
116 | unsigned int, int, btr_def_group *); | |
117 | static btr_user new_btr_user (basic_block, int, rtx); | |
118 | static void dump_hard_reg_set (HARD_REG_SET); | |
119 | static void dump_btrs_live (int); | |
120 | static void note_other_use_this_block (unsigned int, btr_user); | |
121 | static void compute_defs_uses_and_gen (fibheap_t, btr_def *,btr_user *, | |
122 | sbitmap *, sbitmap *, HARD_REG_SET *); | |
123 | static void compute_kill (sbitmap *, sbitmap *, HARD_REG_SET *); | |
124 | static void compute_out (sbitmap *bb_out, sbitmap *, sbitmap *, int); | |
125 | static void link_btr_uses (btr_def *, btr_user *, sbitmap *, sbitmap *, int); | |
126 | static void build_btr_def_use_webs (fibheap_t); | |
127 | static int block_at_edge_of_live_range_p (int, btr_def); | |
128 | static void clear_btr_from_live_range (btr_def def); | |
129 | static void add_btr_to_live_range (btr_def); | |
130 | static void augment_live_range (bitmap, HARD_REG_SET *, basic_block, | |
131 | basic_block); | |
132 | static int choose_btr (HARD_REG_SET); | |
133 | static void combine_btr_defs (btr_def, HARD_REG_SET *); | |
134 | static void btr_def_live_range (btr_def, HARD_REG_SET *); | |
135 | static void move_btr_def (basic_block, int, btr_def, bitmap, HARD_REG_SET *); | |
136 | static int migrate_btr_def (btr_def, int); | |
137 | static void migrate_btr_defs (enum reg_class, int); | |
138 | static int can_move_up (basic_block, rtx, int); | |
139 | static void note_btr_set (rtx, rtx, void *); | |
140 | \f | |
141 | /* The following code performs code motion of target load instructions | |
142 | (instructions that set branch target registers), to move them | |
143 | forward away from the branch instructions and out of loops (or, | |
144 | more generally, from a more frequently executed place to a less | |
145 | frequently executed place). | |
146 | Moving target load instructions further in front of the branch | |
147 | instruction that uses the target register value means that the hardware | |
148 | has a better chance of preloading the instructions at the branch | |
149 | target by the time the branch is reached. This avoids bubbles | |
150 | when a taken branch needs to flush out the pipeline. | |
151 | Moving target load instructions out of loops means they are executed | |
152 | less frequently. */ | |
153 | ||
154 | /* An obstack to hold the def-use web data structures built up for | |
155 | migrating branch target load instructions. */ | |
156 | static struct obstack migrate_btrl_obstack; | |
157 | ||
158 | /* Basic block dominator information used when migrating PT instructions */ | |
159 | static dominance_info dom; | |
160 | ||
161 | /* Array indexed by basic block number, giving the set of registers | |
162 | live in that block. */ | |
163 | static HARD_REG_SET *btrs_live; | |
164 | ||
165 | /* Set of all target registers that we are willing to allocate. */ | |
166 | static HARD_REG_SET all_btrs; | |
167 | ||
168 | /* Provide lower and upper bounds for target register numbers, so that | |
169 | we don't need to search through all the hard registers all the time. */ | |
170 | static int first_btr, last_btr; | |
171 | ||
172 | ||
173 | ||
174 | /* Return an estimate of the frequency of execution of block bb. | |
175 | If we have a profiling count available, we could use it here. */ | |
176 | static int | |
177 | basic_block_freq (basic_block bb) | |
178 | { | |
179 | return bb->frequency; | |
180 | } | |
181 | ||
182 | static rtx *btr_reference_found; | |
183 | ||
184 | /* A subroutine of btr_referenced_p, called through for_each_rtx. | |
185 | PREG is a pointer to an rtx that is to be excluded from the | |
186 | traversal. If we find a reference to a target register anywhere | |
187 | else, return 1, and put a pointer to it into btr_reference_found. */ | |
188 | static int | |
189 | find_btr_reference (rtx *px, void *preg) | |
190 | { | |
191 | rtx x; | |
192 | int regno, i; | |
193 | ||
194 | if (px == preg) | |
195 | return -1; | |
196 | x = *px; | |
197 | if (GET_CODE (x) != REG) | |
198 | return 0; | |
199 | regno = REGNO (x); | |
200 | for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1; i >= 0; i--) | |
201 | if (TEST_HARD_REG_BIT (all_btrs, regno+i)) | |
202 | { | |
203 | btr_reference_found = px; | |
204 | return 1; | |
205 | } | |
206 | return -1; | |
207 | } | |
208 | ||
209 | /* Return nonzero if X references (sets or reads) any branch target register. | |
210 | If EXCLUDEP is set, disregard any references within the rtx pointed to | |
211 | by it. If returning nonzero, also set btr_reference_found as above. */ | |
212 | static int | |
213 | btr_referenced_p (rtx x, rtx *excludep) | |
214 | { | |
215 | return for_each_rtx (&x, find_btr_reference, excludep); | |
216 | } | |
217 | ||
218 | /* Return true if insn is an instruction that sets a target register. | |
219 | if CHECK_CONST is true, only return true if the source is constant. | |
220 | If such a set is found and REGNO is nonzero, assign the register number | |
221 | of the destination register to *REGNO. */ | |
222 | static int | |
223 | insn_sets_btr_p (rtx insn, int check_const, int *regno) | |
224 | { | |
225 | rtx set; | |
226 | ||
227 | if (GET_CODE (insn) == INSN | |
228 | && (set = single_set (insn))) | |
229 | { | |
230 | rtx dest = SET_DEST (set); | |
231 | rtx src = SET_SRC (set); | |
232 | ||
233 | if (GET_CODE (dest) == SUBREG) | |
234 | dest = XEXP (dest, 0); | |
235 | ||
236 | if (GET_CODE (dest) == REG | |
237 | && TEST_HARD_REG_BIT (all_btrs, REGNO (dest))) | |
238 | { | |
239 | if (btr_referenced_p (src, NULL)) | |
240 | abort(); | |
241 | if (!check_const || CONSTANT_P (src)) | |
242 | { | |
243 | if (regno) | |
244 | *regno = REGNO (dest); | |
245 | return 1; | |
246 | } | |
247 | } | |
248 | } | |
249 | return 0; | |
250 | } | |
251 | ||
71c0e7fc | 252 | /* Find and return a use of a target register within an instruction INSN. */ |
fe3ad572 SC |
253 | static rtx * |
254 | find_btr_use (rtx insn) | |
255 | { | |
256 | return btr_referenced_p (insn, NULL) ? btr_reference_found : NULL; | |
257 | } | |
258 | ||
259 | /* Find the group that the target register definition DEF belongs | |
260 | to in the list starting with *ALL_BTR_DEF_GROUPS. If no such | |
261 | group exists, create one. Add def to the group. */ | |
262 | static void | |
263 | find_btr_def_group (btr_def_group *all_btr_def_groups, btr_def def) | |
264 | { | |
265 | if (insn_sets_btr_p (def->insn, 1, NULL)) | |
266 | { | |
267 | btr_def_group this_group; | |
268 | rtx def_src = SET_SRC (single_set (def->insn)); | |
269 | ||
270 | /* ?? This linear search is an efficiency concern, particularly | |
271 | as the search will almost always fail to find a match. */ | |
272 | for (this_group = *all_btr_def_groups; | |
273 | this_group != NULL; | |
274 | this_group = this_group->next) | |
275 | if (rtx_equal_p (def_src, this_group->src)) | |
276 | break; | |
277 | ||
278 | if (!this_group) | |
279 | { | |
703ad42b KG |
280 | this_group = obstack_alloc (&migrate_btrl_obstack, |
281 | sizeof (struct btr_def_group_s)); | |
fe3ad572 SC |
282 | this_group->src = def_src; |
283 | this_group->members = NULL; | |
284 | this_group->next = *all_btr_def_groups; | |
285 | *all_btr_def_groups = this_group; | |
286 | } | |
287 | def->group = this_group; | |
288 | def->next_this_group = this_group->members; | |
289 | this_group->members = def; | |
290 | } | |
291 | else | |
292 | def->group = NULL; | |
293 | } | |
294 | ||
295 | /* Create a new target register definition structure, for a definition in | |
296 | block BB, instruction INSN, and insert it into ALL_BTR_DEFS. Return | |
297 | the new definition. */ | |
298 | static btr_def | |
299 | add_btr_def (fibheap_t all_btr_defs, basic_block bb, int insn_luid, rtx insn, | |
300 | unsigned int dest_reg, int other_btr_uses_before_def, | |
301 | btr_def_group *all_btr_def_groups) | |
302 | { | |
703ad42b KG |
303 | btr_def this |
304 | = obstack_alloc (&migrate_btrl_obstack, sizeof (struct btr_def_s)); | |
fe3ad572 SC |
305 | this->bb = bb; |
306 | this->luid = insn_luid; | |
307 | this->insn = insn; | |
308 | this->btr = dest_reg; | |
309 | this->cost = basic_block_freq (bb); | |
310 | this->has_ambiguous_use = 0; | |
311 | this->other_btr_uses_before_def = other_btr_uses_before_def; | |
312 | this->other_btr_uses_after_use = 0; | |
313 | this->next_this_bb = NULL; | |
314 | this->next_this_group = NULL; | |
315 | this->uses = NULL; | |
316 | this->live_range = NULL; | |
317 | find_btr_def_group (all_btr_def_groups, this); | |
318 | ||
319 | fibheap_insert (all_btr_defs, -this->cost, this); | |
320 | ||
321 | if (rtl_dump_file) | |
322 | fprintf (rtl_dump_file, | |
323 | "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n", | |
324 | dest_reg, bb->index, INSN_UID (insn), (this->group ? "" : ":not const"), | |
325 | this->cost); | |
326 | ||
327 | return this; | |
328 | } | |
329 | ||
330 | /* Create a new target register user structure, for a use in block BB, | |
331 | instruction INSN. Return the new user. */ | |
332 | static btr_user | |
333 | new_btr_user (basic_block bb, int insn_luid, rtx insn) | |
334 | { | |
335 | /* This instruction reads target registers. We need | |
336 | to decide whether we can replace all target register | |
337 | uses easily. | |
338 | */ | |
339 | rtx *usep = find_btr_use (PATTERN (insn)); | |
340 | rtx use; | |
341 | btr_user user = NULL; | |
342 | ||
343 | if (usep) | |
344 | { | |
345 | int unambiguous_single_use; | |
346 | ||
347 | /* We want to ensure that USE is the only use of a target | |
348 | register in INSN, so that we know that to rewrite INSN to use | |
349 | a different target register, all we have to do is replace USE. */ | |
350 | unambiguous_single_use = !btr_referenced_p (PATTERN (insn), usep); | |
351 | if (!unambiguous_single_use) | |
352 | usep = NULL; | |
353 | } | |
354 | use = usep ? *usep : NULL_RTX; | |
703ad42b | 355 | user = obstack_alloc (&migrate_btrl_obstack, sizeof (struct btr_user_s)); |
fe3ad572 SC |
356 | user->bb = bb; |
357 | user->luid = insn_luid; | |
358 | user->insn = insn; | |
359 | user->use = use; | |
360 | user->other_use_this_block = 0; | |
361 | user->next = NULL; | |
362 | user->n_reaching_defs = 0; | |
363 | user->first_reaching_def = -1; | |
364 | ||
365 | if (rtl_dump_file) | |
366 | { | |
367 | fprintf (rtl_dump_file, "Uses target reg: { bb %d, insn %d }", | |
368 | bb->index, INSN_UID (insn)); | |
369 | ||
370 | if (user->use) | |
371 | fprintf (rtl_dump_file, ": unambiguous use of reg %d\n", | |
372 | REGNO (user->use)); | |
373 | } | |
374 | ||
375 | return user; | |
376 | } | |
377 | ||
71c0e7fc | 378 | /* Write the contents of S to the dump file. */ |
fe3ad572 SC |
379 | static void |
380 | dump_hard_reg_set (HARD_REG_SET s) | |
381 | { | |
382 | int reg; | |
383 | for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++) | |
384 | if (TEST_HARD_REG_BIT (s, reg)) | |
385 | fprintf (rtl_dump_file, " %d", reg); | |
386 | } | |
387 | ||
71c0e7fc | 388 | /* Write the set of target regs live in block BB to the dump file. */ |
fe3ad572 SC |
389 | static void |
390 | dump_btrs_live (int bb) | |
391 | { | |
392 | fprintf (rtl_dump_file, "BB%d live:", bb); | |
393 | dump_hard_reg_set (btrs_live[bb]); | |
394 | fprintf (rtl_dump_file, "\n"); | |
395 | } | |
396 | ||
397 | /* REGNO is the number of a branch target register that is being used or | |
398 | set. USERS_THIS_BB is a list of preceding branch target register users; | |
399 | If any of them use the same register, set their other_use_this_block | |
400 | flag. */ | |
401 | static void | |
402 | note_other_use_this_block (unsigned int regno, btr_user users_this_bb) | |
403 | { | |
404 | btr_user user; | |
405 | ||
406 | for (user = users_this_bb; user != NULL; user = user->next) | |
407 | if (user->use && REGNO (user->use) == regno) | |
408 | user->other_use_this_block = 1; | |
409 | } | |
410 | ||
411 | typedef struct { | |
412 | btr_user users_this_bb; | |
413 | HARD_REG_SET btrs_written_in_block; | |
414 | HARD_REG_SET btrs_live_in_block; | |
415 | sbitmap bb_gen; | |
416 | sbitmap *btr_defset; | |
417 | } defs_uses_info; | |
418 | ||
419 | /* Called via note_stores or directly to register stores into / | |
420 | clobbers of a branch target register DEST that are not recognized as | |
421 | straightforward definitions. DATA points to information about the | |
f9da5064 | 422 | current basic block that needs updating. */ |
fe3ad572 SC |
423 | static void |
424 | note_btr_set (rtx dest, rtx set ATTRIBUTE_UNUSED, void *data) | |
425 | { | |
426 | defs_uses_info *info = data; | |
427 | int regno, end_regno; | |
428 | ||
429 | if (GET_CODE (dest) != REG) | |
430 | return; | |
431 | regno = REGNO (dest); | |
432 | end_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest)); | |
433 | for (; regno < end_regno; regno++) | |
434 | if (TEST_HARD_REG_BIT (all_btrs, regno)) | |
435 | { | |
436 | note_other_use_this_block (regno, info->users_this_bb); | |
437 | SET_HARD_REG_BIT (info->btrs_written_in_block, regno); | |
438 | SET_HARD_REG_BIT (info->btrs_live_in_block, regno); | |
439 | sbitmap_difference (info->bb_gen, info->bb_gen, | |
440 | info->btr_defset[regno - first_btr]); | |
441 | } | |
442 | } | |
443 | ||
444 | static void | |
445 | compute_defs_uses_and_gen (fibheap_t all_btr_defs, btr_def *def_array, | |
446 | btr_user *use_array, sbitmap *btr_defset, | |
447 | sbitmap *bb_gen, HARD_REG_SET *btrs_written) | |
448 | { | |
449 | /* Scan the code building up the set of all defs and all uses. | |
450 | For each target register, build the set of defs of that register. | |
451 | For each block, calculate the set of target registers | |
452 | written in that block. | |
453 | Also calculate the set of btrs ever live in that block. | |
454 | */ | |
455 | int i; | |
456 | int insn_luid = 0; | |
457 | btr_def_group all_btr_def_groups = NULL; | |
458 | defs_uses_info info; | |
459 | ||
460 | sbitmap_vector_zero (bb_gen, n_basic_blocks); | |
461 | for (i = 0; i < n_basic_blocks; i++) | |
462 | { | |
463 | basic_block bb = BASIC_BLOCK (i); | |
464 | int reg; | |
465 | btr_def defs_this_bb = NULL; | |
466 | rtx insn; | |
467 | rtx last; | |
468 | ||
469 | info.users_this_bb = NULL; | |
470 | info.bb_gen = bb_gen[i]; | |
471 | info.btr_defset = btr_defset; | |
472 | ||
473 | CLEAR_HARD_REG_SET (info.btrs_live_in_block); | |
474 | CLEAR_HARD_REG_SET (info.btrs_written_in_block); | |
475 | for (reg = first_btr; reg <= last_btr; reg++) | |
476 | if (TEST_HARD_REG_BIT (all_btrs, reg) | |
477 | && REGNO_REG_SET_P (bb->global_live_at_start, reg)) | |
478 | SET_HARD_REG_BIT (info.btrs_live_in_block, reg); | |
479 | ||
a813c111 | 480 | for (insn = BB_HEAD (bb), last = NEXT_INSN (BB_END (bb)); |
fe3ad572 SC |
481 | insn != last; |
482 | insn = NEXT_INSN (insn), insn_luid++) | |
483 | { | |
484 | if (INSN_P (insn)) | |
485 | { | |
486 | int regno; | |
487 | int insn_uid = INSN_UID (insn); | |
488 | ||
489 | if (insn_sets_btr_p (insn, 0, ®no)) | |
490 | { | |
491 | btr_def def = add_btr_def ( | |
492 | all_btr_defs, bb, insn_luid, insn, regno, | |
493 | TEST_HARD_REG_BIT (info.btrs_live_in_block, regno), | |
494 | &all_btr_def_groups); | |
495 | ||
496 | def_array[insn_uid] = def; | |
497 | SET_HARD_REG_BIT (info.btrs_written_in_block, regno); | |
498 | SET_HARD_REG_BIT (info.btrs_live_in_block, regno); | |
499 | sbitmap_difference (bb_gen[i], bb_gen[i], | |
500 | btr_defset[regno - first_btr]); | |
501 | SET_BIT (bb_gen[i], insn_uid); | |
502 | def->next_this_bb = defs_this_bb; | |
503 | defs_this_bb = def; | |
504 | SET_BIT (btr_defset[regno - first_btr], insn_uid); | |
505 | note_other_use_this_block (regno, info.users_this_bb); | |
506 | } | |
507 | else | |
508 | { | |
509 | if (btr_referenced_p (PATTERN (insn), NULL)) | |
510 | { | |
511 | btr_user user = new_btr_user (bb, insn_luid, insn); | |
512 | ||
513 | use_array[insn_uid] = user; | |
514 | if (user->use) | |
515 | SET_HARD_REG_BIT (info.btrs_live_in_block, | |
516 | REGNO (user->use)); | |
517 | else | |
518 | { | |
519 | int reg; | |
520 | for (reg = first_btr; reg <= last_btr; reg++) | |
521 | if (TEST_HARD_REG_BIT (all_btrs, reg) | |
522 | && refers_to_regno_p (reg, reg + 1, user->insn, | |
523 | NULL)) | |
524 | { | |
525 | note_other_use_this_block (reg, | |
526 | info.users_this_bb); | |
527 | SET_HARD_REG_BIT (info.btrs_live_in_block, reg); | |
528 | } | |
529 | note_stores (PATTERN (insn), note_btr_set, &info); | |
530 | } | |
531 | user->next = info.users_this_bb; | |
532 | info.users_this_bb = user; | |
533 | } | |
534 | if (GET_CODE (insn) == CALL_INSN) | |
535 | { | |
536 | HARD_REG_SET *clobbered = &call_used_reg_set; | |
537 | HARD_REG_SET call_saved; | |
538 | rtx pat = PATTERN (insn); | |
539 | int i; | |
540 | ||
541 | /* Check for sibcall. */ | |
542 | if (GET_CODE (pat) == PARALLEL) | |
543 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) | |
544 | if (GET_CODE (XVECEXP (pat, 0, i)) == RETURN) | |
545 | { | |
546 | COMPL_HARD_REG_SET (call_saved, | |
547 | call_used_reg_set); | |
548 | clobbered = &call_saved; | |
549 | } | |
550 | ||
551 | for (regno = first_btr; regno <= last_btr; regno++) | |
552 | if (TEST_HARD_REG_BIT (*clobbered, regno)) | |
553 | note_btr_set (regno_reg_rtx[regno], NULL_RTX, &info); | |
554 | } | |
555 | } | |
556 | } | |
557 | } | |
558 | ||
559 | COPY_HARD_REG_SET (btrs_live[i], info.btrs_live_in_block); | |
560 | COPY_HARD_REG_SET (btrs_written[i], info.btrs_written_in_block); | |
561 | if (rtl_dump_file) | |
562 | dump_btrs_live(i); | |
563 | } | |
564 | } | |
565 | ||
566 | static void | |
567 | compute_kill (sbitmap *bb_kill, sbitmap *btr_defset, | |
568 | HARD_REG_SET *btrs_written) | |
569 | { | |
570 | int i; | |
571 | int regno; | |
572 | ||
573 | /* For each basic block, form the set BB_KILL - the set | |
71c0e7fc | 574 | of definitions that the block kills. */ |
fe3ad572 SC |
575 | sbitmap_vector_zero (bb_kill, n_basic_blocks); |
576 | for (i = 0; i < n_basic_blocks; i++) | |
577 | { | |
578 | for (regno = first_btr; regno <= last_btr; regno++) | |
579 | if (TEST_HARD_REG_BIT (all_btrs, regno) | |
580 | && TEST_HARD_REG_BIT (btrs_written[i], regno)) | |
581 | sbitmap_a_or_b (bb_kill[i], bb_kill[i], | |
582 | btr_defset[regno - first_btr]); | |
583 | } | |
584 | } | |
585 | ||
586 | static void | |
587 | compute_out (sbitmap *bb_out, sbitmap *bb_gen, sbitmap *bb_kill, int max_uid) | |
588 | { | |
589 | /* Perform iterative dataflow: | |
590 | Initially, for all blocks, BB_OUT = BB_GEN. | |
591 | For each block, | |
592 | BB_IN = union over predecessors of BB_OUT(pred) | |
593 | BB_OUT = (BB_IN - BB_KILL) + BB_GEN | |
f9da5064 | 594 | Iterate until the bb_out sets stop growing. */ |
fe3ad572 SC |
595 | int i; |
596 | int changed; | |
597 | sbitmap bb_in = sbitmap_alloc (max_uid); | |
598 | ||
599 | for (i = 0; i < n_basic_blocks; i++) | |
600 | sbitmap_copy (bb_out[i], bb_gen[i]); | |
601 | ||
602 | changed = 1; | |
603 | while (changed) | |
604 | { | |
605 | changed = 0; | |
606 | for (i = 0; i < n_basic_blocks; i++) | |
607 | { | |
608 | sbitmap_union_of_preds (bb_in, bb_out, i); | |
609 | changed |= sbitmap_union_of_diff_cg (bb_out[i], bb_gen[i], | |
610 | bb_in, bb_kill[i]); | |
611 | } | |
612 | } | |
613 | sbitmap_free (bb_in); | |
614 | } | |
615 | ||
616 | static void | |
617 | link_btr_uses (btr_def *def_array, btr_user *use_array, sbitmap *bb_out, | |
618 | sbitmap *btr_defset, int max_uid) | |
619 | { | |
620 | int i; | |
621 | sbitmap reaching_defs = sbitmap_alloc (max_uid); | |
622 | ||
623 | /* Link uses to the uses lists of all of their reaching defs. | |
71c0e7fc | 624 | Count up the number of reaching defs of each use. */ |
fe3ad572 SC |
625 | for (i = 0; i < n_basic_blocks; i++) |
626 | { | |
627 | basic_block bb = BASIC_BLOCK (i); | |
628 | rtx insn; | |
629 | rtx last; | |
630 | ||
631 | sbitmap_union_of_preds (reaching_defs, bb_out, i); | |
a813c111 | 632 | for (insn = BB_HEAD (bb), last = NEXT_INSN (BB_END (bb)); |
fe3ad572 SC |
633 | insn != last; |
634 | insn = NEXT_INSN (insn)) | |
635 | { | |
636 | if (INSN_P (insn)) | |
637 | { | |
638 | int insn_uid = INSN_UID (insn); | |
639 | ||
640 | btr_def def = def_array[insn_uid]; | |
641 | btr_user user = use_array[insn_uid]; | |
642 | if (def != NULL) | |
643 | { | |
644 | /* Remove all reaching defs of regno except | |
71c0e7fc | 645 | for this one. */ |
fe3ad572 SC |
646 | sbitmap_difference (reaching_defs, reaching_defs, |
647 | btr_defset[def->btr - first_btr]); | |
648 | SET_BIT(reaching_defs, insn_uid); | |
649 | } | |
650 | ||
651 | if (user != NULL) | |
652 | { | |
f9da5064 | 653 | /* Find all the reaching defs for this use. */ |
fe3ad572 SC |
654 | sbitmap reaching_defs_of_reg = sbitmap_alloc(max_uid); |
655 | int uid; | |
656 | ||
657 | if (user->use) | |
658 | sbitmap_a_and_b ( | |
659 | reaching_defs_of_reg, | |
660 | reaching_defs, | |
661 | btr_defset[REGNO (user->use) - first_btr]); | |
662 | else | |
663 | { | |
664 | int reg; | |
665 | ||
666 | sbitmap_zero (reaching_defs_of_reg); | |
667 | for (reg = first_btr; reg <= last_btr; reg++) | |
668 | if (TEST_HARD_REG_BIT (all_btrs, reg) | |
669 | && refers_to_regno_p (reg, reg + 1, user->insn, | |
670 | NULL)) | |
671 | sbitmap_a_or_b_and_c (reaching_defs_of_reg, | |
672 | reaching_defs_of_reg, | |
673 | reaching_defs, | |
674 | btr_defset[reg - first_btr]); | |
675 | } | |
676 | EXECUTE_IF_SET_IN_SBITMAP (reaching_defs_of_reg, 0, uid, | |
677 | { | |
678 | btr_def def = def_array[uid]; | |
679 | ||
f9da5064 | 680 | /* We now know that def reaches user. */ |
fe3ad572 SC |
681 | |
682 | if (rtl_dump_file) | |
683 | fprintf (rtl_dump_file, | |
684 | "Def in insn %d reaches use in insn %d\n", | |
685 | uid, insn_uid); | |
686 | ||
687 | user->n_reaching_defs++; | |
688 | if (!user->use) | |
689 | def->has_ambiguous_use = 1; | |
690 | if (user->first_reaching_def != -1) | |
691 | { /* There is more than one reaching def. This is | |
692 | a rare case, so just give up on this def/use | |
71c0e7fc | 693 | web when it occurs. */ |
fe3ad572 SC |
694 | def->has_ambiguous_use = 1; |
695 | def_array[user->first_reaching_def] | |
696 | ->has_ambiguous_use = 1; | |
697 | if (rtl_dump_file) | |
698 | fprintf (rtl_dump_file, | |
699 | "(use %d has multiple reaching defs)\n", | |
700 | insn_uid); | |
701 | } | |
702 | else | |
703 | user->first_reaching_def = uid; | |
704 | if (user->other_use_this_block) | |
705 | def->other_btr_uses_after_use = 1; | |
706 | user->next = def->uses; | |
707 | def->uses = user; | |
708 | }); | |
709 | sbitmap_free (reaching_defs_of_reg); | |
710 | } | |
711 | ||
712 | if (GET_CODE (insn) == CALL_INSN) | |
713 | { | |
714 | int regno; | |
715 | ||
716 | for (regno = first_btr; regno <= last_btr; regno++) | |
717 | if (TEST_HARD_REG_BIT (all_btrs, regno) | |
718 | && TEST_HARD_REG_BIT (call_used_reg_set, regno)) | |
719 | sbitmap_difference (reaching_defs, reaching_defs, | |
720 | btr_defset[regno - first_btr]); | |
721 | } | |
722 | } | |
723 | } | |
724 | } | |
725 | sbitmap_free (reaching_defs); | |
726 | } | |
727 | ||
728 | static void | |
729 | build_btr_def_use_webs (fibheap_t all_btr_defs) | |
730 | { | |
731 | const int max_uid = get_max_uid (); | |
732 | btr_def *def_array = xcalloc (max_uid, sizeof (btr_def)); | |
733 | btr_user *use_array = xcalloc (max_uid, sizeof (btr_user)); | |
734 | sbitmap *btr_defset = sbitmap_vector_alloc ( | |
735 | (last_btr - first_btr) + 1, max_uid); | |
736 | sbitmap *bb_gen = sbitmap_vector_alloc (n_basic_blocks, max_uid); | |
703ad42b | 737 | HARD_REG_SET *btrs_written = xcalloc (n_basic_blocks, sizeof (HARD_REG_SET)); |
fe3ad572 SC |
738 | sbitmap *bb_kill; |
739 | sbitmap *bb_out; | |
740 | ||
741 | sbitmap_vector_zero (btr_defset, (last_btr - first_btr) + 1); | |
742 | ||
743 | compute_defs_uses_and_gen (all_btr_defs, def_array, use_array, btr_defset, | |
744 | bb_gen, btrs_written); | |
745 | ||
746 | bb_kill = sbitmap_vector_alloc (n_basic_blocks, max_uid); | |
747 | compute_kill (bb_kill, btr_defset, btrs_written); | |
748 | free (btrs_written); | |
749 | ||
750 | bb_out = sbitmap_vector_alloc (n_basic_blocks, max_uid); | |
751 | compute_out (bb_out, bb_gen, bb_kill, max_uid); | |
752 | ||
753 | sbitmap_vector_free (bb_gen); | |
754 | sbitmap_vector_free (bb_kill); | |
755 | ||
756 | link_btr_uses (def_array, use_array, bb_out, btr_defset, max_uid); | |
757 | ||
758 | sbitmap_vector_free (bb_out); | |
759 | sbitmap_vector_free (btr_defset); | |
760 | free (use_array); | |
761 | free (def_array); | |
762 | } | |
763 | ||
764 | /* Return true if basic block BB contains the start or end of the | |
765 | live range of the definition DEF, AND there are other live | |
766 | ranges of the same target register that include BB. */ | |
767 | static int | |
768 | block_at_edge_of_live_range_p (int bb, btr_def def) | |
769 | { | |
770 | if (def->other_btr_uses_before_def && BASIC_BLOCK (bb) == def->bb) | |
771 | return 1; | |
772 | else if (def->other_btr_uses_after_use) | |
773 | { | |
774 | btr_user user; | |
775 | for (user = def->uses; user != NULL; user = user->next) | |
776 | if (BASIC_BLOCK (bb) == user->bb) | |
777 | return 1; | |
778 | } | |
779 | return 0; | |
780 | } | |
781 | ||
782 | /* We are removing the def/use web DEF. The target register | |
783 | used in this web is therefore no longer live in the live range | |
784 | of this web, so remove it from the live set of all basic blocks | |
785 | in the live range of the web. | |
786 | Blocks at the boundary of the live range may contain other live | |
787 | ranges for the same target register, so we have to be careful | |
788 | to remove the target register from the live set of these blocks | |
71c0e7fc | 789 | only if they do not contain other live ranges for the same register. */ |
fe3ad572 SC |
790 | static void |
791 | clear_btr_from_live_range (btr_def def) | |
792 | { | |
793 | int bb; | |
794 | ||
795 | EXECUTE_IF_SET_IN_BITMAP | |
796 | (def->live_range, 0, bb, | |
797 | { | |
798 | if ((!def->other_btr_uses_before_def | |
799 | && !def->other_btr_uses_after_use) | |
800 | || !block_at_edge_of_live_range_p (bb, def)) | |
801 | { | |
802 | CLEAR_HARD_REG_BIT (btrs_live[bb], def->btr); | |
803 | if (rtl_dump_file) | |
804 | dump_btrs_live (bb); | |
805 | } | |
806 | }); | |
807 | } | |
808 | ||
809 | ||
810 | /* We are adding the def/use web DEF. Add the target register used | |
811 | in this web to the live set of all of the basic blocks that contain | |
812 | the live range of the web. */ | |
813 | static void | |
814 | add_btr_to_live_range (btr_def def) | |
815 | { | |
816 | int bb; | |
817 | EXECUTE_IF_SET_IN_BITMAP | |
818 | (def->live_range, 0, bb, | |
819 | { | |
820 | SET_HARD_REG_BIT (btrs_live[bb], def->btr); | |
821 | if (rtl_dump_file) | |
822 | dump_btrs_live (bb); | |
823 | }); | |
824 | } | |
825 | ||
826 | /* Update a live range to contain the basic block NEW_BLOCK, and all | |
827 | blocks on paths between the existing live range and NEW_BLOCK. | |
828 | HEAD is a block contained in the existing live range that dominates | |
829 | all other blocks in the existing live range. | |
830 | Also add to the set BTRS_LIVE_IN_RANGE all target registers that | |
831 | are live in the blocks that we add to the live range. | |
832 | It is a precondition that either NEW_BLOCK dominates HEAD,or | |
833 | HEAD dom NEW_BLOCK. This is used to speed up the | |
834 | implementation of this function. */ | |
835 | static void | |
836 | augment_live_range (bitmap live_range, HARD_REG_SET *btrs_live_in_range, | |
837 | basic_block head_bb, basic_block new_bb) | |
838 | { | |
839 | basic_block *worklist, *tos; | |
840 | ||
703ad42b | 841 | tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1)); |
fe3ad572 SC |
842 | |
843 | if (dominated_by_p (dom, new_bb, head_bb)) | |
844 | *tos++ = new_bb; | |
845 | else if (dominated_by_p (dom, head_bb, new_bb)) | |
846 | { | |
847 | edge e; | |
848 | int new_block = new_bb->index; | |
849 | ||
850 | bitmap_set_bit (live_range, new_block); | |
851 | IOR_HARD_REG_SET (*btrs_live_in_range, btrs_live[new_block]); | |
852 | if (rtl_dump_file) | |
853 | { | |
854 | fprintf (rtl_dump_file, | |
855 | "Adding block %d to live range\n", new_block); | |
856 | fprintf (rtl_dump_file,"Now live btrs are "); | |
857 | dump_hard_reg_set (*btrs_live_in_range); | |
858 | fprintf (rtl_dump_file, "\n"); | |
859 | } | |
860 | for (e = head_bb->pred; e; e = e->pred_next) | |
861 | *tos++ = e->src; | |
862 | } | |
863 | else | |
864 | abort(); | |
865 | ||
866 | while (tos != worklist) | |
867 | { | |
868 | basic_block bb = *--tos; | |
869 | if (!bitmap_bit_p (live_range, bb->index)) | |
870 | { | |
871 | edge e; | |
872 | ||
873 | bitmap_set_bit (live_range, bb->index); | |
874 | IOR_HARD_REG_SET (*btrs_live_in_range, | |
875 | btrs_live[bb->index]); | |
876 | if (rtl_dump_file) | |
877 | { | |
878 | fprintf (rtl_dump_file, | |
879 | "Adding block %d to live range\n", bb->index); | |
880 | fprintf (rtl_dump_file,"Now live btrs are "); | |
881 | dump_hard_reg_set (*btrs_live_in_range); | |
882 | fprintf (rtl_dump_file, "\n"); | |
883 | } | |
884 | ||
885 | for (e = bb->pred; e != NULL; e = e->pred_next) | |
886 | { | |
887 | basic_block pred = e->src; | |
888 | if (!bitmap_bit_p (live_range, pred->index)) | |
889 | *tos++ = pred; | |
890 | } | |
891 | } | |
892 | } | |
893 | ||
894 | free (worklist); | |
895 | } | |
896 | ||
897 | /* Return the most desirable target register that is not in | |
898 | the set USED_BTRS. */ | |
899 | static int | |
900 | choose_btr (HARD_REG_SET used_btrs) | |
901 | { | |
902 | int i; | |
903 | GO_IF_HARD_REG_SUBSET (all_btrs, used_btrs, give_up); | |
904 | ||
905 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
906 | { | |
907 | #ifdef REG_ALLOC_ORDER | |
908 | int regno = reg_alloc_order[i]; | |
909 | #else | |
910 | int regno = i; | |
911 | #endif | |
912 | if (TEST_HARD_REG_BIT (all_btrs, regno) | |
913 | && !TEST_HARD_REG_BIT (used_btrs, regno)) | |
914 | return regno; | |
915 | } | |
916 | give_up: | |
917 | return -1; | |
918 | } | |
919 | ||
920 | /* Calculate the set of basic blocks that contain the live range of | |
921 | the def/use web DEF. | |
922 | Also calculate the set of target registers that are live at time | |
923 | in this live range, but ignore the live range represented by DEF | |
924 | when calculating this set. */ | |
925 | static void | |
926 | btr_def_live_range (btr_def def, HARD_REG_SET *btrs_live_in_range) | |
927 | { | |
928 | if (!def->live_range) | |
929 | { | |
930 | btr_user user; | |
931 | ||
932 | def->live_range = BITMAP_XMALLOC (); | |
933 | ||
934 | bitmap_set_bit (def->live_range, def->bb->index); | |
935 | COPY_HARD_REG_SET (*btrs_live_in_range, btrs_live[def->bb->index]); | |
936 | ||
937 | for (user = def->uses; user != NULL; user = user->next) | |
938 | augment_live_range (def->live_range, btrs_live_in_range, | |
939 | def->bb, user->bb); | |
940 | } | |
941 | else | |
942 | { | |
943 | /* def->live_range is accurate, but we need to recompute | |
944 | the set of target registers live over it, because migration | |
945 | of other PT instructions may have affected it. | |
946 | */ | |
947 | int bb; | |
948 | ||
949 | CLEAR_HARD_REG_SET (*btrs_live_in_range); | |
950 | EXECUTE_IF_SET_IN_BITMAP | |
951 | (def->live_range, 0, bb, | |
952 | { | |
953 | IOR_HARD_REG_SET (*btrs_live_in_range, | |
954 | btrs_live[bb]); | |
955 | }); | |
956 | } | |
957 | if (!def->other_btr_uses_before_def && | |
958 | !def->other_btr_uses_after_use) | |
959 | CLEAR_HARD_REG_BIT (*btrs_live_in_range, def->btr); | |
960 | } | |
961 | ||
962 | /* Merge into the def/use web DEF any other def/use webs in the same | |
963 | group that are dominated by DEF, provided that there is a target | |
964 | register available to allocate to the merged web. */ | |
965 | static void | |
966 | combine_btr_defs (btr_def def, HARD_REG_SET *btrs_live_in_range) | |
967 | { | |
968 | btr_def other_def; | |
969 | ||
970 | for (other_def = def->group->members; | |
971 | other_def != NULL; | |
972 | other_def = other_def->next_this_group) | |
973 | { | |
974 | if (other_def != def | |
975 | && other_def->uses != NULL | |
976 | && ! other_def->has_ambiguous_use | |
977 | && dominated_by_p (dom, other_def->bb, def->bb)) | |
978 | { | |
979 | /* def->bb dominates the other def, so def and other_def could | |
71c0e7fc | 980 | be combined. */ |
fe3ad572 | 981 | /* Merge their live ranges, and get the set of |
71c0e7fc | 982 | target registers live over the merged range. */ |
fe3ad572 SC |
983 | int btr; |
984 | HARD_REG_SET combined_btrs_live; | |
985 | bitmap combined_live_range = BITMAP_XMALLOC (); | |
986 | btr_user user; | |
987 | ||
988 | if (other_def->live_range == NULL) | |
989 | { | |
990 | HARD_REG_SET dummy_btrs_live_in_range; | |
991 | btr_def_live_range (other_def, &dummy_btrs_live_in_range); | |
992 | } | |
993 | COPY_HARD_REG_SET (combined_btrs_live, *btrs_live_in_range); | |
994 | bitmap_copy (combined_live_range, def->live_range); | |
995 | ||
996 | for (user = other_def->uses; user != NULL; user = user->next) | |
997 | augment_live_range (combined_live_range, &combined_btrs_live, | |
998 | def->bb, user->bb); | |
999 | ||
1000 | btr = choose_btr (combined_btrs_live); | |
1001 | if (btr != -1) | |
1002 | { | |
f9da5064 | 1003 | /* We can combine them. */ |
fe3ad572 SC |
1004 | if (rtl_dump_file) |
1005 | fprintf (rtl_dump_file, | |
1006 | "Combining def in insn %d with def in insn %d\n", | |
1007 | INSN_UID (other_def->insn), INSN_UID (def->insn)); | |
1008 | ||
1009 | def->btr = btr; | |
1010 | user = other_def->uses; | |
1011 | while (user != NULL) | |
1012 | { | |
1013 | btr_user next = user->next; | |
1014 | ||
1015 | user->next = def->uses; | |
1016 | def->uses = user; | |
1017 | user = next; | |
1018 | } | |
1019 | /* Combining def/use webs can make target registers live | |
1020 | after uses where they previously were not. This means | |
1021 | some REG_DEAD notes may no longer be correct. We could | |
1022 | be more precise about this if we looked at the combined | |
1023 | live range, but here I just delete any REG_DEAD notes | |
71c0e7fc | 1024 | in case they are no longer correct. */ |
fe3ad572 SC |
1025 | for (user = def->uses; user != NULL; user = user->next) |
1026 | remove_note (user->insn, | |
1027 | find_regno_note (user->insn, REG_DEAD, | |
1028 | REGNO (user->use))); | |
1029 | clear_btr_from_live_range (other_def); | |
1030 | other_def->uses = NULL; | |
1031 | bitmap_copy (def->live_range, combined_live_range); | |
1032 | if (other_def->other_btr_uses_after_use) | |
1033 | def->other_btr_uses_after_use = 1; | |
1034 | COPY_HARD_REG_SET (*btrs_live_in_range, combined_btrs_live); | |
1035 | ||
f9da5064 | 1036 | /* Delete the old target register initialization. */ |
fe3ad572 SC |
1037 | delete_insn (other_def->insn); |
1038 | ||
1039 | } | |
1040 | BITMAP_XFREE (combined_live_range); | |
1041 | } | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | /* Move the definition DEF from its current position to basic | |
1046 | block NEW_DEF_BB, and modify it to use branch target register BTR. | |
1047 | Delete the old defining insn, and insert a new one in NEW_DEF_BB. | |
1048 | Update all reaching uses of DEF in the RTL to use BTR. | |
1049 | If this new position means that other defs in the | |
1050 | same group can be combined with DEF then combine them. */ | |
1051 | static void | |
1052 | move_btr_def (basic_block new_def_bb, int btr, btr_def def, bitmap live_range, | |
1053 | HARD_REG_SET *btrs_live_in_range) | |
1054 | { | |
1055 | /* We can move the instruction. | |
1056 | Set a target register in block NEW_DEF_BB to the value | |
1057 | needed for this target register definition. | |
1058 | Replace all uses of the old target register definition by | |
71c0e7fc | 1059 | uses of the new definition. Delete the old definition. */ |
fe3ad572 | 1060 | basic_block b = new_def_bb; |
a813c111 | 1061 | rtx insp = BB_HEAD (b); |
fe3ad572 SC |
1062 | rtx old_insn = def->insn; |
1063 | rtx src; | |
1064 | rtx btr_rtx; | |
1065 | rtx new_insn; | |
1066 | enum machine_mode btr_mode; | |
1067 | btr_user user; | |
1068 | rtx set; | |
1069 | ||
1070 | if (rtl_dump_file) | |
1071 | fprintf(rtl_dump_file, "migrating to basic block %d, using reg %d\n", | |
1072 | new_def_bb->index, btr); | |
1073 | ||
1074 | clear_btr_from_live_range (def); | |
1075 | def->btr = btr; | |
1076 | def->bb = new_def_bb; | |
1077 | def->luid = 0; | |
1078 | def->cost = basic_block_freq (new_def_bb); | |
1079 | def->other_btr_uses_before_def = 0; | |
1080 | bitmap_copy (def->live_range, live_range); | |
1081 | combine_btr_defs (def, btrs_live_in_range); | |
1082 | btr = def->btr; | |
1083 | add_btr_to_live_range (def); | |
1084 | if (GET_CODE (insp) == CODE_LABEL) | |
1085 | insp = NEXT_INSN (insp); | |
1086 | /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some | |
1087 | optimizations can result in insp being both first and last insn of | |
1088 | its basic block. */ | |
1089 | /* ?? some assertions to check that insp is sensible? */ | |
1090 | ||
1091 | set = single_set (old_insn); | |
1092 | src = SET_SRC (set); | |
1093 | btr_mode = GET_MODE (SET_DEST (set)); | |
1094 | btr_rtx = gen_rtx (REG, btr_mode, btr); | |
1095 | ||
1096 | new_insn = gen_move_insn (btr_rtx, src); | |
1097 | ||
71c0e7fc | 1098 | /* Insert target register initialization at head of basic block. */ |
fe3ad572 SC |
1099 | def->insn = emit_insn_after (new_insn, insp); |
1100 | ||
1101 | regs_ever_live[btr] = 1; | |
1102 | ||
1103 | if (rtl_dump_file) | |
1104 | fprintf (rtl_dump_file, "New pt is insn %d, inserted after insn %d\n", | |
1105 | INSN_UID (def->insn), INSN_UID (insp)); | |
1106 | ||
f9da5064 | 1107 | /* Delete the old target register initialization. */ |
fe3ad572 SC |
1108 | delete_insn (old_insn); |
1109 | ||
1110 | /* Replace each use of the old target register by a use of the new target | |
71c0e7fc | 1111 | register. */ |
fe3ad572 SC |
1112 | for (user = def->uses; user != NULL; user = user->next) |
1113 | { | |
1114 | /* Some extra work here to ensure consistent modes, because | |
1115 | it seems that a target register REG rtx can be given a different | |
1116 | mode depending on the context (surely that should not be | |
71c0e7fc | 1117 | the case?). */ |
fe3ad572 SC |
1118 | rtx replacement_rtx; |
1119 | if (GET_MODE (user->use) == GET_MODE (btr_rtx) | |
1120 | || GET_MODE (user->use) == VOIDmode) | |
1121 | replacement_rtx = btr_rtx; | |
1122 | else | |
1123 | replacement_rtx = gen_rtx (REG, GET_MODE (user->use), btr); | |
1124 | replace_rtx (user->insn, user->use, replacement_rtx); | |
1125 | user->use = replacement_rtx; | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | /* We anticipate intra-block scheduling to be done. See if INSN could move | |
1130 | up within BB by N_INSNS. */ | |
1131 | static int | |
1132 | can_move_up (basic_block bb, rtx insn, int n_insns) | |
1133 | { | |
a813c111 | 1134 | while (insn != BB_HEAD (bb) && n_insns > 0) |
fe3ad572 SC |
1135 | { |
1136 | insn = PREV_INSN (insn); | |
1137 | /* ??? What if we have an anti-dependency that actually prevents the | |
1138 | scheduler from doing the move? We'd like to re-allocate the register, | |
1139 | but not necessarily put the load into another basic block. */ | |
1140 | if (INSN_P (insn)) | |
1141 | n_insns--; | |
1142 | } | |
1143 | return n_insns <= 0; | |
1144 | } | |
1145 | ||
1146 | /* Attempt to migrate the target register definition DEF to an | |
1147 | earlier point in the flowgraph. | |
1148 | ||
1149 | It is a precondition of this function that DEF is migratable: | |
1150 | i.e. it has a constant source, and all uses are unambiguous. | |
1151 | ||
1152 | Only migrations that reduce the cost of DEF will be made. | |
1153 | MIN_COST is the lower bound on the cost of the DEF after migration. | |
1154 | If we migrate DEF so that its cost falls below MIN_COST, | |
1155 | then we do not attempt to migrate further. The idea is that | |
4d6922ee | 1156 | we migrate definitions in a priority order based on their cost, |
fe3ad572 SC |
1157 | when the cost of this definition falls below MIN_COST, then |
1158 | there is another definition with cost == MIN_COST which now | |
1159 | has a higher priority than this definition. | |
1160 | ||
cc0efd0b | 1161 | Return nonzero if there may be benefit from attempting to |
fe3ad572 SC |
1162 | migrate this DEF further (i.e. we have reduced the cost below |
1163 | MIN_COST, but we may be able to reduce it further). | |
71c0e7fc | 1164 | Return zero if no further migration is possible. */ |
fe3ad572 SC |
1165 | static int |
1166 | migrate_btr_def (btr_def def, int min_cost) | |
1167 | { | |
1168 | bitmap live_range; | |
1169 | HARD_REG_SET btrs_live_in_range; | |
1170 | int btr_used_near_def = 0; | |
1171 | int def_basic_block_freq; | |
1172 | basic_block try; | |
1173 | int give_up = 0; | |
1174 | int def_moved = 0; | |
1175 | btr_user user; | |
5a9384dd | 1176 | int def_latency = 1; |
fe3ad572 SC |
1177 | |
1178 | if (rtl_dump_file) | |
1179 | fprintf (rtl_dump_file, | |
1180 | "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ", | |
1181 | INSN_UID (def->insn), def->cost, min_cost); | |
1182 | ||
1183 | if (!def->group || def->has_ambiguous_use) | |
f9da5064 | 1184 | /* These defs are not migratable. */ |
fe3ad572 SC |
1185 | { |
1186 | if (rtl_dump_file) | |
1187 | fprintf (rtl_dump_file, "it's not migratable\n"); | |
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | if (!def->uses) | |
1192 | /* We have combined this def with another in the same group, so | |
1193 | no need to consider it further. | |
1194 | */ | |
1195 | { | |
1196 | if (rtl_dump_file) | |
1197 | fprintf (rtl_dump_file, "it's already combined with another pt\n"); | |
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | btr_def_live_range (def, &btrs_live_in_range); | |
1202 | live_range = BITMAP_XMALLOC (); | |
1203 | bitmap_copy (live_range, def->live_range); | |
1204 | ||
5a9384dd | 1205 | #ifdef INSN_SCHEDULING |
fe3ad572 SC |
1206 | if ((*targetm.sched.use_dfa_pipeline_interface) ()) |
1207 | def_latency = insn_default_latency (def->insn); | |
1208 | else | |
1209 | def_latency = result_ready_cost (def->insn); | |
5a9384dd HPN |
1210 | #endif |
1211 | ||
fe3ad572 SC |
1212 | def_latency *= issue_rate; |
1213 | ||
1214 | for (user = def->uses; user != NULL; user = user->next) | |
1215 | { | |
1216 | if (user->bb == def->bb | |
1217 | && user->luid > def->luid | |
1218 | && (def->luid + def_latency) > user->luid | |
1219 | && ! can_move_up (def->bb, def->insn, | |
1220 | (def->luid + def_latency) - user->luid)) | |
1221 | { | |
1222 | btr_used_near_def = 1; | |
1223 | break; | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | def_basic_block_freq = basic_block_freq (def->bb); | |
1228 | ||
1229 | for (try = get_immediate_dominator (dom, def->bb); | |
1230 | !give_up && try && try != ENTRY_BLOCK_PTR && def->cost >= min_cost; | |
1231 | try = get_immediate_dominator (dom, try)) | |
1232 | { | |
1233 | /* Try to move the instruction that sets the target register into | |
71c0e7fc | 1234 | basic block TRY. */ |
fe3ad572 SC |
1235 | int try_freq = basic_block_freq (try); |
1236 | ||
1237 | if (rtl_dump_file) | |
1238 | fprintf (rtl_dump_file, "trying block %d ...", try->index); | |
1239 | ||
1240 | if (try_freq < def_basic_block_freq | |
1241 | || (try_freq == def_basic_block_freq && btr_used_near_def)) | |
1242 | { | |
1243 | int btr; | |
1244 | augment_live_range (live_range, &btrs_live_in_range, def->bb, try); | |
1245 | if (rtl_dump_file) | |
1246 | { | |
1247 | fprintf (rtl_dump_file, "Now btrs live in range are: "); | |
1248 | dump_hard_reg_set (btrs_live_in_range); | |
1249 | fprintf (rtl_dump_file, "\n"); | |
1250 | } | |
1251 | btr = choose_btr (btrs_live_in_range); | |
1252 | if (btr != -1) | |
1253 | { | |
1254 | move_btr_def (try, btr, def, live_range, &btrs_live_in_range); | |
1255 | bitmap_copy(live_range, def->live_range); | |
1256 | btr_used_near_def = 0; | |
1257 | def_moved = 1; | |
1258 | def_basic_block_freq = basic_block_freq (def->bb); | |
1259 | } | |
1260 | else | |
1261 | { | |
1262 | /* There are no free target registers available to move | |
1263 | this far forward, so give up */ | |
1264 | give_up = 1; | |
1265 | if (rtl_dump_file) | |
1266 | fprintf (rtl_dump_file, | |
1267 | "giving up because there are no free target registers\n"); | |
1268 | } | |
1269 | ||
1270 | } | |
1271 | } | |
1272 | if (!def_moved) | |
1273 | { | |
1274 | give_up = 1; | |
1275 | if (rtl_dump_file) | |
1276 | fprintf (rtl_dump_file, "failed to move\n"); | |
1277 | } | |
1278 | BITMAP_XFREE (live_range); | |
1279 | return !give_up; | |
1280 | } | |
1281 | ||
1282 | /* Attempt to move instructions that set target registers earlier | |
71c0e7fc | 1283 | in the flowgraph, away from their corresponding uses. */ |
fe3ad572 SC |
1284 | static void |
1285 | migrate_btr_defs (enum reg_class btr_class, int allow_callee_save) | |
1286 | { | |
1287 | fibheap_t all_btr_defs = fibheap_new (); | |
1288 | int reg; | |
1289 | ||
1290 | gcc_obstack_init (&migrate_btrl_obstack); | |
1291 | if (rtl_dump_file) | |
1292 | { | |
1293 | int i; | |
1294 | ||
1295 | for (i = 0; i < n_basic_blocks; i++) | |
1296 | { | |
1297 | basic_block bb = BASIC_BLOCK (i); | |
1298 | fprintf(rtl_dump_file, | |
551dc360 AJ |
1299 | "Basic block %d: count = " HOST_WIDEST_INT_PRINT_DEC |
1300 | " loop-depth = %d idom = %d\n", | |
1301 | i, (HOST_WIDEST_INT) bb->count, bb->loop_depth, | |
fe3ad572 SC |
1302 | get_immediate_dominator (dom, bb)->index); |
1303 | } | |
1304 | } | |
1305 | ||
1306 | CLEAR_HARD_REG_SET (all_btrs); | |
1307 | for (first_btr = -1, reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++) | |
1308 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) btr_class], reg) | |
1309 | && (allow_callee_save || call_used_regs[reg] || regs_ever_live[reg])) | |
1310 | { | |
1311 | SET_HARD_REG_BIT (all_btrs, reg); | |
1312 | last_btr = reg; | |
1313 | if (first_btr < 0) | |
1314 | first_btr = reg; | |
1315 | } | |
1316 | ||
703ad42b | 1317 | btrs_live = xcalloc (n_basic_blocks, sizeof (HARD_REG_SET)); |
fe3ad572 SC |
1318 | |
1319 | build_btr_def_use_webs (all_btr_defs); | |
1320 | ||
1321 | while (!fibheap_empty (all_btr_defs)) | |
1322 | { | |
1323 | btr_def def = | |
1324 | (btr_def) fibheap_extract_min (all_btr_defs); | |
1325 | int min_cost = -fibheap_min_key (all_btr_defs); | |
1326 | if (migrate_btr_def (def, min_cost)) | |
1327 | { | |
1328 | fibheap_insert (all_btr_defs, -def->cost, (void *) def); | |
1329 | if (rtl_dump_file) | |
1330 | { | |
1331 | fprintf (rtl_dump_file, | |
1332 | "Putting insn %d back on queue with priority %d\n", | |
1333 | INSN_UID (def->insn), def->cost); | |
1334 | } | |
1335 | } | |
1336 | else | |
1337 | { | |
1338 | if (def->live_range) | |
1339 | BITMAP_XFREE (def->live_range); | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | free (btrs_live); | |
1344 | obstack_free (&migrate_btrl_obstack, NULL); | |
1345 | fibheap_delete (all_btr_defs); | |
1346 | } | |
1347 | ||
1348 | void | |
1349 | branch_target_load_optimize (rtx insns, bool after_prologue_epilogue_gen) | |
1350 | { | |
1351 | enum reg_class class = (*targetm.branch_target_register_class) (); | |
1352 | if (class != NO_REGS) | |
1353 | { | |
1354 | /* Initialize issue_rate. */ | |
1355 | if (targetm.sched.issue_rate) | |
1356 | issue_rate = (*targetm.sched.issue_rate) (); | |
1357 | else | |
1358 | issue_rate = 1; | |
1359 | ||
71c0e7fc | 1360 | /* Build the CFG for migrate_btr_defs. */ |
fe3ad572 SC |
1361 | #if 1 |
1362 | /* This may or may not be needed, depending on where we | |
71c0e7fc | 1363 | run this phase. */ |
fe3ad572 SC |
1364 | cleanup_cfg (optimize ? CLEANUP_EXPENSIVE : 0); |
1365 | #endif | |
1366 | ||
1367 | life_analysis (insns, NULL, 0); | |
1368 | ||
71c0e7fc | 1369 | /* Dominator info is also needed for migrate_btr_def. */ |
fe3ad572 SC |
1370 | dom = calculate_dominance_info (CDI_DOMINATORS); |
1371 | migrate_btr_defs (class, | |
1372 | ((*targetm.branch_target_register_callee_saved) | |
1373 | (after_prologue_epilogue_gen))); | |
1374 | ||
1375 | free_dominance_info (dom); | |
1376 | ||
1377 | update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, | |
1378 | PROP_DEATH_NOTES | PROP_REG_INFO); | |
1379 | } | |
1380 | } |