]>
Commit | Line | Data |
---|---|---|
3b9d3628 | 1 | /* Save and restore call-clobbered registers which are live across a call. |
fbd26352 | 2 | Copyright (C) 1989-2019 Free Software Foundation, Inc. |
3b9d3628 | 3 | |
f12b58b3 | 4 | This file is part of GCC. |
3b9d3628 | 5 | |
f12b58b3 | 6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 8 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 9 | version. |
3b9d3628 | 10 | |
f12b58b3 | 11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
3b9d3628 | 15 | |
16 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
3b9d3628 | 19 | |
20 | #include "config.h" | |
405711de | 21 | #include "system.h" |
805e22b2 | 22 | #include "coretypes.h" |
9ef16211 | 23 | #include "backend.h" |
3b9d3628 | 24 | #include "rtl.h" |
7c29e30e | 25 | #include "tree.h" |
26 | #include "predict.h" | |
9ef16211 | 27 | #include "df.h" |
ad7b10a2 | 28 | #include "memmodel.h" |
7c29e30e | 29 | #include "tm_p.h" |
3b9d3628 | 30 | #include "insn-config.h" |
7c29e30e | 31 | #include "regs.h" |
32 | #include "emit-rtl.h" | |
3b9d3628 | 33 | #include "recog.h" |
94ea8568 | 34 | #include "reload.h" |
d53441c8 | 35 | #include "alias.h" |
7a37d50b | 36 | #include "addresses.h" |
b9ed1410 | 37 | #include "dumpfile.h" |
0e74eb28 | 38 | #include "rtl-iter.h" |
b395382f | 39 | #include "target.h" |
3b9d3628 | 40 | |
590ec786 | 41 | #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD) |
42 | ||
c3997e3d | 43 | #define regno_save_mode \ |
44 | (this_target_reload->x_regno_save_mode) | |
1ad9923a | 45 | #define cached_reg_save_code \ |
46 | (this_target_reload->x_cached_reg_save_code) | |
47 | #define cached_reg_restore_code \ | |
48 | (this_target_reload->x_cached_reg_restore_code) | |
3b9d3628 | 49 | |
50 | /* For each hard register, a place on the stack where it can be saved, | |
51 | if needed. */ | |
52 | ||
4c9e08a4 | 53 | static rtx |
65748b1b | 54 | regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]; |
3b9d3628 | 55 | |
47dd2e78 | 56 | /* The number of elements in the subsequent array. */ |
57 | static int save_slots_num; | |
58 | ||
59 | /* Allocated slots so far. */ | |
60 | static rtx save_slots[FIRST_PSEUDO_REGISTER]; | |
61 | ||
3b9d3628 | 62 | /* Set of hard regs currently residing in save area (during insn scan). */ |
63 | ||
64 | static HARD_REG_SET hard_regs_saved; | |
65 | ||
590ec786 | 66 | /* Number of registers currently in hard_regs_saved. */ |
379d2d5f | 67 | |
590ec786 | 68 | static int n_regs_saved; |
379d2d5f | 69 | |
590ec786 | 70 | /* Computed by mark_referenced_regs, all regs referenced in a given |
71 | insn. */ | |
72 | static HARD_REG_SET referenced_regs; | |
3b9d3628 | 73 | |
590ec786 | 74 | |
3754d046 | 75 | typedef void refmarker_fn (rtx *loc, machine_mode mode, int hardregno, |
9845d120 | 76 | void *mark_arg); |
77 | ||
3754d046 | 78 | static int reg_save_code (int, machine_mode); |
79 | static int reg_restore_code (int, machine_mode); | |
47dd2e78 | 80 | |
81 | struct saved_hard_reg; | |
82 | static void initiate_saved_hard_regs (void); | |
1084097d | 83 | static void new_saved_hard_reg (int, int); |
47dd2e78 | 84 | static void finish_saved_hard_regs (void); |
85 | static int saved_hard_reg_compare_func (const void *, const void *); | |
86 | ||
81a410b1 | 87 | static void mark_set_regs (rtx, const_rtx, void *); |
9845d120 | 88 | static void mark_referenced_regs (rtx *, refmarker_fn *mark, void *mark_arg); |
89 | static refmarker_fn mark_reg_as_referenced; | |
90 | static refmarker_fn replace_reg_with_saved_mem; | |
2e966e2a | 91 | static int insert_save (class insn_chain *, int, HARD_REG_SET *, |
3754d046 | 92 | machine_mode *); |
2e966e2a | 93 | static int insert_restore (class insn_chain *, int, int, int, |
3754d046 | 94 | machine_mode *); |
2e966e2a | 95 | static class insn_chain *insert_one_insn (class insn_chain *, int, int, |
4c9e08a4 | 96 | rtx); |
81a410b1 | 97 | static void add_stored_regs (rtx, const_rtx, void *); |
47dd2e78 | 98 | |
3b9d3628 | 99 | \f |
47dd2e78 | 100 | |
d7be1dc6 | 101 | static GTY(()) rtx savepat; |
102 | static GTY(()) rtx restpat; | |
103 | static GTY(()) rtx test_reg; | |
104 | static GTY(()) rtx test_mem; | |
ed3e6e5d | 105 | static GTY(()) rtx_insn *saveinsn; |
106 | static GTY(()) rtx_insn *restinsn; | |
d7be1dc6 | 107 | |
108 | /* Return the INSN_CODE used to save register REG in mode MODE. */ | |
109 | static int | |
3754d046 | 110 | reg_save_code (int reg, machine_mode mode) |
d7be1dc6 | 111 | { |
112 | bool ok; | |
113 | if (cached_reg_save_code[reg][mode]) | |
114 | return cached_reg_save_code[reg][mode]; | |
b395382f | 115 | if (!targetm.hard_regno_mode_ok (reg, mode)) |
728e6fe8 | 116 | { |
b395382f | 117 | /* Depending on how targetm.hard_regno_mode_ok is defined, range |
118 | propagation might deduce here that reg >= FIRST_PSEUDO_REGISTER. | |
119 | So the assert below silences a warning. */ | |
728e6fe8 | 120 | gcc_assert (reg < FIRST_PSEUDO_REGISTER); |
121 | cached_reg_save_code[reg][mode] = -1; | |
122 | cached_reg_restore_code[reg][mode] = -1; | |
123 | return -1; | |
124 | } | |
d7be1dc6 | 125 | |
126 | /* Update the register number and modes of the register | |
127 | and memory operand. */ | |
937ca48e | 128 | set_mode_and_regno (test_reg, mode, reg); |
d7be1dc6 | 129 | PUT_MODE (test_mem, mode); |
130 | ||
131 | /* Force re-recognition of the modified insns. */ | |
132 | INSN_CODE (saveinsn) = -1; | |
0b3fe24b | 133 | INSN_CODE (restinsn) = -1; |
d7be1dc6 | 134 | |
135 | cached_reg_save_code[reg][mode] = recog_memoized (saveinsn); | |
136 | cached_reg_restore_code[reg][mode] = recog_memoized (restinsn); | |
137 | ||
138 | /* Now extract both insns and see if we can meet their | |
e2f730a9 | 139 | constraints. We don't know here whether the save and restore will |
140 | be in size- or speed-tuned code, so just use the set of enabled | |
141 | alternatives. */ | |
d7be1dc6 | 142 | ok = (cached_reg_save_code[reg][mode] != -1 |
143 | && cached_reg_restore_code[reg][mode] != -1); | |
144 | if (ok) | |
145 | { | |
146 | extract_insn (saveinsn); | |
e2f730a9 | 147 | ok = constrain_operands (1, get_enabled_alternatives (saveinsn)); |
d7be1dc6 | 148 | extract_insn (restinsn); |
e2f730a9 | 149 | ok &= constrain_operands (1, get_enabled_alternatives (restinsn)); |
d7be1dc6 | 150 | } |
151 | ||
152 | if (! ok) | |
153 | { | |
154 | cached_reg_save_code[reg][mode] = -1; | |
155 | cached_reg_restore_code[reg][mode] = -1; | |
156 | } | |
157 | gcc_assert (cached_reg_save_code[reg][mode]); | |
158 | return cached_reg_save_code[reg][mode]; | |
159 | } | |
160 | ||
161 | /* Return the INSN_CODE used to restore register REG in mode MODE. */ | |
162 | static int | |
3754d046 | 163 | reg_restore_code (int reg, machine_mode mode) |
d7be1dc6 | 164 | { |
165 | if (cached_reg_restore_code[reg][mode]) | |
166 | return cached_reg_restore_code[reg][mode]; | |
167 | /* Populate our cache. */ | |
168 | reg_save_code (reg, mode); | |
169 | return cached_reg_restore_code[reg][mode]; | |
170 | } | |
171 | \f | |
3b9d3628 | 172 | /* Initialize for caller-save. |
173 | ||
174 | Look at all the hard registers that are used by a call and for which | |
ac502adf | 175 | reginfo.c has not already excluded from being used across a call. |
3b9d3628 | 176 | |
4c9e08a4 | 177 | Ensure that we can find a mode to save the register and that there is a |
3b9d3628 | 178 | simple insn to save and restore the register. This latter check avoids |
179 | problems that would occur if we tried to save the MQ register of some | |
180 | machines directly into memory. */ | |
181 | ||
182 | void | |
4c9e08a4 | 183 | init_caller_save (void) |
3b9d3628 | 184 | { |
3b9d3628 | 185 | rtx addr_reg; |
186 | int offset; | |
187 | rtx address; | |
379d2d5f | 188 | int i, j; |
3b9d3628 | 189 | |
4e4c89ec | 190 | if (caller_save_initialized_p) |
191 | return; | |
192 | ||
193 | caller_save_initialized_p = true; | |
194 | ||
47dd2e78 | 195 | CLEAR_HARD_REG_SET (no_caller_save_reg_set); |
3b9d3628 | 196 | /* First find all the registers that we need to deal with and all |
197 | the modes that they can have. If we can't find a mode to use, | |
198 | we can't have the register live over calls. */ | |
199 | ||
200 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
201 | { | |
4d8644f3 | 202 | if (call_used_regs[i] |
203 | && !TEST_HARD_REG_BIT (call_fixed_reg_set, i)) | |
3b9d3628 | 204 | { |
590ec786 | 205 | for (j = 1; j <= MOVE_MAX_WORDS; j++) |
3b9d3628 | 206 | { |
301652e2 | 207 | regno_save_mode[i][j] = HARD_REGNO_CALLER_SAVE_MODE (i, j, |
208 | VOIDmode); | |
379d2d5f | 209 | if (regno_save_mode[i][j] == VOIDmode && j == 1) |
210 | { | |
379d2d5f | 211 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
212 | } | |
3b9d3628 | 213 | } |
214 | } | |
215 | else | |
379d2d5f | 216 | regno_save_mode[i][1] = VOIDmode; |
3b9d3628 | 217 | } |
218 | ||
219 | /* The following code tries to approximate the conditions under which | |
220 | we can easily save and restore a register without scratch registers or | |
221 | other complexities. It will usually work, except under conditions where | |
222 | the validity of an insn operand is dependent on the address offset. | |
223 | No such cases are currently known. | |
224 | ||
225 | We first find a typical offset from some BASE_REG_CLASS register. | |
226 | This address is chosen by finding the first register in the class | |
227 | and by finding the smallest power of two that is a valid offset from | |
228 | that register in every mode we will use to save registers. */ | |
229 | ||
230 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2e6d14e8 | 231 | if (TEST_HARD_REG_BIT |
232 | (reg_class_contents | |
f8a8fc7b | 233 | [(int) base_reg_class (regno_save_mode[i][1], ADDR_SPACE_GENERIC, |
234 | PLUS, CONST_INT)], i)) | |
3b9d3628 | 235 | break; |
236 | ||
231bd014 | 237 | gcc_assert (i < FIRST_PSEUDO_REGISTER); |
3b9d3628 | 238 | |
941522d6 | 239 | addr_reg = gen_rtx_REG (Pmode, i); |
3b9d3628 | 240 | |
241 | for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1) | |
242 | { | |
c338f2e3 | 243 | address = gen_rtx_PLUS (Pmode, addr_reg, gen_int_mode (offset, Pmode)); |
3b9d3628 | 244 | |
245 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
379d2d5f | 246 | if (regno_save_mode[i][1] != VOIDmode |
247 | && ! strict_memory_address_p (regno_save_mode[i][1], address)) | |
3b9d3628 | 248 | break; |
249 | ||
250 | if (i == FIRST_PSEUDO_REGISTER) | |
251 | break; | |
252 | } | |
253 | ||
254 | /* If we didn't find a valid address, we must use register indirect. */ | |
255 | if (offset == 0) | |
256 | address = addr_reg; | |
257 | ||
258 | /* Next we try to form an insn to save and restore the register. We | |
4c9e08a4 | 259 | see if such an insn is recognized and meets its constraints. |
0c7f5242 | 260 | |
261 | To avoid lots of unnecessary RTL allocation, we construct all the RTL | |
262 | once, then modify the memory and register operands in-place. */ | |
263 | ||
dcd6d0f4 | 264 | test_reg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
06a78ffe | 265 | test_mem = gen_rtx_MEM (word_mode, address); |
d1f9b275 | 266 | savepat = gen_rtx_SET (test_mem, test_reg); |
267 | restpat = gen_rtx_SET (test_reg, test_mem); | |
3b9d3628 | 268 | |
5cda2bd0 | 269 | saveinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, savepat, 0, -1, 0); |
270 | restinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, restpat, 0, -1, 0); | |
55e5ddb4 | 271 | |
301652e2 | 272 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
273 | for (j = 1; j <= MOVE_MAX_WORDS; j++) | |
d7be1dc6 | 274 | if (reg_save_code (i,regno_save_mode[i][j]) == -1) |
301652e2 | 275 | { |
276 | regno_save_mode[i][j] = VOIDmode; | |
277 | if (j == 1) | |
278 | { | |
301652e2 | 279 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
47dd2e78 | 280 | if (call_used_regs[i]) |
281 | SET_HARD_REG_BIT (no_caller_save_reg_set, i); | |
301652e2 | 282 | } |
283 | } | |
3b9d3628 | 284 | } |
47dd2e78 | 285 | |
3b9d3628 | 286 | \f |
47dd2e78 | 287 | |
3b9d3628 | 288 | /* Initialize save areas by showing that we haven't allocated any yet. */ |
289 | ||
290 | void | |
4c9e08a4 | 291 | init_save_areas (void) |
3b9d3628 | 292 | { |
379d2d5f | 293 | int i, j; |
3b9d3628 | 294 | |
295 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
590ec786 | 296 | for (j = 1; j <= MOVE_MAX_WORDS; j++) |
379d2d5f | 297 | regno_save_mem[i][j] = 0; |
47dd2e78 | 298 | save_slots_num = 0; |
48e1416a | 299 | |
47dd2e78 | 300 | } |
301 | ||
302 | /* The structure represents a hard register which should be saved | |
303 | through the call. It is used when the integrated register | |
304 | allocator (IRA) is used and sharing save slots is on. */ | |
305 | struct saved_hard_reg | |
306 | { | |
307 | /* Order number starting with 0. */ | |
308 | int num; | |
309 | /* The hard regno. */ | |
310 | int hard_regno; | |
311 | /* Execution frequency of all calls through which given hard | |
312 | register should be saved. */ | |
313 | int call_freq; | |
314 | /* Stack slot reserved to save the hard register through calls. */ | |
315 | rtx slot; | |
316 | /* True if it is first hard register in the chain of hard registers | |
317 | sharing the same stack slot. */ | |
318 | int first_p; | |
319 | /* Order number of the next hard register structure with the same | |
320 | slot in the chain. -1 represents end of the chain. */ | |
321 | int next; | |
322 | }; | |
323 | ||
324 | /* Map: hard register number to the corresponding structure. */ | |
325 | static struct saved_hard_reg *hard_reg_map[FIRST_PSEUDO_REGISTER]; | |
326 | ||
327 | /* The number of all structures representing hard registers should be | |
328 | saved, in order words, the number of used elements in the following | |
329 | array. */ | |
330 | static int saved_regs_num; | |
331 | ||
332 | /* Pointers to all the structures. Index is the order number of the | |
333 | corresponding structure. */ | |
334 | static struct saved_hard_reg *all_saved_regs[FIRST_PSEUDO_REGISTER]; | |
335 | ||
336 | /* First called function for work with saved hard registers. */ | |
337 | static void | |
338 | initiate_saved_hard_regs (void) | |
339 | { | |
340 | int i; | |
341 | ||
342 | saved_regs_num = 0; | |
343 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
344 | hard_reg_map[i] = NULL; | |
345 | } | |
346 | ||
347 | /* Allocate and return new saved hard register with given REGNO and | |
348 | CALL_FREQ. */ | |
1084097d | 349 | static void |
47dd2e78 | 350 | new_saved_hard_reg (int regno, int call_freq) |
351 | { | |
352 | struct saved_hard_reg *saved_reg; | |
353 | ||
354 | saved_reg | |
355 | = (struct saved_hard_reg *) xmalloc (sizeof (struct saved_hard_reg)); | |
356 | hard_reg_map[regno] = all_saved_regs[saved_regs_num] = saved_reg; | |
357 | saved_reg->num = saved_regs_num++; | |
358 | saved_reg->hard_regno = regno; | |
359 | saved_reg->call_freq = call_freq; | |
360 | saved_reg->first_p = FALSE; | |
361 | saved_reg->next = -1; | |
47dd2e78 | 362 | } |
363 | ||
364 | /* Free memory allocated for the saved hard registers. */ | |
365 | static void | |
366 | finish_saved_hard_regs (void) | |
367 | { | |
368 | int i; | |
369 | ||
370 | for (i = 0; i < saved_regs_num; i++) | |
371 | free (all_saved_regs[i]); | |
372 | } | |
373 | ||
374 | /* The function is used to sort the saved hard register structures | |
375 | according their frequency. */ | |
376 | static int | |
377 | saved_hard_reg_compare_func (const void *v1p, const void *v2p) | |
378 | { | |
379 | const struct saved_hard_reg *p1 = *(struct saved_hard_reg * const *) v1p; | |
380 | const struct saved_hard_reg *p2 = *(struct saved_hard_reg * const *) v2p; | |
48e1416a | 381 | |
47dd2e78 | 382 | if (flag_omit_frame_pointer) |
383 | { | |
384 | if (p1->call_freq - p2->call_freq != 0) | |
385 | return p1->call_freq - p2->call_freq; | |
386 | } | |
387 | else if (p2->call_freq - p1->call_freq != 0) | |
388 | return p2->call_freq - p1->call_freq; | |
389 | ||
390 | return p1->num - p2->num; | |
3b9d3628 | 391 | } |
392 | ||
393 | /* Allocate save areas for any hard registers that might need saving. | |
394 | We take a conservative approach here and look for call-clobbered hard | |
395 | registers that are assigned to pseudos that cross calls. This may | |
396 | overestimate slightly (especially if some of these registers are later | |
397 | used as spill registers), but it should not be significant. | |
398 | ||
47dd2e78 | 399 | For IRA we use priority coloring to decrease stack slots needed for |
400 | saving hard registers through calls. We build conflicts for them | |
401 | to do coloring. | |
402 | ||
379d2d5f | 403 | Future work: |
404 | ||
405 | In the fallback case we should iterate backwards across all possible | |
4c9e08a4 | 406 | modes for the save, choosing the largest available one instead of |
379d2d5f | 407 | falling back to the smallest mode immediately. (eg TF -> DF -> SF). |
408 | ||
409 | We do not try to use "move multiple" instructions that exist | |
4c9e08a4 | 410 | on some machines (such as the 68k moveml). It could be a win to try |
379d2d5f | 411 | and use them when possible. The hard part is doing it in a way that is |
4c9e08a4 | 412 | machine independent since they might be saving non-consecutive |
379d2d5f | 413 | registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */ |
3b9d3628 | 414 | |
e546118a | 415 | void |
4c9e08a4 | 416 | setup_save_areas (void) |
3b9d3628 | 417 | { |
0268f1d4 | 418 | int i, j, k, freq; |
379d2d5f | 419 | HARD_REG_SET hard_regs_used; |
0268f1d4 | 420 | struct saved_hard_reg *saved_reg; |
a5412d60 | 421 | rtx_insn *insn; |
2e966e2a | 422 | class insn_chain *chain, *next; |
0268f1d4 | 423 | unsigned int regno; |
424 | HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets; | |
425 | reg_set_iterator rsi; | |
379d2d5f | 426 | |
379d2d5f | 427 | CLEAR_HARD_REG_SET (hard_regs_used); |
379d2d5f | 428 | |
0268f1d4 | 429 | /* Find every CALL_INSN and record which hard regs are live across the |
430 | call into HARD_REG_MAP and HARD_REGS_USED. */ | |
431 | initiate_saved_hard_regs (); | |
432 | /* Create hard reg saved regs. */ | |
433 | for (chain = reload_insn_chain; chain != 0; chain = next) | |
47dd2e78 | 434 | { |
c8010b80 | 435 | rtx cheap; |
436 | ||
0268f1d4 | 437 | insn = chain->insn; |
438 | next = chain->next; | |
439 | if (!CALL_P (insn) | |
440 | || find_reg_note (insn, REG_NORETURN, NULL)) | |
441 | continue; | |
442 | freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)); | |
443 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
444 | &chain->live_throughout); | |
754158d9 | 445 | get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); |
0268f1d4 | 446 | |
447 | /* Record all registers set in this call insn. These don't | |
448 | need to be saved. N.B. the call insn might set a subreg | |
449 | of a multi-hard-reg pseudo; then the pseudo is considered | |
450 | live during the call, but the subreg that is set | |
451 | isn't. */ | |
452 | CLEAR_HARD_REG_SET (this_insn_sets); | |
453 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
454 | /* Sibcalls are considered to set the return value. */ | |
455 | if (SIBLING_CALL_P (insn) && crtl->return_rtx) | |
456 | mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
457 | ||
458 | AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
459 | AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
460 | AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
461 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
462 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
463 | { | |
464 | if (hard_reg_map[regno] != NULL) | |
465 | hard_reg_map[regno]->call_freq += freq; | |
466 | else | |
1084097d | 467 | new_saved_hard_reg (regno, freq); |
0268f1d4 | 468 | SET_HARD_REG_BIT (hard_regs_used, regno); |
469 | } | |
c8010b80 | 470 | cheap = find_reg_note (insn, REG_RETURNED, NULL); |
471 | if (cheap) | |
472 | cheap = XEXP (cheap, 0); | |
0268f1d4 | 473 | /* Look through all live pseudos, mark their hard registers. */ |
474 | EXECUTE_IF_SET_IN_REG_SET | |
475 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
47dd2e78 | 476 | { |
0268f1d4 | 477 | int r = reg_renumber[regno]; |
478 | int bound; | |
47dd2e78 | 479 | |
c8010b80 | 480 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
0268f1d4 | 481 | continue; |
47dd2e78 | 482 | |
92d2aec3 | 483 | bound = r + hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno)); |
0268f1d4 | 484 | for (; r < bound; r++) |
485 | if (TEST_HARD_REG_BIT (used_regs, r)) | |
47dd2e78 | 486 | { |
0268f1d4 | 487 | if (hard_reg_map[r] != NULL) |
488 | hard_reg_map[r]->call_freq += freq; | |
47dd2e78 | 489 | else |
1084097d | 490 | new_saved_hard_reg (r, freq); |
0268f1d4 | 491 | SET_HARD_REG_BIT (hard_regs_to_save, r); |
492 | SET_HARD_REG_BIT (hard_regs_used, r); | |
47dd2e78 | 493 | } |
0268f1d4 | 494 | } |
495 | } | |
48e1416a | 496 | |
0268f1d4 | 497 | /* If requested, figure out which hard regs can share save slots. */ |
498 | if (optimize && flag_ira_share_save_slots) | |
499 | { | |
500 | rtx slot; | |
501 | char *saved_reg_conflicts; | |
502 | int next_k; | |
503 | struct saved_hard_reg *saved_reg2, *saved_reg3; | |
504 | int call_saved_regs_num; | |
505 | struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER]; | |
506 | int best_slot_num; | |
507 | int prev_save_slots_num; | |
508 | rtx prev_save_slots[FIRST_PSEUDO_REGISTER]; | |
48e1416a | 509 | |
47dd2e78 | 510 | /* Find saved hard register conflicts. */ |
511 | saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num); | |
512 | memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num); | |
513 | for (chain = reload_insn_chain; chain != 0; chain = next) | |
514 | { | |
c8010b80 | 515 | rtx cheap; |
47dd2e78 | 516 | call_saved_regs_num = 0; |
517 | insn = chain->insn; | |
518 | next = chain->next; | |
971ba038 | 519 | if (!CALL_P (insn) |
47dd2e78 | 520 | || find_reg_note (insn, REG_NORETURN, NULL)) |
521 | continue; | |
c8010b80 | 522 | |
523 | cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
524 | if (cheap) | |
525 | cheap = XEXP (cheap, 0); | |
526 | ||
47dd2e78 | 527 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, |
528 | &chain->live_throughout); | |
754158d9 | 529 | get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); |
47dd2e78 | 530 | |
531 | /* Record all registers set in this call insn. These don't | |
532 | need to be saved. N.B. the call insn might set a subreg | |
533 | of a multi-hard-reg pseudo; then the pseudo is considered | |
534 | live during the call, but the subreg that is set | |
535 | isn't. */ | |
536 | CLEAR_HARD_REG_SET (this_insn_sets); | |
537 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
538 | /* Sibcalls are considered to set the return value, | |
72c0c58f | 539 | compare df-scan.c:df_get_call_refs. */ |
47dd2e78 | 540 | if (SIBLING_CALL_P (insn) && crtl->return_rtx) |
541 | mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
542 | ||
543 | AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
544 | AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
545 | AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
546 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
547 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
548 | { | |
549 | gcc_assert (hard_reg_map[regno] != NULL); | |
550 | call_saved_regs[call_saved_regs_num++] = hard_reg_map[regno]; | |
551 | } | |
552 | /* Look through all live pseudos, mark their hard registers. */ | |
553 | EXECUTE_IF_SET_IN_REG_SET | |
554 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
3b9d3628 | 555 | { |
47dd2e78 | 556 | int r = reg_renumber[regno]; |
557 | int bound; | |
48e1416a | 558 | |
c8010b80 | 559 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
47dd2e78 | 560 | continue; |
561 | ||
92d2aec3 | 562 | bound = r + hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno)); |
47dd2e78 | 563 | for (; r < bound; r++) |
564 | if (TEST_HARD_REG_BIT (used_regs, r)) | |
565 | call_saved_regs[call_saved_regs_num++] = hard_reg_map[r]; | |
3b9d3628 | 566 | } |
47dd2e78 | 567 | for (i = 0; i < call_saved_regs_num; i++) |
568 | { | |
569 | saved_reg = call_saved_regs[i]; | |
570 | for (j = 0; j < call_saved_regs_num; j++) | |
571 | if (i != j) | |
572 | { | |
573 | saved_reg2 = call_saved_regs[j]; | |
574 | saved_reg_conflicts[saved_reg->num * saved_regs_num | |
575 | + saved_reg2->num] | |
576 | = saved_reg_conflicts[saved_reg2->num * saved_regs_num | |
577 | + saved_reg->num] | |
578 | = TRUE; | |
579 | } | |
580 | } | |
581 | } | |
582 | /* Sort saved hard regs. */ | |
583 | qsort (all_saved_regs, saved_regs_num, sizeof (struct saved_hard_reg *), | |
584 | saved_hard_reg_compare_func); | |
585 | /* Initiate slots available from the previous reload | |
586 | iteration. */ | |
587 | prev_save_slots_num = save_slots_num; | |
588 | memcpy (prev_save_slots, save_slots, save_slots_num * sizeof (rtx)); | |
589 | save_slots_num = 0; | |
590 | /* Allocate stack slots for the saved hard registers. */ | |
591 | for (i = 0; i < saved_regs_num; i++) | |
592 | { | |
593 | saved_reg = all_saved_regs[i]; | |
594 | regno = saved_reg->hard_regno; | |
595 | for (j = 0; j < i; j++) | |
596 | { | |
597 | saved_reg2 = all_saved_regs[j]; | |
598 | if (! saved_reg2->first_p) | |
599 | continue; | |
600 | slot = saved_reg2->slot; | |
601 | for (k = j; k >= 0; k = next_k) | |
602 | { | |
603 | saved_reg3 = all_saved_regs[k]; | |
604 | next_k = saved_reg3->next; | |
605 | if (saved_reg_conflicts[saved_reg->num * saved_regs_num | |
606 | + saved_reg3->num]) | |
607 | break; | |
608 | } | |
609 | if (k < 0 | |
52acb7ae | 610 | && known_le (GET_MODE_SIZE (regno_save_mode[regno][1]), |
611 | GET_MODE_SIZE (regno_save_mode | |
612 | [saved_reg2->hard_regno][1]))) | |
47dd2e78 | 613 | { |
614 | saved_reg->slot | |
615 | = adjust_address_nv | |
616 | (slot, regno_save_mode[saved_reg->hard_regno][1], 0); | |
617 | regno_save_mem[regno][1] = saved_reg->slot; | |
618 | saved_reg->next = saved_reg2->next; | |
619 | saved_reg2->next = i; | |
620 | if (dump_file != NULL) | |
621 | fprintf (dump_file, "%d uses slot of %d\n", | |
622 | regno, saved_reg2->hard_regno); | |
623 | break; | |
624 | } | |
625 | } | |
626 | if (j == i) | |
627 | { | |
628 | saved_reg->first_p = TRUE; | |
629 | for (best_slot_num = -1, j = 0; j < prev_save_slots_num; j++) | |
630 | { | |
631 | slot = prev_save_slots[j]; | |
632 | if (slot == NULL_RTX) | |
633 | continue; | |
52acb7ae | 634 | if (known_le (GET_MODE_SIZE (regno_save_mode[regno][1]), |
635 | GET_MODE_SIZE (GET_MODE (slot))) | |
47dd2e78 | 636 | && best_slot_num < 0) |
637 | best_slot_num = j; | |
638 | if (GET_MODE (slot) == regno_save_mode[regno][1]) | |
639 | break; | |
640 | } | |
641 | if (best_slot_num >= 0) | |
642 | { | |
643 | saved_reg->slot = prev_save_slots[best_slot_num]; | |
644 | saved_reg->slot | |
645 | = adjust_address_nv | |
646 | (saved_reg->slot, | |
647 | regno_save_mode[saved_reg->hard_regno][1], 0); | |
648 | if (dump_file != NULL) | |
649 | fprintf (dump_file, | |
650 | "%d uses a slot from prev iteration\n", regno); | |
651 | prev_save_slots[best_slot_num] = NULL_RTX; | |
652 | if (best_slot_num + 1 == prev_save_slots_num) | |
653 | prev_save_slots_num--; | |
654 | } | |
655 | else | |
656 | { | |
657 | saved_reg->slot | |
658 | = assign_stack_local_1 | |
659 | (regno_save_mode[regno][1], | |
943d8723 | 660 | GET_MODE_SIZE (regno_save_mode[regno][1]), 0, |
661 | ASLK_REDUCE_ALIGN); | |
47dd2e78 | 662 | if (dump_file != NULL) |
663 | fprintf (dump_file, "%d uses a new slot\n", regno); | |
664 | } | |
665 | regno_save_mem[regno][1] = saved_reg->slot; | |
666 | save_slots[save_slots_num++] = saved_reg->slot; | |
667 | } | |
668 | } | |
669 | free (saved_reg_conflicts); | |
670 | finish_saved_hard_regs (); | |
671 | } | |
672 | else | |
673 | { | |
0268f1d4 | 674 | /* We are not sharing slots. |
675 | ||
676 | Run through all the call-used hard-registers and allocate | |
677 | space for each in the caller-save area. Try to allocate space | |
47dd2e78 | 678 | in a manner which allows multi-register saves/restores to be done. */ |
48e1416a | 679 | |
47dd2e78 | 680 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
681 | for (j = MOVE_MAX_WORDS; j > 0; j--) | |
682 | { | |
683 | int do_save = 1; | |
48e1416a | 684 | |
47dd2e78 | 685 | /* If no mode exists for this size, try another. Also break out |
686 | if we have already saved this hard register. */ | |
687 | if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0) | |
688 | continue; | |
48e1416a | 689 | |
47dd2e78 | 690 | /* See if any register in this group has been saved. */ |
691 | for (k = 0; k < j; k++) | |
692 | if (regno_save_mem[i + k][1]) | |
693 | { | |
694 | do_save = 0; | |
695 | break; | |
696 | } | |
697 | if (! do_save) | |
698 | continue; | |
48e1416a | 699 | |
47dd2e78 | 700 | for (k = 0; k < j; k++) |
701 | if (! TEST_HARD_REG_BIT (hard_regs_used, i + k)) | |
702 | { | |
703 | do_save = 0; | |
704 | break; | |
705 | } | |
706 | if (! do_save) | |
707 | continue; | |
48e1416a | 708 | |
47dd2e78 | 709 | /* We have found an acceptable mode to store in. Since |
710 | hard register is always saved in the widest mode | |
711 | available, the mode may be wider than necessary, it is | |
712 | OK to reduce the alignment of spill space. We will | |
713 | verify that it is equal to or greater than required | |
714 | when we restore and save the hard register in | |
715 | insert_restore and insert_save. */ | |
716 | regno_save_mem[i][j] | |
717 | = assign_stack_local_1 (regno_save_mode[i][j], | |
718 | GET_MODE_SIZE (regno_save_mode[i][j]), | |
943d8723 | 719 | 0, ASLK_REDUCE_ALIGN); |
48e1416a | 720 | |
47dd2e78 | 721 | /* Setup single word save area just in case... */ |
722 | for (k = 0; k < j; k++) | |
723 | /* This should not depend on WORDS_BIG_ENDIAN. | |
724 | The order of words in regs is the same as in memory. */ | |
725 | regno_save_mem[i + k][1] | |
726 | = adjust_address_nv (regno_save_mem[i][j], | |
727 | regno_save_mode[i + k][1], | |
728 | k * UNITS_PER_WORD); | |
729 | } | |
730 | } | |
f7c44134 | 731 | |
732 | /* Now loop again and set the alias set of any save areas we made to | |
733 | the alias set used to represent frame objects. */ | |
734 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
735 | for (j = MOVE_MAX_WORDS; j > 0; j--) | |
736 | if (regno_save_mem[i][j] != 0) | |
ab6ab77e | 737 | set_mem_alias_set (regno_save_mem[i][j], get_frame_alias_set ()); |
3b9d3628 | 738 | } |
47dd2e78 | 739 | |
3b9d3628 | 740 | \f |
47dd2e78 | 741 | |
e546118a | 742 | /* Find the places where hard regs are live across calls and save them. */ |
f7c44134 | 743 | |
3b9d3628 | 744 | void |
4c9e08a4 | 745 | save_call_clobbered_regs (void) |
3b9d3628 | 746 | { |
2e966e2a | 747 | class insn_chain *chain, *next, *last = NULL; |
3754d046 | 748 | machine_mode save_mode [FIRST_PSEUDO_REGISTER]; |
590ec786 | 749 | |
d7e1f248 | 750 | /* Computed in mark_set_regs, holds all registers set by the current |
751 | instruction. */ | |
752 | HARD_REG_SET this_insn_sets; | |
753 | ||
590ec786 | 754 | CLEAR_HARD_REG_SET (hard_regs_saved); |
755 | n_regs_saved = 0; | |
3b9d3628 | 756 | |
590ec786 | 757 | for (chain = reload_insn_chain; chain != 0; chain = next) |
3b9d3628 | 758 | { |
7e48bf22 | 759 | rtx_insn *insn = chain->insn; |
590ec786 | 760 | enum rtx_code code = GET_CODE (insn); |
761 | ||
762 | next = chain->next; | |
763 | ||
231bd014 | 764 | gcc_assert (!chain->is_caller_save_insn); |
590ec786 | 765 | |
9845d120 | 766 | if (NONDEBUG_INSN_P (insn)) |
3b9d3628 | 767 | { |
590ec786 | 768 | /* If some registers have been saved, see if INSN references |
769 | any of them. We must restore them before the insn if so. */ | |
3b9d3628 | 770 | |
590ec786 | 771 | if (n_regs_saved) |
3b9d3628 | 772 | { |
590ec786 | 773 | int regno; |
d762f8cc | 774 | HARD_REG_SET this_insn_sets; |
590ec786 | 775 | |
776 | if (code == JUMP_INSN) | |
777 | /* Restore all registers if this is a JUMP_INSN. */ | |
778 | COPY_HARD_REG_SET (referenced_regs, hard_regs_saved); | |
c7279596 | 779 | else |
60d61663 | 780 | { |
590ec786 | 781 | CLEAR_HARD_REG_SET (referenced_regs); |
9845d120 | 782 | mark_referenced_regs (&PATTERN (insn), |
783 | mark_reg_as_referenced, NULL); | |
590ec786 | 784 | AND_HARD_REG_SET (referenced_regs, hard_regs_saved); |
60d61663 | 785 | } |
3b9d3628 | 786 | |
590ec786 | 787 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
788 | if (TEST_HARD_REG_BIT (referenced_regs, regno)) | |
d762f8cc | 789 | regno += insert_restore (chain, 1, regno, MOVE_MAX_WORDS, |
790 | save_mode); | |
791 | /* If a saved register is set after the call, this means we no | |
792 | longer should restore it. This can happen when parts of a | |
793 | multi-word pseudo do not conflict with other pseudos, so | |
794 | IRA may allocate the same hard register for both. One may | |
795 | be live across the call, while the other is set | |
796 | afterwards. */ | |
797 | CLEAR_HARD_REG_SET (this_insn_sets); | |
798 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
799 | AND_COMPL_HARD_REG_SET (hard_regs_saved, this_insn_sets); | |
3b9d3628 | 800 | } |
801 | ||
35c2394d | 802 | if (code == CALL_INSN |
803 | && ! SIBLING_CALL_P (insn) | |
804 | && ! find_reg_note (insn, REG_NORETURN, NULL)) | |
590ec786 | 805 | { |
4f917ffe | 806 | unsigned regno; |
590ec786 | 807 | HARD_REG_SET hard_regs_to_save; |
754158d9 | 808 | HARD_REG_SET call_def_reg_set; |
8c97cf13 | 809 | reg_set_iterator rsi; |
c8010b80 | 810 | rtx cheap; |
811 | ||
812 | cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
813 | if (cheap) | |
814 | cheap = XEXP (cheap, 0); | |
590ec786 | 815 | |
816 | /* Use the register life information in CHAIN to compute which | |
a570a59f | 817 | regs are live during the call. */ |
818 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
f62c22a7 | 819 | &chain->live_throughout); |
dd5b4b36 | 820 | /* Save hard registers always in the widest mode available. */ |
301652e2 | 821 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
822 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
823 | save_mode [regno] = regno_save_mode [regno][1]; | |
824 | else | |
825 | save_mode [regno] = VOIDmode; | |
826 | ||
35a3065a | 827 | /* Look through all live pseudos, mark their hard registers |
301652e2 | 828 | and choose proper mode for saving. */ |
829 | EXECUTE_IF_SET_IN_REG_SET | |
8c97cf13 | 830 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) |
831 | { | |
832 | int r = reg_renumber[regno]; | |
833 | int nregs; | |
3754d046 | 834 | machine_mode mode; |
8c97cf13 | 835 | |
c8010b80 | 836 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
47dd2e78 | 837 | continue; |
92d2aec3 | 838 | nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno)); |
8c97cf13 | 839 | mode = HARD_REGNO_CALLER_SAVE_MODE |
840 | (r, nregs, PSEUDO_REGNO_MODE (regno)); | |
974534ab | 841 | if (partial_subreg_p (save_mode[r], mode)) |
8c97cf13 | 842 | save_mode[r] = mode; |
843 | while (nregs-- > 0) | |
844 | SET_HARD_REG_BIT (hard_regs_to_save, r + nregs); | |
845 | } | |
590ec786 | 846 | |
847 | /* Record all registers set in this call insn. These don't need | |
a570a59f | 848 | to be saved. N.B. the call insn might set a subreg of a |
849 | multi-hard-reg pseudo; then the pseudo is considered live | |
850 | during the call, but the subreg that is set isn't. */ | |
590ec786 | 851 | CLEAR_HARD_REG_SET (this_insn_sets); |
d7e1f248 | 852 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); |
590ec786 | 853 | |
854 | /* Compute which hard regs must be saved before this call. */ | |
855 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, call_fixed_reg_set); | |
856 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, this_insn_sets); | |
857 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved); | |
754158d9 | 858 | get_call_reg_set_usage (insn, &call_def_reg_set, |
859 | call_used_reg_set); | |
860 | AND_HARD_REG_SET (hard_regs_to_save, call_def_reg_set); | |
590ec786 | 861 | |
590ec786 | 862 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
863 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
10640189 | 864 | regno += insert_save (chain, regno, |
865 | &hard_regs_to_save, save_mode); | |
590ec786 | 866 | |
867 | /* Must recompute n_regs_saved. */ | |
868 | n_regs_saved = 0; | |
869 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
870 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
871 | n_regs_saved++; | |
c8010b80 | 872 | |
873 | if (cheap | |
874 | && HARD_REGISTER_P (cheap) | |
875 | && TEST_HARD_REG_BIT (call_used_reg_set, REGNO (cheap))) | |
876 | { | |
d73df292 | 877 | rtx dest, newpat; |
878 | rtx pat = PATTERN (insn); | |
879 | if (GET_CODE (pat) == PARALLEL) | |
880 | pat = XVECEXP (pat, 0, 0); | |
881 | dest = SET_DEST (pat); | |
e88cf7af | 882 | /* For multiple return values dest is PARALLEL. |
883 | Currently we handle only single return value case. */ | |
884 | if (REG_P (dest)) | |
885 | { | |
d1f9b275 | 886 | newpat = gen_rtx_SET (cheap, copy_rtx (dest)); |
e88cf7af | 887 | chain = insert_one_insn (chain, 0, -1, newpat); |
888 | } | |
c8010b80 | 889 | } |
590ec786 | 890 | } |
4812f6d0 | 891 | last = chain; |
590ec786 | 892 | } |
9845d120 | 893 | else if (DEBUG_INSN_P (insn) && n_regs_saved) |
894 | mark_referenced_regs (&PATTERN (insn), | |
895 | replace_reg_with_saved_mem, | |
896 | save_mode); | |
3b9d3628 | 897 | |
47dd2e78 | 898 | if (chain->next == 0 || chain->next->block != chain->block) |
590ec786 | 899 | { |
900 | int regno; | |
901 | /* At the end of the basic block, we must restore any registers that | |
902 | remain saved. If the last insn in the block is a JUMP_INSN, put | |
903 | the restore before the insn, otherwise, put it after the insn. */ | |
904 | ||
fab1066d | 905 | if (n_regs_saved |
906 | && DEBUG_INSN_P (insn) | |
907 | && last | |
908 | && last->block == chain->block) | |
4812f6d0 | 909 | { |
f4bcab45 | 910 | rtx_insn *ins, *prev; |
4812f6d0 | 911 | basic_block bb = BLOCK_FOR_INSN (insn); |
912 | ||
913 | /* When adding hard reg restores after a DEBUG_INSN, move | |
914 | all notes between last real insn and this DEBUG_INSN after | |
915 | the DEBUG_INSN, otherwise we could get code | |
916 | -g/-g0 differences. */ | |
917 | for (ins = PREV_INSN (insn); ins != last->insn; ins = prev) | |
918 | { | |
919 | prev = PREV_INSN (ins); | |
920 | if (NOTE_P (ins)) | |
921 | { | |
4a57a2e8 | 922 | SET_NEXT_INSN (prev) = NEXT_INSN (ins); |
923 | SET_PREV_INSN (NEXT_INSN (ins)) = prev; | |
924 | SET_PREV_INSN (ins) = insn; | |
925 | SET_NEXT_INSN (ins) = NEXT_INSN (insn); | |
926 | SET_NEXT_INSN (insn) = ins; | |
4812f6d0 | 927 | if (NEXT_INSN (ins)) |
4a57a2e8 | 928 | SET_PREV_INSN (NEXT_INSN (ins)) = ins; |
4812f6d0 | 929 | if (BB_END (bb) == insn) |
26bb3cb2 | 930 | BB_END (bb) = ins; |
4812f6d0 | 931 | } |
932 | else | |
933 | gcc_assert (DEBUG_INSN_P (ins)); | |
934 | } | |
935 | } | |
936 | last = NULL; | |
937 | ||
590ec786 | 938 | if (n_regs_saved) |
939 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
940 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
6d7dc5b9 | 941 | regno += insert_restore (chain, JUMP_P (insn), |
301652e2 | 942 | regno, MOVE_MAX_WORDS, save_mode); |
590ec786 | 943 | } |
4c9e08a4 | 944 | } |
3b9d3628 | 945 | } |
946 | ||
d7e1f248 | 947 | /* Here from note_stores, or directly from save_call_clobbered_regs, when |
948 | an insn stores a value in a register. | |
590ec786 | 949 | Set the proper bit or bits in this_insn_sets. All pseudos that have |
3b9d3628 | 950 | been assigned hard regs have had their register number changed already, |
951 | so we can ignore pseudos. */ | |
3b9d3628 | 952 | static void |
81a410b1 | 953 | mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data) |
3b9d3628 | 954 | { |
19cb6b50 | 955 | int regno, endregno, i; |
364c0c59 | 956 | HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data; |
3b9d3628 | 957 | |
958 | if (GET_CODE (reg) == SUBREG) | |
959 | { | |
701e46d0 | 960 | rtx inner = SUBREG_REG (reg); |
8ad4c111 | 961 | if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER) |
701e46d0 | 962 | return; |
e9de4a6b | 963 | regno = subreg_regno (reg); |
fe2ebfc8 | 964 | endregno = regno + subreg_nregs (reg); |
701e46d0 | 965 | } |
8ad4c111 | 966 | else if (REG_P (reg) |
701e46d0 | 967 | && REGNO (reg) < FIRST_PSEUDO_REGISTER) |
fe2ebfc8 | 968 | { |
969 | regno = REGNO (reg); | |
788bed51 | 970 | endregno = END_REGNO (reg); |
fe2ebfc8 | 971 | } |
701e46d0 | 972 | else |
3b9d3628 | 973 | return; |
974 | ||
3b9d3628 | 975 | for (i = regno; i < endregno; i++) |
d7e1f248 | 976 | SET_HARD_REG_BIT (*this_insn_sets, i); |
3b9d3628 | 977 | } |
978 | ||
a570a59f | 979 | /* Here from note_stores when an insn stores a value in a register. |
980 | Set the proper bit or bits in the passed regset. All pseudos that have | |
981 | been assigned hard regs have had their register number changed already, | |
982 | so we can ignore pseudos. */ | |
983 | static void | |
81a410b1 | 984 | add_stored_regs (rtx reg, const_rtx setter, void *data) |
a570a59f | 985 | { |
19cb6b50 | 986 | int regno, endregno, i; |
3754d046 | 987 | machine_mode mode = GET_MODE (reg); |
701e46d0 | 988 | int offset = 0; |
a570a59f | 989 | |
990 | if (GET_CODE (setter) == CLOBBER) | |
991 | return; | |
992 | ||
8ef3d190 | 993 | if (GET_CODE (reg) == SUBREG |
994 | && REG_P (SUBREG_REG (reg)) | |
995 | && REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER) | |
a570a59f | 996 | { |
701e46d0 | 997 | offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)), |
998 | GET_MODE (SUBREG_REG (reg)), | |
999 | SUBREG_BYTE (reg), | |
1000 | GET_MODE (reg)); | |
8ef3d190 | 1001 | regno = REGNO (SUBREG_REG (reg)) + offset; |
fe2ebfc8 | 1002 | endregno = regno + subreg_nregs (reg); |
a570a59f | 1003 | } |
fe2ebfc8 | 1004 | else |
1005 | { | |
1006 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
1007 | return; | |
a570a59f | 1008 | |
fe2ebfc8 | 1009 | regno = REGNO (reg) + offset; |
a2c6f0b7 | 1010 | endregno = end_hard_regno (mode, regno); |
fe2ebfc8 | 1011 | } |
a570a59f | 1012 | |
1013 | for (i = regno; i < endregno; i++) | |
1014 | SET_REGNO_REG_SET ((regset) data, i); | |
1015 | } | |
1016 | ||
590ec786 | 1017 | /* Walk X and record all referenced registers in REFERENCED_REGS. */ |
3b9d3628 | 1018 | static void |
9845d120 | 1019 | mark_referenced_regs (rtx *loc, refmarker_fn *mark, void *arg) |
3b9d3628 | 1020 | { |
9845d120 | 1021 | enum rtx_code code = GET_CODE (*loc); |
d2ca078f | 1022 | const char *fmt; |
3b9d3628 | 1023 | int i, j; |
1024 | ||
590ec786 | 1025 | if (code == SET) |
9845d120 | 1026 | mark_referenced_regs (&SET_SRC (*loc), mark, arg); |
590ec786 | 1027 | if (code == SET || code == CLOBBER) |
1028 | { | |
9845d120 | 1029 | loc = &SET_DEST (*loc); |
1030 | code = GET_CODE (*loc); | |
1031 | if ((code == REG && REGNO (*loc) < FIRST_PSEUDO_REGISTER) | |
074d3abf | 1032 | || code == PC || code == CC0 |
9845d120 | 1033 | || (code == SUBREG && REG_P (SUBREG_REG (*loc)) |
1034 | && REGNO (SUBREG_REG (*loc)) < FIRST_PSEUDO_REGISTER | |
9d19a10d | 1035 | /* If we're setting only part of a multi-word register, |
1036 | we shall mark it as referenced, because the words | |
1037 | that are not being set should be restored. */ | |
9f2c0e68 | 1038 | && !read_modify_subreg_p (*loc))) |
590ec786 | 1039 | return; |
1040 | } | |
1041 | if (code == MEM || code == SUBREG) | |
1042 | { | |
9845d120 | 1043 | loc = &XEXP (*loc, 0); |
1044 | code = GET_CODE (*loc); | |
590ec786 | 1045 | } |
379d2d5f | 1046 | |
3b9d3628 | 1047 | if (code == REG) |
1048 | { | |
9845d120 | 1049 | int regno = REGNO (*loc); |
590ec786 | 1050 | int hardregno = (regno < FIRST_PSEUDO_REGISTER ? regno |
1051 | : reg_renumber[regno]); | |
3b9d3628 | 1052 | |
590ec786 | 1053 | if (hardregno >= 0) |
9845d120 | 1054 | mark (loc, GET_MODE (*loc), hardregno, arg); |
1055 | else if (arg) | |
1056 | /* ??? Will we ever end up with an equiv expression in a debug | |
1057 | insn, that would have required restoring a reg, or will | |
1058 | reload take care of it for us? */ | |
1059 | return; | |
590ec786 | 1060 | /* If this is a pseudo that did not get a hard register, scan its |
1061 | memory location, since it might involve the use of another | |
1062 | register, which might be saved. */ | |
1c654ff1 | 1063 | else if (reg_equiv_mem (regno) != 0) |
1064 | mark_referenced_regs (&XEXP (reg_equiv_mem (regno), 0), mark, arg); | |
1065 | else if (reg_equiv_address (regno) != 0) | |
1066 | mark_referenced_regs (®_equiv_address (regno), mark, arg); | |
3b9d3628 | 1067 | return; |
1068 | } | |
590ec786 | 1069 | |
3b9d3628 | 1070 | fmt = GET_RTX_FORMAT (code); |
1071 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1072 | { | |
1073 | if (fmt[i] == 'e') | |
9845d120 | 1074 | mark_referenced_regs (&XEXP (*loc, i), mark, arg); |
3b9d3628 | 1075 | else if (fmt[i] == 'E') |
9845d120 | 1076 | for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) |
1077 | mark_referenced_regs (&XVECEXP (*loc, i, j), mark, arg); | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | /* Parameter function for mark_referenced_regs() that adds registers | |
1082 | present in the insn and in equivalent mems and addresses to | |
1083 | referenced_regs. */ | |
1084 | ||
1085 | static void | |
1086 | mark_reg_as_referenced (rtx *loc ATTRIBUTE_UNUSED, | |
3754d046 | 1087 | machine_mode mode, |
9845d120 | 1088 | int hardregno, |
1089 | void *arg ATTRIBUTE_UNUSED) | |
1090 | { | |
1091 | add_to_hard_reg_set (&referenced_regs, mode, hardregno); | |
1092 | } | |
1093 | ||
1094 | /* Parameter function for mark_referenced_regs() that replaces | |
1095 | registers referenced in a debug_insn that would have been restored, | |
1096 | should it be a non-debug_insn, with their save locations. */ | |
1097 | ||
1098 | static void | |
1099 | replace_reg_with_saved_mem (rtx *loc, | |
3754d046 | 1100 | machine_mode mode, |
9845d120 | 1101 | int regno, |
1102 | void *arg) | |
1103 | { | |
92d2aec3 | 1104 | unsigned int i, nregs = hard_regno_nregs (regno, mode); |
9845d120 | 1105 | rtx mem; |
3754d046 | 1106 | machine_mode *save_mode = (machine_mode *)arg; |
9845d120 | 1107 | |
1108 | for (i = 0; i < nregs; i++) | |
1109 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1110 | break; | |
1111 | ||
1112 | /* If none of the registers in the range would need restoring, we're | |
1113 | all set. */ | |
1114 | if (i == nregs) | |
1115 | return; | |
1116 | ||
1117 | while (++i < nregs) | |
1118 | if (!TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1119 | break; | |
1120 | ||
1121 | if (i == nregs | |
1122 | && regno_save_mem[regno][nregs]) | |
1123 | { | |
1124 | mem = copy_rtx (regno_save_mem[regno][nregs]); | |
1125 | ||
92d2aec3 | 1126 | if (nregs == hard_regno_nregs (regno, save_mode[regno])) |
9845d120 | 1127 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
1128 | ||
1129 | if (GET_MODE (mem) != mode) | |
1130 | { | |
1131 | /* This is gen_lowpart_if_possible(), but without validating | |
1132 | the newly-formed address. */ | |
9edf7ea8 | 1133 | poly_int64 offset = byte_lowpart_offset (mode, GET_MODE (mem)); |
9845d120 | 1134 | mem = adjust_address_nv (mem, mode, offset); |
1135 | } | |
3b9d3628 | 1136 | } |
9845d120 | 1137 | else |
1138 | { | |
1139 | mem = gen_rtx_CONCATN (mode, rtvec_alloc (nregs)); | |
1140 | for (i = 0; i < nregs; i++) | |
1141 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1142 | { | |
1143 | gcc_assert (regno_save_mem[regno + i][1]); | |
1144 | XVECEXP (mem, 0, i) = copy_rtx (regno_save_mem[regno + i][1]); | |
1145 | } | |
1146 | else | |
1147 | { | |
3754d046 | 1148 | machine_mode smode = save_mode[regno]; |
e9ba91ab | 1149 | gcc_assert (smode != VOIDmode); |
92d2aec3 | 1150 | if (hard_regno_nregs (regno, smode) > 1) |
c6d32064 | 1151 | smode = mode_for_size (exact_div (GET_MODE_BITSIZE (mode), |
1152 | nregs), | |
ef379746 | 1153 | GET_MODE_CLASS (mode), 0).require (); |
e9ba91ab | 1154 | XVECEXP (mem, 0, i) = gen_rtx_REG (smode, regno + i); |
9845d120 | 1155 | } |
1156 | } | |
1157 | ||
1158 | gcc_assert (GET_MODE (mem) == mode); | |
1159 | *loc = mem; | |
3b9d3628 | 1160 | } |
9845d120 | 1161 | |
3b9d3628 | 1162 | \f |
590ec786 | 1163 | /* Insert a sequence of insns to restore. Place these insns in front of |
1164 | CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is | |
1165 | the maximum number of registers which should be restored during this call. | |
1166 | It should never be less than 1 since we only work with entire registers. | |
3b9d3628 | 1167 | |
1168 | Note that we have verified in init_caller_save that we can do this | |
1169 | with a simple SET, so use it. Set INSN_CODE to what we save there | |
1170 | since the address might not be valid so the insn might not be recognized. | |
1171 | These insns will be reloaded and have register elimination done by | |
379d2d5f | 1172 | find_reload, so we need not worry about that here. |
3b9d3628 | 1173 | |
379d2d5f | 1174 | Return the extra number of registers saved. */ |
1175 | ||
1176 | static int | |
2e966e2a | 1177 | insert_restore (class insn_chain *chain, int before_p, int regno, |
3754d046 | 1178 | int maxrestore, machine_mode *save_mode) |
3b9d3628 | 1179 | { |
a570a59f | 1180 | int i, k; |
2041cfd9 | 1181 | rtx pat = NULL_RTX; |
05d0dcea | 1182 | int code; |
301652e2 | 1183 | unsigned int numregs = 0; |
2e966e2a | 1184 | class insn_chain *new_chain; |
301652e2 | 1185 | rtx mem; |
3b9d3628 | 1186 | |
a53ff4c1 | 1187 | /* A common failure mode if register status is not correct in the |
1188 | RTL is for this routine to be called with a REGNO we didn't | |
1189 | expect to save. That will cause us to write an insn with a (nil) | |
1190 | SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
1191 | later, check for this common case here instead. This will remove | |
1192 | one step in debugging such problems. */ | |
231bd014 | 1193 | gcc_assert (regno_save_mem[regno][1]); |
0217d33f | 1194 | |
590ec786 | 1195 | /* Get the pattern to emit and update our status. |
ba84d47b | 1196 | |
590ec786 | 1197 | See if we can restore `maxrestore' registers at once. Work |
ba84d47b | 1198 | backwards to the single register case. */ |
1199 | for (i = maxrestore; i > 0; i--) | |
3b9d3628 | 1200 | { |
a570a59f | 1201 | int j; |
590ec786 | 1202 | int ok = 1; |
1203 | ||
1204 | if (regno_save_mem[regno][i] == 0) | |
ba84d47b | 1205 | continue; |
1206 | ||
590ec786 | 1207 | for (j = 0; j < i; j++) |
1208 | if (! TEST_HARD_REG_BIT (hard_regs_saved, regno + j)) | |
1209 | { | |
1210 | ok = 0; | |
1211 | break; | |
1212 | } | |
2358393e | 1213 | /* Must do this one restore at a time. */ |
ba84d47b | 1214 | if (! ok) |
1215 | continue; | |
590ec786 | 1216 | |
ba84d47b | 1217 | numregs = i; |
1218 | break; | |
1219 | } | |
379d2d5f | 1220 | |
301652e2 | 1221 | mem = regno_save_mem [regno][numregs]; |
1222 | if (save_mode [regno] != VOIDmode | |
1223 | && save_mode [regno] != GET_MODE (mem) | |
92d2aec3 | 1224 | && numregs == hard_regno_nregs (regno, save_mode [regno]) |
be707eff | 1225 | /* Check that insn to restore REGNO in save_mode[regno] is |
1226 | correct. */ | |
1227 | && reg_save_code (regno, save_mode[regno]) >= 0) | |
1fa19877 | 1228 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
6f5b55f8 | 1229 | else |
1230 | mem = copy_rtx (mem); | |
ad33891d | 1231 | |
1232 | /* Verify that the alignment of spill space is equal to or greater | |
1233 | than required. */ | |
47dd2e78 | 1234 | gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, |
1235 | GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
ad33891d | 1236 | |
d1f9b275 | 1237 | pat = gen_rtx_SET (gen_rtx_REG (GET_MODE (mem), regno), mem); |
d7be1dc6 | 1238 | code = reg_restore_code (regno, GET_MODE (mem)); |
d328ebdf | 1239 | new_chain = insert_one_insn (chain, before_p, code, pat); |
a570a59f | 1240 | |
1241 | /* Clear status for all registers we restored. */ | |
1242 | for (k = 0; k < i; k++) | |
1243 | { | |
1244 | CLEAR_HARD_REG_BIT (hard_regs_saved, regno + k); | |
d328ebdf | 1245 | SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); |
a570a59f | 1246 | n_regs_saved--; |
1247 | } | |
1248 | ||
8b332087 | 1249 | /* Tell our callers how many extra registers we saved/restored. */ |
ba84d47b | 1250 | return numregs - 1; |
1251 | } | |
379d2d5f | 1252 | |
590ec786 | 1253 | /* Like insert_restore above, but save registers instead. */ |
80fabb90 | 1254 | |
ba84d47b | 1255 | static int |
2e966e2a | 1256 | insert_save (class insn_chain *chain, int regno, |
a29167d3 | 1257 | HARD_REG_SET *to_save, machine_mode *save_mode) |
ba84d47b | 1258 | { |
301652e2 | 1259 | int i; |
1260 | unsigned int k; | |
ba84d47b | 1261 | rtx pat = NULL_RTX; |
05d0dcea | 1262 | int code; |
301652e2 | 1263 | unsigned int numregs = 0; |
2e966e2a | 1264 | class insn_chain *new_chain; |
301652e2 | 1265 | rtx mem; |
379d2d5f | 1266 | |
a53ff4c1 | 1267 | /* A common failure mode if register status is not correct in the |
1268 | RTL is for this routine to be called with a REGNO we didn't | |
1269 | expect to save. That will cause us to write an insn with a (nil) | |
1270 | SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
1271 | later, check for this common case here. This will remove one | |
ba84d47b | 1272 | step in debugging such problems. */ |
231bd014 | 1273 | gcc_assert (regno_save_mem[regno][1]); |
3b9d3628 | 1274 | |
590ec786 | 1275 | /* Get the pattern to emit and update our status. |
379d2d5f | 1276 | |
4c9e08a4 | 1277 | See if we can save several registers with a single instruction. |
ba84d47b | 1278 | Work backwards to the single register case. */ |
590ec786 | 1279 | for (i = MOVE_MAX_WORDS; i > 0; i--) |
ba84d47b | 1280 | { |
a570a59f | 1281 | int j; |
590ec786 | 1282 | int ok = 1; |
1283 | if (regno_save_mem[regno][i] == 0) | |
ba84d47b | 1284 | continue; |
379d2d5f | 1285 | |
590ec786 | 1286 | for (j = 0; j < i; j++) |
1287 | if (! TEST_HARD_REG_BIT (*to_save, regno + j)) | |
1288 | { | |
1289 | ok = 0; | |
1290 | break; | |
1291 | } | |
2358393e | 1292 | /* Must do this one save at a time. */ |
ba84d47b | 1293 | if (! ok) |
1294 | continue; | |
1295 | ||
ba84d47b | 1296 | numregs = i; |
1297 | break; | |
379d2d5f | 1298 | } |
3b9d3628 | 1299 | |
301652e2 | 1300 | mem = regno_save_mem [regno][numregs]; |
1301 | if (save_mode [regno] != VOIDmode | |
1302 | && save_mode [regno] != GET_MODE (mem) | |
92d2aec3 | 1303 | && numregs == hard_regno_nregs (regno, save_mode [regno]) |
be707eff | 1304 | /* Check that insn to save REGNO in save_mode[regno] is |
1305 | correct. */ | |
1306 | && reg_save_code (regno, save_mode[regno]) >= 0) | |
1fa19877 | 1307 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
6f5b55f8 | 1308 | else |
1309 | mem = copy_rtx (mem); | |
ad33891d | 1310 | |
1311 | /* Verify that the alignment of spill space is equal to or greater | |
1312 | than required. */ | |
47dd2e78 | 1313 | gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, |
1314 | GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
ad33891d | 1315 | |
d1f9b275 | 1316 | pat = gen_rtx_SET (mem, gen_rtx_REG (GET_MODE (mem), regno)); |
d7be1dc6 | 1317 | code = reg_save_code (regno, GET_MODE (mem)); |
10640189 | 1318 | new_chain = insert_one_insn (chain, 1, code, pat); |
a570a59f | 1319 | |
1320 | /* Set hard_regs_saved and dead_or_set for all the registers we saved. */ | |
1321 | for (k = 0; k < numregs; k++) | |
1322 | { | |
1323 | SET_HARD_REG_BIT (hard_regs_saved, regno + k); | |
d328ebdf | 1324 | SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); |
a570a59f | 1325 | n_regs_saved++; |
1326 | } | |
379d2d5f | 1327 | |
8b332087 | 1328 | /* Tell our callers how many extra registers we saved/restored. */ |
379d2d5f | 1329 | return numregs - 1; |
3b9d3628 | 1330 | } |
ba84d47b | 1331 | |
f5b7c8a5 | 1332 | /* A note_uses callback used by insert_one_insn. Add the hard-register |
1333 | equivalent of each REG to regset DATA. */ | |
1334 | ||
1335 | static void | |
1336 | add_used_regs (rtx *loc, void *data) | |
1337 | { | |
0e74eb28 | 1338 | subrtx_iterator::array_type array; |
1339 | FOR_EACH_SUBRTX (iter, array, *loc, NONCONST) | |
1340 | { | |
1341 | const_rtx x = *iter; | |
1342 | if (REG_P (x)) | |
1343 | { | |
1344 | unsigned int regno = REGNO (x); | |
1345 | if (HARD_REGISTER_NUM_P (regno)) | |
10fa8f76 | 1346 | bitmap_set_range ((regset) data, regno, REG_NREGS (x)); |
0e74eb28 | 1347 | else |
1348 | gcc_checking_assert (reg_renumber[regno] < 0); | |
1349 | } | |
1350 | } | |
f5b7c8a5 | 1351 | } |
1352 | ||
590ec786 | 1353 | /* Emit a new caller-save insn and set the code. */ |
2e966e2a | 1354 | static class insn_chain * |
1355 | insert_one_insn (class insn_chain *chain, int before_p, int code, rtx pat) | |
ba84d47b | 1356 | { |
7e48bf22 | 1357 | rtx_insn *insn = chain->insn; |
2e966e2a | 1358 | class insn_chain *new_chain; |
4c9e08a4 | 1359 | |
ba84d47b | 1360 | /* If INSN references CC0, put our insns in front of the insn that sets |
1361 | CC0. This is always safe, since the only way we could be passed an | |
1362 | insn that references CC0 is for a restore, and doing a restore earlier | |
1363 | isn't a problem. We do, however, assume here that CALL_INSNs don't | |
1364 | reference CC0. Guard against non-INSN's like CODE_LABEL. */ | |
1365 | ||
693c9f42 | 1366 | if (HAVE_cc0 && (NONJUMP_INSN_P (insn) || JUMP_P (insn)) |
ba84d47b | 1367 | && before_p |
1368 | && reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
590ec786 | 1369 | chain = chain->prev, insn = chain->insn; |
ba84d47b | 1370 | |
d328ebdf | 1371 | new_chain = new_insn_chain (); |
ba84d47b | 1372 | if (before_p) |
1373 | { | |
a570a59f | 1374 | rtx link; |
1375 | ||
d328ebdf | 1376 | new_chain->prev = chain->prev; |
1377 | if (new_chain->prev != 0) | |
1378 | new_chain->prev->next = new_chain; | |
590ec786 | 1379 | else |
d328ebdf | 1380 | reload_insn_chain = new_chain; |
590ec786 | 1381 | |
d328ebdf | 1382 | chain->prev = new_chain; |
1383 | new_chain->next = chain; | |
1384 | new_chain->insn = emit_insn_before (pat, insn); | |
188b3398 | 1385 | /* ??? It would be nice if we could exclude the already / still saved |
1386 | registers from the live sets. */ | |
d328ebdf | 1387 | COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); |
f5b7c8a5 | 1388 | note_uses (&PATTERN (chain->insn), add_used_regs, |
1389 | &new_chain->live_throughout); | |
87bd12fc | 1390 | /* If CHAIN->INSN is a call, then the registers which contain |
1391 | the arguments to the function are live in the new insn. */ | |
1392 | if (CALL_P (chain->insn)) | |
f5b7c8a5 | 1393 | for (link = CALL_INSN_FUNCTION_USAGE (chain->insn); |
1394 | link != NULL_RTX; | |
1395 | link = XEXP (link, 1)) | |
1396 | note_uses (&XEXP (link, 0), add_used_regs, | |
1397 | &new_chain->live_throughout); | |
87bd12fc | 1398 | |
d328ebdf | 1399 | CLEAR_REG_SET (&new_chain->dead_or_set); |
f5a6b05f | 1400 | if (chain->insn == BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block))) |
26bb3cb2 | 1401 | BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; |
ba84d47b | 1402 | } |
1403 | else | |
1404 | { | |
d328ebdf | 1405 | new_chain->next = chain->next; |
1406 | if (new_chain->next != 0) | |
1407 | new_chain->next->prev = new_chain; | |
1408 | chain->next = new_chain; | |
1409 | new_chain->prev = chain; | |
1410 | new_chain->insn = emit_insn_after (pat, insn); | |
188b3398 | 1411 | /* ??? It would be nice if we could exclude the already / still saved |
1412 | registers from the live sets, and observe REG_UNUSED notes. */ | |
d328ebdf | 1413 | COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); |
a570a59f | 1414 | /* Registers that are set in CHAIN->INSN live in the new insn. |
a0c938f0 | 1415 | (Unless there is a REG_UNUSED note for them, but we don't |
a570a59f | 1416 | look for them here.) */ |
1417 | note_stores (PATTERN (chain->insn), add_stored_regs, | |
d328ebdf | 1418 | &new_chain->live_throughout); |
1419 | CLEAR_REG_SET (&new_chain->dead_or_set); | |
f5a6b05f | 1420 | if (chain->insn == BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block))) |
26bb3cb2 | 1421 | BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; |
ba84d47b | 1422 | } |
d328ebdf | 1423 | new_chain->block = chain->block; |
1424 | new_chain->is_caller_save_insn = 1; | |
e546118a | 1425 | |
d328ebdf | 1426 | INSN_CODE (new_chain->insn) = code; |
1427 | return new_chain; | |
ba84d47b | 1428 | } |
d7be1dc6 | 1429 | #include "gt-caller-save.h" |