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c5986054 | 1 | /* Save and restore call-clobbered registers which are live across a call. |
cbe34bb5 | 2 | Copyright (C) 1989-2017 Free Software Foundation, Inc. |
c5986054 | 3 | |
1322177d | 4 | This file is part of GCC. |
c5986054 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
c5986054 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
c5986054 RS |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
c5986054 RS |
19 | |
20 | #include "config.h" | |
670ee920 | 21 | #include "system.h" |
4977bab6 | 22 | #include "coretypes.h" |
c7131fb2 | 23 | #include "backend.h" |
c5986054 | 24 | #include "rtl.h" |
957060b5 AM |
25 | #include "tree.h" |
26 | #include "predict.h" | |
c7131fb2 | 27 | #include "df.h" |
4d0cdd0c | 28 | #include "memmodel.h" |
957060b5 | 29 | #include "tm_p.h" |
c5986054 | 30 | #include "insn-config.h" |
957060b5 AM |
31 | #include "regs.h" |
32 | #include "emit-rtl.h" | |
c5986054 | 33 | #include "recog.h" |
60393bbc | 34 | #include "reload.h" |
36566b39 | 35 | #include "alias.h" |
f6c4ed08 | 36 | #include "addresses.h" |
7ee2468b | 37 | #include "dumpfile.h" |
1cb22a67 | 38 | #include "rtl-iter.h" |
f939c3e6 | 39 | #include "target.h" |
c5986054 | 40 | |
7609e720 BS |
41 | #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD) |
42 | ||
bcbaaba1 RS |
43 | #define regno_save_mode \ |
44 | (this_target_reload->x_regno_save_mode) | |
cc14227f RS |
45 | #define cached_reg_save_code \ |
46 | (this_target_reload->x_cached_reg_save_code) | |
47 | #define cached_reg_restore_code \ | |
48 | (this_target_reload->x_cached_reg_restore_code) | |
c5986054 RS |
49 | |
50 | /* For each hard register, a place on the stack where it can be saved, | |
51 | if needed. */ | |
52 | ||
d329e058 | 53 | static rtx |
ef0e53ce | 54 | regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]; |
c5986054 | 55 | |
058e97ec VM |
56 | /* The number of elements in the subsequent array. */ |
57 | static int save_slots_num; | |
58 | ||
59 | /* Allocated slots so far. */ | |
60 | static rtx save_slots[FIRST_PSEUDO_REGISTER]; | |
61 | ||
c5986054 RS |
62 | /* Set of hard regs currently residing in save area (during insn scan). */ |
63 | ||
64 | static HARD_REG_SET hard_regs_saved; | |
65 | ||
7609e720 | 66 | /* Number of registers currently in hard_regs_saved. */ |
f95361c8 | 67 | |
7609e720 | 68 | static int n_regs_saved; |
f95361c8 | 69 | |
7609e720 BS |
70 | /* Computed by mark_referenced_regs, all regs referenced in a given |
71 | insn. */ | |
72 | static HARD_REG_SET referenced_regs; | |
c5986054 | 73 | |
7609e720 | 74 | |
ef4bddc2 | 75 | typedef void refmarker_fn (rtx *loc, machine_mode mode, int hardregno, |
b5b8b0ac AO |
76 | void *mark_arg); |
77 | ||
ef4bddc2 RS |
78 | static int reg_save_code (int, machine_mode); |
79 | static int reg_restore_code (int, machine_mode); | |
058e97ec VM |
80 | |
81 | struct saved_hard_reg; | |
82 | static void initiate_saved_hard_regs (void); | |
e16b6fd0 | 83 | static void new_saved_hard_reg (int, int); |
058e97ec VM |
84 | static void finish_saved_hard_regs (void); |
85 | static int saved_hard_reg_compare_func (const void *, const void *); | |
86 | ||
7bc980e1 | 87 | static void mark_set_regs (rtx, const_rtx, void *); |
b5b8b0ac AO |
88 | static void mark_referenced_regs (rtx *, refmarker_fn *mark, void *mark_arg); |
89 | static refmarker_fn mark_reg_as_referenced; | |
90 | static refmarker_fn replace_reg_with_saved_mem; | |
d329e058 | 91 | static int insert_save (struct insn_chain *, int, int, HARD_REG_SET *, |
ef4bddc2 | 92 | machine_mode *); |
d329e058 | 93 | static int insert_restore (struct insn_chain *, int, int, int, |
ef4bddc2 | 94 | machine_mode *); |
d329e058 AJ |
95 | static struct insn_chain *insert_one_insn (struct insn_chain *, int, int, |
96 | rtx); | |
7bc980e1 | 97 | static void add_stored_regs (rtx, const_rtx, void *); |
058e97ec | 98 | |
c5986054 | 99 | \f |
058e97ec | 100 | |
78187f5a JH |
101 | static GTY(()) rtx savepat; |
102 | static GTY(()) rtx restpat; | |
103 | static GTY(()) rtx test_reg; | |
104 | static GTY(()) rtx test_mem; | |
647d790d DM |
105 | static GTY(()) rtx_insn *saveinsn; |
106 | static GTY(()) rtx_insn *restinsn; | |
78187f5a JH |
107 | |
108 | /* Return the INSN_CODE used to save register REG in mode MODE. */ | |
109 | static int | |
ef4bddc2 | 110 | reg_save_code (int reg, machine_mode mode) |
78187f5a JH |
111 | { |
112 | bool ok; | |
113 | if (cached_reg_save_code[reg][mode]) | |
114 | return cached_reg_save_code[reg][mode]; | |
f939c3e6 | 115 | if (!targetm.hard_regno_mode_ok (reg, mode)) |
f57e2756 | 116 | { |
f939c3e6 RS |
117 | /* Depending on how targetm.hard_regno_mode_ok is defined, range |
118 | propagation might deduce here that reg >= FIRST_PSEUDO_REGISTER. | |
119 | So the assert below silences a warning. */ | |
f57e2756 JR |
120 | gcc_assert (reg < FIRST_PSEUDO_REGISTER); |
121 | cached_reg_save_code[reg][mode] = -1; | |
122 | cached_reg_restore_code[reg][mode] = -1; | |
123 | return -1; | |
124 | } | |
78187f5a JH |
125 | |
126 | /* Update the register number and modes of the register | |
127 | and memory operand. */ | |
8deccbb7 | 128 | set_mode_and_regno (test_reg, mode, reg); |
78187f5a JH |
129 | PUT_MODE (test_mem, mode); |
130 | ||
131 | /* Force re-recognition of the modified insns. */ | |
132 | INSN_CODE (saveinsn) = -1; | |
f81e79b5 | 133 | INSN_CODE (restinsn) = -1; |
78187f5a JH |
134 | |
135 | cached_reg_save_code[reg][mode] = recog_memoized (saveinsn); | |
136 | cached_reg_restore_code[reg][mode] = recog_memoized (restinsn); | |
137 | ||
138 | /* Now extract both insns and see if we can meet their | |
daca1a96 RS |
139 | constraints. We don't know here whether the save and restore will |
140 | be in size- or speed-tuned code, so just use the set of enabled | |
141 | alternatives. */ | |
78187f5a JH |
142 | ok = (cached_reg_save_code[reg][mode] != -1 |
143 | && cached_reg_restore_code[reg][mode] != -1); | |
144 | if (ok) | |
145 | { | |
146 | extract_insn (saveinsn); | |
daca1a96 | 147 | ok = constrain_operands (1, get_enabled_alternatives (saveinsn)); |
78187f5a | 148 | extract_insn (restinsn); |
daca1a96 | 149 | ok &= constrain_operands (1, get_enabled_alternatives (restinsn)); |
78187f5a JH |
150 | } |
151 | ||
152 | if (! ok) | |
153 | { | |
154 | cached_reg_save_code[reg][mode] = -1; | |
155 | cached_reg_restore_code[reg][mode] = -1; | |
156 | } | |
157 | gcc_assert (cached_reg_save_code[reg][mode]); | |
158 | return cached_reg_save_code[reg][mode]; | |
159 | } | |
160 | ||
161 | /* Return the INSN_CODE used to restore register REG in mode MODE. */ | |
162 | static int | |
ef4bddc2 | 163 | reg_restore_code (int reg, machine_mode mode) |
78187f5a JH |
164 | { |
165 | if (cached_reg_restore_code[reg][mode]) | |
166 | return cached_reg_restore_code[reg][mode]; | |
167 | /* Populate our cache. */ | |
168 | reg_save_code (reg, mode); | |
169 | return cached_reg_restore_code[reg][mode]; | |
170 | } | |
171 | \f | |
c5986054 RS |
172 | /* Initialize for caller-save. |
173 | ||
174 | Look at all the hard registers that are used by a call and for which | |
328e13b7 | 175 | reginfo.c has not already excluded from being used across a call. |
c5986054 | 176 | |
d329e058 | 177 | Ensure that we can find a mode to save the register and that there is a |
c5986054 RS |
178 | simple insn to save and restore the register. This latter check avoids |
179 | problems that would occur if we tried to save the MQ register of some | |
180 | machines directly into memory. */ | |
181 | ||
182 | void | |
d329e058 | 183 | init_caller_save (void) |
c5986054 | 184 | { |
c5986054 RS |
185 | rtx addr_reg; |
186 | int offset; | |
187 | rtx address; | |
f95361c8 | 188 | int i, j; |
c5986054 | 189 | |
dc12b70e JZ |
190 | if (caller_save_initialized_p) |
191 | return; | |
192 | ||
193 | caller_save_initialized_p = true; | |
194 | ||
058e97ec | 195 | CLEAR_HARD_REG_SET (no_caller_save_reg_set); |
c5986054 RS |
196 | /* First find all the registers that we need to deal with and all |
197 | the modes that they can have. If we can't find a mode to use, | |
198 | we can't have the register live over calls. */ | |
199 | ||
200 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
201 | { | |
adee59ae AS |
202 | if (call_used_regs[i] |
203 | && !TEST_HARD_REG_BIT (call_fixed_reg_set, i)) | |
c5986054 | 204 | { |
7609e720 | 205 | for (j = 1; j <= MOVE_MAX_WORDS; j++) |
c5986054 | 206 | { |
787dc842 JH |
207 | regno_save_mode[i][j] = HARD_REGNO_CALLER_SAVE_MODE (i, j, |
208 | VOIDmode); | |
f95361c8 JL |
209 | if (regno_save_mode[i][j] == VOIDmode && j == 1) |
210 | { | |
f95361c8 JL |
211 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
212 | } | |
c5986054 RS |
213 | } |
214 | } | |
215 | else | |
f95361c8 | 216 | regno_save_mode[i][1] = VOIDmode; |
c5986054 RS |
217 | } |
218 | ||
219 | /* The following code tries to approximate the conditions under which | |
220 | we can easily save and restore a register without scratch registers or | |
221 | other complexities. It will usually work, except under conditions where | |
222 | the validity of an insn operand is dependent on the address offset. | |
223 | No such cases are currently known. | |
224 | ||
225 | We first find a typical offset from some BASE_REG_CLASS register. | |
226 | This address is chosen by finding the first register in the class | |
227 | and by finding the smallest power of two that is a valid offset from | |
228 | that register in every mode we will use to save registers. */ | |
229 | ||
230 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3dcc68a4 NC |
231 | if (TEST_HARD_REG_BIT |
232 | (reg_class_contents | |
86fc3d06 UW |
233 | [(int) base_reg_class (regno_save_mode[i][1], ADDR_SPACE_GENERIC, |
234 | PLUS, CONST_INT)], i)) | |
c5986054 RS |
235 | break; |
236 | ||
366de0ce | 237 | gcc_assert (i < FIRST_PSEUDO_REGISTER); |
c5986054 | 238 | |
38a448ca | 239 | addr_reg = gen_rtx_REG (Pmode, i); |
c5986054 RS |
240 | |
241 | for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1) | |
242 | { | |
4789c0ce | 243 | address = gen_rtx_PLUS (Pmode, addr_reg, gen_int_mode (offset, Pmode)); |
c5986054 RS |
244 | |
245 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
f95361c8 JL |
246 | if (regno_save_mode[i][1] != VOIDmode |
247 | && ! strict_memory_address_p (regno_save_mode[i][1], address)) | |
c5986054 RS |
248 | break; |
249 | ||
250 | if (i == FIRST_PSEUDO_REGISTER) | |
251 | break; | |
252 | } | |
253 | ||
254 | /* If we didn't find a valid address, we must use register indirect. */ | |
255 | if (offset == 0) | |
256 | address = addr_reg; | |
257 | ||
258 | /* Next we try to form an insn to save and restore the register. We | |
d329e058 | 259 | see if such an insn is recognized and meets its constraints. |
bf1660a6 JL |
260 | |
261 | To avoid lots of unnecessary RTL allocation, we construct all the RTL | |
262 | once, then modify the memory and register operands in-place. */ | |
263 | ||
c3dc5e66 | 264 | test_reg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); |
5d2446b1 | 265 | test_mem = gen_rtx_MEM (word_mode, address); |
f7df4a84 RS |
266 | savepat = gen_rtx_SET (test_mem, test_reg); |
267 | restpat = gen_rtx_SET (test_reg, test_mem); | |
c5986054 | 268 | |
ed8921dc RS |
269 | saveinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, savepat, 0, -1, 0); |
270 | restinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, restpat, 0, -1, 0); | |
0db79a6b | 271 | |
787dc842 JH |
272 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
273 | for (j = 1; j <= MOVE_MAX_WORDS; j++) | |
78187f5a | 274 | if (reg_save_code (i,regno_save_mode[i][j]) == -1) |
787dc842 JH |
275 | { |
276 | regno_save_mode[i][j] = VOIDmode; | |
277 | if (j == 1) | |
278 | { | |
787dc842 | 279 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
058e97ec VM |
280 | if (call_used_regs[i]) |
281 | SET_HARD_REG_BIT (no_caller_save_reg_set, i); | |
787dc842 JH |
282 | } |
283 | } | |
c5986054 | 284 | } |
058e97ec | 285 | |
c5986054 | 286 | \f |
058e97ec | 287 | |
c5986054 RS |
288 | /* Initialize save areas by showing that we haven't allocated any yet. */ |
289 | ||
290 | void | |
d329e058 | 291 | init_save_areas (void) |
c5986054 | 292 | { |
f95361c8 | 293 | int i, j; |
c5986054 RS |
294 | |
295 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7609e720 | 296 | for (j = 1; j <= MOVE_MAX_WORDS; j++) |
f95361c8 | 297 | regno_save_mem[i][j] = 0; |
058e97ec | 298 | save_slots_num = 0; |
b8698a0f | 299 | |
058e97ec VM |
300 | } |
301 | ||
302 | /* The structure represents a hard register which should be saved | |
303 | through the call. It is used when the integrated register | |
304 | allocator (IRA) is used and sharing save slots is on. */ | |
305 | struct saved_hard_reg | |
306 | { | |
307 | /* Order number starting with 0. */ | |
308 | int num; | |
309 | /* The hard regno. */ | |
310 | int hard_regno; | |
311 | /* Execution frequency of all calls through which given hard | |
312 | register should be saved. */ | |
313 | int call_freq; | |
314 | /* Stack slot reserved to save the hard register through calls. */ | |
315 | rtx slot; | |
316 | /* True if it is first hard register in the chain of hard registers | |
317 | sharing the same stack slot. */ | |
318 | int first_p; | |
319 | /* Order number of the next hard register structure with the same | |
320 | slot in the chain. -1 represents end of the chain. */ | |
321 | int next; | |
322 | }; | |
323 | ||
324 | /* Map: hard register number to the corresponding structure. */ | |
325 | static struct saved_hard_reg *hard_reg_map[FIRST_PSEUDO_REGISTER]; | |
326 | ||
327 | /* The number of all structures representing hard registers should be | |
328 | saved, in order words, the number of used elements in the following | |
329 | array. */ | |
330 | static int saved_regs_num; | |
331 | ||
332 | /* Pointers to all the structures. Index is the order number of the | |
333 | corresponding structure. */ | |
334 | static struct saved_hard_reg *all_saved_regs[FIRST_PSEUDO_REGISTER]; | |
335 | ||
336 | /* First called function for work with saved hard registers. */ | |
337 | static void | |
338 | initiate_saved_hard_regs (void) | |
339 | { | |
340 | int i; | |
341 | ||
342 | saved_regs_num = 0; | |
343 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
344 | hard_reg_map[i] = NULL; | |
345 | } | |
346 | ||
347 | /* Allocate and return new saved hard register with given REGNO and | |
348 | CALL_FREQ. */ | |
e16b6fd0 | 349 | static void |
058e97ec VM |
350 | new_saved_hard_reg (int regno, int call_freq) |
351 | { | |
352 | struct saved_hard_reg *saved_reg; | |
353 | ||
354 | saved_reg | |
355 | = (struct saved_hard_reg *) xmalloc (sizeof (struct saved_hard_reg)); | |
356 | hard_reg_map[regno] = all_saved_regs[saved_regs_num] = saved_reg; | |
357 | saved_reg->num = saved_regs_num++; | |
358 | saved_reg->hard_regno = regno; | |
359 | saved_reg->call_freq = call_freq; | |
360 | saved_reg->first_p = FALSE; | |
361 | saved_reg->next = -1; | |
058e97ec VM |
362 | } |
363 | ||
364 | /* Free memory allocated for the saved hard registers. */ | |
365 | static void | |
366 | finish_saved_hard_regs (void) | |
367 | { | |
368 | int i; | |
369 | ||
370 | for (i = 0; i < saved_regs_num; i++) | |
371 | free (all_saved_regs[i]); | |
372 | } | |
373 | ||
374 | /* The function is used to sort the saved hard register structures | |
375 | according their frequency. */ | |
376 | static int | |
377 | saved_hard_reg_compare_func (const void *v1p, const void *v2p) | |
378 | { | |
379 | const struct saved_hard_reg *p1 = *(struct saved_hard_reg * const *) v1p; | |
380 | const struct saved_hard_reg *p2 = *(struct saved_hard_reg * const *) v2p; | |
b8698a0f | 381 | |
058e97ec VM |
382 | if (flag_omit_frame_pointer) |
383 | { | |
384 | if (p1->call_freq - p2->call_freq != 0) | |
385 | return p1->call_freq - p2->call_freq; | |
386 | } | |
387 | else if (p2->call_freq - p1->call_freq != 0) | |
388 | return p2->call_freq - p1->call_freq; | |
389 | ||
390 | return p1->num - p2->num; | |
c5986054 RS |
391 | } |
392 | ||
393 | /* Allocate save areas for any hard registers that might need saving. | |
394 | We take a conservative approach here and look for call-clobbered hard | |
395 | registers that are assigned to pseudos that cross calls. This may | |
396 | overestimate slightly (especially if some of these registers are later | |
397 | used as spill registers), but it should not be significant. | |
398 | ||
058e97ec VM |
399 | For IRA we use priority coloring to decrease stack slots needed for |
400 | saving hard registers through calls. We build conflicts for them | |
401 | to do coloring. | |
402 | ||
f95361c8 JL |
403 | Future work: |
404 | ||
405 | In the fallback case we should iterate backwards across all possible | |
d329e058 | 406 | modes for the save, choosing the largest available one instead of |
f95361c8 JL |
407 | falling back to the smallest mode immediately. (eg TF -> DF -> SF). |
408 | ||
409 | We do not try to use "move multiple" instructions that exist | |
d329e058 | 410 | on some machines (such as the 68k moveml). It could be a win to try |
f95361c8 | 411 | and use them when possible. The hard part is doing it in a way that is |
d329e058 | 412 | machine independent since they might be saving non-consecutive |
f95361c8 | 413 | registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */ |
c5986054 | 414 | |
437a710d | 415 | void |
d329e058 | 416 | setup_save_areas (void) |
c5986054 | 417 | { |
e90b336f | 418 | int i, j, k, freq; |
f95361c8 | 419 | HARD_REG_SET hard_regs_used; |
e90b336f | 420 | struct saved_hard_reg *saved_reg; |
86bf2d46 | 421 | rtx_insn *insn; |
e90b336f JL |
422 | struct insn_chain *chain, *next; |
423 | unsigned int regno; | |
424 | HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets; | |
425 | reg_set_iterator rsi; | |
f95361c8 | 426 | |
f95361c8 | 427 | CLEAR_HARD_REG_SET (hard_regs_used); |
f95361c8 | 428 | |
e90b336f JL |
429 | /* Find every CALL_INSN and record which hard regs are live across the |
430 | call into HARD_REG_MAP and HARD_REGS_USED. */ | |
431 | initiate_saved_hard_regs (); | |
432 | /* Create hard reg saved regs. */ | |
433 | for (chain = reload_insn_chain; chain != 0; chain = next) | |
058e97ec | 434 | { |
e384e6b5 BS |
435 | rtx cheap; |
436 | ||
e90b336f JL |
437 | insn = chain->insn; |
438 | next = chain->next; | |
439 | if (!CALL_P (insn) | |
440 | || find_reg_note (insn, REG_NORETURN, NULL)) | |
441 | continue; | |
442 | freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)); | |
443 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
444 | &chain->live_throughout); | |
c2ba7e7a | 445 | get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); |
e90b336f JL |
446 | |
447 | /* Record all registers set in this call insn. These don't | |
448 | need to be saved. N.B. the call insn might set a subreg | |
449 | of a multi-hard-reg pseudo; then the pseudo is considered | |
450 | live during the call, but the subreg that is set | |
451 | isn't. */ | |
452 | CLEAR_HARD_REG_SET (this_insn_sets); | |
453 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
454 | /* Sibcalls are considered to set the return value. */ | |
455 | if (SIBLING_CALL_P (insn) && crtl->return_rtx) | |
456 | mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
457 | ||
458 | AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
459 | AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
460 | AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
461 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
462 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
463 | { | |
464 | if (hard_reg_map[regno] != NULL) | |
465 | hard_reg_map[regno]->call_freq += freq; | |
466 | else | |
e16b6fd0 | 467 | new_saved_hard_reg (regno, freq); |
e90b336f JL |
468 | SET_HARD_REG_BIT (hard_regs_used, regno); |
469 | } | |
e384e6b5 BS |
470 | cheap = find_reg_note (insn, REG_RETURNED, NULL); |
471 | if (cheap) | |
472 | cheap = XEXP (cheap, 0); | |
e90b336f JL |
473 | /* Look through all live pseudos, mark their hard registers. */ |
474 | EXECUTE_IF_SET_IN_REG_SET | |
475 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
058e97ec | 476 | { |
e90b336f JL |
477 | int r = reg_renumber[regno]; |
478 | int bound; | |
058e97ec | 479 | |
e384e6b5 | 480 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
e90b336f | 481 | continue; |
058e97ec | 482 | |
e90b336f JL |
483 | bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; |
484 | for (; r < bound; r++) | |
485 | if (TEST_HARD_REG_BIT (used_regs, r)) | |
058e97ec | 486 | { |
e90b336f JL |
487 | if (hard_reg_map[r] != NULL) |
488 | hard_reg_map[r]->call_freq += freq; | |
058e97ec | 489 | else |
e16b6fd0 | 490 | new_saved_hard_reg (r, freq); |
e90b336f JL |
491 | SET_HARD_REG_BIT (hard_regs_to_save, r); |
492 | SET_HARD_REG_BIT (hard_regs_used, r); | |
058e97ec | 493 | } |
e90b336f JL |
494 | } |
495 | } | |
b8698a0f | 496 | |
e90b336f JL |
497 | /* If requested, figure out which hard regs can share save slots. */ |
498 | if (optimize && flag_ira_share_save_slots) | |
499 | { | |
500 | rtx slot; | |
501 | char *saved_reg_conflicts; | |
502 | int next_k; | |
503 | struct saved_hard_reg *saved_reg2, *saved_reg3; | |
504 | int call_saved_regs_num; | |
505 | struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER]; | |
506 | int best_slot_num; | |
507 | int prev_save_slots_num; | |
508 | rtx prev_save_slots[FIRST_PSEUDO_REGISTER]; | |
b8698a0f | 509 | |
058e97ec VM |
510 | /* Find saved hard register conflicts. */ |
511 | saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num); | |
512 | memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num); | |
513 | for (chain = reload_insn_chain; chain != 0; chain = next) | |
514 | { | |
e384e6b5 | 515 | rtx cheap; |
058e97ec VM |
516 | call_saved_regs_num = 0; |
517 | insn = chain->insn; | |
518 | next = chain->next; | |
481683e1 | 519 | if (!CALL_P (insn) |
058e97ec VM |
520 | || find_reg_note (insn, REG_NORETURN, NULL)) |
521 | continue; | |
e384e6b5 BS |
522 | |
523 | cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
524 | if (cheap) | |
525 | cheap = XEXP (cheap, 0); | |
526 | ||
058e97ec VM |
527 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, |
528 | &chain->live_throughout); | |
c2ba7e7a | 529 | get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); |
058e97ec VM |
530 | |
531 | /* Record all registers set in this call insn. These don't | |
532 | need to be saved. N.B. the call insn might set a subreg | |
533 | of a multi-hard-reg pseudo; then the pseudo is considered | |
534 | live during the call, but the subreg that is set | |
535 | isn't. */ | |
536 | CLEAR_HARD_REG_SET (this_insn_sets); | |
537 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
538 | /* Sibcalls are considered to set the return value, | |
912eb5a4 | 539 | compare df-scan.c:df_get_call_refs. */ |
058e97ec VM |
540 | if (SIBLING_CALL_P (insn) && crtl->return_rtx) |
541 | mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
542 | ||
543 | AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
544 | AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
545 | AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
546 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
547 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
548 | { | |
549 | gcc_assert (hard_reg_map[regno] != NULL); | |
550 | call_saved_regs[call_saved_regs_num++] = hard_reg_map[regno]; | |
551 | } | |
552 | /* Look through all live pseudos, mark their hard registers. */ | |
553 | EXECUTE_IF_SET_IN_REG_SET | |
554 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
c5986054 | 555 | { |
058e97ec VM |
556 | int r = reg_renumber[regno]; |
557 | int bound; | |
b8698a0f | 558 | |
e384e6b5 | 559 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
058e97ec VM |
560 | continue; |
561 | ||
562 | bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; | |
563 | for (; r < bound; r++) | |
564 | if (TEST_HARD_REG_BIT (used_regs, r)) | |
565 | call_saved_regs[call_saved_regs_num++] = hard_reg_map[r]; | |
c5986054 | 566 | } |
058e97ec VM |
567 | for (i = 0; i < call_saved_regs_num; i++) |
568 | { | |
569 | saved_reg = call_saved_regs[i]; | |
570 | for (j = 0; j < call_saved_regs_num; j++) | |
571 | if (i != j) | |
572 | { | |
573 | saved_reg2 = call_saved_regs[j]; | |
574 | saved_reg_conflicts[saved_reg->num * saved_regs_num | |
575 | + saved_reg2->num] | |
576 | = saved_reg_conflicts[saved_reg2->num * saved_regs_num | |
577 | + saved_reg->num] | |
578 | = TRUE; | |
579 | } | |
580 | } | |
581 | } | |
582 | /* Sort saved hard regs. */ | |
583 | qsort (all_saved_regs, saved_regs_num, sizeof (struct saved_hard_reg *), | |
584 | saved_hard_reg_compare_func); | |
585 | /* Initiate slots available from the previous reload | |
586 | iteration. */ | |
587 | prev_save_slots_num = save_slots_num; | |
588 | memcpy (prev_save_slots, save_slots, save_slots_num * sizeof (rtx)); | |
589 | save_slots_num = 0; | |
590 | /* Allocate stack slots for the saved hard registers. */ | |
591 | for (i = 0; i < saved_regs_num; i++) | |
592 | { | |
593 | saved_reg = all_saved_regs[i]; | |
594 | regno = saved_reg->hard_regno; | |
595 | for (j = 0; j < i; j++) | |
596 | { | |
597 | saved_reg2 = all_saved_regs[j]; | |
598 | if (! saved_reg2->first_p) | |
599 | continue; | |
600 | slot = saved_reg2->slot; | |
601 | for (k = j; k >= 0; k = next_k) | |
602 | { | |
603 | saved_reg3 = all_saved_regs[k]; | |
604 | next_k = saved_reg3->next; | |
605 | if (saved_reg_conflicts[saved_reg->num * saved_regs_num | |
606 | + saved_reg3->num]) | |
607 | break; | |
608 | } | |
609 | if (k < 0 | |
610 | && (GET_MODE_SIZE (regno_save_mode[regno][1]) | |
611 | <= GET_MODE_SIZE (regno_save_mode | |
612 | [saved_reg2->hard_regno][1]))) | |
613 | { | |
614 | saved_reg->slot | |
615 | = adjust_address_nv | |
616 | (slot, regno_save_mode[saved_reg->hard_regno][1], 0); | |
617 | regno_save_mem[regno][1] = saved_reg->slot; | |
618 | saved_reg->next = saved_reg2->next; | |
619 | saved_reg2->next = i; | |
620 | if (dump_file != NULL) | |
621 | fprintf (dump_file, "%d uses slot of %d\n", | |
622 | regno, saved_reg2->hard_regno); | |
623 | break; | |
624 | } | |
625 | } | |
626 | if (j == i) | |
627 | { | |
628 | saved_reg->first_p = TRUE; | |
629 | for (best_slot_num = -1, j = 0; j < prev_save_slots_num; j++) | |
630 | { | |
631 | slot = prev_save_slots[j]; | |
632 | if (slot == NULL_RTX) | |
633 | continue; | |
634 | if (GET_MODE_SIZE (regno_save_mode[regno][1]) | |
635 | <= GET_MODE_SIZE (GET_MODE (slot)) | |
636 | && best_slot_num < 0) | |
637 | best_slot_num = j; | |
638 | if (GET_MODE (slot) == regno_save_mode[regno][1]) | |
639 | break; | |
640 | } | |
641 | if (best_slot_num >= 0) | |
642 | { | |
643 | saved_reg->slot = prev_save_slots[best_slot_num]; | |
644 | saved_reg->slot | |
645 | = adjust_address_nv | |
646 | (saved_reg->slot, | |
647 | regno_save_mode[saved_reg->hard_regno][1], 0); | |
648 | if (dump_file != NULL) | |
649 | fprintf (dump_file, | |
650 | "%d uses a slot from prev iteration\n", regno); | |
651 | prev_save_slots[best_slot_num] = NULL_RTX; | |
652 | if (best_slot_num + 1 == prev_save_slots_num) | |
653 | prev_save_slots_num--; | |
654 | } | |
655 | else | |
656 | { | |
657 | saved_reg->slot | |
658 | = assign_stack_local_1 | |
659 | (regno_save_mode[regno][1], | |
80a832cd JJ |
660 | GET_MODE_SIZE (regno_save_mode[regno][1]), 0, |
661 | ASLK_REDUCE_ALIGN); | |
058e97ec VM |
662 | if (dump_file != NULL) |
663 | fprintf (dump_file, "%d uses a new slot\n", regno); | |
664 | } | |
665 | regno_save_mem[regno][1] = saved_reg->slot; | |
666 | save_slots[save_slots_num++] = saved_reg->slot; | |
667 | } | |
668 | } | |
669 | free (saved_reg_conflicts); | |
670 | finish_saved_hard_regs (); | |
671 | } | |
672 | else | |
673 | { | |
e90b336f JL |
674 | /* We are not sharing slots. |
675 | ||
676 | Run through all the call-used hard-registers and allocate | |
677 | space for each in the caller-save area. Try to allocate space | |
058e97ec | 678 | in a manner which allows multi-register saves/restores to be done. */ |
b8698a0f | 679 | |
058e97ec VM |
680 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
681 | for (j = MOVE_MAX_WORDS; j > 0; j--) | |
682 | { | |
683 | int do_save = 1; | |
b8698a0f | 684 | |
058e97ec VM |
685 | /* If no mode exists for this size, try another. Also break out |
686 | if we have already saved this hard register. */ | |
687 | if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0) | |
688 | continue; | |
b8698a0f | 689 | |
058e97ec VM |
690 | /* See if any register in this group has been saved. */ |
691 | for (k = 0; k < j; k++) | |
692 | if (regno_save_mem[i + k][1]) | |
693 | { | |
694 | do_save = 0; | |
695 | break; | |
696 | } | |
697 | if (! do_save) | |
698 | continue; | |
b8698a0f | 699 | |
058e97ec VM |
700 | for (k = 0; k < j; k++) |
701 | if (! TEST_HARD_REG_BIT (hard_regs_used, i + k)) | |
702 | { | |
703 | do_save = 0; | |
704 | break; | |
705 | } | |
706 | if (! do_save) | |
707 | continue; | |
b8698a0f | 708 | |
058e97ec VM |
709 | /* We have found an acceptable mode to store in. Since |
710 | hard register is always saved in the widest mode | |
711 | available, the mode may be wider than necessary, it is | |
712 | OK to reduce the alignment of spill space. We will | |
713 | verify that it is equal to or greater than required | |
714 | when we restore and save the hard register in | |
715 | insert_restore and insert_save. */ | |
716 | regno_save_mem[i][j] | |
717 | = assign_stack_local_1 (regno_save_mode[i][j], | |
718 | GET_MODE_SIZE (regno_save_mode[i][j]), | |
80a832cd | 719 | 0, ASLK_REDUCE_ALIGN); |
b8698a0f | 720 | |
058e97ec VM |
721 | /* Setup single word save area just in case... */ |
722 | for (k = 0; k < j; k++) | |
723 | /* This should not depend on WORDS_BIG_ENDIAN. | |
724 | The order of words in regs is the same as in memory. */ | |
725 | regno_save_mem[i + k][1] | |
726 | = adjust_address_nv (regno_save_mem[i][j], | |
727 | regno_save_mode[i + k][1], | |
728 | k * UNITS_PER_WORD); | |
729 | } | |
730 | } | |
3bdf5ad1 RK |
731 | |
732 | /* Now loop again and set the alias set of any save areas we made to | |
733 | the alias set used to represent frame objects. */ | |
734 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
735 | for (j = MOVE_MAX_WORDS; j > 0; j--) | |
736 | if (regno_save_mem[i][j] != 0) | |
ba4828e0 | 737 | set_mem_alias_set (regno_save_mem[i][j], get_frame_alias_set ()); |
c5986054 | 738 | } |
058e97ec | 739 | |
c5986054 | 740 | \f |
058e97ec | 741 | |
437a710d | 742 | /* Find the places where hard regs are live across calls and save them. */ |
3bdf5ad1 | 743 | |
c5986054 | 744 | void |
d329e058 | 745 | save_call_clobbered_regs (void) |
c5986054 | 746 | { |
169e464e | 747 | struct insn_chain *chain, *next, *last = NULL; |
ef4bddc2 | 748 | machine_mode save_mode [FIRST_PSEUDO_REGISTER]; |
7609e720 | 749 | |
e30edd6c R |
750 | /* Computed in mark_set_regs, holds all registers set by the current |
751 | instruction. */ | |
752 | HARD_REG_SET this_insn_sets; | |
753 | ||
7609e720 BS |
754 | CLEAR_HARD_REG_SET (hard_regs_saved); |
755 | n_regs_saved = 0; | |
c5986054 | 756 | |
7609e720 | 757 | for (chain = reload_insn_chain; chain != 0; chain = next) |
c5986054 | 758 | { |
5d86f5f9 | 759 | rtx_insn *insn = chain->insn; |
7609e720 BS |
760 | enum rtx_code code = GET_CODE (insn); |
761 | ||
762 | next = chain->next; | |
763 | ||
366de0ce | 764 | gcc_assert (!chain->is_caller_save_insn); |
7609e720 | 765 | |
b5b8b0ac | 766 | if (NONDEBUG_INSN_P (insn)) |
c5986054 | 767 | { |
7609e720 BS |
768 | /* If some registers have been saved, see if INSN references |
769 | any of them. We must restore them before the insn if so. */ | |
c5986054 | 770 | |
7609e720 | 771 | if (n_regs_saved) |
c5986054 | 772 | { |
7609e720 | 773 | int regno; |
14292418 | 774 | HARD_REG_SET this_insn_sets; |
7609e720 BS |
775 | |
776 | if (code == JUMP_INSN) | |
777 | /* Restore all registers if this is a JUMP_INSN. */ | |
778 | COPY_HARD_REG_SET (referenced_regs, hard_regs_saved); | |
0e6362d9 | 779 | else |
0887bd4b | 780 | { |
7609e720 | 781 | CLEAR_HARD_REG_SET (referenced_regs); |
b5b8b0ac AO |
782 | mark_referenced_regs (&PATTERN (insn), |
783 | mark_reg_as_referenced, NULL); | |
7609e720 | 784 | AND_HARD_REG_SET (referenced_regs, hard_regs_saved); |
0887bd4b | 785 | } |
c5986054 | 786 | |
7609e720 BS |
787 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
788 | if (TEST_HARD_REG_BIT (referenced_regs, regno)) | |
14292418 BS |
789 | regno += insert_restore (chain, 1, regno, MOVE_MAX_WORDS, |
790 | save_mode); | |
791 | /* If a saved register is set after the call, this means we no | |
792 | longer should restore it. This can happen when parts of a | |
793 | multi-word pseudo do not conflict with other pseudos, so | |
794 | IRA may allocate the same hard register for both. One may | |
795 | be live across the call, while the other is set | |
796 | afterwards. */ | |
797 | CLEAR_HARD_REG_SET (this_insn_sets); | |
798 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
799 | AND_COMPL_HARD_REG_SET (hard_regs_saved, this_insn_sets); | |
c5986054 RS |
800 | } |
801 | ||
ed765125 PB |
802 | if (code == CALL_INSN |
803 | && ! SIBLING_CALL_P (insn) | |
804 | && ! find_reg_note (insn, REG_NORETURN, NULL)) | |
7609e720 | 805 | { |
3cd8c58a | 806 | unsigned regno; |
7609e720 | 807 | HARD_REG_SET hard_regs_to_save; |
c2ba7e7a | 808 | HARD_REG_SET call_def_reg_set; |
a2041967 | 809 | reg_set_iterator rsi; |
e384e6b5 BS |
810 | rtx cheap; |
811 | ||
812 | cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
813 | if (cheap) | |
814 | cheap = XEXP (cheap, 0); | |
7609e720 BS |
815 | |
816 | /* Use the register life information in CHAIN to compute which | |
285f3cf0 R |
817 | regs are live during the call. */ |
818 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
239a0f5b | 819 | &chain->live_throughout); |
f63d1bf7 | 820 | /* Save hard registers always in the widest mode available. */ |
787dc842 JH |
821 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
822 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
823 | save_mode [regno] = regno_save_mode [regno][1]; | |
824 | else | |
825 | save_mode [regno] = VOIDmode; | |
826 | ||
f5143c46 | 827 | /* Look through all live pseudos, mark their hard registers |
787dc842 JH |
828 | and choose proper mode for saving. */ |
829 | EXECUTE_IF_SET_IN_REG_SET | |
a2041967 KH |
830 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) |
831 | { | |
832 | int r = reg_renumber[regno]; | |
833 | int nregs; | |
ef4bddc2 | 834 | machine_mode mode; |
a2041967 | 835 | |
e384e6b5 | 836 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
058e97ec | 837 | continue; |
a2041967 KH |
838 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; |
839 | mode = HARD_REGNO_CALLER_SAVE_MODE | |
840 | (r, nregs, PSEUDO_REGNO_MODE (regno)); | |
bd4288c0 | 841 | if (partial_subreg_p (save_mode[r], mode)) |
a2041967 KH |
842 | save_mode[r] = mode; |
843 | while (nregs-- > 0) | |
844 | SET_HARD_REG_BIT (hard_regs_to_save, r + nregs); | |
845 | } | |
7609e720 BS |
846 | |
847 | /* Record all registers set in this call insn. These don't need | |
285f3cf0 R |
848 | to be saved. N.B. the call insn might set a subreg of a |
849 | multi-hard-reg pseudo; then the pseudo is considered live | |
850 | during the call, but the subreg that is set isn't. */ | |
7609e720 | 851 | CLEAR_HARD_REG_SET (this_insn_sets); |
e30edd6c | 852 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); |
7609e720 BS |
853 | |
854 | /* Compute which hard regs must be saved before this call. */ | |
855 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, call_fixed_reg_set); | |
856 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, this_insn_sets); | |
857 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved); | |
c2ba7e7a RO |
858 | get_call_reg_set_usage (insn, &call_def_reg_set, |
859 | call_used_reg_set); | |
860 | AND_HARD_REG_SET (hard_regs_to_save, call_def_reg_set); | |
7609e720 | 861 | |
7609e720 BS |
862 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
863 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
787dc842 | 864 | regno += insert_save (chain, 1, regno, &hard_regs_to_save, save_mode); |
7609e720 BS |
865 | |
866 | /* Must recompute n_regs_saved. */ | |
867 | n_regs_saved = 0; | |
868 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
869 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
870 | n_regs_saved++; | |
e384e6b5 BS |
871 | |
872 | if (cheap | |
873 | && HARD_REGISTER_P (cheap) | |
874 | && TEST_HARD_REG_BIT (call_used_reg_set, REGNO (cheap))) | |
875 | { | |
1d2944a3 BS |
876 | rtx dest, newpat; |
877 | rtx pat = PATTERN (insn); | |
878 | if (GET_CODE (pat) == PARALLEL) | |
879 | pat = XVECEXP (pat, 0, 0); | |
880 | dest = SET_DEST (pat); | |
54bddf1d IE |
881 | /* For multiple return values dest is PARALLEL. |
882 | Currently we handle only single return value case. */ | |
883 | if (REG_P (dest)) | |
884 | { | |
f7df4a84 | 885 | newpat = gen_rtx_SET (cheap, copy_rtx (dest)); |
54bddf1d IE |
886 | chain = insert_one_insn (chain, 0, -1, newpat); |
887 | } | |
e384e6b5 | 888 | } |
7609e720 | 889 | } |
169e464e | 890 | last = chain; |
7609e720 | 891 | } |
b5b8b0ac AO |
892 | else if (DEBUG_INSN_P (insn) && n_regs_saved) |
893 | mark_referenced_regs (&PATTERN (insn), | |
894 | replace_reg_with_saved_mem, | |
895 | save_mode); | |
c5986054 | 896 | |
058e97ec | 897 | if (chain->next == 0 || chain->next->block != chain->block) |
7609e720 BS |
898 | { |
899 | int regno; | |
900 | /* At the end of the basic block, we must restore any registers that | |
901 | remain saved. If the last insn in the block is a JUMP_INSN, put | |
902 | the restore before the insn, otherwise, put it after the insn. */ | |
903 | ||
49b48605 JJ |
904 | if (n_regs_saved |
905 | && DEBUG_INSN_P (insn) | |
906 | && last | |
907 | && last->block == chain->block) | |
169e464e | 908 | { |
44b9179f | 909 | rtx_insn *ins, *prev; |
169e464e JJ |
910 | basic_block bb = BLOCK_FOR_INSN (insn); |
911 | ||
912 | /* When adding hard reg restores after a DEBUG_INSN, move | |
913 | all notes between last real insn and this DEBUG_INSN after | |
914 | the DEBUG_INSN, otherwise we could get code | |
915 | -g/-g0 differences. */ | |
916 | for (ins = PREV_INSN (insn); ins != last->insn; ins = prev) | |
917 | { | |
918 | prev = PREV_INSN (ins); | |
919 | if (NOTE_P (ins)) | |
920 | { | |
0f82e5c9 DM |
921 | SET_NEXT_INSN (prev) = NEXT_INSN (ins); |
922 | SET_PREV_INSN (NEXT_INSN (ins)) = prev; | |
923 | SET_PREV_INSN (ins) = insn; | |
924 | SET_NEXT_INSN (ins) = NEXT_INSN (insn); | |
925 | SET_NEXT_INSN (insn) = ins; | |
169e464e | 926 | if (NEXT_INSN (ins)) |
0f82e5c9 | 927 | SET_PREV_INSN (NEXT_INSN (ins)) = ins; |
169e464e | 928 | if (BB_END (bb) == insn) |
1130d5e3 | 929 | BB_END (bb) = ins; |
169e464e JJ |
930 | } |
931 | else | |
932 | gcc_assert (DEBUG_INSN_P (ins)); | |
933 | } | |
934 | } | |
935 | last = NULL; | |
936 | ||
7609e720 BS |
937 | if (n_regs_saved) |
938 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
939 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
4b4bf941 | 940 | regno += insert_restore (chain, JUMP_P (insn), |
787dc842 | 941 | regno, MOVE_MAX_WORDS, save_mode); |
7609e720 | 942 | } |
d329e058 | 943 | } |
c5986054 RS |
944 | } |
945 | ||
e30edd6c R |
946 | /* Here from note_stores, or directly from save_call_clobbered_regs, when |
947 | an insn stores a value in a register. | |
7609e720 | 948 | Set the proper bit or bits in this_insn_sets. All pseudos that have |
c5986054 RS |
949 | been assigned hard regs have had their register number changed already, |
950 | so we can ignore pseudos. */ | |
c5986054 | 951 | static void |
7bc980e1 | 952 | mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data) |
c5986054 | 953 | { |
b3694847 | 954 | int regno, endregno, i; |
f883e0a7 | 955 | HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data; |
c5986054 RS |
956 | |
957 | if (GET_CODE (reg) == SUBREG) | |
958 | { | |
ddef6bc7 | 959 | rtx inner = SUBREG_REG (reg); |
f8cfc6aa | 960 | if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 961 | return; |
6f9e3578 | 962 | regno = subreg_regno (reg); |
f1f4e530 | 963 | endregno = regno + subreg_nregs (reg); |
ddef6bc7 | 964 | } |
f8cfc6aa | 965 | else if (REG_P (reg) |
ddef6bc7 | 966 | && REGNO (reg) < FIRST_PSEUDO_REGISTER) |
f1f4e530 JM |
967 | { |
968 | regno = REGNO (reg); | |
72d19505 | 969 | endregno = END_REGNO (reg); |
f1f4e530 | 970 | } |
ddef6bc7 | 971 | else |
c5986054 RS |
972 | return; |
973 | ||
c5986054 | 974 | for (i = regno; i < endregno; i++) |
e30edd6c | 975 | SET_HARD_REG_BIT (*this_insn_sets, i); |
c5986054 RS |
976 | } |
977 | ||
285f3cf0 R |
978 | /* Here from note_stores when an insn stores a value in a register. |
979 | Set the proper bit or bits in the passed regset. All pseudos that have | |
980 | been assigned hard regs have had their register number changed already, | |
981 | so we can ignore pseudos. */ | |
982 | static void | |
7bc980e1 | 983 | add_stored_regs (rtx reg, const_rtx setter, void *data) |
285f3cf0 | 984 | { |
b3694847 | 985 | int regno, endregno, i; |
ef4bddc2 | 986 | machine_mode mode = GET_MODE (reg); |
ddef6bc7 | 987 | int offset = 0; |
285f3cf0 R |
988 | |
989 | if (GET_CODE (setter) == CLOBBER) | |
990 | return; | |
991 | ||
a446b4e8 JM |
992 | if (GET_CODE (reg) == SUBREG |
993 | && REG_P (SUBREG_REG (reg)) | |
994 | && REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER) | |
285f3cf0 | 995 | { |
ddef6bc7 JJ |
996 | offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)), |
997 | GET_MODE (SUBREG_REG (reg)), | |
998 | SUBREG_BYTE (reg), | |
999 | GET_MODE (reg)); | |
a446b4e8 | 1000 | regno = REGNO (SUBREG_REG (reg)) + offset; |
f1f4e530 | 1001 | endregno = regno + subreg_nregs (reg); |
285f3cf0 | 1002 | } |
f1f4e530 JM |
1003 | else |
1004 | { | |
1005 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
1006 | return; | |
285f3cf0 | 1007 | |
f1f4e530 | 1008 | regno = REGNO (reg) + offset; |
09e18274 | 1009 | endregno = end_hard_regno (mode, regno); |
f1f4e530 | 1010 | } |
285f3cf0 R |
1011 | |
1012 | for (i = regno; i < endregno; i++) | |
1013 | SET_REGNO_REG_SET ((regset) data, i); | |
1014 | } | |
1015 | ||
7609e720 | 1016 | /* Walk X and record all referenced registers in REFERENCED_REGS. */ |
c5986054 | 1017 | static void |
b5b8b0ac | 1018 | mark_referenced_regs (rtx *loc, refmarker_fn *mark, void *arg) |
c5986054 | 1019 | { |
b5b8b0ac | 1020 | enum rtx_code code = GET_CODE (*loc); |
6f7d635c | 1021 | const char *fmt; |
c5986054 RS |
1022 | int i, j; |
1023 | ||
7609e720 | 1024 | if (code == SET) |
b5b8b0ac | 1025 | mark_referenced_regs (&SET_SRC (*loc), mark, arg); |
7609e720 BS |
1026 | if (code == SET || code == CLOBBER) |
1027 | { | |
b5b8b0ac AO |
1028 | loc = &SET_DEST (*loc); |
1029 | code = GET_CODE (*loc); | |
1030 | if ((code == REG && REGNO (*loc) < FIRST_PSEUDO_REGISTER) | |
4d450e9a | 1031 | || code == PC || code == CC0 |
b5b8b0ac AO |
1032 | || (code == SUBREG && REG_P (SUBREG_REG (*loc)) |
1033 | && REGNO (SUBREG_REG (*loc)) < FIRST_PSEUDO_REGISTER | |
2696f6a4 AO |
1034 | /* If we're setting only part of a multi-word register, |
1035 | we shall mark it as referenced, because the words | |
1036 | that are not being set should be restored. */ | |
b5b8b0ac AO |
1037 | && ((GET_MODE_SIZE (GET_MODE (*loc)) |
1038 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc)))) | |
1039 | || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc))) | |
2696f6a4 | 1040 | <= UNITS_PER_WORD)))) |
7609e720 BS |
1041 | return; |
1042 | } | |
1043 | if (code == MEM || code == SUBREG) | |
1044 | { | |
b5b8b0ac AO |
1045 | loc = &XEXP (*loc, 0); |
1046 | code = GET_CODE (*loc); | |
7609e720 | 1047 | } |
f95361c8 | 1048 | |
c5986054 RS |
1049 | if (code == REG) |
1050 | { | |
b5b8b0ac | 1051 | int regno = REGNO (*loc); |
7609e720 BS |
1052 | int hardregno = (regno < FIRST_PSEUDO_REGISTER ? regno |
1053 | : reg_renumber[regno]); | |
c5986054 | 1054 | |
7609e720 | 1055 | if (hardregno >= 0) |
b5b8b0ac AO |
1056 | mark (loc, GET_MODE (*loc), hardregno, arg); |
1057 | else if (arg) | |
1058 | /* ??? Will we ever end up with an equiv expression in a debug | |
1059 | insn, that would have required restoring a reg, or will | |
1060 | reload take care of it for us? */ | |
1061 | return; | |
7609e720 BS |
1062 | /* If this is a pseudo that did not get a hard register, scan its |
1063 | memory location, since it might involve the use of another | |
1064 | register, which might be saved. */ | |
f2034d06 JL |
1065 | else if (reg_equiv_mem (regno) != 0) |
1066 | mark_referenced_regs (&XEXP (reg_equiv_mem (regno), 0), mark, arg); | |
1067 | else if (reg_equiv_address (regno) != 0) | |
1068 | mark_referenced_regs (®_equiv_address (regno), mark, arg); | |
c5986054 RS |
1069 | return; |
1070 | } | |
7609e720 | 1071 | |
c5986054 RS |
1072 | fmt = GET_RTX_FORMAT (code); |
1073 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1074 | { | |
1075 | if (fmt[i] == 'e') | |
b5b8b0ac | 1076 | mark_referenced_regs (&XEXP (*loc, i), mark, arg); |
c5986054 | 1077 | else if (fmt[i] == 'E') |
b5b8b0ac AO |
1078 | for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) |
1079 | mark_referenced_regs (&XVECEXP (*loc, i, j), mark, arg); | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | /* Parameter function for mark_referenced_regs() that adds registers | |
1084 | present in the insn and in equivalent mems and addresses to | |
1085 | referenced_regs. */ | |
1086 | ||
1087 | static void | |
1088 | mark_reg_as_referenced (rtx *loc ATTRIBUTE_UNUSED, | |
ef4bddc2 | 1089 | machine_mode mode, |
b5b8b0ac AO |
1090 | int hardregno, |
1091 | void *arg ATTRIBUTE_UNUSED) | |
1092 | { | |
1093 | add_to_hard_reg_set (&referenced_regs, mode, hardregno); | |
1094 | } | |
1095 | ||
1096 | /* Parameter function for mark_referenced_regs() that replaces | |
1097 | registers referenced in a debug_insn that would have been restored, | |
1098 | should it be a non-debug_insn, with their save locations. */ | |
1099 | ||
1100 | static void | |
1101 | replace_reg_with_saved_mem (rtx *loc, | |
ef4bddc2 | 1102 | machine_mode mode, |
b5b8b0ac AO |
1103 | int regno, |
1104 | void *arg) | |
1105 | { | |
1106 | unsigned int i, nregs = hard_regno_nregs [regno][mode]; | |
1107 | rtx mem; | |
ef4bddc2 | 1108 | machine_mode *save_mode = (machine_mode *)arg; |
b5b8b0ac AO |
1109 | |
1110 | for (i = 0; i < nregs; i++) | |
1111 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1112 | break; | |
1113 | ||
1114 | /* If none of the registers in the range would need restoring, we're | |
1115 | all set. */ | |
1116 | if (i == nregs) | |
1117 | return; | |
1118 | ||
1119 | while (++i < nregs) | |
1120 | if (!TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1121 | break; | |
1122 | ||
1123 | if (i == nregs | |
1124 | && regno_save_mem[regno][nregs]) | |
1125 | { | |
1126 | mem = copy_rtx (regno_save_mem[regno][nregs]); | |
1127 | ||
1128 | if (nregs == (unsigned int) hard_regno_nregs[regno][save_mode[regno]]) | |
1129 | mem = adjust_address_nv (mem, save_mode[regno], 0); | |
1130 | ||
1131 | if (GET_MODE (mem) != mode) | |
1132 | { | |
1133 | /* This is gen_lowpart_if_possible(), but without validating | |
1134 | the newly-formed address. */ | |
1135 | int offset = 0; | |
1136 | ||
1137 | if (WORDS_BIG_ENDIAN) | |
1138 | offset = (MAX (GET_MODE_SIZE (GET_MODE (mem)), UNITS_PER_WORD) | |
1139 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1140 | if (BYTES_BIG_ENDIAN) | |
1141 | /* Adjust the address so that the address-after-the-data is | |
1142 | unchanged. */ | |
1143 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1144 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (mem)))); | |
1145 | ||
1146 | mem = adjust_address_nv (mem, mode, offset); | |
1147 | } | |
c5986054 | 1148 | } |
b5b8b0ac AO |
1149 | else |
1150 | { | |
1151 | mem = gen_rtx_CONCATN (mode, rtvec_alloc (nregs)); | |
1152 | for (i = 0; i < nregs; i++) | |
1153 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1154 | { | |
1155 | gcc_assert (regno_save_mem[regno + i][1]); | |
1156 | XVECEXP (mem, 0, i) = copy_rtx (regno_save_mem[regno + i][1]); | |
1157 | } | |
1158 | else | |
1159 | { | |
ef4bddc2 | 1160 | machine_mode smode = save_mode[regno]; |
6393e9d6 JR |
1161 | gcc_assert (smode != VOIDmode); |
1162 | if (hard_regno_nregs [regno][smode] > 1) | |
1163 | smode = mode_for_size (GET_MODE_SIZE (mode) / nregs, | |
1164 | GET_MODE_CLASS (mode), 0); | |
1165 | XVECEXP (mem, 0, i) = gen_rtx_REG (smode, regno + i); | |
b5b8b0ac AO |
1166 | } |
1167 | } | |
1168 | ||
1169 | gcc_assert (GET_MODE (mem) == mode); | |
1170 | *loc = mem; | |
c5986054 | 1171 | } |
b5b8b0ac | 1172 | |
c5986054 | 1173 | \f |
7609e720 BS |
1174 | /* Insert a sequence of insns to restore. Place these insns in front of |
1175 | CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is | |
1176 | the maximum number of registers which should be restored during this call. | |
1177 | It should never be less than 1 since we only work with entire registers. | |
c5986054 RS |
1178 | |
1179 | Note that we have verified in init_caller_save that we can do this | |
1180 | with a simple SET, so use it. Set INSN_CODE to what we save there | |
1181 | since the address might not be valid so the insn might not be recognized. | |
1182 | These insns will be reloaded and have register elimination done by | |
f95361c8 | 1183 | find_reload, so we need not worry about that here. |
c5986054 | 1184 | |
f95361c8 JL |
1185 | Return the extra number of registers saved. */ |
1186 | ||
1187 | static int | |
d329e058 | 1188 | insert_restore (struct insn_chain *chain, int before_p, int regno, |
ef4bddc2 | 1189 | int maxrestore, machine_mode *save_mode) |
c5986054 | 1190 | { |
285f3cf0 | 1191 | int i, k; |
aefdd5ab | 1192 | rtx pat = NULL_RTX; |
830a47ec | 1193 | int code; |
787dc842 | 1194 | unsigned int numregs = 0; |
32e9fa48 | 1195 | struct insn_chain *new_chain; |
787dc842 | 1196 | rtx mem; |
c5986054 | 1197 | |
41806d92 NS |
1198 | /* A common failure mode if register status is not correct in the |
1199 | RTL is for this routine to be called with a REGNO we didn't | |
1200 | expect to save. That will cause us to write an insn with a (nil) | |
1201 | SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
1202 | later, check for this common case here instead. This will remove | |
1203 | one step in debugging such problems. */ | |
366de0ce | 1204 | gcc_assert (regno_save_mem[regno][1]); |
09835ed2 | 1205 | |
7609e720 | 1206 | /* Get the pattern to emit and update our status. |
4554e20d | 1207 | |
7609e720 | 1208 | See if we can restore `maxrestore' registers at once. Work |
4554e20d JL |
1209 | backwards to the single register case. */ |
1210 | for (i = maxrestore; i > 0; i--) | |
c5986054 | 1211 | { |
285f3cf0 | 1212 | int j; |
7609e720 BS |
1213 | int ok = 1; |
1214 | ||
1215 | if (regno_save_mem[regno][i] == 0) | |
4554e20d JL |
1216 | continue; |
1217 | ||
7609e720 BS |
1218 | for (j = 0; j < i; j++) |
1219 | if (! TEST_HARD_REG_BIT (hard_regs_saved, regno + j)) | |
1220 | { | |
1221 | ok = 0; | |
1222 | break; | |
1223 | } | |
f9da5064 | 1224 | /* Must do this one restore at a time. */ |
4554e20d JL |
1225 | if (! ok) |
1226 | continue; | |
7609e720 | 1227 | |
4554e20d JL |
1228 | numregs = i; |
1229 | break; | |
1230 | } | |
f95361c8 | 1231 | |
787dc842 JH |
1232 | mem = regno_save_mem [regno][numregs]; |
1233 | if (save_mode [regno] != VOIDmode | |
1234 | && save_mode [regno] != GET_MODE (mem) | |
c3c96e68 L |
1235 | && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] |
1236 | /* Check that insn to restore REGNO in save_mode[regno] is | |
1237 | correct. */ | |
1238 | && reg_save_code (regno, save_mode[regno]) >= 0) | |
8d2547f2 | 1239 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
ce7b36a4 JW |
1240 | else |
1241 | mem = copy_rtx (mem); | |
76fe54f0 L |
1242 | |
1243 | /* Verify that the alignment of spill space is equal to or greater | |
1244 | than required. */ | |
058e97ec VM |
1245 | gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, |
1246 | GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
76fe54f0 | 1247 | |
f7df4a84 | 1248 | pat = gen_rtx_SET (gen_rtx_REG (GET_MODE (mem), regno), mem); |
78187f5a | 1249 | code = reg_restore_code (regno, GET_MODE (mem)); |
32e9fa48 | 1250 | new_chain = insert_one_insn (chain, before_p, code, pat); |
285f3cf0 R |
1251 | |
1252 | /* Clear status for all registers we restored. */ | |
1253 | for (k = 0; k < i; k++) | |
1254 | { | |
1255 | CLEAR_HARD_REG_BIT (hard_regs_saved, regno + k); | |
32e9fa48 | 1256 | SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); |
285f3cf0 R |
1257 | n_regs_saved--; |
1258 | } | |
1259 | ||
6614fd40 | 1260 | /* Tell our callers how many extra registers we saved/restored. */ |
4554e20d JL |
1261 | return numregs - 1; |
1262 | } | |
f95361c8 | 1263 | |
7609e720 | 1264 | /* Like insert_restore above, but save registers instead. */ |
2cc2d4bb | 1265 | |
4554e20d | 1266 | static int |
d329e058 | 1267 | insert_save (struct insn_chain *chain, int before_p, int regno, |
ef4bddc2 | 1268 | HARD_REG_SET (*to_save), machine_mode *save_mode) |
4554e20d | 1269 | { |
787dc842 JH |
1270 | int i; |
1271 | unsigned int k; | |
4554e20d | 1272 | rtx pat = NULL_RTX; |
830a47ec | 1273 | int code; |
787dc842 | 1274 | unsigned int numregs = 0; |
32e9fa48 | 1275 | struct insn_chain *new_chain; |
787dc842 | 1276 | rtx mem; |
f95361c8 | 1277 | |
41806d92 NS |
1278 | /* A common failure mode if register status is not correct in the |
1279 | RTL is for this routine to be called with a REGNO we didn't | |
1280 | expect to save. That will cause us to write an insn with a (nil) | |
1281 | SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
1282 | later, check for this common case here. This will remove one | |
4554e20d | 1283 | step in debugging such problems. */ |
366de0ce | 1284 | gcc_assert (regno_save_mem[regno][1]); |
c5986054 | 1285 | |
7609e720 | 1286 | /* Get the pattern to emit and update our status. |
f95361c8 | 1287 | |
d329e058 | 1288 | See if we can save several registers with a single instruction. |
4554e20d | 1289 | Work backwards to the single register case. */ |
7609e720 | 1290 | for (i = MOVE_MAX_WORDS; i > 0; i--) |
4554e20d | 1291 | { |
285f3cf0 | 1292 | int j; |
7609e720 BS |
1293 | int ok = 1; |
1294 | if (regno_save_mem[regno][i] == 0) | |
4554e20d | 1295 | continue; |
f95361c8 | 1296 | |
7609e720 BS |
1297 | for (j = 0; j < i; j++) |
1298 | if (! TEST_HARD_REG_BIT (*to_save, regno + j)) | |
1299 | { | |
1300 | ok = 0; | |
1301 | break; | |
1302 | } | |
f9da5064 | 1303 | /* Must do this one save at a time. */ |
4554e20d JL |
1304 | if (! ok) |
1305 | continue; | |
1306 | ||
4554e20d JL |
1307 | numregs = i; |
1308 | break; | |
f95361c8 | 1309 | } |
c5986054 | 1310 | |
787dc842 JH |
1311 | mem = regno_save_mem [regno][numregs]; |
1312 | if (save_mode [regno] != VOIDmode | |
1313 | && save_mode [regno] != GET_MODE (mem) | |
c3c96e68 L |
1314 | && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] |
1315 | /* Check that insn to save REGNO in save_mode[regno] is | |
1316 | correct. */ | |
1317 | && reg_save_code (regno, save_mode[regno]) >= 0) | |
8d2547f2 | 1318 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
ce7b36a4 JW |
1319 | else |
1320 | mem = copy_rtx (mem); | |
76fe54f0 L |
1321 | |
1322 | /* Verify that the alignment of spill space is equal to or greater | |
1323 | than required. */ | |
058e97ec VM |
1324 | gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, |
1325 | GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
76fe54f0 | 1326 | |
f7df4a84 | 1327 | pat = gen_rtx_SET (mem, gen_rtx_REG (GET_MODE (mem), regno)); |
78187f5a | 1328 | code = reg_save_code (regno, GET_MODE (mem)); |
32e9fa48 | 1329 | new_chain = insert_one_insn (chain, before_p, code, pat); |
285f3cf0 R |
1330 | |
1331 | /* Set hard_regs_saved and dead_or_set for all the registers we saved. */ | |
1332 | for (k = 0; k < numregs; k++) | |
1333 | { | |
1334 | SET_HARD_REG_BIT (hard_regs_saved, regno + k); | |
32e9fa48 | 1335 | SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); |
285f3cf0 R |
1336 | n_regs_saved++; |
1337 | } | |
f95361c8 | 1338 | |
6614fd40 | 1339 | /* Tell our callers how many extra registers we saved/restored. */ |
f95361c8 | 1340 | return numregs - 1; |
c5986054 | 1341 | } |
4554e20d | 1342 | |
574af2d6 RS |
1343 | /* A note_uses callback used by insert_one_insn. Add the hard-register |
1344 | equivalent of each REG to regset DATA. */ | |
1345 | ||
1346 | static void | |
1347 | add_used_regs (rtx *loc, void *data) | |
1348 | { | |
1cb22a67 RS |
1349 | subrtx_iterator::array_type array; |
1350 | FOR_EACH_SUBRTX (iter, array, *loc, NONCONST) | |
1351 | { | |
1352 | const_rtx x = *iter; | |
1353 | if (REG_P (x)) | |
1354 | { | |
1355 | unsigned int regno = REGNO (x); | |
1356 | if (HARD_REGISTER_NUM_P (regno)) | |
1357 | bitmap_set_range ((regset) data, regno, | |
1358 | hard_regno_nregs[regno][GET_MODE (x)]); | |
1359 | else | |
1360 | gcc_checking_assert (reg_renumber[regno] < 0); | |
1361 | } | |
1362 | } | |
574af2d6 RS |
1363 | } |
1364 | ||
7609e720 | 1365 | /* Emit a new caller-save insn and set the code. */ |
285f3cf0 | 1366 | static struct insn_chain * |
d329e058 | 1367 | insert_one_insn (struct insn_chain *chain, int before_p, int code, rtx pat) |
4554e20d | 1368 | { |
5d86f5f9 | 1369 | rtx_insn *insn = chain->insn; |
32e9fa48 | 1370 | struct insn_chain *new_chain; |
d329e058 | 1371 | |
4554e20d JL |
1372 | /* If INSN references CC0, put our insns in front of the insn that sets |
1373 | CC0. This is always safe, since the only way we could be passed an | |
1374 | insn that references CC0 is for a restore, and doing a restore earlier | |
1375 | isn't a problem. We do, however, assume here that CALL_INSNs don't | |
1376 | reference CC0. Guard against non-INSN's like CODE_LABEL. */ | |
1377 | ||
618f4073 | 1378 | if (HAVE_cc0 && (NONJUMP_INSN_P (insn) || JUMP_P (insn)) |
4554e20d JL |
1379 | && before_p |
1380 | && reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
7609e720 | 1381 | chain = chain->prev, insn = chain->insn; |
4554e20d | 1382 | |
32e9fa48 | 1383 | new_chain = new_insn_chain (); |
4554e20d JL |
1384 | if (before_p) |
1385 | { | |
285f3cf0 R |
1386 | rtx link; |
1387 | ||
32e9fa48 KG |
1388 | new_chain->prev = chain->prev; |
1389 | if (new_chain->prev != 0) | |
1390 | new_chain->prev->next = new_chain; | |
7609e720 | 1391 | else |
32e9fa48 | 1392 | reload_insn_chain = new_chain; |
7609e720 | 1393 | |
32e9fa48 KG |
1394 | chain->prev = new_chain; |
1395 | new_chain->next = chain; | |
1396 | new_chain->insn = emit_insn_before (pat, insn); | |
92691d7d JL |
1397 | /* ??? It would be nice if we could exclude the already / still saved |
1398 | registers from the live sets. */ | |
32e9fa48 | 1399 | COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); |
574af2d6 RS |
1400 | note_uses (&PATTERN (chain->insn), add_used_regs, |
1401 | &new_chain->live_throughout); | |
ac8bc93e PB |
1402 | /* If CHAIN->INSN is a call, then the registers which contain |
1403 | the arguments to the function are live in the new insn. */ | |
1404 | if (CALL_P (chain->insn)) | |
574af2d6 RS |
1405 | for (link = CALL_INSN_FUNCTION_USAGE (chain->insn); |
1406 | link != NULL_RTX; | |
1407 | link = XEXP (link, 1)) | |
1408 | note_uses (&XEXP (link, 0), add_used_regs, | |
1409 | &new_chain->live_throughout); | |
ac8bc93e | 1410 | |
32e9fa48 | 1411 | CLEAR_REG_SET (&new_chain->dead_or_set); |
06e28de2 | 1412 | if (chain->insn == BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block))) |
1130d5e3 | 1413 | BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; |
4554e20d JL |
1414 | } |
1415 | else | |
1416 | { | |
32e9fa48 KG |
1417 | new_chain->next = chain->next; |
1418 | if (new_chain->next != 0) | |
1419 | new_chain->next->prev = new_chain; | |
1420 | chain->next = new_chain; | |
1421 | new_chain->prev = chain; | |
1422 | new_chain->insn = emit_insn_after (pat, insn); | |
92691d7d JL |
1423 | /* ??? It would be nice if we could exclude the already / still saved |
1424 | registers from the live sets, and observe REG_UNUSED notes. */ | |
32e9fa48 | 1425 | COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); |
285f3cf0 | 1426 | /* Registers that are set in CHAIN->INSN live in the new insn. |
c22cacf3 | 1427 | (Unless there is a REG_UNUSED note for them, but we don't |
285f3cf0 R |
1428 | look for them here.) */ |
1429 | note_stores (PATTERN (chain->insn), add_stored_regs, | |
32e9fa48 KG |
1430 | &new_chain->live_throughout); |
1431 | CLEAR_REG_SET (&new_chain->dead_or_set); | |
06e28de2 | 1432 | if (chain->insn == BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block))) |
1130d5e3 | 1433 | BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; |
4554e20d | 1434 | } |
32e9fa48 KG |
1435 | new_chain->block = chain->block; |
1436 | new_chain->is_caller_save_insn = 1; | |
437a710d | 1437 | |
32e9fa48 KG |
1438 | INSN_CODE (new_chain->insn) = code; |
1439 | return new_chain; | |
4554e20d | 1440 | } |
78187f5a | 1441 | #include "gt-caller-save.h" |