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ccfa01f5 | 1 | /* Optimize by combining instructions for GNU compiler. |
3aea1f79 | 2 | Copyright (C) 1987-2014 Free Software Foundation, Inc. |
ccfa01f5 | 3 | |
f12b58b3 | 4 | This file is part of GCC. |
ccfa01f5 | 5 | |
f12b58b3 | 6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 8 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 9 | version. |
ccfa01f5 | 10 | |
f12b58b3 | 11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
ccfa01f5 | 15 | |
16 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
ccfa01f5 | 19 | |
ccfa01f5 | 20 | /* This module is essentially the "combiner" phase of the U. of Arizona |
21 | Portable Optimizer, but redone to work on our list-structured | |
22 | representation for RTL instead of their string representation. | |
23 | ||
24 | The LOG_LINKS of each insn identify the most recent assignment | |
25 | to each REG used in the insn. It is a list of previous insns, | |
26 | each of which contains a SET for a REG that is used in this insn | |
27 | and not used or set in between. LOG_LINKs never cross basic blocks. | |
28 | They were set up by the preceding pass (lifetime analysis). | |
29 | ||
30 | We try to combine each pair of insns joined by a logical link. | |
139a6a2b | 31 | We also try to combine triplets of insns A, B and C when C has |
32 | a link back to B and B has a link back to A. Likewise for a | |
33 | small number of quadruplets of insns A, B, C and D for which | |
34 | there's high likelihood of of success. | |
ccfa01f5 | 35 | |
36 | LOG_LINKS does not have links for use of the CC0. They don't | |
37 | need to, because the insn that sets the CC0 is always immediately | |
38 | before the insn that tests it. So we always regard a branch | |
39 | insn as having a logical link to the preceding insn. The same is true | |
40 | for an insn explicitly using CC0. | |
41 | ||
42 | We check (with use_crosses_set_p) to avoid combining in such a way | |
43 | as to move a computation to a place where its value would be different. | |
44 | ||
45 | Combination is done by mathematically substituting the previous | |
46 | insn(s) values for the regs they set into the expressions in | |
47 | the later insns that refer to these regs. If the result is a valid insn | |
48 | for our target machine, according to the machine description, | |
49 | we install it, delete the earlier insns, and update the data flow | |
50 | information (LOG_LINKS and REG_NOTES) for what we did. | |
51 | ||
3072d30e | 52 | There are a few exceptions where the dataflow information isn't |
53 | completely updated (however this is only a local issue since it is | |
54 | regenerated before the next pass that uses it): | |
ccfa01f5 | 55 | |
56 | - reg_live_length is not updated | |
40a8fb89 | 57 | - reg_n_refs is not adjusted in the rare case when a register is |
58 | no longer required in a computation | |
4d2e5d52 | 59 | - there are extremely rare cases (see distribute_notes) when a |
40a8fb89 | 60 | REG_DEAD note is lost |
ccfa01f5 | 61 | - a LOG_LINKS entry that refers to an insn with multiple SETs may be |
510f7125 | 62 | removed because there is no way to know which register it was |
ccfa01f5 | 63 | linking |
64 | ||
65 | To simplify substitution, we combine only when the earlier insn(s) | |
66 | consist of only a single assignment. To simplify updating afterward, | |
67 | we never combine when a subroutine call appears in the middle. | |
68 | ||
69 | Since we do not represent assignments to CC0 explicitly except when that | |
70 | is all an insn does, there is no LOG_LINKS entry in an insn that uses | |
71 | the condition code for the insn that set the condition code. | |
72 | Fortunately, these two insns must be consecutive. | |
73 | Therefore, every JUMP_INSN is taken to have an implicit logical link | |
74 | to the preceding insn. This is not quite right, since non-jumps can | |
75 | also use the condition code; but in practice such insns would not | |
76 | combine anyway. */ | |
77 | ||
ccfa01f5 | 78 | #include "config.h" |
405711de | 79 | #include "system.h" |
805e22b2 | 80 | #include "coretypes.h" |
81 | #include "tm.h" | |
7014838c | 82 | #include "rtl.h" |
45550790 | 83 | #include "tree.h" |
9ed99284 | 84 | #include "stor-layout.h" |
945646c1 | 85 | #include "tm_p.h" |
ccfa01f5 | 86 | #include "flags.h" |
87 | #include "regs.h" | |
e7731ac6 | 88 | #include "hard-reg-set.h" |
94ea8568 | 89 | #include "predict.h" |
90 | #include "vec.h" | |
a3020f2f | 91 | #include "hashtab.h" |
92 | #include "hash-set.h" | |
a3020f2f | 93 | #include "machmode.h" |
94 | #include "input.h" | |
0a893c29 | 95 | #include "function.h" |
94ea8568 | 96 | #include "dominance.h" |
97 | #include "cfg.h" | |
98 | #include "cfgrtl.h" | |
99 | #include "cfgcleanup.h" | |
100 | #include "basic-block.h" | |
101 | #include "insn-config.h" | |
2c0e001b | 102 | /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ |
cd03a192 | 103 | #include "expr.h" |
ccfa01f5 | 104 | #include "insn-attr.h" |
105 | #include "recog.h" | |
0b205f4c | 106 | #include "diagnostic-core.h" |
45550790 | 107 | #include "target.h" |
71b0614d | 108 | #include "optabs.h" |
109 | #include "insn-codes.h" | |
d263732c | 110 | #include "rtlhooks-def.h" |
9c8b7028 | 111 | #include "params.h" |
77fce4cd | 112 | #include "tree-pass.h" |
3072d30e | 113 | #include "df.h" |
e6637753 | 114 | #include "valtrack.h" |
5d932349 | 115 | #include "cgraph.h" |
2a0877d8 | 116 | #include "obstack.h" |
5b3d4832 | 117 | #include "statistics.h" |
118 | #include "params.h" | |
802dfe65 | 119 | #include "rtl-iter.h" |
4448f543 | 120 | |
ccfa01f5 | 121 | /* Number of attempts to combine instructions in this function. */ |
122 | ||
123 | static int combine_attempts; | |
124 | ||
125 | /* Number of attempts that got as far as substitution in this function. */ | |
126 | ||
127 | static int combine_merges; | |
128 | ||
129 | /* Number of instructions combined with added SETs in this function. */ | |
130 | ||
131 | static int combine_extras; | |
132 | ||
133 | /* Number of instructions combined in this function. */ | |
134 | ||
135 | static int combine_successes; | |
136 | ||
137 | /* Totals over entire compilation. */ | |
138 | ||
139 | static int total_attempts, total_merges, total_extras, total_successes; | |
5056f17b | 140 | |
cf86e5ce | 141 | /* combine_instructions may try to replace the right hand side of the |
142 | second instruction with the value of an associated REG_EQUAL note | |
143 | before throwing it at try_combine. That is problematic when there | |
144 | is a REG_DEAD note for a register used in the old right hand side | |
145 | and can cause distribute_notes to do wrong things. This is the | |
146 | second instruction if it has been so modified, null otherwise. */ | |
810d7bbd | 147 | |
35330d19 | 148 | static rtx_insn *i2mod; |
98c26c78 | 149 | |
cf86e5ce | 150 | /* When I2MOD is nonnull, this is a copy of the old right hand side. */ |
98c26c78 | 151 | |
cf86e5ce | 152 | static rtx i2mod_old_rhs; |
153 | ||
154 | /* When I2MOD is nonnull, this is a copy of the new right hand side. */ | |
155 | ||
156 | static rtx i2mod_new_rhs; | |
ccfa01f5 | 157 | \f |
7ed1bb71 | 158 | typedef struct reg_stat_struct { |
acac6d5d | 159 | /* Record last point of death of (hard or pseudo) register n. */ |
35330d19 | 160 | rtx_insn *last_death; |
ccfa01f5 | 161 | |
acac6d5d | 162 | /* Record last point of modification of (hard or pseudo) register n. */ |
35330d19 | 163 | rtx_insn *last_set; |
ccfa01f5 | 164 | |
acac6d5d | 165 | /* The next group of fields allows the recording of the last value assigned |
166 | to (hard or pseudo) register n. We use this information to see if an | |
167 | operation being processed is redundant given a prior operation performed | |
168 | on the register. For example, an `and' with a constant is redundant if | |
169 | all the zero bits are already known to be turned off. | |
ccfa01f5 | 170 | |
acac6d5d | 171 | We use an approach similar to that used by cse, but change it in the |
172 | following ways: | |
173 | ||
174 | (1) We do not want to reinitialize at each label. | |
175 | (2) It is useful, but not critical, to know the actual value assigned | |
a0c938f0 | 176 | to a register. Often just its form is helpful. |
acac6d5d | 177 | |
178 | Therefore, we maintain the following fields: | |
179 | ||
180 | last_set_value the last value assigned | |
181 | last_set_label records the value of label_tick when the | |
182 | register was assigned | |
183 | last_set_table_tick records the value of label_tick when a | |
184 | value using the register is assigned | |
185 | last_set_invalid set to nonzero when it is not valid | |
186 | to use the value of this register in some | |
187 | register's value | |
188 | ||
189 | To understand the usage of these tables, it is important to understand | |
190 | the distinction between the value in last_set_value being valid and | |
191 | the register being validly contained in some other expression in the | |
192 | table. | |
193 | ||
194 | (The next two parameters are out of date). | |
195 | ||
196 | reg_stat[i].last_set_value is valid if it is nonzero, and either | |
197 | reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick. | |
198 | ||
199 | Register I may validly appear in any expression returned for the value | |
200 | of another register if reg_n_sets[i] is 1. It may also appear in the | |
201 | value for register J if reg_stat[j].last_set_invalid is zero, or | |
202 | reg_stat[i].last_set_label < reg_stat[j].last_set_label. | |
203 | ||
204 | If an expression is found in the table containing a register which may | |
205 | not validly appear in an expression, the register is replaced by | |
206 | something that won't match, (clobber (const_int 0)). */ | |
207 | ||
208 | /* Record last value assigned to (hard or pseudo) register n. */ | |
209 | ||
210 | rtx last_set_value; | |
211 | ||
212 | /* Record the value of label_tick when an expression involving register n | |
213 | is placed in last_set_value. */ | |
214 | ||
215 | int last_set_table_tick; | |
216 | ||
217 | /* Record the value of label_tick when the value for register n is placed in | |
218 | last_set_value. */ | |
219 | ||
220 | int last_set_label; | |
221 | ||
222 | /* These fields are maintained in parallel with last_set_value and are | |
51a26f41 | 223 | used to store the mode in which the register was last set, the bits |
acac6d5d | 224 | that were known to be zero when it was last set, and the number of |
225 | sign bits copies it was known to have when it was last set. */ | |
226 | ||
227 | unsigned HOST_WIDE_INT last_set_nonzero_bits; | |
228 | char last_set_sign_bit_copies; | |
4c199243 | 229 | ENUM_BITFIELD(machine_mode) last_set_mode : 8; |
acac6d5d | 230 | |
231 | /* Set nonzero if references to register n in expressions should not be | |
232 | used. last_set_invalid is set nonzero when this register is being | |
233 | assigned to and last_set_table_tick == label_tick. */ | |
234 | ||
235 | char last_set_invalid; | |
236 | ||
237 | /* Some registers that are set more than once and used in more than one | |
238 | basic block are nevertheless always set in similar ways. For example, | |
239 | a QImode register may be loaded from memory in two places on a machine | |
240 | where byte loads zero extend. | |
241 | ||
242 | We record in the following fields if a register has some leading bits | |
243 | that are always equal to the sign bit, and what we know about the | |
244 | nonzero bits of a register, specifically which bits are known to be | |
245 | zero. | |
246 | ||
247 | If an entry is zero, it means that we don't know anything special. */ | |
248 | ||
249 | unsigned char sign_bit_copies; | |
250 | ||
251 | unsigned HOST_WIDE_INT nonzero_bits; | |
4c199243 | 252 | |
253 | /* Record the value of the label_tick when the last truncation | |
254 | happened. The field truncated_to_mode is only valid if | |
255 | truncation_label == label_tick. */ | |
256 | ||
257 | int truncation_label; | |
258 | ||
259 | /* Record the last truncation seen for this register. If truncation | |
260 | is not a nop to this mode we might be able to save an explicit | |
261 | truncation if we know that value already contains a truncated | |
262 | value. */ | |
263 | ||
a0c938f0 | 264 | ENUM_BITFIELD(machine_mode) truncated_to_mode : 8; |
7ed1bb71 | 265 | } reg_stat_type; |
266 | ||
acac6d5d | 267 | |
f1f41a6c | 268 | static vec<reg_stat_type> reg_stat; |
ccfa01f5 | 269 | |
3072d30e | 270 | /* Record the luid of the last insn that invalidated memory |
ccfa01f5 | 271 | (anything that writes memory, and subroutine calls, but not pushes). */ |
272 | ||
273 | static int mem_last_set; | |
274 | ||
3072d30e | 275 | /* Record the luid of the last CALL_INSN |
ccfa01f5 | 276 | so we can tell whether a potential combination crosses any calls. */ |
277 | ||
3072d30e | 278 | static int last_call_luid; |
ccfa01f5 | 279 | |
280 | /* When `subst' is called, this is the insn that is being modified | |
281 | (by combining in a previous insn). The PATTERN of this insn | |
282 | is still the old pattern partially modified and it should not be | |
283 | looked at, but this may be used to examine the successors of the insn | |
284 | to judge whether a simplification is valid. */ | |
285 | ||
35330d19 | 286 | static rtx_insn *subst_insn; |
ccfa01f5 | 287 | |
3072d30e | 288 | /* This is the lowest LUID that `subst' is currently dealing with. |
ccfa01f5 | 289 | get_last_value will not return a value if the register was set at or |
3072d30e | 290 | after this LUID. If not for this mechanism, we could get confused if |
ccfa01f5 | 291 | I2 or I1 in try_combine were an insn that used the old value of a register |
292 | to obtain a new value. In that case, we might erroneously get the | |
293 | new value of the register when we wanted the old one. */ | |
294 | ||
3072d30e | 295 | static int subst_low_luid; |
ccfa01f5 | 296 | |
cee293e3 | 297 | /* This contains any hard registers that are used in newpat; reg_dead_at_p |
298 | must consider all these registers to be always live. */ | |
299 | ||
300 | static HARD_REG_SET newpat_used_regs; | |
301 | ||
862e4898 | 302 | /* This is an insn to which a LOG_LINKS entry has been added. If this |
303 | insn is the earlier than I2 or I3, combine should rescan starting at | |
304 | that location. */ | |
305 | ||
35330d19 | 306 | static rtx_insn *added_links_insn; |
862e4898 | 307 | |
345ac34a | 308 | /* Basic block in which we are performing combines. */ |
309 | static basic_block this_basic_block; | |
f529eb25 | 310 | static bool optimize_this_for_speed_p; |
091291bb | 311 | |
ccfa01f5 | 312 | \f |
3072d30e | 313 | /* Length of the currently allocated uid_insn_cost array. */ |
314 | ||
315 | static int max_uid_known; | |
316 | ||
0a8a047c | 317 | /* The following array records the insn_rtx_cost for every insn |
f1a2a2d6 | 318 | in the instruction stream. */ |
319 | ||
320 | static int *uid_insn_cost; | |
321 | ||
3072d30e | 322 | /* The following array records the LOG_LINKS for every insn in the |
2a0877d8 | 323 | instruction stream as struct insn_link pointers. */ |
f1a2a2d6 | 324 | |
2a0877d8 | 325 | struct insn_link { |
35330d19 | 326 | rtx_insn *insn; |
2a0877d8 | 327 | struct insn_link *next; |
328 | }; | |
329 | ||
330 | static struct insn_link **uid_log_links; | |
f1a2a2d6 | 331 | |
3072d30e | 332 | #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)]) |
333 | #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)]) | |
334 | ||
2a0877d8 | 335 | #define FOR_EACH_LOG_LINK(L, INSN) \ |
336 | for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next) | |
337 | ||
338 | /* Links for LOG_LINKS are allocated from this obstack. */ | |
339 | ||
340 | static struct obstack insn_link_obstack; | |
341 | ||
342 | /* Allocate a link. */ | |
343 | ||
344 | static inline struct insn_link * | |
35330d19 | 345 | alloc_insn_link (rtx_insn *insn, struct insn_link *next) |
2a0877d8 | 346 | { |
347 | struct insn_link *l | |
348 | = (struct insn_link *) obstack_alloc (&insn_link_obstack, | |
349 | sizeof (struct insn_link)); | |
350 | l->insn = insn; | |
351 | l->next = next; | |
352 | return l; | |
353 | } | |
354 | ||
3072d30e | 355 | /* Incremented for each basic block. */ |
ccfa01f5 | 356 | |
d2fb1bae | 357 | static int label_tick; |
ccfa01f5 | 358 | |
096125f1 | 359 | /* Reset to label_tick for each extended basic block in scanning order. */ |
3072d30e | 360 | |
361 | static int label_tick_ebb_start; | |
362 | ||
acac6d5d | 363 | /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the |
364 | largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ | |
ccfa01f5 | 365 | |
3d882a35 | 366 | static enum machine_mode nonzero_bits_mode; |
ccfa01f5 | 367 | |
acac6d5d | 368 | /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can |
369 | be safely used. It is zero while computing them and after combine has | |
370 | completed. This former test prevents propagating values based on | |
371 | previously set values, which can be incorrect if a variable is modified | |
372 | in a loop. */ | |
ccfa01f5 | 373 | |
3d882a35 | 374 | static int nonzero_sign_valid; |
e7731ac6 | 375 | |
ccfa01f5 | 376 | \f |
377 | /* Record one modification to rtl structure | |
df738c1f | 378 | to be undone by storing old_contents into *where. */ |
ccfa01f5 | 379 | |
eed2904a | 380 | enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS }; |
0b09525f | 381 | |
ccfa01f5 | 382 | struct undo |
383 | { | |
5b946b05 | 384 | struct undo *next; |
0b09525f | 385 | enum undo_kind kind; |
eed2904a | 386 | union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents; |
387 | union { rtx *r; int *i; struct insn_link **l; } where; | |
ccfa01f5 | 388 | }; |
389 | ||
390 | /* Record a bunch of changes to be undone, up to MAX_UNDO of them. | |
391 | num_undo says how many are currently recorded. | |
392 | ||
ccfa01f5 | 393 | other_insn is nonzero if we have modified some other insn in the process |
3380b197 | 394 | of working on subst_insn. It must be verified too. */ |
ccfa01f5 | 395 | |
396 | struct undobuf | |
397 | { | |
5b946b05 | 398 | struct undo *undos; |
399 | struct undo *frees; | |
35330d19 | 400 | rtx_insn *other_insn; |
ccfa01f5 | 401 | }; |
402 | ||
403 | static struct undobuf undobuf; | |
404 | ||
ccfa01f5 | 405 | /* Number of times the pseudo being substituted for |
406 | was found and replaced. */ | |
407 | ||
408 | static int n_occurrences; | |
409 | ||
b7bf20db | 410 | static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx, |
d263732c | 411 | enum machine_mode, |
412 | unsigned HOST_WIDE_INT, | |
413 | unsigned HOST_WIDE_INT *); | |
b7bf20db | 414 | static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx, |
d263732c | 415 | enum machine_mode, |
416 | unsigned int, unsigned int *); | |
d598ad0d | 417 | static void do_SUBST (rtx *, rtx); |
418 | static void do_SUBST_INT (int *, int); | |
acac6d5d | 419 | static void init_reg_last (void); |
35330d19 | 420 | static void setup_incoming_promotions (rtx_insn *); |
81a410b1 | 421 | static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *); |
35330d19 | 422 | static int cant_combine_insn_p (rtx_insn *); |
423 | static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *, | |
424 | rtx_insn *, rtx_insn *, rtx *, rtx *); | |
425 | static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *); | |
d598ad0d | 426 | static int contains_muldiv (rtx); |
35330d19 | 427 | static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *, |
428 | int *, rtx_insn *); | |
d598ad0d | 429 | static void undo_all (void); |
430 | static void undo_commit (void); | |
35330d19 | 431 | static rtx *find_split_point (rtx *, rtx_insn *, bool); |
34dd021c | 432 | static rtx subst (rtx, rtx, rtx, int, int, int); |
433 | static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int); | |
d598ad0d | 434 | static rtx simplify_if_then_else (rtx); |
435 | static rtx simplify_set (rtx); | |
d7ef6792 | 436 | static rtx simplify_logical (rtx); |
d598ad0d | 437 | static rtx expand_compound_operation (rtx); |
81a410b1 | 438 | static const_rtx expand_field_assignment (const_rtx); |
d598ad0d | 439 | static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT, |
440 | rtx, unsigned HOST_WIDE_INT, int, int, int); | |
441 | static rtx extract_left_shift (rtx, int); | |
d598ad0d | 442 | static int get_pos_from_mask (unsigned HOST_WIDE_INT, |
443 | unsigned HOST_WIDE_INT *); | |
b92e2e43 | 444 | static rtx canon_reg_for_combine (rtx, rtx); |
d598ad0d | 445 | static rtx force_to_mode (rtx, enum machine_mode, |
b92e2e43 | 446 | unsigned HOST_WIDE_INT, int); |
d598ad0d | 447 | static rtx if_then_else_cond (rtx, rtx *, rtx *); |
448 | static rtx known_cond (rtx, enum rtx_code, rtx, rtx); | |
449 | static int rtx_equal_for_field_assignment_p (rtx, rtx); | |
450 | static rtx make_field_assignment (rtx); | |
451 | static rtx apply_distributive_law (rtx); | |
800a7def | 452 | static rtx distribute_and_simplify_rtx (rtx, int); |
1282ed8f | 453 | static rtx simplify_and_const_int_1 (enum machine_mode, rtx, |
454 | unsigned HOST_WIDE_INT); | |
d598ad0d | 455 | static rtx simplify_and_const_int (rtx, enum machine_mode, rtx, |
456 | unsigned HOST_WIDE_INT); | |
d598ad0d | 457 | static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code, |
458 | HOST_WIDE_INT, enum machine_mode, int *); | |
1282ed8f | 459 | static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int); |
460 | static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx, | |
d598ad0d | 461 | int); |
35330d19 | 462 | static int recog_for_combine (rtx *, rtx_insn *, rtx *); |
d598ad0d | 463 | static rtx gen_lowpart_for_combine (enum machine_mode, rtx); |
9ec27261 | 464 | static enum rtx_code simplify_compare_const (enum rtx_code, enum machine_mode, |
465 | rtx, rtx *); | |
d598ad0d | 466 | static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *); |
467 | static void update_table_tick (rtx); | |
35330d19 | 468 | static void record_value_for_reg (rtx, rtx_insn *, rtx); |
469 | static void check_promoted_subreg (rtx_insn *, rtx); | |
81a410b1 | 470 | static void record_dead_and_set_regs_1 (rtx, const_rtx, void *); |
35330d19 | 471 | static void record_dead_and_set_regs (rtx_insn *); |
472 | static int get_last_value_validate (rtx *, rtx_insn *, int, int); | |
b7bf20db | 473 | static rtx get_last_value (const_rtx); |
81a410b1 | 474 | static int use_crosses_set_p (const_rtx, int); |
475 | static void reg_dead_at_p_1 (rtx, const_rtx, void *); | |
35330d19 | 476 | static int reg_dead_at_p (rtx, rtx_insn *); |
477 | static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *); | |
d598ad0d | 478 | static int reg_bitfield_target_p (rtx, rtx); |
35330d19 | 479 | static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx); |
2a0877d8 | 480 | static void distribute_links (struct insn_link *); |
d598ad0d | 481 | static void mark_used_regs_combine (rtx); |
35330d19 | 482 | static void record_promoted_value (rtx_insn *, rtx); |
7d87562d | 483 | static bool unmentioned_reg_p (rtx, rtx); |
d9a71d72 | 484 | static void record_truncated_values (rtx *, void *); |
b7bf20db | 485 | static bool reg_truncated_to_mode (enum machine_mode, const_rtx); |
4c199243 | 486 | static rtx gen_lowpart_or_truncate (enum machine_mode, rtx); |
d263732c | 487 | \f |
488 | ||
489 | /* It is not safe to use ordinary gen_lowpart in combine. | |
490 | See comments in gen_lowpart_for_combine. */ | |
491 | #undef RTL_HOOKS_GEN_LOWPART | |
492 | #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine | |
493 | ||
f4a8fff4 | 494 | /* Our implementation of gen_lowpart never emits a new pseudo. */ |
495 | #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT | |
496 | #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine | |
497 | ||
d263732c | 498 | #undef RTL_HOOKS_REG_NONZERO_REG_BITS |
499 | #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine | |
500 | ||
501 | #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES | |
502 | #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine | |
503 | ||
fd95fba4 | 504 | #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE |
505 | #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode | |
506 | ||
d263732c | 507 | static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER; |
508 | ||
3072d30e | 509 | \f |
d5065e6e | 510 | /* Convenience wrapper for the canonicalize_comparison target hook. |
511 | Target hooks cannot use enum rtx_code. */ | |
512 | static inline void | |
513 | target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1, | |
514 | bool op0_preserve_value) | |
515 | { | |
516 | int code_int = (int)*code; | |
517 | targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value); | |
518 | *code = (enum rtx_code)code_int; | |
519 | } | |
520 | ||
7ed1bb71 | 521 | /* Try to split PATTERN found in INSN. This returns NULL_RTX if |
522 | PATTERN can not be split. Otherwise, it returns an insn sequence. | |
523 | This is a wrapper around split_insns which ensures that the | |
524 | reg_stat vector is made larger if the splitter creates a new | |
525 | register. */ | |
526 | ||
4cd001d5 | 527 | static rtx_insn * |
7ed1bb71 | 528 | combine_split_insns (rtx pattern, rtx insn) |
529 | { | |
4cd001d5 | 530 | rtx_insn *ret; |
7ed1bb71 | 531 | unsigned int nregs; |
532 | ||
4cd001d5 | 533 | ret = safe_as_a <rtx_insn *> (split_insns (pattern, insn)); |
7ed1bb71 | 534 | nregs = max_reg_num (); |
f1f41a6c | 535 | if (nregs > reg_stat.length ()) |
536 | reg_stat.safe_grow_cleared (nregs); | |
7ed1bb71 | 537 | return ret; |
538 | } | |
539 | ||
3072d30e | 540 | /* This is used by find_single_use to locate an rtx in LOC that |
541 | contains exactly one use of DEST, which is typically either a REG | |
542 | or CC0. It returns a pointer to the innermost rtx expression | |
543 | containing DEST. Appearances of DEST that are being used to | |
544 | totally replace it are not counted. */ | |
545 | ||
546 | static rtx * | |
547 | find_single_use_1 (rtx dest, rtx *loc) | |
548 | { | |
549 | rtx x = *loc; | |
550 | enum rtx_code code = GET_CODE (x); | |
551 | rtx *result = NULL; | |
552 | rtx *this_result; | |
553 | int i; | |
554 | const char *fmt; | |
555 | ||
556 | switch (code) | |
557 | { | |
3072d30e | 558 | case CONST: |
559 | case LABEL_REF: | |
560 | case SYMBOL_REF: | |
0349edce | 561 | CASE_CONST_ANY: |
3072d30e | 562 | case CLOBBER: |
563 | return 0; | |
564 | ||
565 | case SET: | |
566 | /* If the destination is anything other than CC0, PC, a REG or a SUBREG | |
567 | of a REG that occupies all of the REG, the insn uses DEST if | |
568 | it is mentioned in the destination or the source. Otherwise, we | |
569 | need just check the source. */ | |
570 | if (GET_CODE (SET_DEST (x)) != CC0 | |
571 | && GET_CODE (SET_DEST (x)) != PC | |
572 | && !REG_P (SET_DEST (x)) | |
573 | && ! (GET_CODE (SET_DEST (x)) == SUBREG | |
574 | && REG_P (SUBREG_REG (SET_DEST (x))) | |
575 | && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
576 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
577 | == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
578 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
579 | break; | |
580 | ||
581 | return find_single_use_1 (dest, &SET_SRC (x)); | |
582 | ||
583 | case MEM: | |
584 | case SUBREG: | |
585 | return find_single_use_1 (dest, &XEXP (x, 0)); | |
586 | ||
587 | default: | |
588 | break; | |
589 | } | |
590 | ||
591 | /* If it wasn't one of the common cases above, check each expression and | |
592 | vector of this code. Look for a unique usage of DEST. */ | |
593 | ||
594 | fmt = GET_RTX_FORMAT (code); | |
595 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
596 | { | |
597 | if (fmt[i] == 'e') | |
598 | { | |
599 | if (dest == XEXP (x, i) | |
600 | || (REG_P (dest) && REG_P (XEXP (x, i)) | |
601 | && REGNO (dest) == REGNO (XEXP (x, i)))) | |
602 | this_result = loc; | |
603 | else | |
604 | this_result = find_single_use_1 (dest, &XEXP (x, i)); | |
605 | ||
606 | if (result == NULL) | |
607 | result = this_result; | |
608 | else if (this_result) | |
609 | /* Duplicate usage. */ | |
610 | return NULL; | |
611 | } | |
612 | else if (fmt[i] == 'E') | |
613 | { | |
614 | int j; | |
615 | ||
616 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
617 | { | |
618 | if (XVECEXP (x, i, j) == dest | |
619 | || (REG_P (dest) | |
620 | && REG_P (XVECEXP (x, i, j)) | |
621 | && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) | |
622 | this_result = loc; | |
623 | else | |
624 | this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); | |
625 | ||
626 | if (result == NULL) | |
627 | result = this_result; | |
628 | else if (this_result) | |
629 | return NULL; | |
630 | } | |
631 | } | |
632 | } | |
633 | ||
634 | return result; | |
635 | } | |
636 | ||
637 | ||
638 | /* See if DEST, produced in INSN, is used only a single time in the | |
639 | sequel. If so, return a pointer to the innermost rtx expression in which | |
640 | it is used. | |
641 | ||
642 | If PLOC is nonzero, *PLOC is set to the insn containing the single use. | |
643 | ||
644 | If DEST is cc0_rtx, we look only at the next insn. In that case, we don't | |
645 | care about REG_DEAD notes or LOG_LINKS. | |
646 | ||
647 | Otherwise, we find the single use by finding an insn that has a | |
648 | LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is | |
649 | only referenced once in that insn, we know that it must be the first | |
650 | and last insn referencing DEST. */ | |
651 | ||
652 | static rtx * | |
35330d19 | 653 | find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc) |
3072d30e | 654 | { |
ee4d588d | 655 | basic_block bb; |
35330d19 | 656 | rtx_insn *next; |
3072d30e | 657 | rtx *result; |
2a0877d8 | 658 | struct insn_link *link; |
3072d30e | 659 | |
660 | #ifdef HAVE_cc0 | |
661 | if (dest == cc0_rtx) | |
662 | { | |
663 | next = NEXT_INSN (insn); | |
664 | if (next == 0 | |
665 | || (!NONJUMP_INSN_P (next) && !JUMP_P (next))) | |
666 | return 0; | |
667 | ||
668 | result = find_single_use_1 (dest, &PATTERN (next)); | |
669 | if (result && ploc) | |
670 | *ploc = next; | |
671 | return result; | |
672 | } | |
673 | #endif | |
674 | ||
675 | if (!REG_P (dest)) | |
676 | return 0; | |
677 | ||
ee4d588d | 678 | bb = BLOCK_FOR_INSN (insn); |
679 | for (next = NEXT_INSN (insn); | |
680 | next && BLOCK_FOR_INSN (next) == bb; | |
681 | next = NEXT_INSN (next)) | |
3072d30e | 682 | if (INSN_P (next) && dead_or_set_p (next, dest)) |
683 | { | |
2a0877d8 | 684 | FOR_EACH_LOG_LINK (link, next) |
685 | if (link->insn == insn) | |
3072d30e | 686 | break; |
687 | ||
688 | if (link) | |
689 | { | |
690 | result = find_single_use_1 (dest, &PATTERN (next)); | |
691 | if (ploc) | |
692 | *ploc = next; | |
693 | return result; | |
694 | } | |
695 | } | |
696 | ||
697 | return 0; | |
698 | } | |
ccfa01f5 | 699 | \f |
2c8daaf1 | 700 | /* Substitute NEWVAL, an rtx expression, into INTO, a place in some |
701 | insn. The substitution can be undone by undo_all. If INTO is already | |
702 | set to NEWVAL, do not record this change. Because computing NEWVAL might | |
703 | also call SUBST, we have to compute it before we put anything into | |
704 | the undo table. */ | |
705 | ||
706 | static void | |
d598ad0d | 707 | do_SUBST (rtx *into, rtx newval) |
2c8daaf1 | 708 | { |
709 | struct undo *buf; | |
710 | rtx oldval = *into; | |
711 | ||
712 | if (oldval == newval) | |
713 | return; | |
714 | ||
bd72d0ee | 715 | /* We'd like to catch as many invalid transformations here as |
716 | possible. Unfortunately, there are way too many mode changes | |
717 | that are perfectly valid, so we'd waste too much effort for | |
718 | little gain doing the checks here. Focus on catching invalid | |
719 | transformations involving integer constants. */ | |
720 | if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT | |
971ba038 | 721 | && CONST_INT_P (newval)) |
bd72d0ee | 722 | { |
723 | /* Sanity check that we're replacing oldval with a CONST_INT | |
724 | that is a valid sign-extension for the original mode. */ | |
cc636d56 | 725 | gcc_assert (INTVAL (newval) |
726 | == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval))); | |
bd72d0ee | 727 | |
728 | /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a | |
729 | CONST_INT is not valid, because after the replacement, the | |
730 | original mode would be gone. Unfortunately, we can't tell | |
731 | when do_SUBST is called to replace the operand thereof, so we | |
732 | perform this test on oldval instead, checking whether an | |
733 | invalid replacement took place before we got here. */ | |
cc636d56 | 734 | gcc_assert (!(GET_CODE (oldval) == SUBREG |
971ba038 | 735 | && CONST_INT_P (SUBREG_REG (oldval)))); |
cc636d56 | 736 | gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND |
971ba038 | 737 | && CONST_INT_P (XEXP (oldval, 0)))); |
77676a31 | 738 | } |
bd72d0ee | 739 | |
2c8daaf1 | 740 | if (undobuf.frees) |
741 | buf = undobuf.frees, undobuf.frees = buf->next; | |
742 | else | |
4c36ffe6 | 743 | buf = XNEW (struct undo); |
2c8daaf1 | 744 | |
df738c1f | 745 | buf->kind = UNDO_RTX; |
2c8daaf1 | 746 | buf->where.r = into; |
747 | buf->old_contents.r = oldval; | |
748 | *into = newval; | |
749 | ||
750 | buf->next = undobuf.undos, undobuf.undos = buf; | |
751 | } | |
752 | ||
9af5ce0c | 753 | #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL)) |
2c8daaf1 | 754 | |
755 | /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution | |
756 | for the value of a HOST_WIDE_INT value (including CONST_INT) is | |
757 | not safe. */ | |
758 | ||
759 | static void | |
d598ad0d | 760 | do_SUBST_INT (int *into, int newval) |
2c8daaf1 | 761 | { |
762 | struct undo *buf; | |
c1131678 | 763 | int oldval = *into; |
2c8daaf1 | 764 | |
765 | if (oldval == newval) | |
766 | return; | |
767 | ||
768 | if (undobuf.frees) | |
769 | buf = undobuf.frees, undobuf.frees = buf->next; | |
770 | else | |
4c36ffe6 | 771 | buf = XNEW (struct undo); |
2c8daaf1 | 772 | |
df738c1f | 773 | buf->kind = UNDO_INT; |
2c8daaf1 | 774 | buf->where.i = into; |
775 | buf->old_contents.i = oldval; | |
776 | *into = newval; | |
777 | ||
778 | buf->next = undobuf.undos, undobuf.undos = buf; | |
779 | } | |
780 | ||
9af5ce0c | 781 | #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL)) |
df738c1f | 782 | |
783 | /* Similar to SUBST, but just substitute the mode. This is used when | |
784 | changing the mode of a pseudo-register, so that any other | |
785 | references to the entry in the regno_reg_rtx array will change as | |
786 | well. */ | |
787 | ||
788 | static void | |
789 | do_SUBST_MODE (rtx *into, enum machine_mode newval) | |
790 | { | |
791 | struct undo *buf; | |
792 | enum machine_mode oldval = GET_MODE (*into); | |
793 | ||
794 | if (oldval == newval) | |
795 | return; | |
796 | ||
797 | if (undobuf.frees) | |
798 | buf = undobuf.frees, undobuf.frees = buf->next; | |
799 | else | |
4c36ffe6 | 800 | buf = XNEW (struct undo); |
df738c1f | 801 | |
802 | buf->kind = UNDO_MODE; | |
803 | buf->where.r = into; | |
804 | buf->old_contents.m = oldval; | |
80c70e76 | 805 | adjust_reg_mode (*into, newval); |
df738c1f | 806 | |
807 | buf->next = undobuf.undos, undobuf.undos = buf; | |
808 | } | |
809 | ||
9af5ce0c | 810 | #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL)) |
eed2904a | 811 | |
3e9db8fa | 812 | #ifndef HAVE_cc0 |
eed2904a | 813 | /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */ |
814 | ||
815 | static void | |
816 | do_SUBST_LINK (struct insn_link **into, struct insn_link *newval) | |
817 | { | |
818 | struct undo *buf; | |
819 | struct insn_link * oldval = *into; | |
820 | ||
821 | if (oldval == newval) | |
822 | return; | |
823 | ||
824 | if (undobuf.frees) | |
825 | buf = undobuf.frees, undobuf.frees = buf->next; | |
826 | else | |
827 | buf = XNEW (struct undo); | |
828 | ||
829 | buf->kind = UNDO_LINKS; | |
830 | buf->where.l = into; | |
831 | buf->old_contents.l = oldval; | |
832 | *into = newval; | |
833 | ||
834 | buf->next = undobuf.undos, undobuf.undos = buf; | |
835 | } | |
836 | ||
837 | #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval) | |
3e9db8fa | 838 | #endif |
2c8daaf1 | 839 | \f |
1aaffeb7 | 840 | /* Subroutine of try_combine. Determine whether the replacement patterns |
841 | NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost | |
842 | than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note | |
843 | that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and | |
844 | undobuf.other_insn may also both be NULL_RTX. Return false if the cost | |
845 | of all the instructions can be estimated and the replacements are more | |
846 | expensive than the original sequence. */ | |
f1a2a2d6 | 847 | |
848 | static bool | |
35330d19 | 849 | combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3, |
850 | rtx newpat, rtx newi2pat, rtx newotherpat) | |
f1a2a2d6 | 851 | { |
6342422c | 852 | int i0_cost, i1_cost, i2_cost, i3_cost; |
f1a2a2d6 | 853 | int new_i2_cost, new_i3_cost; |
854 | int old_cost, new_cost; | |
855 | ||
0a8a047c | 856 | /* Lookup the original insn_rtx_costs. */ |
3072d30e | 857 | i2_cost = INSN_COST (i2); |
858 | i3_cost = INSN_COST (i3); | |
f1a2a2d6 | 859 | |
860 | if (i1) | |
861 | { | |
3072d30e | 862 | i1_cost = INSN_COST (i1); |
6342422c | 863 | if (i0) |
864 | { | |
865 | i0_cost = INSN_COST (i0); | |
866 | old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0 | |
867 | ? i0_cost + i1_cost + i2_cost + i3_cost : 0); | |
868 | } | |
869 | else | |
870 | { | |
871 | old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0 | |
872 | ? i1_cost + i2_cost + i3_cost : 0); | |
873 | i0_cost = 0; | |
874 | } | |
f1a2a2d6 | 875 | } |
876 | else | |
877 | { | |
878 | old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0; | |
6342422c | 879 | i1_cost = i0_cost = 0; |
f1a2a2d6 | 880 | } |
881 | ||
0a8a047c | 882 | /* Calculate the replacement insn_rtx_costs. */ |
f529eb25 | 883 | new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p); |
f1a2a2d6 | 884 | if (newi2pat) |
885 | { | |
f529eb25 | 886 | new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p); |
f1a2a2d6 | 887 | new_cost = (new_i2_cost > 0 && new_i3_cost > 0) |
888 | ? new_i2_cost + new_i3_cost : 0; | |
889 | } | |
890 | else | |
891 | { | |
892 | new_cost = new_i3_cost; | |
893 | new_i2_cost = 0; | |
894 | } | |
895 | ||
a9dea2f0 | 896 | if (undobuf.other_insn) |
897 | { | |
898 | int old_other_cost, new_other_cost; | |
899 | ||
3072d30e | 900 | old_other_cost = INSN_COST (undobuf.other_insn); |
f529eb25 | 901 | new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p); |
a9dea2f0 | 902 | if (old_other_cost > 0 && new_other_cost > 0) |
903 | { | |
904 | old_cost += old_other_cost; | |
905 | new_cost += new_other_cost; | |
906 | } | |
907 | else | |
908 | old_cost = 0; | |
909 | } | |
910 | ||
1aaffeb7 | 911 | /* Disallow this combination if both new_cost and old_cost are greater than |
912 | zero, and new_cost is greater than old cost. */ | |
913 | if (old_cost > 0 && new_cost > old_cost) | |
f1a2a2d6 | 914 | { |
915 | if (dump_file) | |
916 | { | |
6342422c | 917 | if (i0) |
918 | { | |
919 | fprintf (dump_file, | |
920 | "rejecting combination of insns %d, %d, %d and %d\n", | |
921 | INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), | |
922 | INSN_UID (i3)); | |
923 | fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n", | |
924 | i0_cost, i1_cost, i2_cost, i3_cost, old_cost); | |
925 | } | |
926 | else if (i1) | |
f1a2a2d6 | 927 | { |
928 | fprintf (dump_file, | |
929 | "rejecting combination of insns %d, %d and %d\n", | |
930 | INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); | |
931 | fprintf (dump_file, "original costs %d + %d + %d = %d\n", | |
932 | i1_cost, i2_cost, i3_cost, old_cost); | |
933 | } | |
934 | else | |
935 | { | |
936 | fprintf (dump_file, | |
937 | "rejecting combination of insns %d and %d\n", | |
938 | INSN_UID (i2), INSN_UID (i3)); | |
939 | fprintf (dump_file, "original costs %d + %d = %d\n", | |
940 | i2_cost, i3_cost, old_cost); | |
941 | } | |
942 | ||
943 | if (newi2pat) | |
944 | { | |
945 | fprintf (dump_file, "replacement costs %d + %d = %d\n", | |
946 | new_i2_cost, new_i3_cost, new_cost); | |
947 | } | |
948 | else | |
949 | fprintf (dump_file, "replacement cost %d\n", new_cost); | |
950 | } | |
951 | ||
952 | return false; | |
953 | } | |
954 | ||
955 | /* Update the uid_insn_cost array with the replacement costs. */ | |
3072d30e | 956 | INSN_COST (i2) = new_i2_cost; |
957 | INSN_COST (i3) = new_i3_cost; | |
f1a2a2d6 | 958 | if (i1) |
1aaffeb7 | 959 | { |
960 | INSN_COST (i1) = 0; | |
961 | if (i0) | |
962 | INSN_COST (i0) = 0; | |
963 | } | |
f1a2a2d6 | 964 | |
965 | return true; | |
966 | } | |
3072d30e | 967 | |
968 | ||
969 | /* Delete any insns that copy a register to itself. */ | |
970 | ||
971 | static void | |
972 | delete_noop_moves (void) | |
973 | { | |
35330d19 | 974 | rtx_insn *insn, *next; |
3072d30e | 975 | basic_block bb; |
976 | ||
fc00614f | 977 | FOR_EACH_BB_FN (bb, cfun) |
3072d30e | 978 | { |
979 | for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next) | |
980 | { | |
981 | next = NEXT_INSN (insn); | |
982 | if (INSN_P (insn) && noop_move_p (insn)) | |
983 | { | |
3072d30e | 984 | if (dump_file) |
985 | fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn)); | |
986 | ||
987 | delete_insn_and_edges (insn); | |
988 | } | |
989 | } | |
990 | } | |
991 | } | |
992 | ||
993 | \f | |
994 | /* Fill in log links field for all insns. */ | |
995 | ||
996 | static void | |
997 | create_log_links (void) | |
998 | { | |
999 | basic_block bb; | |
35330d19 | 1000 | rtx_insn **next_use; |
1001 | rtx_insn *insn; | |
be10bb5a | 1002 | df_ref def, use; |
3072d30e | 1003 | |
35330d19 | 1004 | next_use = XCNEWVEC (rtx_insn *, max_reg_num ()); |
3072d30e | 1005 | |
1006 | /* Pass through each block from the end, recording the uses of each | |
1007 | register and establishing log links when def is encountered. | |
1008 | Note that we do not clear next_use array in order to save time, | |
1009 | so we have to test whether the use is in the same basic block as def. | |
48e1416a | 1010 | |
3072d30e | 1011 | There are a few cases below when we do not consider the definition or |
1012 | usage -- these are taken from original flow.c did. Don't ask me why it is | |
1013 | done this way; I don't know and if it works, I don't want to know. */ | |
1014 | ||
fc00614f | 1015 | FOR_EACH_BB_FN (bb, cfun) |
3072d30e | 1016 | { |
1017 | FOR_BB_INSNS_REVERSE (bb, insn) | |
1018 | { | |
9845d120 | 1019 | if (!NONDEBUG_INSN_P (insn)) |
3072d30e | 1020 | continue; |
1021 | ||
1022 | /* Log links are created only once. */ | |
1023 | gcc_assert (!LOG_LINKS (insn)); | |
1024 | ||
be10bb5a | 1025 | FOR_EACH_INSN_DEF (def, insn) |
3072d30e | 1026 | { |
3072d30e | 1027 | int regno = DF_REF_REGNO (def); |
35330d19 | 1028 | rtx_insn *use_insn; |
3072d30e | 1029 | |
1030 | if (!next_use[regno]) | |
1031 | continue; | |
1032 | ||
1033 | /* Do not consider if it is pre/post modification in MEM. */ | |
1034 | if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY) | |
1035 | continue; | |
1036 | ||
1037 | /* Do not make the log link for frame pointer. */ | |
1038 | if ((regno == FRAME_POINTER_REGNUM | |
1039 | && (! reload_completed || frame_pointer_needed)) | |
5ae82d58 | 1040 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
3072d30e | 1041 | || (regno == HARD_FRAME_POINTER_REGNUM |
1042 | && (! reload_completed || frame_pointer_needed)) | |
1043 | #endif | |
1044 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
1045 | || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
1046 | #endif | |
1047 | ) | |
1048 | continue; | |
1049 | ||
1050 | use_insn = next_use[regno]; | |
1051 | if (BLOCK_FOR_INSN (use_insn) == bb) | |
1052 | { | |
1053 | /* flow.c claimed: | |
1054 | ||
1055 | We don't build a LOG_LINK for hard registers contained | |
1056 | in ASM_OPERANDs. If these registers get replaced, | |
1057 | we might wind up changing the semantics of the insn, | |
1058 | even if reload can make what appear to be valid | |
1059 | assignments later. */ | |
1060 | if (regno >= FIRST_PSEUDO_REGISTER | |
1061 | || asm_noperands (PATTERN (use_insn)) < 0) | |
67f57040 | 1062 | { |
1063 | /* Don't add duplicate links between instructions. */ | |
2a0877d8 | 1064 | struct insn_link *links; |
1065 | FOR_EACH_LOG_LINK (links, use_insn) | |
1066 | if (insn == links->insn) | |
67f57040 | 1067 | break; |
1068 | ||
1069 | if (!links) | |
2a0877d8 | 1070 | LOG_LINKS (use_insn) |
1071 | = alloc_insn_link (insn, LOG_LINKS (use_insn)); | |
67f57040 | 1072 | } |
3072d30e | 1073 | } |
35330d19 | 1074 | next_use[regno] = NULL; |
3072d30e | 1075 | } |
1076 | ||
be10bb5a | 1077 | FOR_EACH_INSN_USE (use, insn) |
3072d30e | 1078 | { |
3072d30e | 1079 | int regno = DF_REF_REGNO (use); |
1080 | ||
1081 | /* Do not consider the usage of the stack pointer | |
1082 | by function call. */ | |
1083 | if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE) | |
1084 | continue; | |
1085 | ||
1086 | next_use[regno] = insn; | |
1087 | } | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | free (next_use); | |
1092 | } | |
1093 | ||
6342422c | 1094 | /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return |
1095 | true if we found a LOG_LINK that proves that A feeds B. This only works | |
1096 | if there are no instructions between A and B which could have a link | |
c0ed6498 | 1097 | depending on A, since in that case we would not record a link for B. |
1098 | We also check the implicit dependency created by a cc0 setter/user | |
1099 | pair. */ | |
6342422c | 1100 | |
1101 | static bool | |
35330d19 | 1102 | insn_a_feeds_b (rtx_insn *a, rtx_insn *b) |
6342422c | 1103 | { |
2a0877d8 | 1104 | struct insn_link *links; |
1105 | FOR_EACH_LOG_LINK (links, b) | |
1106 | if (links->insn == a) | |
6342422c | 1107 | return true; |
c0ed6498 | 1108 | #ifdef HAVE_cc0 |
1109 | if (sets_cc0_p (a)) | |
1110 | return true; | |
1111 | #endif | |
6342422c | 1112 | return false; |
1113 | } | |
f1a2a2d6 | 1114 | \f |
ccfa01f5 | 1115 | /* Main entry point for combiner. F is the first insn of the function. |
510f7125 | 1116 | NREGS is the first unused pseudo-reg number. |
ccfa01f5 | 1117 | |
d10cfa8d | 1118 | Return nonzero if the combiner has turned an indirect jump |
ca1b9c76 | 1119 | instruction into a direct jump. */ |
c78f0f87 | 1120 | static int |
35330d19 | 1121 | combine_instructions (rtx_insn *f, unsigned int nregs) |
ccfa01f5 | 1122 | { |
35330d19 | 1123 | rtx_insn *insn, *next; |
6536bc06 | 1124 | #ifdef HAVE_cc0 |
35330d19 | 1125 | rtx_insn *prev; |
6536bc06 | 1126 | #endif |
2a0877d8 | 1127 | struct insn_link *links, *nextlinks; |
35330d19 | 1128 | rtx_insn *first; |
096125f1 | 1129 | basic_block last_bb; |
ccfa01f5 | 1130 | |
ca1b9c76 | 1131 | int new_direct_jump_p = 0; |
1132 | ||
3072d30e | 1133 | for (first = f; first && !INSN_P (first); ) |
1134 | first = NEXT_INSN (first); | |
1135 | if (!first) | |
1136 | return 0; | |
1137 | ||
ccfa01f5 | 1138 | combine_attempts = 0; |
1139 | combine_merges = 0; | |
1140 | combine_extras = 0; | |
1141 | combine_successes = 0; | |
1142 | ||
d263732c | 1143 | rtl_hooks = combine_rtl_hooks; |
316f48ea | 1144 | |
f1f41a6c | 1145 | reg_stat.safe_grow_cleared (nregs); |
ccfa01f5 | 1146 | |
1147 | init_recog_no_volatile (); | |
1148 | ||
3072d30e | 1149 | /* Allocate array for insn info. */ |
1150 | max_uid_known = get_max_uid (); | |
2a0877d8 | 1151 | uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1); |
3072d30e | 1152 | uid_insn_cost = XCNEWVEC (int, max_uid_known + 1); |
2a0877d8 | 1153 | gcc_obstack_init (&insn_link_obstack); |
ccfa01f5 | 1154 | |
3d882a35 | 1155 | nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
ccfa01f5 | 1156 | |
acac6d5d | 1157 | /* Don't use reg_stat[].nonzero_bits when computing it. This can cause |
1158 | problems when, for example, we have j <<= 1 in a loop. */ | |
ccfa01f5 | 1159 | |
3d882a35 | 1160 | nonzero_sign_valid = 0; |
096125f1 | 1161 | label_tick = label_tick_ebb_start = 1; |
ccfa01f5 | 1162 | |
3072d30e | 1163 | /* Scan all SETs and see if we can deduce anything about what |
3d882a35 | 1164 | bits are known to be zero for some registers and how many copies |
e02a8937 | 1165 | of the sign bit are known to exist for those registers. |
1166 | ||
1167 | Also set any known values so that we can use it while searching | |
1168 | for what bits are known to be set. */ | |
1169 | ||
3072d30e | 1170 | setup_incoming_promotions (first); |
096125f1 | 1171 | /* Allow the entry block and the first block to fall into the same EBB. |
1172 | Conceptually the incoming promotions are assigned to the entry block. */ | |
34154e27 | 1173 | last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun); |
ce11591e | 1174 | |
3072d30e | 1175 | create_log_links (); |
fc00614f | 1176 | FOR_EACH_BB_FN (this_basic_block, cfun) |
ccfa01f5 | 1177 | { |
f529eb25 | 1178 | optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); |
3072d30e | 1179 | last_call_luid = 0; |
1180 | mem_last_set = -1; | |
096125f1 | 1181 | |
1182 | label_tick++; | |
ee4d588d | 1183 | if (!single_pred_p (this_basic_block) |
096125f1 | 1184 | || single_pred (this_basic_block) != last_bb) |
ee4d588d | 1185 | label_tick_ebb_start = label_tick; |
096125f1 | 1186 | last_bb = this_basic_block; |
1187 | ||
3072d30e | 1188 | FOR_BB_INSNS (this_basic_block, insn) |
1189 | if (INSN_P (insn) && BLOCK_FOR_INSN (insn)) | |
1190 | { | |
cebe9a67 | 1191 | #ifdef AUTO_INC_DEC |
2415b8ff | 1192 | rtx links; |
cebe9a67 | 1193 | #endif |
2415b8ff | 1194 | |
3072d30e | 1195 | subst_low_luid = DF_INSN_LUID (insn); |
1196 | subst_insn = insn; | |
e02a8937 | 1197 | |
3072d30e | 1198 | note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, |
1199 | insn); | |
1200 | record_dead_and_set_regs (insn); | |
24460e25 | 1201 | |
1202 | #ifdef AUTO_INC_DEC | |
3072d30e | 1203 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) |
1204 | if (REG_NOTE_KIND (links) == REG_INC) | |
1205 | set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, | |
1206 | insn); | |
24460e25 | 1207 | #endif |
f1a2a2d6 | 1208 | |
3072d30e | 1209 | /* Record the current insn_rtx_cost of this instruction. */ |
1210 | if (NONJUMP_INSN_P (insn)) | |
f529eb25 | 1211 | INSN_COST (insn) = insn_rtx_cost (PATTERN (insn), |
1212 | optimize_this_for_speed_p); | |
3072d30e | 1213 | if (dump_file) |
9af5ce0c | 1214 | fprintf (dump_file, "insn_cost %d: %d\n", |
1215 | INSN_UID (insn), INSN_COST (insn)); | |
3072d30e | 1216 | } |
ccfa01f5 | 1217 | } |
1218 | ||
3d882a35 | 1219 | nonzero_sign_valid = 1; |
ccfa01f5 | 1220 | |
1221 | /* Now scan all the insns in forward order. */ | |
096125f1 | 1222 | label_tick = label_tick_ebb_start = 1; |
acac6d5d | 1223 | init_reg_last (); |
3072d30e | 1224 | setup_incoming_promotions (first); |
34154e27 | 1225 | last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun); |
5b3d4832 | 1226 | int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS); |
ce11591e | 1227 | |
fc00614f | 1228 | FOR_EACH_BB_FN (this_basic_block, cfun) |
ccfa01f5 | 1229 | { |
35330d19 | 1230 | rtx_insn *last_combined_insn = NULL; |
afb33771 | 1231 | optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); |
3072d30e | 1232 | last_call_luid = 0; |
1233 | mem_last_set = -1; | |
096125f1 | 1234 | |
1235 | label_tick++; | |
ee4d588d | 1236 | if (!single_pred_p (this_basic_block) |
096125f1 | 1237 | || single_pred (this_basic_block) != last_bb) |
ee4d588d | 1238 | label_tick_ebb_start = label_tick; |
096125f1 | 1239 | last_bb = this_basic_block; |
1240 | ||
c107ab96 | 1241 | rtl_profile_for_bb (this_basic_block); |
5496dbfc | 1242 | for (insn = BB_HEAD (this_basic_block); |
a0c938f0 | 1243 | insn != NEXT_INSN (BB_END (this_basic_block)); |
4c26117a | 1244 | insn = next ? next : NEXT_INSN (insn)) |
ccfa01f5 | 1245 | { |
4c26117a | 1246 | next = 0; |
5b3d4832 | 1247 | if (!NONDEBUG_INSN_P (insn)) |
1248 | continue; | |
1249 | ||
1250 | while (last_combined_insn | |
dd1286fb | 1251 | && last_combined_insn->deleted ()) |
5b3d4832 | 1252 | last_combined_insn = PREV_INSN (last_combined_insn); |
1253 | if (last_combined_insn == NULL_RTX | |
1254 | || BARRIER_P (last_combined_insn) | |
1255 | || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block | |
1256 | || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn)) | |
1257 | last_combined_insn = insn; | |
1258 | ||
1259 | /* See if we know about function return values before this | |
1260 | insn based upon SUBREG flags. */ | |
1261 | check_promoted_subreg (insn, PATTERN (insn)); | |
1262 | ||
1263 | /* See if we can find hardregs and subreg of pseudos in | |
1264 | narrower modes. This could help turning TRUNCATEs | |
1265 | into SUBREGs. */ | |
1266 | note_uses (&PATTERN (insn), record_truncated_values, NULL); | |
1267 | ||
1268 | /* Try this insn with each insn it links back to. */ | |
1269 | ||
1270 | FOR_EACH_LOG_LINK (links, insn) | |
35330d19 | 1271 | if ((next = try_combine (insn, links->insn, NULL, |
1272 | NULL, &new_direct_jump_p, | |
5b3d4832 | 1273 | last_combined_insn)) != 0) |
1274 | { | |
1275 | statistics_counter_event (cfun, "two-insn combine", 1); | |
1276 | goto retry; | |
1277 | } | |
1278 | ||
1279 | /* Try each sequence of three linked insns ending with this one. */ | |
1280 | ||
1281 | if (max_combine >= 3) | |
1282 | FOR_EACH_LOG_LINK (links, insn) | |
1283 | { | |
35330d19 | 1284 | rtx_insn *link = links->insn; |
5b3d4832 | 1285 | |
1286 | /* If the linked insn has been replaced by a note, then there | |
1287 | is no point in pursuing this chain any further. */ | |
1288 | if (NOTE_P (link)) | |
1289 | continue; | |
1290 | ||
1291 | FOR_EACH_LOG_LINK (nextlinks, link) | |
1292 | if ((next = try_combine (insn, link, nextlinks->insn, | |
35330d19 | 1293 | NULL, &new_direct_jump_p, |
5b3d4832 | 1294 | last_combined_insn)) != 0) |
1295 | { | |
1296 | statistics_counter_event (cfun, "three-insn combine", 1); | |
4c26117a | 1297 | goto retry; |
5b3d4832 | 1298 | } |
1299 | } | |
ccfa01f5 | 1300 | |
650acf9d | 1301 | #ifdef HAVE_cc0 |
5b3d4832 | 1302 | /* Try to combine a jump insn that uses CC0 |
1303 | with a preceding insn that sets CC0, and maybe with its | |
1304 | logical predecessor as well. | |
1305 | This is how we make decrement-and-branch insns. | |
1306 | We need this special code because data flow connections | |
1307 | via CC0 do not get entered in LOG_LINKS. */ | |
1308 | ||
1309 | if (JUMP_P (insn) | |
1310 | && (prev = prev_nonnote_insn (insn)) != 0 | |
1311 | && NONJUMP_INSN_P (prev) | |
1312 | && sets_cc0_p (PATTERN (prev))) | |
1313 | { | |
35330d19 | 1314 | if ((next = try_combine (insn, prev, NULL, NULL, |
5b3d4832 | 1315 | &new_direct_jump_p, |
1316 | last_combined_insn)) != 0) | |
1317 | goto retry; | |
1318 | ||
1319 | FOR_EACH_LOG_LINK (nextlinks, prev) | |
1320 | if ((next = try_combine (insn, prev, nextlinks->insn, | |
35330d19 | 1321 | NULL, &new_direct_jump_p, |
0444b5eb | 1322 | last_combined_insn)) != 0) |
4c26117a | 1323 | goto retry; |
5b3d4832 | 1324 | } |
4c26117a | 1325 | |
5b3d4832 | 1326 | /* Do the same for an insn that explicitly references CC0. */ |
1327 | if (NONJUMP_INSN_P (insn) | |
1328 | && (prev = prev_nonnote_insn (insn)) != 0 | |
1329 | && NONJUMP_INSN_P (prev) | |
1330 | && sets_cc0_p (PATTERN (prev)) | |
1331 | && GET_CODE (PATTERN (insn)) == SET | |
1332 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) | |
1333 | { | |
35330d19 | 1334 | if ((next = try_combine (insn, prev, NULL, NULL, |
5b3d4832 | 1335 | &new_direct_jump_p, |
1336 | last_combined_insn)) != 0) | |
1337 | goto retry; | |
1338 | ||
1339 | FOR_EACH_LOG_LINK (nextlinks, prev) | |
1340 | if ((next = try_combine (insn, prev, nextlinks->insn, | |
35330d19 | 1341 | NULL, &new_direct_jump_p, |
0444b5eb | 1342 | last_combined_insn)) != 0) |
4c26117a | 1343 | goto retry; |
5b3d4832 | 1344 | } |
4c26117a | 1345 | |
5b3d4832 | 1346 | /* Finally, see if any of the insns that this insn links to |
1347 | explicitly references CC0. If so, try this insn, that insn, | |
1348 | and its predecessor if it sets CC0. */ | |
1349 | FOR_EACH_LOG_LINK (links, insn) | |
1350 | if (NONJUMP_INSN_P (links->insn) | |
1351 | && GET_CODE (PATTERN (links->insn)) == SET | |
1352 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn))) | |
1353 | && (prev = prev_nonnote_insn (links->insn)) != 0 | |
1354 | && NONJUMP_INSN_P (prev) | |
1355 | && sets_cc0_p (PATTERN (prev)) | |
1356 | && (next = try_combine (insn, links->insn, | |
35330d19 | 1357 | prev, NULL, &new_direct_jump_p, |
5b3d4832 | 1358 | last_combined_insn)) != 0) |
1359 | goto retry; | |
650acf9d | 1360 | #endif |
4c26117a | 1361 | |
5b3d4832 | 1362 | /* Try combining an insn with two different insns whose results it |
1363 | uses. */ | |
1364 | if (max_combine >= 3) | |
1365 | FOR_EACH_LOG_LINK (links, insn) | |
1366 | for (nextlinks = links->next; nextlinks; | |
1367 | nextlinks = nextlinks->next) | |
1368 | if ((next = try_combine (insn, links->insn, | |
35330d19 | 1369 | nextlinks->insn, NULL, |
5b3d4832 | 1370 | &new_direct_jump_p, |
1371 | last_combined_insn)) != 0) | |
6342422c | 1372 | |
5b3d4832 | 1373 | { |
1374 | statistics_counter_event (cfun, "three-insn combine", 1); | |
1375 | goto retry; | |
1376 | } | |
1377 | ||
1378 | /* Try four-instruction combinations. */ | |
1379 | if (max_combine >= 4) | |
1380 | FOR_EACH_LOG_LINK (links, insn) | |
1381 | { | |
1382 | struct insn_link *next1; | |
35330d19 | 1383 | rtx_insn *link = links->insn; |
5b3d4832 | 1384 | |
1385 | /* If the linked insn has been replaced by a note, then there | |
1386 | is no point in pursuing this chain any further. */ | |
1387 | if (NOTE_P (link)) | |
1388 | continue; | |
1389 | ||
1390 | FOR_EACH_LOG_LINK (next1, link) | |
1391 | { | |
35330d19 | 1392 | rtx_insn *link1 = next1->insn; |
5b3d4832 | 1393 | if (NOTE_P (link1)) |
1394 | continue; | |
1395 | /* I0 -> I1 -> I2 -> I3. */ | |
1396 | FOR_EACH_LOG_LINK (nextlinks, link1) | |
1397 | if ((next = try_combine (insn, link, link1, | |
1398 | nextlinks->insn, | |
1399 | &new_direct_jump_p, | |
1400 | last_combined_insn)) != 0) | |
1401 | { | |
1402 | statistics_counter_event (cfun, "four-insn combine", 1); | |
6342422c | 1403 | goto retry; |
5b3d4832 | 1404 | } |
1405 | /* I0, I1 -> I2, I2 -> I3. */ | |
1406 | for (nextlinks = next1->next; nextlinks; | |
1407 | nextlinks = nextlinks->next) | |
1408 | if ((next = try_combine (insn, link, link1, | |
1409 | nextlinks->insn, | |
1410 | &new_direct_jump_p, | |
1411 | last_combined_insn)) != 0) | |
1412 | { | |
1413 | statistics_counter_event (cfun, "four-insn combine", 1); | |
6342422c | 1414 | goto retry; |
5b3d4832 | 1415 | } |
1416 | } | |
1417 | ||
1418 | for (next1 = links->next; next1; next1 = next1->next) | |
1419 | { | |
35330d19 | 1420 | rtx_insn *link1 = next1->insn; |
5b3d4832 | 1421 | if (NOTE_P (link1)) |
1422 | continue; | |
1423 | /* I0 -> I2; I1, I2 -> I3. */ | |
1424 | FOR_EACH_LOG_LINK (nextlinks, link) | |
1425 | if ((next = try_combine (insn, link, link1, | |
1426 | nextlinks->insn, | |
1427 | &new_direct_jump_p, | |
1428 | last_combined_insn)) != 0) | |
1429 | { | |
1430 | statistics_counter_event (cfun, "four-insn combine", 1); | |
6342422c | 1431 | goto retry; |
5b3d4832 | 1432 | } |
1433 | /* I0 -> I1; I1, I2 -> I3. */ | |
1434 | FOR_EACH_LOG_LINK (nextlinks, link1) | |
1435 | if ((next = try_combine (insn, link, link1, | |
1436 | nextlinks->insn, | |
1437 | &new_direct_jump_p, | |
1438 | last_combined_insn)) != 0) | |
1439 | { | |
1440 | statistics_counter_event (cfun, "four-insn combine", 1); | |
6342422c | 1441 | goto retry; |
5b3d4832 | 1442 | } |
1443 | } | |
1444 | } | |
6342422c | 1445 | |
5b3d4832 | 1446 | /* Try this insn with each REG_EQUAL note it links back to. */ |
1447 | FOR_EACH_LOG_LINK (links, insn) | |
1448 | { | |
1449 | rtx set, note; | |
35330d19 | 1450 | rtx_insn *temp = links->insn; |
5b3d4832 | 1451 | if ((set = single_set (temp)) != 0 |
1452 | && (note = find_reg_equal_equiv_note (temp)) != 0 | |
1453 | && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST | |
1454 | /* Avoid using a register that may already been marked | |
1455 | dead by an earlier instruction. */ | |
1456 | && ! unmentioned_reg_p (note, SET_SRC (set)) | |
1457 | && (GET_MODE (note) == VOIDmode | |
1458 | ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set))) | |
1459 | : GET_MODE (SET_DEST (set)) == GET_MODE (note))) | |
7d87562d | 1460 | { |
5b3d4832 | 1461 | /* Temporarily replace the set's source with the |
1462 | contents of the REG_EQUAL note. The insn will | |
1463 | be deleted or recognized by try_combine. */ | |
1464 | rtx orig = SET_SRC (set); | |
1465 | SET_SRC (set) = note; | |
1466 | i2mod = temp; | |
1467 | i2mod_old_rhs = copy_rtx (orig); | |
1468 | i2mod_new_rhs = copy_rtx (note); | |
35330d19 | 1469 | next = try_combine (insn, i2mod, NULL, NULL, |
5b3d4832 | 1470 | &new_direct_jump_p, |
1471 | last_combined_insn); | |
35330d19 | 1472 | i2mod = NULL; |
5b3d4832 | 1473 | if (next) |
7d87562d | 1474 | { |
5b3d4832 | 1475 | statistics_counter_event (cfun, "insn-with-note combine", 1); |
1476 | goto retry; | |
7d87562d | 1477 | } |
5b3d4832 | 1478 | SET_SRC (set) = orig; |
7d87562d | 1479 | } |
5b3d4832 | 1480 | } |
7d87562d | 1481 | |
5b3d4832 | 1482 | if (!NOTE_P (insn)) |
1483 | record_dead_and_set_regs (insn); | |
4c26117a | 1484 | |
5b3d4832 | 1485 | retry: |
1486 | ; | |
ccfa01f5 | 1487 | } |
1488 | } | |
1489 | ||
c107ab96 | 1490 | default_rtl_profile (); |
3072d30e | 1491 | clear_bb_flags (); |
94ee50e8 | 1492 | new_direct_jump_p |= purge_all_dead_edges (); |
61317220 | 1493 | delete_noop_moves (); |
b08cd584 | 1494 | |
79eaf784 | 1495 | /* Clean up. */ |
2a0877d8 | 1496 | obstack_free (&insn_link_obstack, NULL); |
3072d30e | 1497 | free (uid_log_links); |
f1a2a2d6 | 1498 | free (uid_insn_cost); |
f1f41a6c | 1499 | reg_stat.release (); |
091291bb | 1500 | |
aeee2a4b | 1501 | { |
1502 | struct undo *undo, *next; | |
1503 | for (undo = undobuf.frees; undo; undo = next) | |
1504 | { | |
1505 | next = undo->next; | |
1506 | free (undo); | |
1507 | } | |
1508 | undobuf.frees = 0; | |
1509 | } | |
1510 | ||
ccfa01f5 | 1511 | total_attempts += combine_attempts; |
1512 | total_merges += combine_merges; | |
1513 | total_extras += combine_extras; | |
1514 | total_successes += combine_successes; | |
1f1c8c5a | 1515 | |
3d882a35 | 1516 | nonzero_sign_valid = 0; |
d263732c | 1517 | rtl_hooks = general_rtl_hooks; |
bc311e72 | 1518 | |
1519 | /* Make recognizer allow volatile MEMs again. */ | |
1520 | init_recog (); | |
ca1b9c76 | 1521 | |
1522 | return new_direct_jump_p; | |
ccfa01f5 | 1523 | } |
e647dd3a | 1524 | |
acac6d5d | 1525 | /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */ |
e647dd3a | 1526 | |
1527 | static void | |
acac6d5d | 1528 | init_reg_last (void) |
e647dd3a | 1529 | { |
acac6d5d | 1530 | unsigned int i; |
7ed1bb71 | 1531 | reg_stat_type *p; |
1532 | ||
f1f41a6c | 1533 | FOR_EACH_VEC_ELT (reg_stat, i, p) |
7ed1bb71 | 1534 | memset (p, 0, offsetof (reg_stat_type, sign_bit_copies)); |
e647dd3a | 1535 | } |
ccfa01f5 | 1536 | \f |
ce11591e | 1537 | /* Set up any promoted values for incoming argument registers. */ |
1538 | ||
9bb87275 | 1539 | static void |
35330d19 | 1540 | setup_incoming_promotions (rtx_insn *first) |
ce11591e | 1541 | { |
21ee4079 | 1542 | tree arg; |
5d932349 | 1543 | bool strictly_local = false; |
ce11591e | 1544 | |
21ee4079 | 1545 | for (arg = DECL_ARGUMENTS (current_function_decl); arg; |
1767a056 | 1546 | arg = DECL_CHAIN (arg)) |
45550790 | 1547 | { |
9b8af75b | 1548 | rtx x, reg = DECL_INCOMING_RTL (arg); |
5d932349 | 1549 | int uns1, uns3; |
1550 | enum machine_mode mode1, mode2, mode3, mode4; | |
21ee4079 | 1551 | |
5d932349 | 1552 | /* Only continue if the incoming argument is in a register. */ |
21ee4079 | 1553 | if (!REG_P (reg)) |
1554 | continue; | |
1555 | ||
5d932349 | 1556 | /* Determine, if possible, whether all call sites of the current |
1557 | function lie within the current compilation unit. (This does | |
1558 | take into account the exporting of a function via taking its | |
1559 | address, and so forth.) */ | |
35ee1c66 | 1560 | strictly_local = cgraph_node::local_info (current_function_decl)->local; |
5d932349 | 1561 | |
1562 | /* The mode and signedness of the argument before any promotions happen | |
1563 | (equal to the mode of the pseudo holding it at that stage). */ | |
1564 | mode1 = TYPE_MODE (TREE_TYPE (arg)); | |
1565 | uns1 = TYPE_UNSIGNED (TREE_TYPE (arg)); | |
1566 | ||
1567 | /* The mode and signedness of the argument after any source language and | |
1568 | TARGET_PROMOTE_PROTOTYPES-driven promotions. */ | |
1569 | mode2 = TYPE_MODE (DECL_ARG_TYPE (arg)); | |
1570 | uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg)); | |
1571 | ||
48e1416a | 1572 | /* The mode and signedness of the argument as it is actually passed, |
5d932349 | 1573 | after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */ |
3b2411a8 | 1574 | mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3, |
1575 | TREE_TYPE (cfun->decl), 0); | |
5d932349 | 1576 | |
1577 | /* The mode of the register in which the argument is being passed. */ | |
1578 | mode4 = GET_MODE (reg); | |
1579 | ||
9b8af75b | 1580 | /* Eliminate sign extensions in the callee when: |
1581 | (a) A mode promotion has occurred; */ | |
1582 | if (mode1 == mode3) | |
1583 | continue; | |
1584 | /* (b) The mode of the register is the same as the mode of | |
1585 | the argument as it is passed; */ | |
1586 | if (mode3 != mode4) | |
1587 | continue; | |
1588 | /* (c) There's no language level extension; */ | |
1589 | if (mode1 == mode2) | |
1590 | ; | |
1591 | /* (c.1) All callers are from the current compilation unit. If that's | |
1592 | the case we don't have to rely on an ABI, we only have to know | |
1593 | what we're generating right now, and we know that we will do the | |
1594 | mode1 to mode2 promotion with the given sign. */ | |
1595 | else if (!strictly_local) | |
1596 | continue; | |
1597 | /* (c.2) The combination of the two promotions is useful. This is | |
1598 | true when the signs match, or if the first promotion is unsigned. | |
1599 | In the later case, (sign_extend (zero_extend x)) is the same as | |
1600 | (zero_extend (zero_extend x)), so make sure to force UNS3 true. */ | |
1601 | else if (uns1) | |
1602 | uns3 = true; | |
1603 | else if (uns3) | |
1604 | continue; | |
1605 | ||
1606 | /* Record that the value was promoted from mode1 to mode3, | |
1607 | so that any sign extension at the head of the current | |
1608 | function may be eliminated. */ | |
1609 | x = gen_rtx_CLOBBER (mode1, const0_rtx); | |
1610 | x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x); | |
1611 | record_value_for_reg (reg, first, x); | |
45550790 | 1612 | } |
ce11591e | 1613 | } |
5d932349 | 1614 | |
778cdcb9 | 1615 | /* Called via note_stores. If X is a pseudo that is narrower than |
1616 | HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. | |
ccfa01f5 | 1617 | |
1618 | If we are setting only a portion of X and we can't figure out what | |
1619 | portion, assume all bits will be used since we don't know what will | |
ec90760f | 1620 | be happening. |
1621 | ||
1622 | Similarly, set how many bits of X are known to be copies of the sign bit | |
510f7125 | 1623 | at all locations in the function. This is the smallest number implied |
ec90760f | 1624 | by any set of X. */ |
ccfa01f5 | 1625 | |
1626 | static void | |
81a410b1 | 1627 | set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data) |
ccfa01f5 | 1628 | { |
35330d19 | 1629 | rtx_insn *insn = (rtx_insn *) data; |
02e7a332 | 1630 | unsigned int num; |
ec90760f | 1631 | |
8ad4c111 | 1632 | if (REG_P (x) |
ccfa01f5 | 1633 | && REGNO (x) >= FIRST_PSEUDO_REGISTER |
b079cccb | 1634 | /* If this register is undefined at the start of the file, we can't |
1635 | say what its contents were. */ | |
e0dde8f8 | 1636 | && ! REGNO_REG_SET_P |
34154e27 | 1637 | (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x)) |
f179ee60 | 1638 | && HWI_COMPUTABLE_MODE_P (GET_MODE (x))) |
ccfa01f5 | 1639 | { |
f1f41a6c | 1640 | reg_stat_type *rsp = ®_stat[REGNO (x)]; |
7ed1bb71 | 1641 | |
24460e25 | 1642 | if (set == 0 || GET_CODE (set) == CLOBBER) |
b079cccb | 1643 | { |
7ed1bb71 | 1644 | rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); |
1645 | rsp->sign_bit_copies = 1; | |
b079cccb | 1646 | return; |
1647 | } | |
ccfa01f5 | 1648 | |
3072d30e | 1649 | /* If this register is being initialized using itself, and the |
1650 | register is uninitialized in this basic block, and there are | |
1651 | no LOG_LINKS which set the register, then part of the | |
1652 | register is uninitialized. In that case we can't assume | |
1653 | anything about the number of nonzero bits. | |
1654 | ||
1655 | ??? We could do better if we checked this in | |
1656 | reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we | |
1657 | could avoid making assumptions about the insn which initially | |
1658 | sets the register, while still using the information in other | |
1659 | insns. We would have to be careful to check every insn | |
1660 | involved in the combination. */ | |
1661 | ||
1662 | if (insn | |
1663 | && reg_referenced_p (x, PATTERN (insn)) | |
1664 | && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)), | |
1665 | REGNO (x))) | |
1666 | { | |
2a0877d8 | 1667 | struct insn_link *link; |
3072d30e | 1668 | |
2a0877d8 | 1669 | FOR_EACH_LOG_LINK (link, insn) |
1670 | if (dead_or_set_p (link->insn, x)) | |
1671 | break; | |
3072d30e | 1672 | if (!link) |
1673 | { | |
7ed1bb71 | 1674 | rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); |
1675 | rsp->sign_bit_copies = 1; | |
3072d30e | 1676 | return; |
1677 | } | |
1678 | } | |
1679 | ||
ccfa01f5 | 1680 | /* If this is a complex assignment, see if we can convert it into a |
88355298 | 1681 | simple assignment. */ |
ccfa01f5 | 1682 | set = expand_field_assignment (set); |
e02a8937 | 1683 | |
1684 | /* If this is a simple assignment, or we have a paradoxical SUBREG, | |
1685 | set what we know about X. */ | |
1686 | ||
1687 | if (SET_DEST (set) == x | |
b537bfdb | 1688 | || (paradoxical_subreg_p (SET_DEST (set)) |
e02a8937 | 1689 | && SUBREG_REG (SET_DEST (set)) == x)) |
ec90760f | 1690 | { |
f53963df | 1691 | rtx src = SET_SRC (set); |
1692 | ||
1693 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND | |
1694 | /* If X is narrower than a word and SRC is a non-negative | |
1695 | constant that would appear negative in the mode of X, | |
acac6d5d | 1696 | sign-extend it for use in reg_stat[].nonzero_bits because some |
f53963df | 1697 | machines (maybe most) will actually do the sign-extension |
510f7125 | 1698 | and this is the conservative approach. |
f53963df | 1699 | |
1700 | ??? For 2.5, try to tighten up the MD files in this regard | |
1701 | instead of this kludge. */ | |
1702 | ||
f92430e0 | 1703 | if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD |
971ba038 | 1704 | && CONST_INT_P (src) |
f53963df | 1705 | && INTVAL (src) > 0 |
f92430e0 | 1706 | && val_signbit_known_set_p (GET_MODE (x), INTVAL (src))) |
1707 | src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x))); | |
f53963df | 1708 | #endif |
1709 | ||
faecad48 | 1710 | /* Don't call nonzero_bits if it cannot change anything. */ |
7ed1bb71 | 1711 | if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0) |
1712 | rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode); | |
ec90760f | 1713 | num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); |
7ed1bb71 | 1714 | if (rsp->sign_bit_copies == 0 |
1715 | || rsp->sign_bit_copies > num) | |
1716 | rsp->sign_bit_copies = num; | |
ec90760f | 1717 | } |
ccfa01f5 | 1718 | else |
ec90760f | 1719 | { |
7ed1bb71 | 1720 | rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); |
1721 | rsp->sign_bit_copies = 1; | |
ec90760f | 1722 | } |
ccfa01f5 | 1723 | } |
1724 | } | |
1725 | \f | |
6342422c | 1726 | /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are |
1727 | optionally insns that were previously combined into I3 or that will be | |
1728 | combined into the merger of INSN and I3. The order is PRED, PRED2, | |
1729 | INSN, SUCC, SUCC2, I3. | |
ccfa01f5 | 1730 | |
1731 | Return 0 if the combination is not allowed for any reason. | |
1732 | ||
510f7125 | 1733 | If the combination is allowed, *PDEST will be set to the single |
ccfa01f5 | 1734 | destination of INSN and *PSRC to the single source, and this function |
1735 | will return 1. */ | |
1736 | ||
1737 | static int | |
35330d19 | 1738 | can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED, |
1739 | rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2, | |
d598ad0d | 1740 | rtx *pdest, rtx *psrc) |
ccfa01f5 | 1741 | { |
1742 | int i; | |
81a410b1 | 1743 | const_rtx set = 0; |
1744 | rtx src, dest; | |
35330d19 | 1745 | rtx_insn *p; |
6536bc06 | 1746 | #ifdef AUTO_INC_DEC |
13a0a8d8 | 1747 | rtx link; |
6536bc06 | 1748 | #endif |
6342422c | 1749 | bool all_adjacent = true; |
5dcaa548 | 1750 | int (*is_volatile_p) (const_rtx); |
ccfa01f5 | 1751 | |
6342422c | 1752 | if (succ) |
1753 | { | |
1754 | if (succ2) | |
1755 | { | |
1756 | if (next_active_insn (succ2) != i3) | |
1757 | all_adjacent = false; | |
1758 | if (next_active_insn (succ) != succ2) | |
1759 | all_adjacent = false; | |
1760 | } | |
1761 | else if (next_active_insn (succ) != i3) | |
1762 | all_adjacent = false; | |
1763 | if (next_active_insn (insn) != succ) | |
1764 | all_adjacent = false; | |
1765 | } | |
1766 | else if (next_active_insn (insn) != i3) | |
1767 | all_adjacent = false; | |
1768 | ||
ccfa01f5 | 1769 | /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. |
510f7125 | 1770 | or a PARALLEL consisting of such a SET and CLOBBERs. |
ccfa01f5 | 1771 | |
1772 | If INSN has CLOBBER parallel parts, ignore them for our processing. | |
1773 | By definition, these happen during the execution of the insn. When it | |
1774 | is merged with another insn, all bets are off. If they are, in fact, | |
1775 | needed and aren't also supplied in I3, they may be added by | |
510f7125 | 1776 | recog_for_combine. Otherwise, it won't match. |
ccfa01f5 | 1777 | |
1778 | We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED | |
1779 | note. | |
1780 | ||
510f7125 | 1781 | Get the source and destination of INSN. If more than one, can't |
ccfa01f5 | 1782 | combine. */ |
510f7125 | 1783 | |
ccfa01f5 | 1784 | if (GET_CODE (PATTERN (insn)) == SET) |
1785 | set = PATTERN (insn); | |
1786 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1787 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
1788 | { | |
1789 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
1790 | { | |
1791 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
1792 | ||
1793 | switch (GET_CODE (elt)) | |
1794 | { | |
20beb951 | 1795 | /* This is important to combine floating point insns |
1796 | for the SH4 port. */ | |
1797 | case USE: | |
1798 | /* Combining an isolated USE doesn't make sense. | |
fd9d9afc | 1799 | We depend here on combinable_i3pat to reject them. */ |
20beb951 | 1800 | /* The code below this loop only verifies that the inputs of |
1801 | the SET in INSN do not change. We call reg_set_between_p | |
4a82352a | 1802 | to verify that the REG in the USE does not change between |
20beb951 | 1803 | I3 and INSN. |
1804 | If the USE in INSN was for a pseudo register, the matching | |
1805 | insn pattern will likely match any register; combining this | |
1806 | with any other USE would only be safe if we knew that the | |
1807 | used registers have identical values, or if there was | |
1808 | something to tell them apart, e.g. different modes. For | |
4a82352a | 1809 | now, we forgo such complicated tests and simply disallow |
20beb951 | 1810 | combining of USES of pseudo registers with any other USE. */ |
8ad4c111 | 1811 | if (REG_P (XEXP (elt, 0)) |
20beb951 | 1812 | && GET_CODE (PATTERN (i3)) == PARALLEL) |
1813 | { | |
1814 | rtx i3pat = PATTERN (i3); | |
1815 | int i = XVECLEN (i3pat, 0) - 1; | |
02e7a332 | 1816 | unsigned int regno = REGNO (XEXP (elt, 0)); |
1817 | ||
20beb951 | 1818 | do |
1819 | { | |
1820 | rtx i3elt = XVECEXP (i3pat, 0, i); | |
02e7a332 | 1821 | |
20beb951 | 1822 | if (GET_CODE (i3elt) == USE |
8ad4c111 | 1823 | && REG_P (XEXP (i3elt, 0)) |
20beb951 | 1824 | && (REGNO (XEXP (i3elt, 0)) == regno |
1825 | ? reg_set_between_p (XEXP (elt, 0), | |
1826 | PREV_INSN (insn), i3) | |
1827 | : regno >= FIRST_PSEUDO_REGISTER)) | |
1828 | return 0; | |
1829 | } | |
1830 | while (--i >= 0); | |
1831 | } | |
1832 | break; | |
1833 | ||
ccfa01f5 | 1834 | /* We can ignore CLOBBERs. */ |
1835 | case CLOBBER: | |
1836 | break; | |
1837 | ||
1838 | case SET: | |
1839 | /* Ignore SETs whose result isn't used but not those that | |
1840 | have side-effects. */ | |
1841 | if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) | |
e38def9c | 1842 | && insn_nothrow_p (insn) |
1843 | && !side_effects_p (elt)) | |
ccfa01f5 | 1844 | break; |
1845 | ||
1846 | /* If we have already found a SET, this is a second one and | |
1847 | so we cannot combine with this insn. */ | |
1848 | if (set) | |
1849 | return 0; | |
1850 | ||
1851 | set = elt; | |
1852 | break; | |
1853 | ||
1854 | default: | |
1855 | /* Anything else means we can't combine. */ | |
1856 | return 0; | |
1857 | } | |
1858 | } | |
1859 | ||
1860 | if (set == 0 | |
1861 | /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, | |
1862 | so don't do anything with it. */ | |
1863 | || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) | |
1864 | return 0; | |
1865 | } | |
1866 | else | |
1867 | return 0; | |
1868 | ||
1869 | if (set == 0) | |
1870 | return 0; | |
1871 | ||
bd279947 | 1872 | /* The simplification in expand_field_assignment may call back to |
1873 | get_last_value, so set safe guard here. */ | |
1874 | subst_low_luid = DF_INSN_LUID (insn); | |
1875 | ||
ccfa01f5 | 1876 | set = expand_field_assignment (set); |
1877 | src = SET_SRC (set), dest = SET_DEST (set); | |
1878 | ||
1879 | /* Don't eliminate a store in the stack pointer. */ | |
1880 | if (dest == stack_pointer_rtx | |
ccfa01f5 | 1881 | /* Don't combine with an insn that sets a register to itself if it has |
e29831db | 1882 | a REG_EQUAL note. This may be part of a LIBCALL sequence. */ |
1bb04728 | 1883 | || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) |
25f0da3c | 1884 | /* Can't merge an ASM_OPERANDS. */ |
1885 | || GET_CODE (src) == ASM_OPERANDS | |
ccfa01f5 | 1886 | /* Can't merge a function call. */ |
1887 | || GET_CODE (src) == CALL | |
9aecb787 | 1888 | /* Don't eliminate a function call argument. */ |
6d7dc5b9 | 1889 | || (CALL_P (i3) |
a8a5b67a | 1890 | && (find_reg_fusage (i3, USE, dest) |
8ad4c111 | 1891 | || (REG_P (dest) |
a8a5b67a | 1892 | && REGNO (dest) < FIRST_PSEUDO_REGISTER |
1893 | && global_regs[REGNO (dest)]))) | |
ccfa01f5 | 1894 | /* Don't substitute into an incremented register. */ |
1895 | || FIND_REG_INC_NOTE (i3, dest) | |
1896 | || (succ && FIND_REG_INC_NOTE (succ, dest)) | |
6342422c | 1897 | || (succ2 && FIND_REG_INC_NOTE (succ2, dest)) |
806351c6 | 1898 | /* Don't substitute into a non-local goto, this confuses CFG. */ |
1899 | || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
ccfa01f5 | 1900 | /* Make sure that DEST is not used after SUCC but before I3. */ |
6342422c | 1901 | || (!all_adjacent |
1902 | && ((succ2 | |
1903 | && (reg_used_between_p (dest, succ2, i3) | |
1904 | || reg_used_between_p (dest, succ, succ2))) | |
1905 | || (!succ2 && succ && reg_used_between_p (dest, succ, i3)))) | |
ccfa01f5 | 1906 | /* Make sure that the value that is to be substituted for the register |
1907 | does not use any registers whose values alter in between. However, | |
1908 | If the insns are adjacent, a use can't cross a set even though we | |
1909 | think it might (this can happen for a sequence of insns each setting | |
acac6d5d | 1910 | the same destination; last_set of that register might point to |
7de568f7 | 1911 | a NOTE). If INSN has a REG_EQUIV note, the register is always |
1912 | equivalent to the memory so the substitution is valid even if there | |
1913 | are intervening stores. Also, don't move a volatile asm or | |
1914 | UNSPEC_VOLATILE across any other insns. */ | |
ccfa01f5 | 1915 | || (! all_adjacent |
e16ceb8e | 1916 | && (((!MEM_P (src) |
7de568f7 | 1917 | || ! find_reg_note (insn, REG_EQUIV, src)) |
3072d30e | 1918 | && use_crosses_set_p (src, DF_INSN_LUID (insn))) |
af61660e | 1919 | || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) |
1920 | || GET_CODE (src) == UNSPEC_VOLATILE)) | |
ccfa01f5 | 1921 | /* Don't combine across a CALL_INSN, because that would possibly |
1922 | change whether the life span of some REGs crosses calls or not, | |
1923 | and it is a pain to update that information. | |
1924 | Exception: if source is a constant, moving it later can't hurt. | |
4d25f9eb | 1925 | Accept that as a special case. */ |
3072d30e | 1926 | || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src))) |
ccfa01f5 | 1927 | return 0; |
1928 | ||
1929 | /* DEST must either be a REG or CC0. */ | |
8ad4c111 | 1930 | if (REG_P (dest)) |
ccfa01f5 | 1931 | { |
1932 | /* If register alignment is being enforced for multi-word items in all | |
1933 | cases except for parameters, it is possible to have a register copy | |
1934 | insn referencing a hard register that is not allowed to contain the | |
1935 | mode being copied and which would not be valid as an operand of most | |
1936 | insns. Eliminate this problem by not combining with such an insn. | |
1937 | ||
1938 | Also, on some machines we don't want to extend the life of a hard | |
422ce0f4 | 1939 | register. */ |
ccfa01f5 | 1940 | |
8ad4c111 | 1941 | if (REG_P (src) |
ccfa01f5 | 1942 | && ((REGNO (dest) < FIRST_PSEUDO_REGISTER |
1943 | && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) | |
9355d30b | 1944 | /* Don't extend the life of a hard register unless it is |
1945 | user variable (if we have few registers) or it can't | |
1946 | fit into the desired register (meaning something special | |
3ff9ced7 | 1947 | is going on). |
1948 | Also avoid substituting a return register into I3, because | |
1949 | reload can't handle a conflict with constraints of other | |
1950 | inputs. */ | |
ccfa01f5 | 1951 | || (REGNO (src) < FIRST_PSEUDO_REGISTER |
422ce0f4 | 1952 | && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) |
ccfa01f5 | 1953 | return 0; |
1954 | } | |
1955 | else if (GET_CODE (dest) != CC0) | |
1956 | return 0; | |
1957 | ||
b9f1cca5 | 1958 | |
ccfa01f5 | 1959 | if (GET_CODE (PATTERN (i3)) == PARALLEL) |
1960 | for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) | |
b9f1cca5 | 1961 | if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) |
1962 | { | |
b9f1cca5 | 1963 | rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); |
b9f1cca5 | 1964 | |
1965 | /* If the clobber represents an earlyclobber operand, we must not | |
1966 | substitute an expression containing the clobbered register. | |
2fb89879 | 1967 | As we do not analyze the constraint strings here, we have to |
b9f1cca5 | 1968 | make the conservative assumption. However, if the register is |
1969 | a fixed hard reg, the clobber cannot represent any operand; | |
1970 | we leave it up to the machine description to either accept or | |
1971 | reject use-and-clobber patterns. */ | |
1972 | if (!REG_P (reg) | |
1973 | || REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1974 | || !fixed_regs[REGNO (reg)]) | |
1975 | if (reg_overlap_mentioned_p (reg, src)) | |
1976 | return 0; | |
1977 | } | |
ccfa01f5 | 1978 | |
1979 | /* If INSN contains anything volatile, or is an `asm' (whether volatile | |
72611874 | 1980 | or not), reject, unless nothing volatile comes between it and I3 */ |
ccfa01f5 | 1981 | |
1982 | if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) | |
72611874 | 1983 | { |
6342422c | 1984 | /* Make sure neither succ nor succ2 contains a volatile reference. */ |
1985 | if (succ2 != 0 && volatile_refs_p (PATTERN (succ2))) | |
1986 | return 0; | |
72611874 | 1987 | if (succ != 0 && volatile_refs_p (PATTERN (succ))) |
a0c938f0 | 1988 | return 0; |
6342422c | 1989 | /* We'll check insns between INSN and I3 below. */ |
72611874 | 1990 | } |
ccfa01f5 | 1991 | |
5ba0e4da | 1992 | /* If INSN is an asm, and DEST is a hard register, reject, since it has |
1993 | to be an explicit register variable, and was chosen for a reason. */ | |
1994 | ||
1995 | if (GET_CODE (src) == ASM_OPERANDS | |
8ad4c111 | 1996 | && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER) |
5ba0e4da | 1997 | return 0; |
1998 | ||
5dcaa548 | 1999 | /* If INSN contains volatile references (specifically volatile MEMs), |
2000 | we cannot combine across any other volatile references. | |
2001 | Even if INSN doesn't contain volatile references, any intervening | |
2002 | volatile insn might affect machine state. */ | |
5d71471b | 2003 | |
5dcaa548 | 2004 | is_volatile_p = volatile_refs_p (PATTERN (insn)) |
2005 | ? volatile_refs_p | |
2006 | : volatile_insn_p; | |
2007 | ||
5d71471b | 2008 | for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) |
5dcaa548 | 2009 | if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p))) |
5d71471b | 2010 | return 0; |
2011 | ||
101bd0af | 2012 | /* If INSN contains an autoincrement or autodecrement, make sure that |
2013 | register is not used between there and I3, and not already used in | |
2014 | I3 either. Neither must it be used in PRED or SUCC, if they exist. | |
ccfa01f5 | 2015 | Also insist that I3 not be a jump; if it were one |
2016 | and the incremented register were spilled, we would lose. */ | |
2017 | ||
2018 | #ifdef AUTO_INC_DEC | |
2019 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
2020 | if (REG_NOTE_KIND (link) == REG_INC | |
6d7dc5b9 | 2021 | && (JUMP_P (i3) |
ccfa01f5 | 2022 | || reg_used_between_p (XEXP (link, 0), insn, i3) |
101bd0af | 2023 | || (pred != NULL_RTX |
2024 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) | |
6342422c | 2025 | || (pred2 != NULL_RTX |
2026 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2))) | |
101bd0af | 2027 | || (succ != NULL_RTX |
2028 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ))) | |
6342422c | 2029 | || (succ2 != NULL_RTX |
2030 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2))) | |
ccfa01f5 | 2031 | || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) |
2032 | return 0; | |
2033 | #endif | |
2034 | ||
2035 | #ifdef HAVE_cc0 | |
2036 | /* Don't combine an insn that follows a CC0-setting insn. | |
2037 | An insn that uses CC0 must not be separated from the one that sets it. | |
2038 | We do, however, allow I2 to follow a CC0-setting insn if that insn | |
2039 | is passed as I1; in that case it will be deleted also. | |
2040 | We also allow combining in this case if all the insns are adjacent | |
2041 | because that would leave the two CC0 insns adjacent as well. | |
2042 | It would be more logical to test whether CC0 occurs inside I1 or I2, | |
2043 | but that would be much slower, and this ought to be equivalent. */ | |
2044 | ||
2045 | p = prev_nonnote_insn (insn); | |
6d7dc5b9 | 2046 | if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p)) |
ccfa01f5 | 2047 | && ! all_adjacent) |
2048 | return 0; | |
2049 | #endif | |
2050 | ||
2051 | /* If we get here, we have passed all the tests and the combination is | |
2052 | to be allowed. */ | |
2053 | ||
2054 | *pdest = dest; | |
2055 | *psrc = src; | |
2056 | ||
2057 | return 1; | |
2058 | } | |
2059 | \f | |
2060 | /* LOC is the location within I3 that contains its pattern or the component | |
2061 | of a PARALLEL of the pattern. We validate that it is valid for combining. | |
2062 | ||
2063 | One problem is if I3 modifies its output, as opposed to replacing it | |
6342422c | 2064 | entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as |
2065 | doing so would produce an insn that is not equivalent to the original insns. | |
ccfa01f5 | 2066 | |
2067 | Consider: | |
2068 | ||
a0c938f0 | 2069 | (set (reg:DI 101) (reg:DI 100)) |
ccfa01f5 | 2070 | (set (subreg:SI (reg:DI 101) 0) <foo>) |
2071 | ||
2072 | This is NOT equivalent to: | |
2073 | ||
a0c938f0 | 2074 | (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) |
87e97de6 | 2075 | (set (reg:DI 101) (reg:DI 100))]) |
ccfa01f5 | 2076 | |
2077 | Not only does this modify 100 (in which case it might still be valid | |
510f7125 | 2078 | if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. |
ccfa01f5 | 2079 | |
2080 | We can also run into a problem if I2 sets a register that I1 | |
2081 | uses and I1 gets directly substituted into I3 (not via I2). In that | |
2082 | case, we would be getting the wrong value of I2DEST into I3, so we | |
2083 | must reject the combination. This case occurs when I2 and I1 both | |
2084 | feed into I3, rather than when I1 feeds into I2, which feeds into I3. | |
d10cfa8d | 2085 | If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source |
6342422c | 2086 | of a SET must prevent combination from occurring. The same situation |
2087 | can occur for I0, in which case I0_NOT_IN_SRC is set. | |
ccfa01f5 | 2088 | |
ccfa01f5 | 2089 | Before doing the above check, we first try to expand a field assignment |
2090 | into a set of logical operations. | |
2091 | ||
d10cfa8d | 2092 | If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which |
ccfa01f5 | 2093 | we place a register that is both set and used within I3. If more than one |
2094 | such register is detected, we fail. | |
2095 | ||
2096 | Return 1 if the combination is valid, zero otherwise. */ | |
2097 | ||
2098 | static int | |
35330d19 | 2099 | combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest, |
6342422c | 2100 | int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed) |
ccfa01f5 | 2101 | { |
2102 | rtx x = *loc; | |
2103 | ||
2104 | if (GET_CODE (x) == SET) | |
2105 | { | |
f65c89fb | 2106 | rtx set = x ; |
ccfa01f5 | 2107 | rtx dest = SET_DEST (set); |
2108 | rtx src = SET_SRC (set); | |
7bd36830 | 2109 | rtx inner_dest = dest; |
5b75b0ba | 2110 | rtx subdest; |
510f7125 | 2111 | |
ccfa01f5 | 2112 | while (GET_CODE (inner_dest) == STRICT_LOW_PART |
2113 | || GET_CODE (inner_dest) == SUBREG | |
2114 | || GET_CODE (inner_dest) == ZERO_EXTRACT) | |
2115 | inner_dest = XEXP (inner_dest, 0); | |
2116 | ||
2cc00ea2 | 2117 | /* Check for the case where I3 modifies its output, as discussed |
2118 | above. We don't want to prevent pseudos from being combined | |
2119 | into the address of a MEM, so only prevent the combination if | |
2120 | i1 or i2 set the same MEM. */ | |
2121 | if ((inner_dest != dest && | |
e16ceb8e | 2122 | (!MEM_P (inner_dest) |
2cc00ea2 | 2123 | || rtx_equal_p (i2dest, inner_dest) |
6342422c | 2124 | || (i1dest && rtx_equal_p (i1dest, inner_dest)) |
2125 | || (i0dest && rtx_equal_p (i0dest, inner_dest))) | |
ccfa01f5 | 2126 | && (reg_overlap_mentioned_p (i2dest, inner_dest) |
6342422c | 2127 | || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)) |
2128 | || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest)))) | |
ad87de1e | 2129 | |
422ce0f4 | 2130 | /* This is the same test done in can_combine_p except we can't test |
2131 | all_adjacent; we don't have to, since this instruction will stay | |
2132 | in place, thus we are not considering increasing the lifetime of | |
2133 | INNER_DEST. | |
ad87de1e | 2134 | |
2135 | Also, if this insn sets a function argument, combining it with | |
2136 | something that might need a spill could clobber a previous | |
2137 | function argument; the all_adjacent test in can_combine_p also | |
2138 | checks this; here, we do a more specific test for this case. */ | |
510f7125 | 2139 | |
8ad4c111 | 2140 | || (REG_P (inner_dest) |
9efc0f8e | 2141 | && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER |
9355d30b | 2142 | && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), |
422ce0f4 | 2143 | GET_MODE (inner_dest)))) |
6342422c | 2144 | || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)) |
2145 | || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src))) | |
ccfa01f5 | 2146 | return 0; |
2147 | ||
5b75b0ba | 2148 | /* If DEST is used in I3, it is being killed in this insn, so |
2149 | record that for later. We have to consider paradoxical | |
2150 | subregs here, since they kill the whole register, but we | |
2151 | ignore partial subregs, STRICT_LOW_PART, etc. | |
41a0a377 | 2152 | Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the |
2153 | STACK_POINTER_REGNUM, since these are always considered to be | |
2154 | live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ | |
5b75b0ba | 2155 | subdest = dest; |
2156 | if (GET_CODE (subdest) == SUBREG | |
2157 | && (GET_MODE_SIZE (GET_MODE (subdest)) | |
2158 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest))))) | |
2159 | subdest = SUBREG_REG (subdest); | |
2160 | if (pi3dest_killed | |
2161 | && REG_P (subdest) | |
2162 | && reg_referenced_p (subdest, PATTERN (i3)) | |
2163 | && REGNO (subdest) != FRAME_POINTER_REGNUM | |
5ae82d58 | 2164 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
5b75b0ba | 2165 | && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM |
b8583074 | 2166 | #endif |
41a0a377 | 2167 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM |
5b75b0ba | 2168 | && (REGNO (subdest) != ARG_POINTER_REGNUM |
2169 | || ! fixed_regs [REGNO (subdest)]) | |
41a0a377 | 2170 | #endif |
5b75b0ba | 2171 | && REGNO (subdest) != STACK_POINTER_REGNUM) |
ccfa01f5 | 2172 | { |
2173 | if (*pi3dest_killed) | |
2174 | return 0; | |
2175 | ||
5b75b0ba | 2176 | *pi3dest_killed = subdest; |
ccfa01f5 | 2177 | } |
2178 | } | |
2179 | ||
2180 | else if (GET_CODE (x) == PARALLEL) | |
2181 | { | |
2182 | int i; | |
2183 | ||
2184 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6342422c | 2185 | if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest, |
2186 | i1_not_in_src, i0_not_in_src, pi3dest_killed)) | |
ccfa01f5 | 2187 | return 0; |
2188 | } | |
2189 | ||
2190 | return 1; | |
2191 | } | |
2192 | \f | |
155b05dc | 2193 | /* Return 1 if X is an arithmetic expression that contains a multiplication |
2194 | and division. We don't count multiplications by powers of two here. */ | |
2195 | ||
2196 | static int | |
d598ad0d | 2197 | contains_muldiv (rtx x) |
155b05dc | 2198 | { |
2199 | switch (GET_CODE (x)) | |
2200 | { | |
2201 | case MOD: case DIV: case UMOD: case UDIV: | |
2202 | return 1; | |
2203 | ||
2204 | case MULT: | |
971ba038 | 2205 | return ! (CONST_INT_P (XEXP (x, 1)) |
897c6c81 | 2206 | && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0); |
155b05dc | 2207 | default: |
6720e96c | 2208 | if (BINARY_P (x)) |
2209 | return contains_muldiv (XEXP (x, 0)) | |
155b05dc | 2210 | || contains_muldiv (XEXP (x, 1)); |
2211 | ||
6720e96c | 2212 | if (UNARY_P (x)) |
2213 | return contains_muldiv (XEXP (x, 0)); | |
155b05dc | 2214 | |
6720e96c | 2215 | return 0; |
155b05dc | 2216 | } |
2217 | } | |
2218 | \f | |
e185d186 | 2219 | /* Determine whether INSN can be used in a combination. Return nonzero if |
2220 | not. This is used in try_combine to detect early some cases where we | |
2221 | can't perform combinations. */ | |
2222 | ||
2223 | static int | |
35330d19 | 2224 | cant_combine_insn_p (rtx_insn *insn) |
e185d186 | 2225 | { |
2226 | rtx set; | |
2227 | rtx src, dest; | |
87e97de6 | 2228 | |
e185d186 | 2229 | /* If this isn't really an insn, we can't do anything. |
2230 | This can occur when flow deletes an insn that it has merged into an | |
2231 | auto-increment address. */ | |
2232 | if (! INSN_P (insn)) | |
2233 | return 1; | |
2234 | ||
e7281db0 | 2235 | /* Never combine loads and stores involving hard regs that are likely |
2236 | to be spilled. The register allocator can usually handle such | |
c9e1a048 | 2237 | reg-reg moves by tying. If we allow the combiner to make |
89f18f73 | 2238 | substitutions of likely-spilled regs, reload might die. |
e185d186 | 2239 | As an exception, we allow combinations involving fixed regs; these are |
2240 | not available to the register allocator so there's no risk involved. */ | |
2241 | ||
2242 | set = single_set (insn); | |
2243 | if (! set) | |
2244 | return 0; | |
2245 | src = SET_SRC (set); | |
2246 | dest = SET_DEST (set); | |
8dc02b98 | 2247 | if (GET_CODE (src) == SUBREG) |
2248 | src = SUBREG_REG (src); | |
2249 | if (GET_CODE (dest) == SUBREG) | |
2250 | dest = SUBREG_REG (dest); | |
422ce0f4 | 2251 | if (REG_P (src) && REG_P (dest) |
24dd0668 | 2252 | && ((HARD_REGISTER_P (src) |
2253 | && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)) | |
2254 | && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src)))) | |
2255 | || (HARD_REGISTER_P (dest) | |
2256 | && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest)) | |
2257 | && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest)))))) | |
e185d186 | 2258 | return 1; |
422ce0f4 | 2259 | |
e185d186 | 2260 | return 0; |
2261 | } | |
2262 | ||
b440a47b | 2263 | struct likely_spilled_retval_info |
2264 | { | |
2265 | unsigned regno, nregs; | |
2266 | unsigned mask; | |
2267 | }; | |
2268 | ||
2269 | /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask | |
2270 | hard registers that are known to be written to / clobbered in full. */ | |
2271 | static void | |
81a410b1 | 2272 | likely_spilled_retval_1 (rtx x, const_rtx set, void *data) |
b440a47b | 2273 | { |
364c0c59 | 2274 | struct likely_spilled_retval_info *const info = |
2275 | (struct likely_spilled_retval_info *) data; | |
b440a47b | 2276 | unsigned regno, nregs; |
2277 | unsigned new_mask; | |
2278 | ||
2279 | if (!REG_P (XEXP (set, 0))) | |
2280 | return; | |
2281 | regno = REGNO (x); | |
2282 | if (regno >= info->regno + info->nregs) | |
2283 | return; | |
2284 | nregs = hard_regno_nregs[regno][GET_MODE (x)]; | |
2285 | if (regno + nregs <= info->regno) | |
2286 | return; | |
2287 | new_mask = (2U << (nregs - 1)) - 1; | |
2288 | if (regno < info->regno) | |
2289 | new_mask >>= info->regno - regno; | |
2290 | else | |
2291 | new_mask <<= regno - info->regno; | |
1403633e | 2292 | info->mask &= ~new_mask; |
b440a47b | 2293 | } |
2294 | ||
2295 | /* Return nonzero iff part of the return value is live during INSN, and | |
2296 | it is likely spilled. This can happen when more than one insn is needed | |
2297 | to copy the return value, e.g. when we consider to combine into the | |
2298 | second copy insn for a complex value. */ | |
2299 | ||
2300 | static int | |
35330d19 | 2301 | likely_spilled_retval_p (rtx_insn *insn) |
b440a47b | 2302 | { |
4cd001d5 | 2303 | rtx_insn *use = BB_END (this_basic_block); |
2304 | rtx reg; | |
2305 | rtx_insn *p; | |
b440a47b | 2306 | unsigned regno, nregs; |
2307 | /* We assume here that no machine mode needs more than | |
2308 | 32 hard registers when the value overlaps with a register | |
e1ce1485 | 2309 | for which TARGET_FUNCTION_VALUE_REGNO_P is true. */ |
b440a47b | 2310 | unsigned mask; |
2311 | struct likely_spilled_retval_info info; | |
2312 | ||
2313 | if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use) | |
2314 | return 0; | |
2315 | reg = XEXP (PATTERN (use), 0); | |
e1ce1485 | 2316 | if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg))) |
b440a47b | 2317 | return 0; |
2318 | regno = REGNO (reg); | |
2319 | nregs = hard_regno_nregs[regno][GET_MODE (reg)]; | |
2320 | if (nregs == 1) | |
2321 | return 0; | |
2322 | mask = (2U << (nregs - 1)) - 1; | |
2323 | ||
2324 | /* Disregard parts of the return value that are set later. */ | |
2325 | info.regno = regno; | |
2326 | info.nregs = nregs; | |
2327 | info.mask = mask; | |
2328 | for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p)) | |
1403633e | 2329 | if (INSN_P (p)) |
2330 | note_stores (PATTERN (p), likely_spilled_retval_1, &info); | |
b440a47b | 2331 | mask = info.mask; |
2332 | ||
2333 | /* Check if any of the (probably) live return value registers is | |
2334 | likely spilled. */ | |
2335 | nregs --; | |
2336 | do | |
2337 | { | |
2338 | if ((mask & 1 << nregs) | |
24dd0668 | 2339 | && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs))) |
b440a47b | 2340 | return 1; |
2341 | } while (nregs--); | |
2342 | return 0; | |
2343 | } | |
2344 | ||
2584991b | 2345 | /* Adjust INSN after we made a change to its destination. |
2346 | ||
2347 | Changing the destination can invalidate notes that say something about | |
2348 | the results of the insn and a LOG_LINK pointing to the insn. */ | |
2349 | ||
2350 | static void | |
35330d19 | 2351 | adjust_for_new_dest (rtx_insn *insn) |
2584991b | 2352 | { |
2584991b | 2353 | /* For notes, be conservative and simply remove them. */ |
f16feee2 | 2354 | remove_reg_equal_equiv_notes (insn); |
2584991b | 2355 | |
2356 | /* The new insn will have a destination that was previously the destination | |
2357 | of an insn just above it. Call distribute_links to make a LOG_LINK from | |
2358 | the next use of that destination. */ | |
2a0877d8 | 2359 | distribute_links (alloc_insn_link (insn, NULL)); |
d40c9fd1 | 2360 | |
2361 | df_insn_rescan (insn); | |
2584991b | 2362 | } |
2363 | ||
136305f4 | 2364 | /* Return TRUE if combine can reuse reg X in mode MODE. |
2365 | ADDED_SETS is nonzero if the original set is still required. */ | |
2366 | static bool | |
2367 | can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode) | |
2368 | { | |
2369 | unsigned int regno; | |
2370 | ||
9af5ce0c | 2371 | if (!REG_P (x)) |
136305f4 | 2372 | return false; |
2373 | ||
2374 | regno = REGNO (x); | |
2375 | /* Allow hard registers if the new mode is legal, and occupies no more | |
2376 | registers than the old mode. */ | |
2377 | if (regno < FIRST_PSEUDO_REGISTER) | |
2378 | return (HARD_REGNO_MODE_OK (regno, mode) | |
2379 | && (hard_regno_nregs[regno][GET_MODE (x)] | |
2380 | >= hard_regno_nregs[regno][mode])); | |
2381 | ||
2382 | /* Or a pseudo that is only used once. */ | |
2383 | return (REG_N_SETS (regno) == 1 && !added_sets | |
2384 | && !REG_USERVAR_P (x)); | |
2385 | } | |
2386 | ||
996daf00 | 2387 | |
2388 | /* Check whether X, the destination of a set, refers to part of | |
2389 | the register specified by REG. */ | |
2390 | ||
2391 | static bool | |
2392 | reg_subword_p (rtx x, rtx reg) | |
2393 | { | |
2394 | /* Check that reg is an integer mode register. */ | |
2395 | if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) | |
2396 | return false; | |
2397 | ||
2398 | if (GET_CODE (x) == STRICT_LOW_PART | |
2399 | || GET_CODE (x) == ZERO_EXTRACT) | |
2400 | x = XEXP (x, 0); | |
2401 | ||
2402 | return GET_CODE (x) == SUBREG | |
2403 | && SUBREG_REG (x) == reg | |
2404 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT; | |
2405 | } | |
2406 | ||
2f6eedc2 | 2407 | /* Delete the unconditional jump INSN and adjust the CFG correspondingly. |
ee4d588d | 2408 | Note that the INSN should be deleted *after* removing dead edges, so |
2409 | that the kept edge is the fallthrough edge for a (set (pc) (pc)) | |
2410 | but not for a (set (pc) (label_ref FOO)). */ | |
2411 | ||
2412 | static void | |
35330d19 | 2413 | update_cfg_for_uncondjump (rtx_insn *insn) |
ee4d588d | 2414 | { |
2415 | basic_block bb = BLOCK_FOR_INSN (insn); | |
41b4f8f9 | 2416 | gcc_assert (BB_END (bb) == insn); |
ee4d588d | 2417 | |
41b4f8f9 | 2418 | purge_dead_edges (bb); |
ee4d588d | 2419 | |
2420 | delete_insn (insn); | |
41b4f8f9 | 2421 | if (EDGE_COUNT (bb->succs) == 1) |
fc2596c8 | 2422 | { |
35330d19 | 2423 | rtx_insn *insn; |
fc2596c8 | 2424 | |
2425 | single_succ_edge (bb)->flags |= EDGE_FALLTHRU; | |
2426 | ||
2427 | /* Remove barriers from the footer if there are any. */ | |
43e94e51 | 2428 | for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn)) |
fc2596c8 | 2429 | if (BARRIER_P (insn)) |
2430 | { | |
2431 | if (PREV_INSN (insn)) | |
4a57a2e8 | 2432 | SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); |
fc2596c8 | 2433 | else |
943ea6fa | 2434 | BB_FOOTER (bb) = NEXT_INSN (insn); |
fc2596c8 | 2435 | if (NEXT_INSN (insn)) |
4a57a2e8 | 2436 | SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); |
fc2596c8 | 2437 | } |
2438 | else if (LABEL_P (insn)) | |
2439 | break; | |
2440 | } | |
ee4d588d | 2441 | } |
2442 | ||
6342422c | 2443 | /* Try to combine the insns I0, I1 and I2 into I3. |
2444 | Here I0, I1 and I2 appear earlier than I3. | |
2445 | I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into | |
2446 | I3. | |
ee4d588d | 2447 | |
6342422c | 2448 | If we are combining more than two insns and the resulting insn is not |
2449 | recognized, try splitting it into two insns. If that happens, I2 and I3 | |
2450 | are retained and I1/I0 are pseudo-deleted by turning them into a NOTE. | |
2451 | Otherwise, I0, I1 and I2 are pseudo-deleted. | |
ccfa01f5 | 2452 | |
510f7125 | 2453 | Return 0 if the combination does not work. Then nothing is changed. |
862e4898 | 2454 | If we did the combination, return the insn at which combine should |
510f7125 | 2455 | resume scanning. |
2456 | ||
d10cfa8d | 2457 | Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a |
0444b5eb | 2458 | new direct jump instruction. |
2459 | ||
2460 | LAST_COMBINED_INSN is either I3, or some insn after I3 that has | |
2461 | been I3 passed to an earlier try_combine within the same basic | |
2462 | block. */ | |
ccfa01f5 | 2463 | |
35330d19 | 2464 | static rtx_insn * |
2465 | try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, | |
2466 | int *new_direct_jump_p, rtx_insn *last_combined_insn) | |
ccfa01f5 | 2467 | { |
d824a5ec | 2468 | /* New patterns for I3 and I2, respectively. */ |
ccfa01f5 | 2469 | rtx newpat, newi2pat = 0; |
b239eadc | 2470 | rtvec newpat_vec_with_clobbers = 0; |
6342422c | 2471 | int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0; |
2472 | /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not | |
2473 | dead. */ | |
2474 | int added_sets_0, added_sets_1, added_sets_2; | |
ccfa01f5 | 2475 | /* Total number of SETs to put into I3. */ |
2476 | int total_sets; | |
6342422c | 2477 | /* Nonzero if I2's or I1's body now appears in I3. */ |
b7d5b445 | 2478 | int i2_is_used = 0, i1_is_used = 0; |
ccfa01f5 | 2479 | /* INSN_CODEs for new I3, new I2, and user of condition code. */ |
df9f2bb6 | 2480 | int insn_code_number, i2_code_number = 0, other_code_number = 0; |
ccfa01f5 | 2481 | /* Contains I3 if the destination of I3 is used in its source, which means |
2482 | that the old life of I3 is being killed. If that usage is placed into | |
2483 | I2 and not in I3, a REG_DEAD note must be made. */ | |
2484 | rtx i3dest_killed = 0; | |
6342422c | 2485 | /* SET_DEST and SET_SRC of I2, I1 and I0. */ |
2486 | rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0; | |
ec458c01 | 2487 | /* Copy of SET_SRC of I1 and I0, if needed. */ |
2488 | rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0; | |
9845d120 | 2489 | /* Set if I2DEST was reused as a scratch register. */ |
2490 | bool i2scratch = false; | |
6342422c | 2491 | /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */ |
2492 | rtx i0pat = 0, i1pat = 0, i2pat = 0; | |
ccfa01f5 | 2493 | /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ |
a66086da | 2494 | int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; |
6342422c | 2495 | int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0; |
2496 | int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0; | |
2497 | int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0; | |
ccfa01f5 | 2498 | /* Notes that must be added to REG_NOTES in I3 and I2. */ |
2499 | rtx new_i3_notes, new_i2_notes; | |
4ac0b86b | 2500 | /* Notes that we substituted I3 into I2 instead of the normal case. */ |
2501 | int i3_subst_into_i2 = 0; | |
7aedce90 | 2502 | /* Notes that I1, I2 or I3 is a MULT operation. */ |
2503 | int have_mult = 0; | |
a1159f52 | 2504 | int swap_i2i3 = 0; |
095050fc | 2505 | int changed_i3_dest = 0; |
ccfa01f5 | 2506 | |
2507 | int maxreg; | |
35330d19 | 2508 | rtx_insn *temp_insn; |
2509 | rtx temp_expr; | |
2a0877d8 | 2510 | struct insn_link *link; |
06a8a63d | 2511 | rtx other_pat = 0; |
2512 | rtx new_other_notes; | |
ccfa01f5 | 2513 | int i; |
2514 | ||
6342422c | 2515 | /* Only try four-insn combinations when there's high likelihood of |
b7d5b445 | 2516 | success. Look for simple insns, such as loads of constants or |
2517 | binary operations involving a constant. */ | |
6342422c | 2518 | if (i0) |
2519 | { | |
2520 | int i; | |
2521 | int ngood = 0; | |
2522 | int nshift = 0; | |
2523 | ||
2524 | if (!flag_expensive_optimizations) | |
2525 | return 0; | |
2526 | ||
2527 | for (i = 0; i < 4; i++) | |
2528 | { | |
35330d19 | 2529 | rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3; |
6342422c | 2530 | rtx set = single_set (insn); |
2531 | rtx src; | |
2532 | if (!set) | |
2533 | continue; | |
2534 | src = SET_SRC (set); | |
2535 | if (CONSTANT_P (src)) | |
2536 | { | |
2537 | ngood += 2; | |
2538 | break; | |
2539 | } | |
2540 | else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1))) | |
2541 | ngood++; | |
2542 | else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT | |
2543 | || GET_CODE (src) == LSHIFTRT) | |
2544 | nshift++; | |
2545 | } | |
2546 | if (ngood < 2 && nshift < 2) | |
2547 | return 0; | |
2548 | } | |
2549 | ||
e185d186 | 2550 | /* Exit early if one of the insns involved can't be used for |
2551 | combinations. */ | |
2552 | if (cant_combine_insn_p (i3) | |
2553 | || cant_combine_insn_p (i2) | |
2554 | || (i1 && cant_combine_insn_p (i1)) | |
6342422c | 2555 | || (i0 && cant_combine_insn_p (i0)) |
1e5b92fa | 2556 | || likely_spilled_retval_p (i3)) |
ccfa01f5 | 2557 | return 0; |
2558 | ||
2559 | combine_attempts++; | |
ccfa01f5 | 2560 | undobuf.other_insn = 0; |
2561 | ||
cee293e3 | 2562 | /* Reset the hard register usage information. */ |
2563 | CLEAR_HARD_REG_SET (newpat_used_regs); | |
2564 | ||
731d1ca3 | 2565 | if (dump_file && (dump_flags & TDF_DETAILS)) |
2566 | { | |
6342422c | 2567 | if (i0) |
2568 | fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n", | |
2569 | INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); | |
2570 | else if (i1) | |
731d1ca3 | 2571 | fprintf (dump_file, "\nTrying %d, %d -> %d:\n", |
2572 | INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); | |
2573 | else | |
2574 | fprintf (dump_file, "\nTrying %d -> %d:\n", | |
2575 | INSN_UID (i2), INSN_UID (i3)); | |
2576 | } | |
2577 | ||
6342422c | 2578 | /* If multiple insns feed into one of I2 or I3, they can be in any |
2579 | order. To simplify the code below, reorder them in sequence. */ | |
2580 | if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2)) | |
35330d19 | 2581 | temp_insn = i2, i2 = i0, i0 = temp_insn; |
6342422c | 2582 | if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1)) |
35330d19 | 2583 | temp_insn = i1, i1 = i0, i0 = temp_insn; |
3072d30e | 2584 | if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2)) |
35330d19 | 2585 | temp_insn = i1, i1 = i2, i2 = temp_insn; |
ccfa01f5 | 2586 | |
862e4898 | 2587 | added_links_insn = 0; |
5a4e4768 | 2588 | |
13e14094 | 2589 | /* First check for one important special case that the code below will |
719d6726 | 2590 | not handle. Namely, the case where I1 is zero, I2 is a PARALLEL |
ccfa01f5 | 2591 | and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, |
2592 | we may be able to replace that destination with the destination of I3. | |
2593 | This occurs in the common code where we compute both a quotient and | |
2594 | remainder into a structure, in which case we want to do the computation | |
2595 | directly into the structure to avoid register-register copies. | |
2596 | ||
13e14094 | 2597 | Note that this case handles both multiple sets in I2 and also cases |
2598 | where I2 has a number of CLOBBERs inside the PARALLEL. | |
719d6726 | 2599 | |
ccfa01f5 | 2600 | We make very conservative checks below and only try to handle the |
2601 | most common cases of this. For example, we only handle the case | |
2602 | where I2 and I3 are adjacent to avoid making difficult register | |
2603 | usage tests. */ | |
2604 | ||
6d7dc5b9 | 2605 | if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET |
8ad4c111 | 2606 | && REG_P (SET_SRC (PATTERN (i3))) |
ccfa01f5 | 2607 | && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER |
ccfa01f5 | 2608 | && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) |
2609 | && GET_CODE (PATTERN (i2)) == PARALLEL | |
2610 | && ! side_effects_p (SET_DEST (PATTERN (i3))) | |
88355298 | 2611 | /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code |
2612 | below would need to check what is inside (and reg_overlap_mentioned_p | |
2613 | doesn't support those codes anyway). Don't allow those destinations; | |
2614 | the resulting insn isn't likely to be recognized anyway. */ | |
2615 | && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT | |
2616 | && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART | |
ccfa01f5 | 2617 | && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), |
2618 | SET_DEST (PATTERN (i3))) | |
9845d120 | 2619 | && next_active_insn (i2) == i3) |
88355298 | 2620 | { |
2621 | rtx p2 = PATTERN (i2); | |
2622 | ||
2623 | /* Make sure that the destination of I3, | |
2624 | which we are going to substitute into one output of I2, | |
2625 | is not used within another output of I2. We must avoid making this: | |
2626 | (parallel [(set (mem (reg 69)) ...) | |
2627 | (set (reg 69) ...)]) | |
2628 | which is not well-defined as to order of actions. | |
2629 | (Besides, reload can't handle output reloads for this.) | |
2630 | ||
2631 | The problem can also happen if the dest of I3 is a memory ref, | |
2632 | if another dest in I2 is an indirect memory ref. */ | |
2633 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
48aa0bc8 | 2634 | if ((GET_CODE (XVECEXP (p2, 0, i)) == SET |
2635 | || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
88355298 | 2636 | && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), |
2637 | SET_DEST (XVECEXP (p2, 0, i)))) | |
2638 | break; | |
ccfa01f5 | 2639 | |
88355298 | 2640 | if (i == XVECLEN (p2, 0)) |
2641 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
13e14094 | 2642 | if (GET_CODE (XVECEXP (p2, 0, i)) == SET |
287e48a0 | 2643 | && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) |
88355298 | 2644 | { |
2645 | combine_merges++; | |
ccfa01f5 | 2646 | |
88355298 | 2647 | subst_insn = i3; |
3072d30e | 2648 | subst_low_luid = DF_INSN_LUID (i2); |
ccfa01f5 | 2649 | |
6342422c | 2650 | added_sets_2 = added_sets_1 = added_sets_0 = 0; |
13e14094 | 2651 | i2src = SET_SRC (XVECEXP (p2, 0, i)); |
2652 | i2dest = SET_DEST (XVECEXP (p2, 0, i)); | |
40a8fb89 | 2653 | i2dest_killed = dead_or_set_p (i2, i2dest); |
ccfa01f5 | 2654 | |
88355298 | 2655 | /* Replace the dest in I2 with our dest and make the resulting |
13e14094 | 2656 | insn the new pattern for I3. Then skip to where we validate |
2657 | the pattern. Everything was set up above. */ | |
2658 | SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3))); | |
88355298 | 2659 | newpat = p2; |
4ac0b86b | 2660 | i3_subst_into_i2 = 1; |
88355298 | 2661 | goto validate_replacement; |
2662 | } | |
2663 | } | |
ccfa01f5 | 2664 | |
996daf00 | 2665 | /* If I2 is setting a pseudo to a constant and I3 is setting some |
2666 | sub-part of it to another constant, merge them by making a new | |
6937799d | 2667 | constant. */ |
2668 | if (i1 == 0 | |
35330d19 | 2669 | && (temp_expr = single_set (i2)) != 0 |
2670 | && CONST_SCALAR_INT_P (SET_SRC (temp_expr)) | |
6937799d | 2671 | && GET_CODE (PATTERN (i3)) == SET |
efa08fc2 | 2672 | && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3))) |
35330d19 | 2673 | && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr))) |
6937799d | 2674 | { |
996daf00 | 2675 | rtx dest = SET_DEST (PATTERN (i3)); |
2676 | int offset = -1; | |
2677 | int width = 0; | |
efa08fc2 | 2678 | |
e20e49db | 2679 | if (GET_CODE (dest) == ZERO_EXTRACT) |
dea958cb | 2680 | { |
971ba038 | 2681 | if (CONST_INT_P (XEXP (dest, 1)) |
2682 | && CONST_INT_P (XEXP (dest, 2))) | |
996daf00 | 2683 | { |
2684 | width = INTVAL (XEXP (dest, 1)); | |
2685 | offset = INTVAL (XEXP (dest, 2)); | |
e20e49db | 2686 | dest = XEXP (dest, 0); |
996daf00 | 2687 | if (BITS_BIG_ENDIAN) |
ded805e6 | 2688 | offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset; |
996daf00 | 2689 | } |
dea958cb | 2690 | } |
e20e49db | 2691 | else |
dea958cb | 2692 | { |
e20e49db | 2693 | if (GET_CODE (dest) == STRICT_LOW_PART) |
2694 | dest = XEXP (dest, 0); | |
ded805e6 | 2695 | width = GET_MODE_PRECISION (GET_MODE (dest)); |
996daf00 | 2696 | offset = 0; |
2697 | } | |
e20e49db | 2698 | |
2699 | if (offset >= 0) | |
996daf00 | 2700 | { |
e20e49db | 2701 | /* If this is the low part, we're done. */ |
2702 | if (subreg_lowpart_p (dest)) | |
2703 | ; | |
2704 | /* Handle the case where inner is twice the size of outer. */ | |
35330d19 | 2705 | else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr))) |
ded805e6 | 2706 | == 2 * GET_MODE_PRECISION (GET_MODE (dest))) |
2707 | offset += GET_MODE_PRECISION (GET_MODE (dest)); | |
e20e49db | 2708 | /* Otherwise give up for now. */ |
2709 | else | |
2710 | offset = -1; | |
996daf00 | 2711 | } |
2712 | ||
e913b5cd | 2713 | if (offset >= 0) |
996daf00 | 2714 | { |
996daf00 | 2715 | rtx inner = SET_SRC (PATTERN (i3)); |
35330d19 | 2716 | rtx outer = SET_SRC (temp_expr); |
796b6678 | 2717 | |
ab2c1de8 | 2718 | wide_int o |
35330d19 | 2719 | = wi::insert (std::make_pair (outer, GET_MODE (SET_DEST (temp_expr))), |
796b6678 | 2720 | std::make_pair (inner, GET_MODE (dest)), |
2721 | offset, width); | |
2722 | ||
996daf00 | 2723 | combine_merges++; |
2724 | subst_insn = i3; | |
3072d30e | 2725 | subst_low_luid = DF_INSN_LUID (i2); |
6342422c | 2726 | added_sets_2 = added_sets_1 = added_sets_0 = 0; |
35330d19 | 2727 | i2dest = SET_DEST (temp_expr); |
996daf00 | 2728 | i2dest_killed = dead_or_set_p (i2, i2dest); |
2729 | ||
92c624a3 | 2730 | /* Replace the source in I2 with the new constant and make the |
2731 | resulting insn the new pattern for I3. Then skip to where we | |
2732 | validate the pattern. Everything was set up above. */ | |
35330d19 | 2733 | SUBST (SET_SRC (temp_expr), |
2734 | immed_wide_int_const (o, GET_MODE (SET_DEST (temp_expr)))); | |
996daf00 | 2735 | |
2736 | newpat = PATTERN (i2); | |
92c624a3 | 2737 | |
2738 | /* The dest of I3 has been replaced with the dest of I2. */ | |
2739 | changed_i3_dest = 1; | |
996daf00 | 2740 | goto validate_replacement; |
dea958cb | 2741 | } |
6937799d | 2742 | } |
2743 | ||
ccfa01f5 | 2744 | #ifndef HAVE_cc0 |
2745 | /* If we have no I1 and I2 looks like: | |
2746 | (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) | |
2747 | (set Y OP)]) | |
2748 | make up a dummy I1 that is | |
2749 | (set Y OP) | |
2750 | and change I2 to be | |
a0c938f0 | 2751 | (set (reg:CC X) (compare:CC Y (const_int 0))) |
ccfa01f5 | 2752 | |
2753 | (We can ignore any trailing CLOBBERs.) | |
2754 | ||
2755 | This undoes a previous combination and allows us to match a branch-and- | |
2756 | decrement insn. */ | |
2757 | ||
2758 | if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL | |
2759 | && XVECLEN (PATTERN (i2), 0) >= 2 | |
2760 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET | |
2761 | && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) | |
2762 | == MODE_CC) | |
2763 | && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE | |
2764 | && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx | |
2765 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET | |
8ad4c111 | 2766 | && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) |
ccfa01f5 | 2767 | && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), |
2768 | SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) | |
2769 | { | |
510f7125 | 2770 | for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) |
ccfa01f5 | 2771 | if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) |
2772 | break; | |
2773 | ||
2774 | if (i == 1) | |
2775 | { | |
2776 | /* We make I1 with the same INSN_UID as I2. This gives it | |
3072d30e | 2777 | the same DF_INSN_LUID for value tracking. Our fake I1 will |
ccfa01f5 | 2778 | never appear in the insn stream so giving it the same INSN_UID |
2779 | as I2 will not cause a problem. */ | |
2780 | ||
f935868a | 2781 | i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2), |
2782 | XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2), | |
2783 | -1, NULL_RTX); | |
5cda2bd0 | 2784 | INSN_UID (i1) = INSN_UID (i2); |
ccfa01f5 | 2785 | |
2786 | SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); | |
2787 | SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), | |
2788 | SET_DEST (PATTERN (i1))); | |
eed2904a | 2789 | SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2))); |
ccfa01f5 | 2790 | } |
2791 | } | |
2792 | #endif | |
2793 | ||
2794 | /* Verify that I2 and I1 are valid for combining. */ | |
35330d19 | 2795 | if (! can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src) |
2796 | || (i1 && ! can_combine_p (i1, i3, i0, NULL, i2, NULL, | |
6342422c | 2797 | &i1dest, &i1src)) |
35330d19 | 2798 | || (i0 && ! can_combine_p (i0, i3, NULL, NULL, i1, i2, |
6342422c | 2799 | &i0dest, &i0src))) |
ccfa01f5 | 2800 | { |
2801 | undo_all (); | |
2802 | return 0; | |
2803 | } | |
2804 | ||
2805 | /* Record whether I2DEST is used in I2SRC and similarly for the other | |
2806 | cases. Knowing this will help in register status updating below. */ | |
2807 | i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); | |
2808 | i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); | |
2809 | i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); | |
6342422c | 2810 | i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src); |
2811 | i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src); | |
2812 | i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src); | |
40a8fb89 | 2813 | i2dest_killed = dead_or_set_p (i2, i2dest); |
2814 | i1dest_killed = i1 && dead_or_set_p (i1, i1dest); | |
6342422c | 2815 | i0dest_killed = i0 && dead_or_set_p (i0, i0dest); |
ccfa01f5 | 2816 | |
6342422c | 2817 | /* For the earlier insns, determine which of the subsequent ones they |
2818 | feed. */ | |
2819 | i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2); | |
2820 | i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1); | |
2821 | i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2) | |
24621f7a | 2822 | : (!reg_overlap_mentioned_p (i1dest, i0dest) |
6342422c | 2823 | && reg_overlap_mentioned_p (i0dest, i2src)))); |
ccfa01f5 | 2824 | |
2825 | /* Ensure that I3's pattern can be the destination of combines. */ | |
6342422c | 2826 | if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest, |
2827 | i1 && i2dest_in_i1src && !i1_feeds_i2_n, | |
2828 | i0 && ((i2dest_in_i0src && !i0_feeds_i2_n) | |
2829 | || (i1dest_in_i0src && !i0_feeds_i1_n)), | |
ccfa01f5 | 2830 | &i3dest_killed)) |
2831 | { | |
2832 | undo_all (); | |
2833 | return 0; | |
2834 | } | |
2835 | ||
7aedce90 | 2836 | /* See if any of the insns is a MULT operation. Unless one is, we will |
2837 | reject a combination that is, since it must be slower. Be conservative | |
2838 | here. */ | |
2839 | if (GET_CODE (i2src) == MULT | |
2840 | || (i1 != 0 && GET_CODE (i1src) == MULT) | |
6342422c | 2841 | || (i0 != 0 && GET_CODE (i0src) == MULT) |
7aedce90 | 2842 | || (GET_CODE (PATTERN (i3)) == SET |
2843 | && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) | |
2844 | have_mult = 1; | |
2845 | ||
ccfa01f5 | 2846 | /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. |
2847 | We used to do this EXCEPT in one case: I3 has a post-inc in an | |
2848 | output operand. However, that exception can give rise to insns like | |
87e97de6 | 2849 | mov r3,(r3)+ |
ccfa01f5 | 2850 | which is a famous insn on the PDP-11 where the value of r3 used as the |
88355298 | 2851 | source was model-dependent. Avoid this sort of thing. */ |
ccfa01f5 | 2852 | |
2853 | #if 0 | |
2854 | if (!(GET_CODE (PATTERN (i3)) == SET | |
8ad4c111 | 2855 | && REG_P (SET_SRC (PATTERN (i3))) |
e16ceb8e | 2856 | && MEM_P (SET_DEST (PATTERN (i3))) |
ccfa01f5 | 2857 | && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC |
2858 | || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) | |
2859 | /* It's not the exception. */ | |
2860 | #endif | |
2861 | #ifdef AUTO_INC_DEC | |
2415b8ff | 2862 | { |
2863 | rtx link; | |
2864 | for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) | |
2865 | if (REG_NOTE_KIND (link) == REG_INC | |
2866 | && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) | |
2867 | || (i1 != 0 | |
2868 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) | |
2869 | { | |
2870 | undo_all (); | |
2871 | return 0; | |
2872 | } | |
2873 | } | |
ccfa01f5 | 2874 | #endif |
2875 | ||
2876 | /* See if the SETs in I1 or I2 need to be kept around in the merged | |
2877 | instruction: whenever the value set there is still needed past I3. | |
32cf0798 | 2878 | For the SET in I2, this is easy: we see if I2DEST dies or is set in I3. |
ccfa01f5 | 2879 | |
32cf0798 | 2880 | For the SET in I1, we have two cases: if I1 and I2 independently feed |
2881 | into I3, the set in I1 needs to be kept around unless I1DEST dies | |
ccfa01f5 | 2882 | or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set |
2883 | in I1 needs to be kept around unless I1DEST dies or is set in either | |
32cf0798 | 2884 | I2 or I3. The same considerations apply to I0. */ |
6342422c | 2885 | |
2886 | added_sets_2 = !dead_or_set_p (i3, i2dest); | |
ccfa01f5 | 2887 | |
6342422c | 2888 | if (i1) |
2889 | added_sets_1 = !(dead_or_set_p (i3, i1dest) | |
2890 | || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest))); | |
2891 | else | |
2892 | added_sets_1 = 0; | |
ccfa01f5 | 2893 | |
6342422c | 2894 | if (i0) |
2895 | added_sets_0 = !(dead_or_set_p (i3, i0dest) | |
32cf0798 | 2896 | || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)) |
2897 | || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) | |
2898 | && dead_or_set_p (i2, i0dest))); | |
6342422c | 2899 | else |
2900 | added_sets_0 = 0; | |
ccfa01f5 | 2901 | |
f5c18c04 | 2902 | /* We are about to copy insns for the case where they need to be kept |
2903 | around. Check that they can be copied in the merged instruction. */ | |
2904 | ||
2905 | if (targetm.cannot_copy_insn_p | |
2906 | && ((added_sets_2 && targetm.cannot_copy_insn_p (i2)) | |
2907 | || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1)) | |
2908 | || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0)))) | |
2909 | { | |
2910 | undo_all (); | |
2911 | return 0; | |
2912 | } | |
2913 | ||
ccfa01f5 | 2914 | /* If the set in I2 needs to be kept around, we must make a copy of |
2915 | PATTERN (I2), so that when we substitute I1SRC for I1DEST in | |
88355298 | 2916 | PATTERN (I2), we are only substituting for the original I1DEST, not into |
ccfa01f5 | 2917 | an already-substituted copy. This also prevents making self-referential |
2918 | rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to | |
2919 | I2DEST. */ | |
2920 | ||
ccfa01f5 | 2921 | if (added_sets_2) |
b6896428 | 2922 | { |
2923 | if (GET_CODE (PATTERN (i2)) == PARALLEL) | |
2924 | i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src)); | |
2925 | else | |
2926 | i2pat = copy_rtx (PATTERN (i2)); | |
2927 | } | |
2928 | ||
2929 | if (added_sets_1) | |
2930 | { | |
2931 | if (GET_CODE (PATTERN (i1)) == PARALLEL) | |
2932 | i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src)); | |
2933 | else | |
2934 | i1pat = copy_rtx (PATTERN (i1)); | |
2935 | } | |
ccfa01f5 | 2936 | |
6342422c | 2937 | if (added_sets_0) |
2938 | { | |
2939 | if (GET_CODE (PATTERN (i0)) == PARALLEL) | |
2940 | i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src)); | |
2941 | else | |
2942 | i0pat = copy_rtx (PATTERN (i0)); | |
2943 | } | |
2944 | ||
ccfa01f5 | 2945 | combine_merges++; |
2946 | ||
2947 | /* Substitute in the latest insn for the regs set by the earlier ones. */ | |
2948 | ||
2949 | maxreg = max_reg_num (); | |
2950 | ||
2951 | subst_insn = i3; | |
ccfa01f5 | 2952 | |
ccfa01f5 | 2953 | #ifndef HAVE_cc0 |
2954 | /* Many machines that don't use CC0 have insns that can both perform an | |
2955 | arithmetic operation and set the condition code. These operations will | |
2956 | be represented as a PARALLEL with the first element of the vector | |
2957 | being a COMPARE of an arithmetic operation with the constant zero. | |
2958 | The second element of the vector will set some pseudo to the result | |
2959 | of the same arithmetic operation. If we simplify the COMPARE, we won't | |
2960 | match such a pattern and so will generate an extra insn. Here we test | |
2961 | for this case, where both the comparison and the operation result are | |
2962 | needed, and make the PARALLEL by just replacing I2DEST in I3SRC with | |
2963 | I2SRC. Later we will make the PARALLEL that contains I2. */ | |
2964 | ||
2965 | if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET | |
2966 | && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE | |
9a86832e | 2967 | && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1)) |
ccfa01f5 | 2968 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) |
2969 | { | |
9a86832e | 2970 | rtx newpat_dest; |
35330d19 | 2971 | rtx *cc_use_loc = NULL; |
2972 | rtx_insn *cc_use_insn = NULL; | |
9a86832e | 2973 | rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1); |
2974 | enum machine_mode compare_mode, orig_compare_mode; | |
2975 | enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN; | |
ccfa01f5 | 2976 | |
2977 | newpat = PATTERN (i3); | |
9a86832e | 2978 | newpat_dest = SET_DEST (newpat); |
2979 | compare_mode = orig_compare_mode = GET_MODE (newpat_dest); | |
ccfa01f5 | 2980 | |
ccfa01f5 | 2981 | if (undobuf.other_insn == 0 |
9a86832e | 2982 | && (cc_use_loc = find_single_use (SET_DEST (newpat), i3, |
2983 | &cc_use_insn))) | |
2984 | { | |
2985 | compare_code = orig_compare_code = GET_CODE (*cc_use_loc); | |
2986 | compare_code = simplify_compare_const (compare_code, | |
9ec27261 | 2987 | GET_MODE (i2dest), op0, &op1); |
d5065e6e | 2988 | target_canonicalize_comparison (&compare_code, &op0, &op1, 1); |
9a86832e | 2989 | } |
136305f4 | 2990 | |
9a86832e | 2991 | /* Do the rest only if op1 is const0_rtx, which may be the |
2992 | result of simplification. */ | |
2993 | if (op1 == const0_rtx) | |
2994 | { | |
2995 | /* If a single use of the CC is found, prepare to modify it | |
2996 | when SELECT_CC_MODE returns a new CC-class mode, or when | |
2997 | the above simplify_compare_const() returned a new comparison | |
2998 | operator. undobuf.other_insn is assigned the CC use insn | |
2999 | when modifying it. */ | |
3000 | if (cc_use_loc) | |
3001 | { | |
3002 | #ifdef SELECT_CC_MODE | |
3003 | enum machine_mode new_mode | |
3004 | = SELECT_CC_MODE (compare_code, op0, op1); | |
3005 | if (new_mode != orig_compare_mode | |
3006 | && can_change_dest_mode (SET_DEST (newpat), | |
3007 | added_sets_2, new_mode)) | |
df738c1f | 3008 | { |
9a86832e | 3009 | unsigned int regno = REGNO (newpat_dest); |
3010 | compare_mode = new_mode; | |
3011 | if (regno < FIRST_PSEUDO_REGISTER) | |
3012 | newpat_dest = gen_rtx_REG (compare_mode, regno); | |
3013 | else | |
3014 | { | |
3015 | SUBST_MODE (regno_reg_rtx[regno], compare_mode); | |
3016 | newpat_dest = regno_reg_rtx[regno]; | |
3017 | } | |
df738c1f | 3018 | } |
9a86832e | 3019 | #endif |
3020 | /* Cases for modifying the CC-using comparison. */ | |
3021 | if (compare_code != orig_compare_code | |
3022 | /* ??? Do we need to verify the zero rtx? */ | |
3023 | && XEXP (*cc_use_loc, 1) == const0_rtx) | |
3024 | { | |
3025 | /* Replace cc_use_loc with entire new RTX. */ | |
3026 | SUBST (*cc_use_loc, | |
3027 | gen_rtx_fmt_ee (compare_code, compare_mode, | |
3028 | newpat_dest, const0_rtx)); | |
3029 | undobuf.other_insn = cc_use_insn; | |
3030 | } | |
3031 | else if (compare_mode != orig_compare_mode) | |
3032 | { | |
3033 | /* Just replace the CC reg with a new mode. */ | |
3034 | SUBST (XEXP (*cc_use_loc, 0), newpat_dest); | |
3035 | undobuf.other_insn = cc_use_insn; | |
3036 | } | |
ccfa01f5 | 3037 | } |
9a86832e | 3038 | |
3039 | /* Now we modify the current newpat: | |
3040 | First, SET_DEST(newpat) is updated if the CC mode has been | |
3041 | altered. For targets without SELECT_CC_MODE, this should be | |
3042 | optimized away. */ | |
3043 | if (compare_mode != orig_compare_mode) | |
3044 | SUBST (SET_DEST (newpat), newpat_dest); | |
3045 | /* This is always done to propagate i2src into newpat. */ | |
3046 | SUBST (SET_SRC (newpat), | |
3047 | gen_rtx_COMPARE (compare_mode, op0, op1)); | |
3048 | /* Create new version of i2pat if needed; the below PARALLEL | |
3049 | creation needs this to work correctly. */ | |
3050 | if (! rtx_equal_p (i2src, op0)) | |
3051 | i2pat = gen_rtx_SET (VOIDmode, i2dest, op0); | |
3052 | i2_is_used = 1; | |
ccfa01f5 | 3053 | } |
ccfa01f5 | 3054 | } |
ccfa01f5 | 3055 | #endif |
9a86832e | 3056 | |
3057 | if (i2_is_used == 0) | |
ccfa01f5 | 3058 | { |
5447c6eb | 3059 | /* It is possible that the source of I2 or I1 may be performing |
3060 | an unneeded operation, such as a ZERO_EXTEND of something | |
3061 | that is known to have the high part zero. Handle that case | |
54a61993 | 3062 | by letting subst look at the inner insns. |
5447c6eb | 3063 | |
3064 | Another way to do this would be to have a function that tries | |
3065 | to simplify a single insn instead of merging two or more | |
3066 | insns. We don't do this because of the potential of infinite | |
3067 | loops and because of the potential extra memory required. | |
3068 | However, doing it the way we are is a bit of a kludge and | |
3069 | doesn't catch all cases. | |
3070 | ||
3071 | But only do this if -fexpensive-optimizations since it slows | |
3072 | things down and doesn't usually win. | |
3073 | ||
3074 | This is not done in the COMPARE case above because the | |
3075 | unmodified I2PAT is used in the PARALLEL and so a pattern | |
3076 | with a modified I2SRC would not match. */ | |
3077 | ||
3078 | if (flag_expensive_optimizations) | |
3079 | { | |
3080 | /* Pass pc_rtx so no substitutions are done, just | |
3081 | simplifications. */ | |
3082 | if (i1) | |
3083 | { | |
3072d30e | 3084 | subst_low_luid = DF_INSN_LUID (i1); |
34dd021c | 3085 | i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); |
5447c6eb | 3086 | } |
54a61993 | 3087 | |
3088 | subst_low_luid = DF_INSN_LUID (i2); | |
34dd021c | 3089 | i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); |
5447c6eb | 3090 | } |
3091 | ||
ccfa01f5 | 3092 | n_occurrences = 0; /* `subst' counts here */ |
3072d30e | 3093 | subst_low_luid = DF_INSN_LUID (i2); |
32f4aea2 | 3094 | |
3095 | /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique | |
3096 | copy of I2SRC each time we substitute it, in order to avoid creating | |
3097 | self-referential RTL when we will be substituting I1SRC for I1DEST | |
d7064052 | 3098 | later. Likewise if I0 feeds into I2, either directly or indirectly |
3099 | through I1, and I0DEST is in I0SRC. */ | |
34dd021c | 3100 | newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0, |
32f4aea2 | 3101 | (i1_feeds_i2_n && i1dest_in_i1src) |
d7064052 | 3102 | || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) |
3103 | && i0dest_in_i0src)); | |
de79a9e1 | 3104 | substed_i2 = 1; |
ccfa01f5 | 3105 | |
32f4aea2 | 3106 | /* Record whether I2's body now appears within I3's body. */ |
ccfa01f5 | 3107 | i2_is_used = n_occurrences; |
3108 | } | |
3109 | ||
32f4aea2 | 3110 | /* If we already got a failure, don't try to do more. Otherwise, try to |
3111 | substitute I1 if we have it. */ | |
ccfa01f5 | 3112 | |
3113 | if (i1 && GET_CODE (newpat) != CLOBBER) | |
3114 | { | |
3888eedd | 3115 | /* Check that an autoincrement side-effect on I1 has not been lost. |
3116 | This happens if I1DEST is mentioned in I2 and dies there, and | |
3117 | has disappeared from the new pattern. */ | |
3118 | if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 | |
6342422c | 3119 | && i1_feeds_i2_n |
3888eedd | 3120 | && dead_or_set_p (i2, i1dest) |
3121 | && !reg_overlap_mentioned_p (i1dest, newpat)) | |
32f4aea2 | 3122 | /* Before we can do this substitution, we must redo the test done |
3123 | above (see detailed comments there) that ensures I1DEST isn't | |
3124 | mentioned in any SETs in NEWPAT that are field assignments. */ | |
35330d19 | 3125 | || !combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX, |
6342422c | 3126 | 0, 0, 0)) |
ccfa01f5 | 3127 | { |
3128 | undo_all (); | |
3129 | return 0; | |
3130 | } | |
3131 | ||
3132 | n_occurrences = 0; | |
3072d30e | 3133 | subst_low_luid = DF_INSN_LUID (i1); |
32f4aea2 | 3134 | |
ec458c01 | 3135 | /* If the following substitution will modify I1SRC, make a copy of it |
3136 | for the case where it is substituted for I1DEST in I2PAT later. */ | |
3137 | if (added_sets_2 && i1_feeds_i2_n) | |
3138 | i1src_copy = copy_rtx (i1src); | |
3139 | ||
32f4aea2 | 3140 | /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique |
3141 | copy of I1SRC each time we substitute it, in order to avoid creating | |
3142 | self-referential RTL when we will be substituting I0SRC for I0DEST | |
3143 | later. */ | |
34dd021c | 3144 | newpat = subst (newpat, i1dest, i1src, 0, 0, |
6342422c | 3145 | i0_feeds_i1_n && i0dest_in_i0src); |
de79a9e1 | 3146 | substed_i1 = 1; |
32f4aea2 | 3147 | |
3148 | /* Record whether I1's body now appears within I3's body. */ | |
6342422c | 3149 | i1_is_used = n_occurrences; |
3150 | } | |
32f4aea2 | 3151 | |
3152 | /* Likewise for I0 if we have it. */ | |
3153 | ||
6342422c | 3154 | if (i0 && GET_CODE (newpat) != CLOBBER) |
3155 | { | |
3156 | if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0 | |
3157 | && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest)) | |
3158 | || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))) | |
3159 | && !reg_overlap_mentioned_p (i0dest, newpat)) | |
35330d19 | 3160 | || !combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX, |
6342422c | 3161 | 0, 0, 0)) |
3162 | { | |
3163 | undo_all (); | |
3164 | return 0; | |
3165 | } | |
3166 | ||
ec458c01 | 3167 | /* If the following substitution will modify I0SRC, make a copy of it |
3168 | for the case where it is substituted for I0DEST in I1PAT later. */ | |
3169 | if (added_sets_1 && i0_feeds_i1_n) | |
3170 | i0src_copy = copy_rtx (i0src); | |
3171 | /* And a copy for I0DEST in I2PAT substitution. */ | |
3172 | if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n) | |
3173 | || (i0_feeds_i2_n))) | |
3174 | i0src_copy2 = copy_rtx (i0src); | |
446c6cb5 | 3175 | |
6342422c | 3176 | n_occurrences = 0; |
a828b39f | 3177 | subst_low_luid = DF_INSN_LUID (i0); |
34dd021c | 3178 | newpat = subst (newpat, i0dest, i0src, 0, 0, 0); |
6342422c | 3179 | substed_i0 = 1; |
ccfa01f5 | 3180 | } |
3181 | ||
a793480c | 3182 | /* Fail if an autoincrement side-effect has been duplicated. Be careful |
3183 | to count all the ways that I2SRC and I1SRC can be used. */ | |
1bb04728 | 3184 | if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 |
a793480c | 3185 | && i2_is_used + added_sets_2 > 1) |
1bb04728 | 3186 | || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 |
6342422c | 3187 | && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) |
3188 | > 1)) | |
3189 | || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0 | |
3190 | && (n_occurrences + added_sets_0 | |
3191 | + (added_sets_1 && i0_feeds_i1_n) | |
3192 | + (added_sets_2 && i0_feeds_i2_n) | |
a793480c | 3193 | > 1)) |
89f18f73 | 3194 | /* Fail if we tried to make a new register. */ |
ccfa01f5 | 3195 | || max_reg_num () != maxreg |
3196 | /* Fail if we couldn't do something and have a CLOBBER. */ | |
7aedce90 | 3197 | || GET_CODE (newpat) == CLOBBER |
3198 | /* Fail if this new pattern is a MULT and we didn't have one before | |
3199 | at the outer level. */ | |
3200 | || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT | |
3201 | && ! have_mult)) | |
ccfa01f5 | 3202 | { |
3203 | undo_all (); | |
3204 | return 0; | |
3205 | } | |
3206 | ||
3207 | /* If the actions of the earlier insns must be kept | |
3208 | in addition to substituting them into the latest one, | |
3209 | we must make a new PARALLEL for the latest insn | |
3210 | to hold additional the SETs. */ | |
3211 | ||
6342422c | 3212 | if (added_sets_0 || added_sets_1 || added_sets_2) |
ccfa01f5 | 3213 | { |
6342422c | 3214 | int extra_sets = added_sets_0 + added_sets_1 + added_sets_2; |
ccfa01f5 | 3215 | combine_extras++; |
3216 | ||
3217 | if (GET_CODE (newpat) == PARALLEL) | |
3218 | { | |
3219 | rtvec old = XVEC (newpat, 0); | |
6342422c | 3220 | total_sets = XVECLEN (newpat, 0) + extra_sets; |
941522d6 | 3221 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); |
03642f48 | 3222 | memcpy (XVEC (newpat, 0)->elem, &old->elem[0], |
3223 | sizeof (old->elem[0]) * old->num_elem); | |
ccfa01f5 | 3224 | } |
3225 | else | |
3226 | { | |
3227 | rtx old = newpat; | |
6342422c | 3228 | total_sets = 1 + extra_sets; |
941522d6 | 3229 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); |
ccfa01f5 | 3230 | XVECEXP (newpat, 0, 0) = old; |
3231 | } | |
3232 | ||
6342422c | 3233 | if (added_sets_0) |
3234 | XVECEXP (newpat, 0, --total_sets) = i0pat; | |
3235 | ||
ea913091 | 3236 | if (added_sets_1) |
6342422c | 3237 | { |
3238 | rtx t = i1pat; | |
3239 | if (i0_feeds_i1_n) | |
ec458c01 | 3240 | t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0); |
ea913091 | 3241 | |
6342422c | 3242 | XVECEXP (newpat, 0, --total_sets) = t; |
3243 | } | |
ea913091 | 3244 | if (added_sets_2) |
3245 | { | |
6342422c | 3246 | rtx t = i2pat; |
6342422c | 3247 | if (i1_feeds_i2_n) |
34dd021c | 3248 | t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0, |
446c6cb5 | 3249 | i0_feeds_i1_n && i0dest_in_i0src); |
3250 | if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n) | |
ec458c01 | 3251 | t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0); |
6342422c | 3252 | |
3253 | XVECEXP (newpat, 0, --total_sets) = t; | |
ea913091 | 3254 | } |
ccfa01f5 | 3255 | } |
3256 | ||
ccfa01f5 | 3257 | validate_replacement: |
3258 | ||
cee293e3 | 3259 | /* Note which hard regs this insn has as inputs. */ |
3260 | mark_used_regs_combine (newpat); | |
3261 | ||
b239eadc | 3262 | /* If recog_for_combine fails, it strips existing clobbers. If we'll |
3263 | consider splitting this pattern, we might need these clobbers. */ | |
3264 | if (i1 && GET_CODE (newpat) == PARALLEL | |
3265 | && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER) | |
3266 | { | |
3267 | int len = XVECLEN (newpat, 0); | |
3268 | ||
3269 | newpat_vec_with_clobbers = rtvec_alloc (len); | |
3270 | for (i = 0; i < len; i++) | |
3271 | RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i); | |
3272 | } | |
3273 | ||
ccfa01f5 | 3274 | /* Is the result of combination a valid instruction? */ |
d9943040 | 3275 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
ccfa01f5 | 3276 | |
3277 | /* If the result isn't valid, see if it is a PARALLEL of two SETs where | |
facad922 | 3278 | the second SET's destination is a register that is unused and isn't |
3279 | marked as an instruction that might trap in an EH region. In that case, | |
ccfa01f5 | 3280 | we just need the first SET. This can occur when simplifying a divmod |
3281 | insn. We *must* test for this case here because the code below that | |
3282 | splits two independent SETs doesn't handle this case correctly when it | |
155184c9 | 3283 | updates the register status. |
ccfa01f5 | 3284 | |
155184c9 | 3285 | It's pointless doing this if we originally had two sets, one from |
3286 | i3, and one from i2. Combining then splitting the parallel results | |
3287 | in the original i2 again plus an invalid insn (which we delete). | |
3288 | The net effect is only to move instructions around, which makes | |
3289 | debug info less accurate. | |
3290 | ||
3291 | Also check the case where the first SET's destination is unused. | |
3292 | That would not cause incorrect code, but does cause an unneeded | |
3293 | insn to remain. */ | |
3294 | ||
3295 | if (insn_code_number < 0 | |
3296 | && !(added_sets_2 && i1 == 0) | |
3297 | && GET_CODE (newpat) == PARALLEL | |
ccfa01f5 | 3298 | && XVECLEN (newpat, 0) == 2 |
3299 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
3300 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
ccfa01f5 | 3301 | && asm_noperands (newpat) < 0) |
3302 | { | |
08eb940c | 3303 | rtx set0 = XVECEXP (newpat, 0, 0); |
3304 | rtx set1 = XVECEXP (newpat, 0, 1); | |
facad922 | 3305 | |
8ad4c111 | 3306 | if (((REG_P (SET_DEST (set1)) |
facad922 | 3307 | && find_reg_note (i3, REG_UNUSED, SET_DEST (set1))) |
3308 | || (GET_CODE (SET_DEST (set1)) == SUBREG | |
3309 | && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))))) | |
e38def9c | 3310 | && insn_nothrow_p (i3) |
3311 | && !side_effects_p (SET_SRC (set1))) | |
facad922 | 3312 | { |
3313 | newpat = set0; | |
3314 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
3315 | } | |
3316 | ||
8ad4c111 | 3317 | else if (((REG_P (SET_DEST (set0)) |
facad922 | 3318 | && find_reg_note (i3, REG_UNUSED, SET_DEST (set0))) |
3319 | || (GET_CODE (SET_DEST (set0)) == SUBREG | |
3320 | && find_reg_note (i3, REG_UNUSED, | |
3321 | SUBREG_REG (SET_DEST (set0))))) | |
e38def9c | 3322 | && insn_nothrow_p (i3) |
3323 | && !side_effects_p (SET_SRC (set0))) | |
facad922 | 3324 | { |
3325 | newpat = set1; | |
3326 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
3327 | ||
3328 | if (insn_code_number >= 0) | |
095050fc | 3329 | changed_i3_dest = 1; |
facad922 | 3330 | } |
ccfa01f5 | 3331 | } |
3332 | ||
3333 | /* If we were combining three insns and the result is a simple SET | |
3334 | with no ASM_OPERANDS that wasn't recognized, try to split it into two | |
510f7125 | 3335 | insns. There are two ways to do this. It can be split using a |
a793480c | 3336 | machine-specific method (like when you have an addition of a large |
3337 | constant) or by combine in the function find_split_point. */ | |
3338 | ||
ccfa01f5 | 3339 | if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET |
3340 | && asm_noperands (newpat) < 0) | |
3341 | { | |
4cd001d5 | 3342 | rtx parallel, *split; |
3343 | rtx_insn *m_split_insn; | |
a793480c | 3344 | |
3345 | /* See if the MD file can split NEWPAT. If it can't, see if letting it | |
c3a052b1 | 3346 | use I2DEST as a scratch register will help. In the latter case, |
3347 | convert I2DEST to the mode of the source of NEWPAT if we can. */ | |
a793480c | 3348 | |
4cd001d5 | 3349 | m_split_insn = combine_split_insns (newpat, i3); |
22e350f4 | 3350 | |
3351 | /* We can only use I2DEST as a scratch reg if it doesn't overlap any | |
3352 | inputs of NEWPAT. */ | |
3353 | ||
3354 | /* ??? If I2DEST is not safe, and I1DEST exists, then it would be | |
3355 | possible to try that as a scratch reg. This would require adding | |
3356 | more code to make it work though. */ | |
3357 | ||
4cd001d5 | 3358 | if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat)) |
c3a052b1 | 3359 | { |
df738c1f | 3360 | enum machine_mode new_mode = GET_MODE (SET_DEST (newpat)); |
7014838c | 3361 | |
df738c1f | 3362 | /* First try to split using the original register as a |
3363 | scratch register. */ | |
7ed1bb71 | 3364 | parallel = gen_rtx_PARALLEL (VOIDmode, |
3365 | gen_rtvec (2, newpat, | |
3366 | gen_rtx_CLOBBER (VOIDmode, | |
3367 | i2dest))); | |
4cd001d5 | 3368 | m_split_insn = combine_split_insns (parallel, i3); |
df738c1f | 3369 | |
3370 | /* If that didn't work, try changing the mode of I2DEST if | |
3371 | we can. */ | |
4cd001d5 | 3372 | if (m_split_insn == 0 |
df738c1f | 3373 | && new_mode != GET_MODE (i2dest) |
3374 | && new_mode != VOIDmode | |
3375 | && can_change_dest_mode (i2dest, added_sets_2, new_mode)) | |
4dd849ed | 3376 | { |
df738c1f | 3377 | enum machine_mode old_mode = GET_MODE (i2dest); |
3378 | rtx ni2dest; | |
3379 | ||
3380 | if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) | |
3381 | ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest)); | |
3382 | else | |
3383 | { | |
3384 | SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode); | |
3385 | ni2dest = regno_reg_rtx[REGNO (i2dest)]; | |
3386 | } | |
3387 | ||
7ed1bb71 | 3388 | parallel = (gen_rtx_PARALLEL |
3389 | (VOIDmode, | |
3390 | gen_rtvec (2, newpat, | |
3391 | gen_rtx_CLOBBER (VOIDmode, | |
3392 | ni2dest)))); | |
4cd001d5 | 3393 | m_split_insn = combine_split_insns (parallel, i3); |
df738c1f | 3394 | |
4cd001d5 | 3395 | if (m_split_insn == 0 |
df738c1f | 3396 | && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) |
3397 | { | |
3398 | struct undo *buf; | |
3399 | ||
80c70e76 | 3400 | adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode); |
df738c1f | 3401 | buf = undobuf.undos; |
3402 | undobuf.undos = buf->next; | |
3403 | buf->next = undobuf.frees; | |
3404 | undobuf.frees = buf; | |
3405 | } | |
4dd849ed | 3406 | } |
9845d120 | 3407 | |
4cd001d5 | 3408 | i2scratch = m_split_insn != 0; |
c3a052b1 | 3409 | } |
a793480c | 3410 | |
b239eadc | 3411 | /* If recog_for_combine has discarded clobbers, try to use them |
3412 | again for the split. */ | |
4cd001d5 | 3413 | if (m_split_insn == 0 && newpat_vec_with_clobbers) |
7ed1bb71 | 3414 | { |
3415 | parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers); | |
4cd001d5 | 3416 | m_split_insn = combine_split_insns (parallel, i3); |
7ed1bb71 | 3417 | } |
b239eadc | 3418 | |
4cd001d5 | 3419 | if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX) |
0cadbc52 | 3420 | { |
4cd001d5 | 3421 | rtx m_split_pat = PATTERN (m_split_insn); |
3422 | insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes); | |
0cadbc52 | 3423 | if (insn_code_number >= 0) |
4cd001d5 | 3424 | newpat = m_split_pat; |
87e97de6 | 3425 | } |
4cd001d5 | 3426 | else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX |
ad971558 | 3427 | && (next_nonnote_nondebug_insn (i2) == i3 |
4cd001d5 | 3428 | || ! use_crosses_set_p (PATTERN (m_split_insn), DF_INSN_LUID (i2)))) |
a793480c | 3429 | { |
1f1c8c5a | 3430 | rtx i2set, i3set; |
4cd001d5 | 3431 | rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn)); |
3432 | newi2pat = PATTERN (m_split_insn); | |
a793480c | 3433 | |
4cd001d5 | 3434 | i3set = single_set (NEXT_INSN (m_split_insn)); |
3435 | i2set = single_set (m_split_insn); | |
1f1c8c5a | 3436 | |
d9943040 | 3437 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
1f1c8c5a | 3438 | |
3439 | /* If I2 or I3 has multiple SETs, we won't know how to track | |
19b3494b | 3440 | register status, so don't use these insns. If I2's destination |
3441 | is used between I2 and I3, we also can't use these insns. */ | |
1f1c8c5a | 3442 | |
19b3494b | 3443 | if (i2_code_number >= 0 && i2set && i3set |
ad971558 | 3444 | && (next_nonnote_nondebug_insn (i2) == i3 |
19b3494b | 3445 | || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) |
d9943040 | 3446 | insn_code_number = recog_for_combine (&newi3pat, i3, |
3447 | &new_i3_notes); | |
ec90760f | 3448 | if (insn_code_number >= 0) |
3449 | newpat = newi3pat; | |
3450 | ||
c301d1fb | 3451 | /* It is possible that both insns now set the destination of I3. |
7270012f | 3452 | If so, we must show an extra use of it. */ |
c301d1fb | 3453 | |
1a679e68 | 3454 | if (insn_code_number >= 0) |
3455 | { | |
3456 | rtx new_i3_dest = SET_DEST (i3set); | |
3457 | rtx new_i2_dest = SET_DEST (i2set); | |
3458 | ||
3459 | while (GET_CODE (new_i3_dest) == ZERO_EXTRACT | |
3460 | || GET_CODE (new_i3_dest) == STRICT_LOW_PART | |
3461 | || GET_CODE (new_i3_dest) == SUBREG) | |
3462 | new_i3_dest = XEXP (new_i3_dest, 0); | |
3463 | ||
301e4ab4 | 3464 | while (GET_CODE (new_i2_dest) == ZERO_EXTRACT |
3465 | || GET_CODE (new_i2_dest) == STRICT_LOW_PART | |
3466 | || GET_CODE (new_i2_dest) == SUBREG) | |
3467 | new_i2_dest = XEXP (new_i2_dest, 0); | |
3468 | ||
8ad4c111 | 3469 | if (REG_P (new_i3_dest) |
3470 | && REG_P (new_i2_dest) | |
1a679e68 | 3471 | && REGNO (new_i3_dest) == REGNO (new_i2_dest)) |
3072d30e | 3472 | INC_REG_N_SETS (REGNO (new_i2_dest), 1); |
1a679e68 | 3473 | } |
a793480c | 3474 | } |
ccfa01f5 | 3475 | |
3476 | /* If we can split it and use I2DEST, go ahead and see if that | |
3477 | helps things be recognized. Verify that none of the registers | |
3478 | are set between I2 and I3. */ | |
b420d71b | 3479 | if (insn_code_number < 0 |
3480 | && (split = find_split_point (&newpat, i3, false)) != 0 | |
ccfa01f5 | 3481 | #ifdef HAVE_cc0 |
8ad4c111 | 3482 | && REG_P (i2dest) |
ccfa01f5 | 3483 | #endif |
3484 | /* We need I2DEST in the proper mode. If it is a hard register | |
6b5f73b1 | 3485 | or the only use of a pseudo, we can change its mode. |
3486 | Make sure we don't change a hard register to have a mode that | |
3487 | isn't valid for it, or change the number of registers. */ | |
ccfa01f5 | 3488 | && (GET_MODE (*split) == GET_MODE (i2dest) |
3489 | || GET_MODE (*split) == VOIDmode | |
136305f4 | 3490 | || can_change_dest_mode (i2dest, added_sets_2, |
3491 | GET_MODE (*split))) | |
ad971558 | 3492 | && (next_nonnote_nondebug_insn (i2) == i3 |
3072d30e | 3493 | || ! use_crosses_set_p (*split, DF_INSN_LUID (i2))) |
ccfa01f5 | 3494 | /* We can't overwrite I2DEST if its value is still used by |
3495 | NEWPAT. */ | |
3496 | && ! reg_referenced_p (i2dest, newpat)) | |
3497 | { | |
3498 | rtx newdest = i2dest; | |
7aedce90 | 3499 | enum rtx_code split_code = GET_CODE (*split); |
3500 | enum machine_mode split_mode = GET_MODE (*split); | |
0335fdcd | 3501 | bool subst_done = false; |
3502 | newi2pat = NULL_RTX; | |
ccfa01f5 | 3503 | |
9845d120 | 3504 | i2scratch = true; |
3505 | ||
42a4b11f | 3506 | /* *SPLIT may be part of I2SRC, so make sure we have the |
3507 | original expression around for later debug processing. | |
3508 | We should not need I2SRC any more in other cases. */ | |
3509 | if (MAY_HAVE_DEBUG_INSNS) | |
3510 | i2src = copy_rtx (i2src); | |
3511 | else | |
3512 | i2src = NULL; | |
3513 | ||
ccfa01f5 | 3514 | /* Get NEWDEST as a register in the proper mode. We have already |
3515 | validated that we can do this. */ | |
7aedce90 | 3516 | if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) |
ccfa01f5 | 3517 | { |
df738c1f | 3518 | if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) |
3519 | newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); | |
3520 | else | |
3521 | { | |
3522 | SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode); | |
3523 | newdest = regno_reg_rtx[REGNO (i2dest)]; | |
3524 | } | |
ccfa01f5 | 3525 | } |
3526 | ||
3527 | /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to | |
3528 | an ASHIFT. This can occur if it was inside a PLUS and hence | |
3529 | appeared to be a memory address. This is a kludge. */ | |
7aedce90 | 3530 | if (split_code == MULT |
971ba038 | 3531 | && CONST_INT_P (XEXP (*split, 1)) |
fd2ce427 | 3532 | && INTVAL (XEXP (*split, 1)) > 0 |
897c6c81 | 3533 | && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0) |
460a73d2 | 3534 | { |
3380b197 | 3535 | SUBST (*split, gen_rtx_ASHIFT (split_mode, |
3536 | XEXP (*split, 0), GEN_INT (i))); | |
460a73d2 | 3537 | /* Update split_code because we may not have a multiply |
3538 | anymore. */ | |
3539 | split_code = GET_CODE (*split); | |
3540 | } | |
ccfa01f5 | 3541 | |
3542 | #ifdef INSN_SCHEDULING | |
3543 | /* If *SPLIT is a paradoxical SUBREG, when we split it, it should | |
3544 | be written as a ZERO_EXTEND. */ | |
e16ceb8e | 3545 | if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) |
b6bf753c | 3546 | { |
3547 | #ifdef LOAD_EXTEND_OP | |
3548 | /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's | |
3549 | what it really is. */ | |
3550 | if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split))) | |
3551 | == SIGN_EXTEND) | |
3552 | SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, | |
3553 | SUBREG_REG (*split))); | |
3554 | else | |
3555 | #endif | |
3556 | SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, | |
3557 | SUBREG_REG (*split))); | |
3558 | } | |
ccfa01f5 | 3559 | #endif |
3560 | ||
0335fdcd | 3561 | /* Attempt to split binary operators using arithmetic identities. */ |
3562 | if (BINARY_P (SET_SRC (newpat)) | |
3563 | && split_mode == GET_MODE (SET_SRC (newpat)) | |
3564 | && ! side_effects_p (SET_SRC (newpat))) | |
3565 | { | |
3566 | rtx setsrc = SET_SRC (newpat); | |
3567 | enum machine_mode mode = GET_MODE (setsrc); | |
3568 | enum rtx_code code = GET_CODE (setsrc); | |
3569 | rtx src_op0 = XEXP (setsrc, 0); | |
3570 | rtx src_op1 = XEXP (setsrc, 1); | |
3571 | ||
3572 | /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */ | |
3573 | if (rtx_equal_p (src_op0, src_op1)) | |
3574 | { | |
3575 | newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0); | |
3576 | SUBST (XEXP (setsrc, 0), newdest); | |
3577 | SUBST (XEXP (setsrc, 1), newdest); | |
3578 | subst_done = true; | |
3579 | } | |
3580 | /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */ | |
3581 | else if ((code == PLUS || code == MULT) | |
3582 | && GET_CODE (src_op0) == code | |
3583 | && GET_CODE (XEXP (src_op0, 0)) == code | |
3584 | && (INTEGRAL_MODE_P (mode) | |
3585 | || (FLOAT_MODE_P (mode) | |
3586 | && flag_unsafe_math_optimizations))) | |
3587 | { | |
3588 | rtx p = XEXP (XEXP (src_op0, 0), 0); | |
3589 | rtx q = XEXP (XEXP (src_op0, 0), 1); | |
3590 | rtx r = XEXP (src_op0, 1); | |
3591 | rtx s = src_op1; | |
3592 | ||
3593 | /* Split both "((X op Y) op X) op Y" and | |
3594 | "((X op Y) op Y) op X" as "T op T" where T is | |
3595 | "X op Y". */ | |
3596 | if ((rtx_equal_p (p,r) && rtx_equal_p (q,s)) | |
3597 | || (rtx_equal_p (p,s) && rtx_equal_p (q,r))) | |
3598 | { | |
3599 | newi2pat = gen_rtx_SET (VOIDmode, newdest, | |
3600 | XEXP (src_op0, 0)); | |
3601 | SUBST (XEXP (setsrc, 0), newdest); | |
3602 | SUBST (XEXP (setsrc, 1), newdest); | |
3603 | subst_done = true; | |
3604 | } | |
3605 | /* Split "((X op X) op Y) op Y)" as "T op T" where | |
3606 | T is "X op Y". */ | |
3607 | else if (rtx_equal_p (p,q) && rtx_equal_p (r,s)) | |
3608 | { | |
3609 | rtx tmp = simplify_gen_binary (code, mode, p, r); | |
3610 | newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp); | |
3611 | SUBST (XEXP (setsrc, 0), newdest); | |
3612 | SUBST (XEXP (setsrc, 1), newdest); | |
3613 | subst_done = true; | |
3614 | } | |
3615 | } | |
3616 | } | |
3617 | ||
3618 | if (!subst_done) | |
3619 | { | |
3620 | newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); | |
3621 | SUBST (*split, newdest); | |
3622 | } | |
3623 | ||
d9943040 | 3624 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
7aedce90 | 3625 | |
1d4e5a23 | 3626 | /* recog_for_combine might have added CLOBBERs to newi2pat. |
3627 | Make sure NEWPAT does not depend on the clobbered regs. */ | |
3628 | if (GET_CODE (newi2pat) == PARALLEL) | |
3629 | for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) | |
3630 | if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) | |
3631 | { | |
3632 | rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); | |
3633 | if (reg_overlap_mentioned_p (reg, newpat)) | |
3634 | { | |
3635 | undo_all (); | |
3636 | return 0; | |
3637 | } | |
3638 | } | |
3639 | ||
7aedce90 | 3640 | /* If the split point was a MULT and we didn't have one before, |
3641 | don't use one now. */ | |
3642 | if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) | |
d9943040 | 3643 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
ccfa01f5 | 3644 | } |
3645 | } | |
3646 | ||
3647 | /* Check for a case where we loaded from memory in a narrow mode and | |
3648 | then sign extended it, but we need both registers. In that case, | |
3649 | we have a PARALLEL with both loads from the same memory location. | |
3650 | We can split this into a load from memory followed by a register-register | |
3651 | copy. This saves at least one insn, more if register allocation can | |
165b8283 | 3652 | eliminate the copy. |
3653 | ||
91cf636e | 3654 | We cannot do this if the destination of the first assignment is a |
3655 | condition code register or cc0. We eliminate this case by making sure | |
3656 | the SET_DEST and SET_SRC have the same mode. | |
3657 | ||
165b8283 | 3658 | We cannot do this if the destination of the second assignment is |
3659 | a register that we have already assumed is zero-extended. Similarly | |
3660 | for a SUBREG of such a register. */ | |
ccfa01f5 | 3661 | |
3662 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
3663 | && GET_CODE (newpat) == PARALLEL | |
3664 | && XVECLEN (newpat, 0) == 2 | |
3665 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
3666 | && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND | |
91cf636e | 3667 | && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) |
3668 | == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) | |
ccfa01f5 | 3669 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET |
3670 | && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
3671 | XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) | |
3672 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
3072d30e | 3673 | DF_INSN_LUID (i2)) |
ccfa01f5 | 3674 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT |
3675 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
35330d19 | 3676 | && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)), |
3677 | (REG_P (temp_expr) | |
3678 | && reg_stat[REGNO (temp_expr)].nonzero_bits != 0 | |
3679 | && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD | |
3680 | && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT | |
3681 | && (reg_stat[REGNO (temp_expr)].nonzero_bits | |
165b8283 | 3682 | != GET_MODE_MASK (word_mode)))) |
3683 | && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG | |
35330d19 | 3684 | && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), |
3685 | (REG_P (temp_expr) | |
3686 | && reg_stat[REGNO (temp_expr)].nonzero_bits != 0 | |
3687 | && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD | |
3688 | && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT | |
3689 | && (reg_stat[REGNO (temp_expr)].nonzero_bits | |
165b8283 | 3690 | != GET_MODE_MASK (word_mode))))) |
ccfa01f5 | 3691 | && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), |
3692 | SET_SRC (XVECEXP (newpat, 0, 1))) | |
3693 | && ! find_reg_note (i3, REG_UNUSED, | |
3694 | SET_DEST (XVECEXP (newpat, 0, 0)))) | |
3695 | { | |
72f7ce65 | 3696 | rtx ni2dest; |
3697 | ||
ccfa01f5 | 3698 | newi2pat = XVECEXP (newpat, 0, 0); |
72f7ce65 | 3699 | ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); |
ccfa01f5 | 3700 | newpat = XVECEXP (newpat, 0, 1); |
3701 | SUBST (SET_SRC (newpat), | |
316f48ea | 3702 | gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest)); |
d9943040 | 3703 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
f44d7107 | 3704 | |
ccfa01f5 | 3705 | if (i2_code_number >= 0) |
d9943040 | 3706 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
88355298 | 3707 | |
3708 | if (insn_code_number >= 0) | |
a1159f52 | 3709 | swap_i2i3 = 1; |
ccfa01f5 | 3710 | } |
510f7125 | 3711 | |
ccfa01f5 | 3712 | /* Similarly, check for a case where we have a PARALLEL of two independent |
3713 | SETs but we started with three insns. In this case, we can do the sets | |
3714 | as two separate insns. This case occurs when some SET allows two | |
3715 | other insns to combine, but the destination of that SET is still live. */ | |
3716 | ||
3717 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
3718 | && GET_CODE (newpat) == PARALLEL | |
3719 | && XVECLEN (newpat, 0) == 2 | |
3720 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
3721 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT | |
3722 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART | |
3723 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
3724 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
3725 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
ccfa01f5 | 3726 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), |
3727 | XVECEXP (newpat, 0, 0)) | |
3728 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), | |
155b05dc | 3729 | XVECEXP (newpat, 0, 1)) |
3730 | && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) | |
5ed36cd5 | 3731 | && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) |
ccfa01f5 | 3732 | { |
522ca540 | 3733 | rtx set0 = XVECEXP (newpat, 0, 0); |
3734 | rtx set1 = XVECEXP (newpat, 0, 1); | |
3735 | ||
0dbd1c74 | 3736 | /* Normally, it doesn't matter which of the two is done first, |
5ed36cd5 | 3737 | but the one that references cc0 can't be the second, and |
3738 | one which uses any regs/memory set in between i2 and i3 can't | |
522ca540 | 3739 | be first. The PARALLEL might also have been pre-existing in i3, |
3740 | so we need to make sure that we won't wrongly hoist a SET to i2 | |
3741 | that would conflict with a death note present in there. */ | |
3742 | if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2)) | |
3743 | && !(REG_P (SET_DEST (set1)) | |
3744 | && find_reg_note (i2, REG_DEAD, SET_DEST (set1))) | |
3745 | && !(GET_CODE (SET_DEST (set1)) == SUBREG | |
3746 | && find_reg_note (i2, REG_DEAD, | |
3747 | SUBREG_REG (SET_DEST (set1)))) | |
0dbd1c74 | 3748 | #ifdef HAVE_cc0 |
522ca540 | 3749 | && !reg_referenced_p (cc0_rtx, set0) |
5ed36cd5 | 3750 | #endif |
7c7451c5 | 3751 | /* If I3 is a jump, ensure that set0 is a jump so that |
3752 | we do not create invalid RTL. */ | |
3753 | && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx) | |
5ed36cd5 | 3754 | ) |
3755 | { | |
522ca540 | 3756 | newi2pat = set1; |
3757 | newpat = set0; | |
5ed36cd5 | 3758 | } |
522ca540 | 3759 | else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2)) |
3760 | && !(REG_P (SET_DEST (set0)) | |
3761 | && find_reg_note (i2, REG_DEAD, SET_DEST (set0))) | |
3762 | && !(GET_CODE (SET_DEST (set0)) == SUBREG | |
3763 | && find_reg_note (i2, REG_DEAD, | |
3764 | SUBREG_REG (SET_DEST (set0)))) | |
5ed36cd5 | 3765 | #ifdef HAVE_cc0 |
522ca540 | 3766 | && !reg_referenced_p (cc0_rtx, set1) |
5ed36cd5 | 3767 | #endif |
7c7451c5 | 3768 | /* If I3 is a jump, ensure that set1 is a jump so that |
3769 | we do not create invalid RTL. */ | |
3770 | && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx) | |
5ed36cd5 | 3771 | ) |
0dbd1c74 | 3772 | { |
522ca540 | 3773 | newi2pat = set0; |
3774 | newpat = set1; | |
0dbd1c74 | 3775 | } |
3776 | else | |
0dbd1c74 | 3777 | { |
5ed36cd5 | 3778 | undo_all (); |
3779 | return 0; | |
0dbd1c74 | 3780 | } |
ccfa01f5 | 3781 | |
d9943040 | 3782 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
f44d7107 | 3783 | |
ccfa01f5 | 3784 | if (i2_code_number >= 0) |
ff52c92e | 3785 | { |
3786 | /* recog_for_combine might have added CLOBBERs to newi2pat. | |
3787 | Make sure NEWPAT does not depend on the clobbered regs. */ | |
3788 | if (GET_CODE (newi2pat) == PARALLEL) | |
3789 | { | |
3790 | for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) | |
3791 | if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) | |
3792 | { | |
3793 | rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); | |
3794 | if (reg_overlap_mentioned_p (reg, newpat)) | |
5ed36cd5 | 3795 | { |
3796 | undo_all (); | |
3797 | return 0; | |
3798 | } | |
ff52c92e | 3799 | } |
ff52c92e | 3800 | } |
3801 | ||
3802 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
3803 | } | |
ccfa01f5 | 3804 | } |
3805 | ||
3806 | /* If it still isn't recognized, fail and change things back the way they | |
3807 | were. */ | |
3808 | if ((insn_code_number < 0 | |
3809 | /* Is the result a reasonable ASM_OPERANDS? */ | |
3810 | && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) | |
3811 | { | |
3812 | undo_all (); | |
3813 | return 0; | |
3814 | } | |
3815 | ||
3816 | /* If we had to change another insn, make sure it is valid also. */ | |
3817 | if (undobuf.other_insn) | |
3818 | { | |
cee293e3 | 3819 | CLEAR_HARD_REG_SET (newpat_used_regs); |
3820 | ||
06a8a63d | 3821 | other_pat = PATTERN (undobuf.other_insn); |
d9943040 | 3822 | other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, |
3823 | &new_other_notes); | |
ccfa01f5 | 3824 | |
3825 | if (other_code_number < 0 && ! check_asm_operands (other_pat)) | |
3826 | { | |
3827 | undo_all (); | |
3828 | return 0; | |
3829 | } | |
ccfa01f5 | 3830 | } |
06a8a63d | 3831 | |
25288c4e | 3832 | #ifdef HAVE_cc0 |
4885b286 | 3833 | /* If I2 is the CC0 setter and I3 is the CC0 user then check whether |
2c0e001b | 3834 | they are adjacent to each other or not. */ |
25288c4e | 3835 | { |
35330d19 | 3836 | rtx_insn *p = prev_nonnote_insn (i3); |
6d7dc5b9 | 3837 | if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat |
510f7125 | 3838 | && sets_cc0_p (newi2pat)) |
25288c4e | 3839 | { |
510f7125 | 3840 | undo_all (); |
3841 | return 0; | |
25288c4e | 3842 | } |
510f7125 | 3843 | } |
3844 | #endif | |
ccfa01f5 | 3845 | |
0a8a047c | 3846 | /* Only allow this combination if insn_rtx_costs reports that the |
f1a2a2d6 | 3847 | replacement instructions are cheaper than the originals. */ |
6342422c | 3848 | if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat)) |
f1a2a2d6 | 3849 | { |
3850 | undo_all (); | |
3851 | return 0; | |
3852 | } | |
3853 | ||
9845d120 | 3854 | if (MAY_HAVE_DEBUG_INSNS) |
3855 | { | |
3856 | struct undo *undo; | |
3857 | ||
3858 | for (undo = undobuf.undos; undo; undo = undo->next) | |
3859 | if (undo->kind == UNDO_MODE) | |
3860 | { | |
3861 | rtx reg = *undo->where.r; | |
3862 | enum machine_mode new_mode = GET_MODE (reg); | |
3863 | enum machine_mode old_mode = undo->old_contents.m; | |
3864 | ||
3865 | /* Temporarily revert mode back. */ | |
3866 | adjust_reg_mode (reg, old_mode); | |
3867 | ||
3868 | if (reg == i2dest && i2scratch) | |
3869 | { | |
3870 | /* If we used i2dest as a scratch register with a | |
3871 | different mode, substitute it for the original | |
3872 | i2src while its original mode is temporarily | |
3873 | restored, and then clear i2scratch so that we don't | |
3874 | do it again later. */ | |
e6637753 | 3875 | propagate_for_debug (i2, last_combined_insn, reg, i2src, |
3876 | this_basic_block); | |
9845d120 | 3877 | i2scratch = false; |
3878 | /* Put back the new mode. */ | |
3879 | adjust_reg_mode (reg, new_mode); | |
3880 | } | |
3881 | else | |
3882 | { | |
3883 | rtx tempreg = gen_raw_REG (old_mode, REGNO (reg)); | |
35330d19 | 3884 | rtx_insn *first, *last; |
9845d120 | 3885 | |
3886 | if (reg == i2dest) | |
3887 | { | |
3888 | first = i2; | |
0444b5eb | 3889 | last = last_combined_insn; |
9845d120 | 3890 | } |
3891 | else | |
3892 | { | |
3893 | first = i3; | |
3894 | last = undobuf.other_insn; | |
3895 | gcc_assert (last); | |
0444b5eb | 3896 | if (DF_INSN_LUID (last) |
3897 | < DF_INSN_LUID (last_combined_insn)) | |
3898 | last = last_combined_insn; | |
9845d120 | 3899 | } |
3900 | ||
3901 | /* We're dealing with a reg that changed mode but not | |
3902 | meaning, so we want to turn it into a subreg for | |
3903 | the new mode. However, because of REG sharing and | |
3904 | because its mode had already changed, we have to do | |
3905 | it in two steps. First, replace any debug uses of | |
3906 | reg, with its original mode temporarily restored, | |
3907 | with this copy we have created; then, replace the | |
3908 | copy with the SUBREG of the original shared reg, | |
3909 | once again changed to the new mode. */ | |
e6637753 | 3910 | propagate_for_debug (first, last, reg, tempreg, |
3911 | this_basic_block); | |
9845d120 | 3912 | adjust_reg_mode (reg, new_mode); |
3913 | propagate_for_debug (first, last, tempreg, | |
e6637753 | 3914 | lowpart_subreg (old_mode, reg, new_mode), |
3915 | this_basic_block); | |
9845d120 | 3916 | } |
3917 | } | |
3918 | } | |
3919 | ||
095050fc | 3920 | /* If we will be able to accept this, we have made a |
3921 | change to the destination of I3. This requires us to | |
3922 | do a few adjustments. */ | |
3923 | ||
3924 | if (changed_i3_dest) | |
3925 | { | |
3926 | PATTERN (i3) = newpat; | |
3927 | adjust_for_new_dest (i3); | |
3928 | } | |
3929 | ||
510f7125 | 3930 | /* We now know that we can do this combination. Merge the insns and |
ccfa01f5 | 3931 | update the status of registers and LOG_LINKS. */ |
3932 | ||
06a8a63d | 3933 | if (undobuf.other_insn) |
3934 | { | |
3935 | rtx note, next; | |
3936 | ||
3937 | PATTERN (undobuf.other_insn) = other_pat; | |
3938 | ||
b7417723 | 3939 | /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED, |
3940 | ensure that they are still valid. Then add any non-duplicate | |
3941 | notes added by recog_for_combine. */ | |
06a8a63d | 3942 | for (note = REG_NOTES (undobuf.other_insn); note; note = next) |
3943 | { | |
3944 | next = XEXP (note, 1); | |
3945 | ||
b7417723 | 3946 | if ((REG_NOTE_KIND (note) == REG_DEAD |
76cf1ec5 | 3947 | && !reg_referenced_p (XEXP (note, 0), |
3948 | PATTERN (undobuf.other_insn))) | |
3949 | ||(REG_NOTE_KIND (note) == REG_UNUSED | |
3950 | && !reg_set_p (XEXP (note, 0), | |
3951 | PATTERN (undobuf.other_insn)))) | |
06a8a63d | 3952 | remove_note (undobuf.other_insn, note); |
3953 | } | |
3954 | ||
35330d19 | 3955 | distribute_notes (new_other_notes, undobuf.other_insn, |
3956 | undobuf.other_insn, NULL, NULL_RTX, NULL_RTX, | |
6342422c | 3957 | NULL_RTX); |
06a8a63d | 3958 | } |
3959 | ||
a1159f52 | 3960 | if (swap_i2i3) |
3961 | { | |
35330d19 | 3962 | rtx_insn *insn; |
2a0877d8 | 3963 | struct insn_link *link; |
a1159f52 | 3964 | rtx ni2dest; |
3965 | ||
3966 | /* I3 now uses what used to be its destination and which is now | |
a0c938f0 | 3967 | I2's destination. This requires us to do a few adjustments. */ |
a1159f52 | 3968 | PATTERN (i3) = newpat; |
3969 | adjust_for_new_dest (i3); | |
3970 | ||
3971 | /* We need a LOG_LINK from I3 to I2. But we used to have one, | |
a0c938f0 | 3972 | so we still will. |
a1159f52 | 3973 | |
3974 | However, some later insn might be using I2's dest and have | |
3975 | a LOG_LINK pointing at I3. We must remove this link. | |
3976 | The simplest way to remove the link is to point it at I1, | |
3977 | which we know will be a NOTE. */ | |
3978 | ||
7f5a7fa1 | 3979 | /* newi2pat is usually a SET here; however, recog_for_combine might |
3980 | have added some clobbers. */ | |
3981 | if (GET_CODE (newi2pat) == PARALLEL) | |
3982 | ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0)); | |
3983 | else | |
3984 | ni2dest = SET_DEST (newi2pat); | |
3985 | ||
a1159f52 | 3986 | for (insn = NEXT_INSN (i3); |
34154e27 | 3987 | insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
a1159f52 | 3988 | || insn != BB_HEAD (this_basic_block->next_bb)); |
3989 | insn = NEXT_INSN (insn)) | |
3990 | { | |
3991 | if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) | |
3992 | { | |
2a0877d8 | 3993 | FOR_EACH_LOG_LINK (link, insn) |
3994 | if (link->insn == i3) | |
3995 | link->insn = i1; | |
a1159f52 | 3996 | |
3997 | break; | |
3998 | } | |
3999 | } | |
4000 | } | |
4001 | ||
ccfa01f5 | 4002 | { |
6342422c | 4003 | rtx i3notes, i2notes, i1notes = 0, i0notes = 0; |
2a0877d8 | 4004 | struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0; |
ccfa01f5 | 4005 | rtx midnotes = 0; |
6342422c | 4006 | int from_luid; |
40a8fb89 | 4007 | /* Compute which registers we expect to eliminate. newi2pat may be setting |
4008 | either i3dest or i2dest, so we must check it. Also, i1dest may be the | |
4009 | same as i3dest, in which case newi2pat may be setting i1dest. */ | |
4010 | rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) | |
6342422c | 4011 | || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src |
40a8fb89 | 4012 | || !i2dest_killed |
4013 | ? 0 : i2dest); | |
6342422c | 4014 | rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src |
40a8fb89 | 4015 | || (newi2pat && reg_set_p (i1dest, newi2pat)) |
4016 | || !i1dest_killed | |
4017 | ? 0 : i1dest); | |
6342422c | 4018 | rtx elim_i0 = (i0 == 0 || i0dest_in_i0src |
4019 | || (newi2pat && reg_set_p (i0dest, newi2pat)) | |
4020 | || !i0dest_killed | |
4021 | ? 0 : i0dest); | |
ccfa01f5 | 4022 | |
4023 | /* Get the old REG_NOTES and LOG_LINKS from all our insns and | |
4024 | clear them. */ | |
4025 | i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); | |
4026 | i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); | |
4027 | if (i1) | |
4028 | i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); | |
6342422c | 4029 | if (i0) |
4030 | i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0); | |
ccfa01f5 | 4031 | |
4032 | /* Ensure that we do not have something that should not be shared but | |
4033 | occurs multiple times in the new insns. Check this by first | |
88355298 | 4034 | resetting all the `used' flags and then copying anything is shared. */ |
ccfa01f5 | 4035 | |
4036 | reset_used_flags (i3notes); | |
4037 | reset_used_flags (i2notes); | |
4038 | reset_used_flags (i1notes); | |
6342422c | 4039 | reset_used_flags (i0notes); |
ccfa01f5 | 4040 | reset_used_flags (newpat); |
4041 | reset_used_flags (newi2pat); | |
4042 | if (undobuf.other_insn) | |
4043 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
4044 | ||
4045 | i3notes = copy_rtx_if_shared (i3notes); | |
4046 | i2notes = copy_rtx_if_shared (i2notes); | |
4047 | i1notes = copy_rtx_if_shared (i1notes); | |
6342422c | 4048 | i0notes = copy_rtx_if_shared (i0notes); |
ccfa01f5 | 4049 | newpat = copy_rtx_if_shared (newpat); |
4050 | newi2pat = copy_rtx_if_shared (newi2pat); | |
4051 | if (undobuf.other_insn) | |
4052 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
4053 | ||
4054 | INSN_CODE (i3) = insn_code_number; | |
4055 | PATTERN (i3) = newpat; | |
de79a9e1 | 4056 | |
6d7dc5b9 | 4057 | if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3)) |
de79a9e1 | 4058 | { |
4059 | rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3); | |
4060 | ||
4061 | reset_used_flags (call_usage); | |
4062 | call_usage = copy_rtx (call_usage); | |
4063 | ||
4064 | if (substed_i2) | |
42a4b11f | 4065 | { |
4066 | /* I2SRC must still be meaningful at this point. Some splitting | |
4067 | operations can invalidate I2SRC, but those operations do not | |
4068 | apply to calls. */ | |
4069 | gcc_assert (i2src); | |
4070 | replace_rtx (call_usage, i2dest, i2src); | |
4071 | } | |
de79a9e1 | 4072 | |
4073 | if (substed_i1) | |
4074 | replace_rtx (call_usage, i1dest, i1src); | |
6342422c | 4075 | if (substed_i0) |
4076 | replace_rtx (call_usage, i0dest, i0src); | |
de79a9e1 | 4077 | |
4078 | CALL_INSN_FUNCTION_USAGE (i3) = call_usage; | |
4079 | } | |
4080 | ||
ccfa01f5 | 4081 | if (undobuf.other_insn) |
4082 | INSN_CODE (undobuf.other_insn) = other_code_number; | |
4083 | ||
4084 | /* We had one special case above where I2 had more than one set and | |
4085 | we replaced a destination of one of those sets with the destination | |
4086 | of I3. In that case, we have to update LOG_LINKS of insns later | |
4ac0b86b | 4087 | in this basic block. Note that this (expensive) case is rare. |
4088 | ||
4089 | Also, in this case, we must pretend that all REG_NOTEs for I2 | |
4090 | actually came from I3, so that REG_UNUSED notes from I2 will be | |
4091 | properly handled. */ | |
4092 | ||
719d6726 | 4093 | if (i3_subst_into_i2) |
4ac0b86b | 4094 | { |
e0fe274b | 4095 | for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) |
43c3808d | 4096 | if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET |
4097 | || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER) | |
8ad4c111 | 4098 | && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) |
e0fe274b | 4099 | && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest |
4100 | && ! find_reg_note (i2, REG_UNUSED, | |
4101 | SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) | |
35330d19 | 4102 | for (temp_insn = NEXT_INSN (i2); |
4103 | temp_insn | |
34154e27 | 4104 | && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
35330d19 | 4105 | || BB_HEAD (this_basic_block) != temp_insn); |
4106 | temp_insn = NEXT_INSN (temp_insn)) | |
4107 | if (temp_insn != i3 && INSN_P (temp_insn)) | |
4108 | FOR_EACH_LOG_LINK (link, temp_insn) | |
2a0877d8 | 4109 | if (link->insn == i2) |
4110 | link->insn = i3; | |
4ac0b86b | 4111 | |
4112 | if (i3notes) | |
4113 | { | |
4114 | rtx link = i3notes; | |
4115 | while (XEXP (link, 1)) | |
4116 | link = XEXP (link, 1); | |
4117 | XEXP (link, 1) = i2notes; | |
4118 | } | |
4119 | else | |
4120 | i3notes = i2notes; | |
4121 | i2notes = 0; | |
4122 | } | |
ccfa01f5 | 4123 | |
2a0877d8 | 4124 | LOG_LINKS (i3) = NULL; |
ccfa01f5 | 4125 | REG_NOTES (i3) = 0; |
2a0877d8 | 4126 | LOG_LINKS (i2) = NULL; |
ccfa01f5 | 4127 | REG_NOTES (i2) = 0; |
4128 | ||
4129 | if (newi2pat) | |
4130 | { | |
9845d120 | 4131 | if (MAY_HAVE_DEBUG_INSNS && i2scratch) |
e6637753 | 4132 | propagate_for_debug (i2, last_combined_insn, i2dest, i2src, |
4133 | this_basic_block); | |
ccfa01f5 | 4134 | INSN_CODE (i2) = i2_code_number; |
4135 | PATTERN (i2) = newi2pat; | |
4136 | } | |
4137 | else | |
9845d120 | 4138 | { |
4139 | if (MAY_HAVE_DEBUG_INSNS && i2src) | |
e6637753 | 4140 | propagate_for_debug (i2, last_combined_insn, i2dest, i2src, |
4141 | this_basic_block); | |
9845d120 | 4142 | SET_INSN_DELETED (i2); |
4143 | } | |
ccfa01f5 | 4144 | |
4145 | if (i1) | |
4146 | { | |
2a0877d8 | 4147 | LOG_LINKS (i1) = NULL; |
ccfa01f5 | 4148 | REG_NOTES (i1) = 0; |
9845d120 | 4149 | if (MAY_HAVE_DEBUG_INSNS) |
e6637753 | 4150 | propagate_for_debug (i1, last_combined_insn, i1dest, i1src, |
4151 | this_basic_block); | |
7bd3dcc4 | 4152 | SET_INSN_DELETED (i1); |
ccfa01f5 | 4153 | } |
4154 | ||
6342422c | 4155 | if (i0) |
4156 | { | |
2a0877d8 | 4157 | LOG_LINKS (i0) = NULL; |
6342422c | 4158 | REG_NOTES (i0) = 0; |
4159 | if (MAY_HAVE_DEBUG_INSNS) | |
e6637753 | 4160 | propagate_for_debug (i0, last_combined_insn, i0dest, i0src, |
4161 | this_basic_block); | |
6342422c | 4162 | SET_INSN_DELETED (i0); |
4163 | } | |
4164 | ||
ccfa01f5 | 4165 | /* Get death notes for everything that is now used in either I3 or |
510f7125 | 4166 | I2 and used to die in a previous insn. If we built two new |
11f912ae | 4167 | patterns, move from I1 to I2 then I2 to I3 so that we get the |
4168 | proper movement on registers that I2 modifies. */ | |
ccfa01f5 | 4169 | |
6342422c | 4170 | if (i0) |
4171 | from_luid = DF_INSN_LUID (i0); | |
4172 | else if (i1) | |
4173 | from_luid = DF_INSN_LUID (i1); | |
11f912ae | 4174 | else |
6342422c | 4175 | from_luid = DF_INSN_LUID (i2); |
4176 | if (newi2pat) | |
4177 | move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes); | |
4178 | move_deaths (newpat, newi2pat, from_luid, i3, &midnotes); | |
ccfa01f5 | 4179 | |
4180 | /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ | |
4181 | if (i3notes) | |
35330d19 | 4182 | distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL, |
6342422c | 4183 | elim_i2, elim_i1, elim_i0); |
ccfa01f5 | 4184 | if (i2notes) |
35330d19 | 4185 | distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL, |
6342422c | 4186 | elim_i2, elim_i1, elim_i0); |
ccfa01f5 | 4187 | if (i1notes) |
35330d19 | 4188 | distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL, |
6342422c | 4189 | elim_i2, elim_i1, elim_i0); |
4190 | if (i0notes) | |
35330d19 | 4191 | distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL, |
6342422c | 4192 | elim_i2, elim_i1, elim_i0); |
ccfa01f5 | 4193 | if (midnotes) |
35330d19 | 4194 | distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL, |
6342422c | 4195 | elim_i2, elim_i1, elim_i0); |
ccfa01f5 | 4196 | |
4197 | /* Distribute any notes added to I2 or I3 by recog_for_combine. We | |
4198 | know these are REG_UNUSED and want them to go to the desired insn, | |
3072d30e | 4199 | so we always pass it as i3. */ |
1f1c8c5a | 4200 | |
ccfa01f5 | 4201 | if (newi2pat && new_i2_notes) |
35330d19 | 4202 | distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX, |
6342422c | 4203 | NULL_RTX); |
48e1416a | 4204 | |
ccfa01f5 | 4205 | if (new_i3_notes) |
35330d19 | 4206 | distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX, |
6342422c | 4207 | NULL_RTX); |
ccfa01f5 | 4208 | |
4209 | /* If I3DEST was used in I3SRC, it really died in I3. We may need to | |
0dbd1c74 | 4210 | put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets |
4211 | I3DEST, the death must be somewhere before I2, not I3. If we passed I3 | |
4212 | in that case, it might delete I2. Similarly for I2 and I1. | |
1f1c8c5a | 4213 | Show an additional death due to the REG_DEAD note we make here. If |
4214 | we discard it in distribute_notes, we will decrement it again. */ | |
ec90760f | 4215 | |
ccfa01f5 | 4216 | if (i3dest_killed) |
1f1c8c5a | 4217 | { |
32cf0798 | 4218 | rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX); |
0dbd1c74 | 4219 | if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) |
35330d19 | 4220 | distribute_notes (new_note, NULL, i2, NULL, elim_i2, |
32cf0798 | 4221 | elim_i1, elim_i0); |
0dbd1c74 | 4222 | else |
35330d19 | 4223 | distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, |
6342422c | 4224 | elim_i2, elim_i1, elim_i0); |
1f1c8c5a | 4225 | } |
607e8d51 | 4226 | |
ccfa01f5 | 4227 | if (i2dest_in_i2src) |
607e8d51 | 4228 | { |
6342422c | 4229 | rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX); |
607e8d51 | 4230 | if (newi2pat && reg_set_p (i2dest, newi2pat)) |
35330d19 | 4231 | distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, |
40a8fb89 | 4232 | NULL_RTX, NULL_RTX); |
6342422c | 4233 | else |
35330d19 | 4234 | distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, |
6342422c | 4235 | NULL_RTX, NULL_RTX, NULL_RTX); |
607e8d51 | 4236 | } |
4237 | ||
ccfa01f5 | 4238 | if (i1dest_in_i1src) |
607e8d51 | 4239 | { |
6342422c | 4240 | rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX); |
607e8d51 | 4241 | if (newi2pat && reg_set_p (i1dest, newi2pat)) |
35330d19 | 4242 | distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, |
6342422c | 4243 | NULL_RTX, NULL_RTX); |
607e8d51 | 4244 | else |
35330d19 | 4245 | distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, |
6342422c | 4246 | NULL_RTX, NULL_RTX, NULL_RTX); |
4247 | } | |
4248 | ||
4249 | if (i0dest_in_i0src) | |
4250 | { | |
4251 | rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX); | |
4252 | if (newi2pat && reg_set_p (i0dest, newi2pat)) | |
35330d19 | 4253 | distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, |
40a8fb89 | 4254 | NULL_RTX, NULL_RTX); |
6342422c | 4255 | else |
35330d19 | 4256 | distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, |
6342422c | 4257 | NULL_RTX, NULL_RTX, NULL_RTX); |
607e8d51 | 4258 | } |
ccfa01f5 | 4259 | |
4260 | distribute_links (i3links); | |
4261 | distribute_links (i2links); | |
4262 | distribute_links (i1links); | |
6342422c | 4263 | distribute_links (i0links); |
ccfa01f5 | 4264 | |
8ad4c111 | 4265 | if (REG_P (i2dest)) |
ccfa01f5 | 4266 | { |
2a0877d8 | 4267 | struct insn_link *link; |
35330d19 | 4268 | rtx_insn *i2_insn = 0; |
4269 | rtx i2_val = 0, set; | |
ec90760f | 4270 | |
4271 | /* The insn that used to set this register doesn't exist, and | |
4272 | this life of the register may not exist either. See if one of | |
510f7125 | 4273 | I3's links points to an insn that sets I2DEST. If it does, |
ec90760f | 4274 | that is now the last known value for I2DEST. If we don't update |
4275 | this and I2 set the register to a value that depended on its old | |
ccfa01f5 | 4276 | contents, we will get confused. If this insn is used, thing |
4277 | will be set correctly in combine_instructions. */ | |
2a0877d8 | 4278 | FOR_EACH_LOG_LINK (link, i3) |
4279 | if ((set = single_set (link->insn)) != 0 | |
ec90760f | 4280 | && rtx_equal_p (i2dest, SET_DEST (set))) |
2a0877d8 | 4281 | i2_insn = link->insn, i2_val = SET_SRC (set); |
ec90760f | 4282 | |
4283 | record_value_for_reg (i2dest, i2_insn, i2_val); | |
ccfa01f5 | 4284 | |
4285 | /* If the reg formerly set in I2 died only once and that was in I3, | |
4286 | zero its use count so it won't make `reload' do any work. */ | |
8671d9ae | 4287 | if (! added_sets_2 |
4288 | && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) | |
4289 | && ! i2dest_in_i2src) | |
e73ba0a7 | 4290 | INC_REG_N_SETS (REGNO (i2dest), -1); |
ccfa01f5 | 4291 | } |
4292 | ||
8ad4c111 | 4293 | if (i1 && REG_P (i1dest)) |
ccfa01f5 | 4294 | { |
2a0877d8 | 4295 | struct insn_link *link; |
35330d19 | 4296 | rtx_insn *i1_insn = 0; |
4297 | rtx i1_val = 0, set; | |
ec90760f | 4298 | |
2a0877d8 | 4299 | FOR_EACH_LOG_LINK (link, i3) |
4300 | if ((set = single_set (link->insn)) != 0 | |
ec90760f | 4301 | && rtx_equal_p (i1dest, SET_DEST (set))) |
2a0877d8 | 4302 | i1_insn = link->insn, i1_val = SET_SRC (set); |
ec90760f | 4303 | |
4304 | record_value_for_reg (i1dest, i1_insn, i1_val); | |
4305 | ||
022cc0d5 | 4306 | if (! added_sets_1 && ! i1dest_in_i1src) |
e73ba0a7 | 4307 | INC_REG_N_SETS (REGNO (i1dest), -1); |
ccfa01f5 | 4308 | } |
4309 | ||
6342422c | 4310 | if (i0 && REG_P (i0dest)) |
4311 | { | |
2a0877d8 | 4312 | struct insn_link *link; |
35330d19 | 4313 | rtx_insn *i0_insn = 0; |
4314 | rtx i0_val = 0, set; | |
6342422c | 4315 | |
2a0877d8 | 4316 | FOR_EACH_LOG_LINK (link, i3) |
4317 | if ((set = single_set (link->insn)) != 0 | |
6342422c | 4318 | && rtx_equal_p (i0dest, SET_DEST (set))) |
2a0877d8 | 4319 | i0_insn = link->insn, i0_val = SET_SRC (set); |
6342422c | 4320 | |
4321 | record_value_for_reg (i0dest, i0_insn, i0_val); | |
4322 | ||
6342422c | 4323 | if (! added_sets_0 && ! i0dest_in_i0src) |
e73ba0a7 | 4324 | INC_REG_N_SETS (REGNO (i0dest), -1); |
6342422c | 4325 | } |
4326 | ||
acac6d5d | 4327 | /* Update reg_stat[].nonzero_bits et al for any changes that may have |
522ca540 | 4328 | been made to this insn. The order is important, because newi2pat |
4329 | can affect nonzero_bits of newpat. */ | |
7270012f | 4330 | if (newi2pat) |
ec8895d7 | 4331 | note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); |
527e5b29 | 4332 | note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); |
ccfa01f5 | 4333 | } |
ee4d588d | 4334 | |
3072d30e | 4335 | if (undobuf.other_insn != NULL_RTX) |
4336 | { | |
4337 | if (dump_file) | |
4338 | { | |
4339 | fprintf (dump_file, "modifying other_insn "); | |
4340 | dump_insn_slim (dump_file, undobuf.other_insn); | |
4341 | } | |
4342 | df_insn_rescan (undobuf.other_insn); | |
4343 | } | |
4344 | ||
9af5ce0c | 4345 | if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED))) |
6342422c | 4346 | { |
4347 | if (dump_file) | |
4348 | { | |
522ca540 | 4349 | fprintf (dump_file, "modifying insn i0 "); |
6342422c | 4350 | dump_insn_slim (dump_file, i0); |
4351 | } | |
4352 | df_insn_rescan (i0); | |
4353 | } | |
4354 | ||
9af5ce0c | 4355 | if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED))) |
3072d30e | 4356 | { |
4357 | if (dump_file) | |
4358 | { | |
4359 | fprintf (dump_file, "modifying insn i1 "); | |
4360 | dump_insn_slim (dump_file, i1); | |
4361 | } | |
4362 | df_insn_rescan (i1); | |
4363 | } | |
ccfa01f5 | 4364 | |
9af5ce0c | 4365 | if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED))) |
3072d30e | 4366 | { |
4367 | if (dump_file) | |
4368 | { | |
4369 | fprintf (dump_file, "modifying insn i2 "); | |
4370 | dump_insn_slim (dump_file, i2); | |
4371 | } | |
4372 | df_insn_rescan (i2); | |
4373 | } | |
4374 | ||
9af5ce0c | 4375 | if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED))) |
3072d30e | 4376 | { |
4377 | if (dump_file) | |
4378 | { | |
4379 | fprintf (dump_file, "modifying insn i3 "); | |
4380 | dump_insn_slim (dump_file, i3); | |
4381 | } | |
4382 | df_insn_rescan (i3); | |
4383 | } | |
48e1416a | 4384 | |
ee4d588d | 4385 | /* Set new_direct_jump_p if a new return or simple jump instruction |
4386 | has been created. Adjust the CFG accordingly. */ | |
ee4d588d | 4387 | if (returnjump_p (i3) || any_uncondjump_p (i3)) |
4388 | { | |
4389 | *new_direct_jump_p = 1; | |
4390 | mark_jump_label (PATTERN (i3), i3, 0); | |
4391 | update_cfg_for_uncondjump (i3); | |
4392 | } | |
4393 | ||
4394 | if (undobuf.other_insn != NULL_RTX | |
4395 | && (returnjump_p (undobuf.other_insn) | |
4396 | || any_uncondjump_p (undobuf.other_insn))) | |
4397 | { | |
4398 | *new_direct_jump_p = 1; | |
4399 | update_cfg_for_uncondjump (undobuf.other_insn); | |
4400 | } | |
4401 | ||
4402 | /* A noop might also need cleaning up of CFG, if it comes from the | |
4403 | simplification of a jump. */ | |
41b4f8f9 | 4404 | if (JUMP_P (i3) |
4405 | && GET_CODE (newpat) == SET | |
ee4d588d | 4406 | && SET_SRC (newpat) == pc_rtx |
4407 | && SET_DEST (newpat) == pc_rtx) | |
4408 | { | |
4409 | *new_direct_jump_p = 1; | |
4410 | update_cfg_for_uncondjump (i3); | |
4411 | } | |
48e1416a | 4412 | |
af9b9305 | 4413 | if (undobuf.other_insn != NULL_RTX |
41b4f8f9 | 4414 | && JUMP_P (undobuf.other_insn) |
af9b9305 | 4415 | && GET_CODE (PATTERN (undobuf.other_insn)) == SET |
4416 | && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx | |
4417 | && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx) | |
4418 | { | |
4419 | *new_direct_jump_p = 1; | |
4420 | update_cfg_for_uncondjump (undobuf.other_insn); | |
4421 | } | |
4422 | ||
ccfa01f5 | 4423 | combine_successes++; |
aeee2a4b | 4424 | undo_commit (); |
ccfa01f5 | 4425 | |
862e4898 | 4426 | if (added_links_insn |
3072d30e | 4427 | && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2)) |
4428 | && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3)) | |
862e4898 | 4429 | return added_links_insn; |
4430 | else | |
4431 | return newi2pat ? i2 : i3; | |
ccfa01f5 | 4432 | } |
4433 | \f | |
4434 | /* Undo all the modifications recorded in undobuf. */ | |
4435 | ||
4436 | static void | |
d598ad0d | 4437 | undo_all (void) |
ccfa01f5 | 4438 | { |
5b946b05 | 4439 | struct undo *undo, *next; |
4440 | ||
4441 | for (undo = undobuf.undos; undo; undo = next) | |
4e3cf00a | 4442 | { |
5b946b05 | 4443 | next = undo->next; |
df738c1f | 4444 | switch (undo->kind) |
4445 | { | |
4446 | case UNDO_RTX: | |
4447 | *undo->where.r = undo->old_contents.r; | |
4448 | break; | |
4449 | case UNDO_INT: | |
4450 | *undo->where.i = undo->old_contents.i; | |
4451 | break; | |
4452 | case UNDO_MODE: | |
80c70e76 | 4453 | adjust_reg_mode (*undo->where.r, undo->old_contents.m); |
df738c1f | 4454 | break; |
eed2904a | 4455 | case UNDO_LINKS: |
4456 | *undo->where.l = undo->old_contents.l; | |
4457 | break; | |
df738c1f | 4458 | default: |
4459 | gcc_unreachable (); | |
4460 | } | |
5b946b05 | 4461 | |
4462 | undo->next = undobuf.frees; | |
4463 | undobuf.frees = undo; | |
4e3cf00a | 4464 | } |
ccfa01f5 | 4465 | |
3380b197 | 4466 | undobuf.undos = 0; |
ccfa01f5 | 4467 | } |
aeee2a4b | 4468 | |
4469 | /* We've committed to accepting the changes we made. Move all | |
4470 | of the undos to the free list. */ | |
4471 | ||
4472 | static void | |
d598ad0d | 4473 | undo_commit (void) |
aeee2a4b | 4474 | { |
4475 | struct undo *undo, *next; | |
4476 | ||
4477 | for (undo = undobuf.undos; undo; undo = next) | |
4478 | { | |
4479 | next = undo->next; | |
4480 | undo->next = undobuf.frees; | |
4481 | undobuf.frees = undo; | |
4482 | } | |
3380b197 | 4483 | undobuf.undos = 0; |
aeee2a4b | 4484 | } |
ccfa01f5 | 4485 | \f |
4486 | /* Find the innermost point within the rtx at LOC, possibly LOC itself, | |
ec90760f | 4487 | where we have an arithmetic expression and return that point. LOC will |
4488 | be inside INSN. | |
ccfa01f5 | 4489 | |
4490 | try_combine will call this function to see if an insn can be split into | |
4491 | two insns. */ | |
4492 | ||
4493 | static rtx * | |
35330d19 | 4494 | find_split_point (rtx *loc, rtx_insn *insn, bool set_src) |
ccfa01f5 | 4495 | { |
4496 | rtx x = *loc; | |
4497 | enum rtx_code code = GET_CODE (x); | |
4498 | rtx *split; | |
02e7a332 | 4499 | unsigned HOST_WIDE_INT len = 0; |
4500 | HOST_WIDE_INT pos = 0; | |
4501 | int unsignedp = 0; | |
df9f2bb6 | 4502 | rtx inner = NULL_RTX; |
ccfa01f5 | 4503 | |
4504 | /* First special-case some codes. */ | |
4505 | switch (code) | |
4506 | { | |
4507 | case SUBREG: | |
4508 | #ifdef INSN_SCHEDULING | |
4509 | /* If we are making a paradoxical SUBREG invalid, it becomes a split | |
4510 | point. */ | |
e16ceb8e | 4511 | if (MEM_P (SUBREG_REG (x))) |
ccfa01f5 | 4512 | return loc; |
4513 | #endif | |
b420d71b | 4514 | return find_split_point (&SUBREG_REG (x), insn, false); |
ccfa01f5 | 4515 | |
ccfa01f5 | 4516 | case MEM: |
a793480c | 4517 | #ifdef HAVE_lo_sum |
ccfa01f5 | 4518 | /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it |
4519 | using LO_SUM and HIGH. */ | |
4520 | if (GET_CODE (XEXP (x, 0)) == CONST | |
4521 | || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
4522 | { | |
87cf5753 | 4523 | enum machine_mode address_mode = get_address_mode (x); |
98155838 | 4524 | |
ccfa01f5 | 4525 | SUBST (XEXP (x, 0), |
98155838 | 4526 | gen_rtx_LO_SUM (address_mode, |
4527 | gen_rtx_HIGH (address_mode, XEXP (x, 0)), | |
3380b197 | 4528 | XEXP (x, 0))); |
ccfa01f5 | 4529 | return &XEXP (XEXP (x, 0), 0); |
4530 | } | |
ccfa01f5 | 4531 | #endif |
4532 | ||
a793480c | 4533 | /* If we have a PLUS whose second operand is a constant and the |
4534 | address is not valid, perhaps will can split it up using | |
4535 | the machine-specific way to split large constants. We use | |
01cc3b75 | 4536 | the first pseudo-reg (one of the virtual regs) as a placeholder; |
a793480c | 4537 | it will not remain in the result. */ |
4538 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
971ba038 | 4539 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) |
bd1a81f7 | 4540 | && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), |
4541 | MEM_ADDR_SPACE (x))) | |
a793480c | 4542 | { |
4543 | rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
4cd001d5 | 4544 | rtx_insn *seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg, |
4545 | XEXP (x, 0)), | |
4546 | subst_insn); | |
a793480c | 4547 | |
4548 | /* This should have produced two insns, each of which sets our | |
4549 | placeholder. If the source of the second is a valid address, | |
4550 | we can make put both sources together and make a split point | |
4551 | in the middle. */ | |
4552 | ||
31d3e01c | 4553 | if (seq |
4554 | && NEXT_INSN (seq) != NULL_RTX | |
4555 | && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX | |
6d7dc5b9 | 4556 | && NONJUMP_INSN_P (seq) |
31d3e01c | 4557 | && GET_CODE (PATTERN (seq)) == SET |
4558 | && SET_DEST (PATTERN (seq)) == reg | |
a793480c | 4559 | && ! reg_mentioned_p (reg, |
31d3e01c | 4560 | SET_SRC (PATTERN (seq))) |
6d7dc5b9 | 4561 | && NONJUMP_INSN_P (NEXT_INSN (seq)) |
31d3e01c | 4562 | && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET |
4563 | && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg | |
bd1a81f7 | 4564 | && memory_address_addr_space_p |
4565 | (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))), | |
4566 | MEM_ADDR_SPACE (x))) | |
a793480c | 4567 | { |
31d3e01c | 4568 | rtx src1 = SET_SRC (PATTERN (seq)); |
4569 | rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); | |
a793480c | 4570 | |
4571 | /* Replace the placeholder in SRC2 with SRC1. If we can | |
4572 | find where in SRC2 it was placed, that can become our | |
4573 | split point and we can replace this address with SRC2. | |
4574 | Just try two obvious places. */ | |
4575 | ||
4576 | src2 = replace_rtx (src2, reg, src1); | |
4577 | split = 0; | |
4578 | if (XEXP (src2, 0) == src1) | |
4579 | split = &XEXP (src2, 0); | |
4580 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' | |
4581 | && XEXP (XEXP (src2, 0), 0) == src1) | |
4582 | split = &XEXP (XEXP (src2, 0), 0); | |
4583 | ||
4584 | if (split) | |
4585 | { | |
4586 | SUBST (XEXP (x, 0), src2); | |
4587 | return split; | |
4588 | } | |
4589 | } | |
510f7125 | 4590 | |
1f1c8c5a | 4591 | /* If that didn't work, perhaps the first operand is complex and |
4592 | needs to be computed separately, so make a split point there. | |
4593 | This will occur on machines that just support REG + CONST | |
4594 | and have a constant moved through some previous computation. */ | |
4595 | ||
6720e96c | 4596 | else if (!OBJECT_P (XEXP (XEXP (x, 0), 0)) |
1f1c8c5a | 4597 | && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG |
6720e96c | 4598 | && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) |
1f1c8c5a | 4599 | return &XEXP (XEXP (x, 0), 0); |
a793480c | 4600 | } |
5bed1dca | 4601 | |
4602 | /* If we have a PLUS whose first operand is complex, try computing it | |
4603 | separately by making a split there. */ | |
4604 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
bd1a81f7 | 4605 | && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), |
4606 | MEM_ADDR_SPACE (x)) | |
5bed1dca | 4607 | && ! OBJECT_P (XEXP (XEXP (x, 0), 0)) |
4608 | && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG | |
4609 | && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) | |
4610 | return &XEXP (XEXP (x, 0), 0); | |
a793480c | 4611 | break; |
4612 | ||
ccfa01f5 | 4613 | case SET: |
4614 | #ifdef HAVE_cc0 | |
4615 | /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a | |
4616 | ZERO_EXTRACT, the most likely reason why this doesn't match is that | |
4617 | we need to put the operand into a register. So split at that | |
4618 | point. */ | |
4619 | ||
4620 | if (SET_DEST (x) == cc0_rtx | |
4621 | && GET_CODE (SET_SRC (x)) != COMPARE | |
4622 | && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT | |
6720e96c | 4623 | && !OBJECT_P (SET_SRC (x)) |
ccfa01f5 | 4624 | && ! (GET_CODE (SET_SRC (x)) == SUBREG |
6720e96c | 4625 | && OBJECT_P (SUBREG_REG (SET_SRC (x))))) |
ccfa01f5 | 4626 | return &SET_SRC (x); |
4627 | #endif | |
4628 | ||
4629 | /* See if we can split SET_SRC as it stands. */ | |
b420d71b | 4630 | split = find_split_point (&SET_SRC (x), insn, true); |
ccfa01f5 | 4631 | if (split && split != &SET_SRC (x)) |
4632 | return split; | |
4633 | ||
b9ff9eef | 4634 | /* See if we can split SET_DEST as it stands. */ |
b420d71b | 4635 | split = find_split_point (&SET_DEST (x), insn, false); |
b9ff9eef | 4636 | if (split && split != &SET_DEST (x)) |
4637 | return split; | |
4638 | ||
ccfa01f5 | 4639 | /* See if this is a bitfield assignment with everything constant. If |
4640 | so, this is an IOR of an AND, so split it into that. */ | |
4641 | if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
f179ee60 | 4642 | && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0))) |
971ba038 | 4643 | && CONST_INT_P (XEXP (SET_DEST (x), 1)) |
4644 | && CONST_INT_P (XEXP (SET_DEST (x), 2)) | |
4645 | && CONST_INT_P (SET_SRC (x)) | |
ccfa01f5 | 4646 | && ((INTVAL (XEXP (SET_DEST (x), 1)) |
ea913091 | 4647 | + INTVAL (XEXP (SET_DEST (x), 2))) |
ded805e6 | 4648 | <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)))) |
ccfa01f5 | 4649 | && ! side_effects_p (XEXP (SET_DEST (x), 0))) |
4650 | { | |
02e7a332 | 4651 | HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); |
4652 | unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); | |
4653 | unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); | |
ccfa01f5 | 4654 | rtx dest = XEXP (SET_DEST (x), 0); |
4655 | enum machine_mode mode = GET_MODE (dest); | |
897c6c81 | 4656 | unsigned HOST_WIDE_INT mask |
4657 | = ((unsigned HOST_WIDE_INT) 1 << len) - 1; | |
2a809e1f | 4658 | rtx or_mask; |
ccfa01f5 | 4659 | |
51356f86 | 4660 | if (BITS_BIG_ENDIAN) |
ded805e6 | 4661 | pos = GET_MODE_PRECISION (mode) - len - pos; |
ccfa01f5 | 4662 | |
2a809e1f | 4663 | or_mask = gen_int_mode (src << pos, mode); |
02e7a332 | 4664 | if (src == mask) |
ccfa01f5 | 4665 | SUBST (SET_SRC (x), |
2a809e1f | 4666 | simplify_gen_binary (IOR, mode, dest, or_mask)); |
ccfa01f5 | 4667 | else |
800a7def | 4668 | { |
4669 | rtx negmask = gen_int_mode (~(mask << pos), mode); | |
4670 | SUBST (SET_SRC (x), | |
4671 | simplify_gen_binary (IOR, mode, | |
a0c938f0 | 4672 | simplify_gen_binary (AND, mode, |
800a7def | 4673 | dest, negmask), |
2a809e1f | 4674 | or_mask)); |
800a7def | 4675 | } |
ccfa01f5 | 4676 | |
4677 | SUBST (SET_DEST (x), dest); | |
4678 | ||
b420d71b | 4679 | split = find_split_point (&SET_SRC (x), insn, true); |
ccfa01f5 | 4680 | if (split && split != &SET_SRC (x)) |
4681 | return split; | |
4682 | } | |
4683 | ||
4684 | /* Otherwise, see if this is an operation that we can split into two. | |
4685 | If so, try to split that. */ | |
4686 | code = GET_CODE (SET_SRC (x)); | |
4687 | ||
4688 | switch (code) | |
4689 | { | |
ec90760f | 4690 | case AND: |
4691 | /* If we are AND'ing with a large constant that is only a single | |
4692 | bit and the result is only being used in a context where we | |
d10cfa8d | 4693 | need to know if it is zero or nonzero, replace it with a bit |
ec90760f | 4694 | extraction. This will avoid the large constant, which might |
4695 | have taken more than one insn to make. If the constant were | |
4696 | not a valid argument to the AND but took only one insn to make, | |
4697 | this is no worse, but if it took more than one insn, it will | |
4698 | be better. */ | |
4699 | ||
971ba038 | 4700 | if (CONST_INT_P (XEXP (SET_SRC (x), 1)) |
8ad4c111 | 4701 | && REG_P (XEXP (SET_SRC (x), 0)) |
897c6c81 | 4702 | && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7 |
8ad4c111 | 4703 | && REG_P (SET_DEST (x)) |
35330d19 | 4704 | && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0 |
ec90760f | 4705 | && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) |
4706 | && XEXP (*split, 0) == SET_DEST (x) | |
4707 | && XEXP (*split, 1) == const0_rtx) | |
4708 | { | |
4dad978c | 4709 | rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), |
4710 | XEXP (SET_SRC (x), 0), | |
4711 | pos, NULL_RTX, 1, 1, 0, 0); | |
4712 | if (extraction != 0) | |
4713 | { | |
4714 | SUBST (SET_SRC (x), extraction); | |
b420d71b | 4715 | return find_split_point (loc, insn, false); |
4dad978c | 4716 | } |
ec90760f | 4717 | } |
4718 | break; | |
4719 | ||
648c610e | 4720 | case NE: |
b4b174c3 | 4721 | /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X |
2c0e001b | 4722 | is known to be on, this can be converted into a NEG of a shift. */ |
648c610e | 4723 | if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx |
4724 | && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) | |
63db35a4 | 4725 | && 1 <= (pos = exact_log2 |
648c610e | 4726 | (nonzero_bits (XEXP (SET_SRC (x), 0), |
4727 | GET_MODE (XEXP (SET_SRC (x), 0)))))) | |
4728 | { | |
4729 | enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); | |
4730 | ||
4731 | SUBST (SET_SRC (x), | |
3380b197 | 4732 | gen_rtx_NEG (mode, |
4733 | gen_rtx_LSHIFTRT (mode, | |
4734 | XEXP (SET_SRC (x), 0), | |
4735 | GEN_INT (pos)))); | |
648c610e | 4736 | |
b420d71b | 4737 | split = find_split_point (&SET_SRC (x), insn, true); |
648c610e | 4738 | if (split && split != &SET_SRC (x)) |
4739 | return split; | |
4740 | } | |
4741 | break; | |
4742 | ||
ccfa01f5 | 4743 | case SIGN_EXTEND: |
4744 | inner = XEXP (SET_SRC (x), 0); | |
f367afaa | 4745 | |
4746 | /* We can't optimize if either mode is a partial integer | |
4747 | mode as we don't know how many bits are significant | |
4748 | in those modes. */ | |
4749 | if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT | |
4750 | || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) | |
4751 | break; | |
4752 | ||
ccfa01f5 | 4753 | pos = 0; |
ded805e6 | 4754 | len = GET_MODE_PRECISION (GET_MODE (inner)); |
ccfa01f5 | 4755 | unsignedp = 0; |
4756 | break; | |
4757 | ||
4758 | case SIGN_EXTRACT: | |
4759 | case ZERO_EXTRACT: | |
971ba038 | 4760 | if (CONST_INT_P (XEXP (SET_SRC (x), 1)) |
4761 | && CONST_INT_P (XEXP (SET_SRC (x), 2))) | |
ccfa01f5 | 4762 | { |
4763 | inner = XEXP (SET_SRC (x), 0); | |
4764 | len = INTVAL (XEXP (SET_SRC (x), 1)); | |
4765 | pos = INTVAL (XEXP (SET_SRC (x), 2)); | |
4766 | ||
51356f86 | 4767 | if (BITS_BIG_ENDIAN) |
ded805e6 | 4768 | pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos; |
ccfa01f5 | 4769 | unsignedp = (code == ZERO_EXTRACT); |
4770 | } | |
4771 | break; | |
0dbd1c74 | 4772 | |
4773 | default: | |
4774 | break; | |
ccfa01f5 | 4775 | } |
4776 | ||
ded805e6 | 4777 | if (len && pos >= 0 |
4778 | && pos + len <= GET_MODE_PRECISION (GET_MODE (inner))) | |
ccfa01f5 | 4779 | { |
4780 | enum machine_mode mode = GET_MODE (SET_SRC (x)); | |
4781 | ||
ec90760f | 4782 | /* For unsigned, we have a choice of a shift followed by an |
4783 | AND or two shifts. Use two shifts for field sizes where the | |
4784 | constant might be too large. We assume here that we can | |
4785 | always at least get 8-bit constants in an AND insn, which is | |
4786 | true for every current RISC. */ | |
4787 | ||
4788 | if (unsignedp && len <= 8) | |
ccfa01f5 | 4789 | { |
c338f2e3 | 4790 | unsigned HOST_WIDE_INT mask |
4791 | = ((unsigned HOST_WIDE_INT) 1 << len) - 1; | |
ccfa01f5 | 4792 | SUBST (SET_SRC (x), |
3380b197 | 4793 | gen_rtx_AND (mode, |
4794 | gen_rtx_LSHIFTRT | |
316f48ea | 4795 | (mode, gen_lowpart (mode, inner), |
3380b197 | 4796 | GEN_INT (pos)), |
c338f2e3 | 4797 | gen_int_mode (mask, mode))); |
ccfa01f5 | 4798 | |
b420d71b | 4799 | split = find_split_point (&SET_SRC (x), insn, true); |
ccfa01f5 | 4800 | if (split && split != &SET_SRC (x)) |
4801 | return split; | |
4802 | } | |
4803 | else | |
4804 | { | |
4805 | SUBST (SET_SRC (x), | |
3380b197 | 4806 | gen_rtx_fmt_ee |
ec90760f | 4807 | (unsignedp ? LSHIFTRT : ASHIFTRT, mode, |
3380b197 | 4808 | gen_rtx_ASHIFT (mode, |
316f48ea | 4809 | gen_lowpart (mode, inner), |
ded805e6 | 4810 | GEN_INT (GET_MODE_PRECISION (mode) |
3380b197 | 4811 | - len - pos)), |
ded805e6 | 4812 | GEN_INT (GET_MODE_PRECISION (mode) - len))); |
ccfa01f5 | 4813 | |
b420d71b | 4814 | split = find_split_point (&SET_SRC (x), insn, true); |
ccfa01f5 | 4815 | if (split && split != &SET_SRC (x)) |
4816 | return split; | |
4817 | } | |
4818 | } | |
4819 | ||
4820 | /* See if this is a simple operation with a constant as the second | |
4821 | operand. It might be that this constant is out of range and hence | |
4822 | could be used as a split point. */ | |
6720e96c | 4823 | if (BINARY_P (SET_SRC (x)) |
ccfa01f5 | 4824 | && CONSTANT_P (XEXP (SET_SRC (x), 1)) |
6720e96c | 4825 | && (OBJECT_P (XEXP (SET_SRC (x), 0)) |
ccfa01f5 | 4826 | || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG |
6720e96c | 4827 | && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0)))))) |
ccfa01f5 | 4828 | return &XEXP (SET_SRC (x), 1); |
4829 | ||
4830 | /* Finally, see if this is a simple operation with its first operand | |
4831 | not in a register. The operation might require this operand in a | |
4832 | register, so return it as a split point. We can always do this | |
4833 | because if the first operand were another operation, we would have | |
4834 | already found it as a split point. */ | |
6720e96c | 4835 | if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x))) |
ccfa01f5 | 4836 | && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) |
4837 | return &XEXP (SET_SRC (x), 0); | |
4838 | ||
4839 | return 0; | |
4840 | ||
4841 | case AND: | |
4842 | case IOR: | |
4843 | /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, | |
4844 | it is better to write this as (not (ior A B)) so we can split it. | |
4845 | Similarly for IOR. */ | |
4846 | if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) | |
4847 | { | |
4848 | SUBST (*loc, | |
3380b197 | 4849 | gen_rtx_NOT (GET_MODE (x), |
4850 | gen_rtx_fmt_ee (code == IOR ? AND : IOR, | |
4851 | GET_MODE (x), | |
4852 | XEXP (XEXP (x, 0), 0), | |
4853 | XEXP (XEXP (x, 1), 0)))); | |
b420d71b | 4854 | return find_split_point (loc, insn, set_src); |
ccfa01f5 | 4855 | } |
4856 | ||
4857 | /* Many RISC machines have a large set of logical insns. If the | |
4858 | second operand is a NOT, put it first so we will try to split the | |
4859 | other operand first. */ | |
4860 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
4861 | { | |
4862 | rtx tem = XEXP (x, 0); | |
4863 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
4864 | SUBST (XEXP (x, 1), tem); | |
4865 | } | |
4866 | break; | |
0dbd1c74 | 4867 | |
b420d71b | 4868 | case PLUS: |
4869 | case MINUS: | |
dcbd909c | 4870 | /* Canonicalization can produce (minus A (mult B C)), where C is a |
4871 | constant. It may be better to try splitting (plus (mult B -C) A) | |
4872 | instead if this isn't a multiply by a power of two. */ | |
4873 | if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT | |
4874 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
4875 | && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0) | |
4876 | { | |
4877 | enum machine_mode mode = GET_MODE (x); | |
4878 | unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1)); | |
4879 | HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode); | |
c338f2e3 | 4880 | SUBST (*loc, gen_rtx_PLUS (mode, |
4881 | gen_rtx_MULT (mode, | |
4882 | XEXP (XEXP (x, 1), 0), | |
4883 | gen_int_mode (other_int, | |
4884 | mode)), | |
dcbd909c | 4885 | XEXP (x, 0))); |
4886 | return find_split_point (loc, insn, set_src); | |
4887 | } | |
4888 | ||
b420d71b | 4889 | /* Split at a multiply-accumulate instruction. However if this is |
4890 | the SET_SRC, we likely do not have such an instruction and it's | |
4891 | worthless to try this split. */ | |
4892 | if (!set_src && GET_CODE (XEXP (x, 0)) == MULT) | |
4893 | return loc; | |
4894 | ||
0dbd1c74 | 4895 | default: |
4896 | break; | |
ccfa01f5 | 4897 | } |
4898 | ||
4899 | /* Otherwise, select our actions depending on our rtx class. */ | |
4900 | switch (GET_RTX_CLASS (code)) | |
4901 | { | |
6720e96c | 4902 | case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ |
4903 | case RTX_TERNARY: | |
b420d71b | 4904 | split = find_split_point (&XEXP (x, 2), insn, false); |
ccfa01f5 | 4905 | if (split) |
4906 | return split; | |
a92771b8 | 4907 | /* ... fall through ... */ |
6720e96c | 4908 | case RTX_BIN_ARITH: |
4909 | case RTX_COMM_ARITH: | |
4910 | case RTX_COMPARE: | |
4911 | case RTX_COMM_COMPARE: | |
b420d71b | 4912 | split = find_split_point (&XEXP (x, 1), insn, false); |
ccfa01f5 | 4913 | if (split) |
4914 | return split; | |
a92771b8 | 4915 | /* ... fall through ... */ |
6720e96c | 4916 | case RTX_UNARY: |
ccfa01f5 | 4917 | /* Some machines have (and (shift ...) ...) insns. If X is not |
4918 | an AND, but XEXP (X, 0) is, use it as our split point. */ | |
4919 | if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) | |
4920 | return &XEXP (x, 0); | |
4921 | ||
b420d71b | 4922 | split = find_split_point (&XEXP (x, 0), insn, false); |
ccfa01f5 | 4923 | if (split) |
4924 | return split; | |
4925 | return loc; | |
ccfa01f5 | 4926 | |
6720e96c | 4927 | default: |
4928 | /* Otherwise, we don't have a split point. */ | |
4929 | return 0; | |
4930 | } | |
ccfa01f5 | 4931 | } |
4932 | \f | |
4933 | /* Throughout X, replace FROM with TO, and return the result. | |
4934 | The result is TO if X is FROM; | |
4935 | otherwise the result is X, but its contents may have been modified. | |
4936 | If they were modified, a record was made in undobuf so that | |
4937 | undo_all will (among other things) return X to its original state. | |
4938 | ||
4939 | If the number of changes necessary is too much to record to undo, | |
4940 | the excess changes are not made, so the result is invalid. | |
4941 | The changes already made can still be undone. | |
4942 | undobuf.num_undo is incremented for such changes, so by testing that | |
4943 | the caller can tell whether the result is valid. | |
4944 | ||
4945 | `n_occurrences' is incremented each time FROM is replaced. | |
510f7125 | 4946 | |
d10cfa8d | 4947 | IN_DEST is nonzero if we are processing the SET_DEST of a SET. |
ccfa01f5 | 4948 | |
34dd021c | 4949 | IN_COND is nonzero if we are at the top level of a condition. |
4950 | ||
d10cfa8d | 4951 | UNIQUE_COPY is nonzero if each substitution must be unique. We do this |
4952 | by copying if `n_occurrences' is nonzero. */ | |
ccfa01f5 | 4953 | |
4954 | static rtx | |
34dd021c | 4955 | subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy) |
ccfa01f5 | 4956 | { |
19cb6b50 | 4957 | enum rtx_code code = GET_CODE (x); |
ccfa01f5 | 4958 | enum machine_mode op0_mode = VOIDmode; |
19cb6b50 | 4959 | const char *fmt; |
4960 | int len, i; | |
d328ebdf | 4961 | rtx new_rtx; |
ccfa01f5 | 4962 | |
4963 | /* Two expressions are equal if they are identical copies of a shared | |
4964 | RTX or if they are both registers with the same register number | |
4965 | and mode. */ | |
4966 | ||
4967 | #define COMBINE_RTX_EQUAL_P(X,Y) \ | |
4968 | ((X) == (Y) \ | |
8ad4c111 | 4969 | || (REG_P (X) && REG_P (Y) \ |
ccfa01f5 | 4970 | && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) |
4971 | ||
6a8bc4ac | 4972 | /* Do not substitute into clobbers of regs -- this will never result in |
4973 | valid RTL. */ | |
4974 | if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0))) | |
4975 | return x; | |
4976 | ||
ccfa01f5 | 4977 | if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) |
4978 | { | |
4979 | n_occurrences++; | |
4980 | return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); | |
4981 | } | |
4982 | ||
3072d30e | 4983 | /* If X and FROM are the same register but different modes, they |
4984 | will not have been seen as equal above. However, the log links code | |
4985 | will make a LOG_LINKS entry for that case. If we do nothing, we | |
4986 | will try to rerecognize our original insn and, when it succeeds, | |
4987 | we will delete the feeding insn, which is incorrect. | |
ccfa01f5 | 4988 | |
4989 | So force this insn not to match in this (rare) case. */ | |
8ad4c111 | 4990 | if (! in_dest && code == REG && REG_P (from) |
6644b3a8 | 4991 | && reg_overlap_mentioned_p (x, from)) |
941522d6 | 4992 | return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
ccfa01f5 | 4993 | |
4994 | /* If this is an object, we are done unless it is a MEM or LO_SUM, both | |
4995 | of which may contain things that can be combined. */ | |
6720e96c | 4996 | if (code != MEM && code != LO_SUM && OBJECT_P (x)) |
ccfa01f5 | 4997 | return x; |
4998 | ||
4999 | /* It is possible to have a subexpression appear twice in the insn. | |
5000 | Suppose that FROM is a register that appears within TO. | |
5001 | Then, after that subexpression has been scanned once by `subst', | |
5002 | the second time it is scanned, TO may be found. If we were | |
5003 | to scan TO here, we would find FROM within it and create a | |
5004 | self-referent rtl structure which is completely wrong. */ | |
5005 | if (COMBINE_RTX_EQUAL_P (x, to)) | |
5006 | return to; | |
5007 | ||
590b7e80 | 5008 | /* Parallel asm_operands need special attention because all of the |
5009 | inputs are shared across the arms. Furthermore, unsharing the | |
5010 | rtl results in recognition failures. Failure to handle this case | |
5011 | specially can result in circular rtl. | |
5012 | ||
5013 | Solve this by doing a normal pass across the first entry of the | |
5014 | parallel, and only processing the SET_DESTs of the subsequent | |
5015 | entries. Ug. */ | |
5016 | ||
5017 | if (code == PARALLEL | |
5018 | && GET_CODE (XVECEXP (x, 0, 0)) == SET | |
5019 | && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) | |
ccfa01f5 | 5020 | { |
34dd021c | 5021 | new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy); |
590b7e80 | 5022 | |
5023 | /* If this substitution failed, this whole thing fails. */ | |
d328ebdf | 5024 | if (GET_CODE (new_rtx) == CLOBBER |
5025 | && XEXP (new_rtx, 0) == const0_rtx) | |
5026 | return new_rtx; | |
590b7e80 | 5027 | |
d328ebdf | 5028 | SUBST (XVECEXP (x, 0, 0), new_rtx); |
590b7e80 | 5029 | |
5030 | for (i = XVECLEN (x, 0) - 1; i >= 1; i--) | |
ccfa01f5 | 5031 | { |
590b7e80 | 5032 | rtx dest = SET_DEST (XVECEXP (x, 0, i)); |
510f7125 | 5033 | |
8ad4c111 | 5034 | if (!REG_P (dest) |
590b7e80 | 5035 | && GET_CODE (dest) != CC0 |
5036 | && GET_CODE (dest) != PC) | |
ccfa01f5 | 5037 | { |
34dd021c | 5038 | new_rtx = subst (dest, from, to, 0, 0, unique_copy); |
ccfa01f5 | 5039 | |
590b7e80 | 5040 | /* If this substitution failed, this whole thing fails. */ |
d328ebdf | 5041 | if (GET_CODE (new_rtx) == CLOBBER |
5042 | && XEXP (new_rtx, 0) == const0_rtx) | |
5043 | return new_rtx; | |
ccfa01f5 | 5044 | |
d328ebdf | 5045 | SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx); |
ccfa01f5 | 5046 | } |
5047 | } | |
590b7e80 | 5048 | } |
5049 | else | |
5050 | { | |
5051 | len = GET_RTX_LENGTH (code); | |
5052 | fmt = GET_RTX_FORMAT (code); | |
5053 | ||
5054 | /* We don't need to process a SET_DEST that is a register, CC0, | |
5055 | or PC, so set up to skip this common case. All other cases | |
5056 | where we want to suppress replacing something inside a | |
5057 | SET_SRC are handled via the IN_DEST operand. */ | |
5058 | if (code == SET | |
8ad4c111 | 5059 | && (REG_P (SET_DEST (x)) |
590b7e80 | 5060 | || GET_CODE (SET_DEST (x)) == CC0 |
5061 | || GET_CODE (SET_DEST (x)) == PC)) | |
5062 | fmt = "ie"; | |
5063 | ||
5064 | /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a | |
5065 | constant. */ | |
5066 | if (fmt[0] == 'e') | |
5067 | op0_mode = GET_MODE (XEXP (x, 0)); | |
5068 | ||
5069 | for (i = 0; i < len; i++) | |
ccfa01f5 | 5070 | { |
590b7e80 | 5071 | if (fmt[i] == 'E') |
ccfa01f5 | 5072 | { |
19cb6b50 | 5073 | int j; |
590b7e80 | 5074 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
5075 | { | |
5076 | if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) | |
5077 | { | |
d328ebdf | 5078 | new_rtx = (unique_copy && n_occurrences |
590b7e80 | 5079 | ? copy_rtx (to) : to); |
5080 | n_occurrences++; | |
5081 | } | |
5082 | else | |
5083 | { | |
34dd021c | 5084 | new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0, |
5085 | unique_copy); | |
590b7e80 | 5086 | |
5087 | /* If this substitution failed, this whole thing | |
5088 | fails. */ | |
d328ebdf | 5089 | if (GET_CODE (new_rtx) == CLOBBER |
5090 | && XEXP (new_rtx, 0) == const0_rtx) | |
5091 | return new_rtx; | |
590b7e80 | 5092 | } |
5093 | ||
d328ebdf | 5094 | SUBST (XVECEXP (x, i, j), new_rtx); |
590b7e80 | 5095 | } |
5096 | } | |
5097 | else if (fmt[i] == 'e') | |
5098 | { | |
5063ebe7 | 5099 | /* If this is a register being set, ignore it. */ |
d328ebdf | 5100 | new_rtx = XEXP (x, i); |
5063ebe7 | 5101 | if (in_dest |
5063ebe7 | 5102 | && i == 0 |
76dada20 | 5103 | && (((code == SUBREG || code == ZERO_EXTRACT) |
d328ebdf | 5104 | && REG_P (new_rtx)) |
76dada20 | 5105 | || code == STRICT_LOW_PART)) |
5063ebe7 | 5106 | ; |
5107 | ||
5108 | else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) | |
590b7e80 | 5109 | { |
5110 | /* In general, don't install a subreg involving two | |
5111 | modes not tieable. It can worsen register | |
5112 | allocation, and can even make invalid reload | |
5113 | insns, since the reg inside may need to be copied | |
5114 | from in the outside mode, and that may be invalid | |
5115 | if it is an fp reg copied in integer mode. | |
5116 | ||
5117 | We allow two exceptions to this: It is valid if | |
5118 | it is inside another SUBREG and the mode of that | |
5119 | SUBREG and the mode of the inside of TO is | |
5120 | tieable and it is valid if X is a SET that copies | |
5121 | FROM to CC0. */ | |
5122 | ||
5123 | if (GET_CODE (to) == SUBREG | |
5124 | && ! MODES_TIEABLE_P (GET_MODE (to), | |
5125 | GET_MODE (SUBREG_REG (to))) | |
5126 | && ! (code == SUBREG | |
5127 | && MODES_TIEABLE_P (GET_MODE (x), | |
5128 | GET_MODE (SUBREG_REG (to)))) | |
5563ada6 | 5129 | #ifdef HAVE_cc0 |
590b7e80 | 5130 | && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) |
5563ada6 | 5131 | #endif |
590b7e80 | 5132 | ) |
5133 | return gen_rtx_CLOBBER (VOIDmode, const0_rtx); | |
5563ada6 | 5134 | |
370e2b8b | 5135 | if (code == SUBREG |
8ad4c111 | 5136 | && REG_P (to) |
370e2b8b | 5137 | && REGNO (to) < FIRST_PSEUDO_REGISTER |
b46f6809 | 5138 | && simplify_subreg_regno (REGNO (to), GET_MODE (to), |
5139 | SUBREG_BYTE (x), | |
5140 | GET_MODE (x)) < 0) | |
370e2b8b | 5141 | return gen_rtx_CLOBBER (VOIDmode, const0_rtx); |
370e2b8b | 5142 | |
d328ebdf | 5143 | new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to); |
590b7e80 | 5144 | n_occurrences++; |
5145 | } | |
5146 | else | |
5147 | /* If we are in a SET_DEST, suppress most cases unless we | |
5148 | have gone inside a MEM, in which case we want to | |
5149 | simplify the address. We assume here that things that | |
5150 | are actually part of the destination have their inner | |
510f7125 | 5151 | parts in the first expression. This is true for SUBREG, |
590b7e80 | 5152 | STRICT_LOW_PART, and ZERO_EXTRACT, which are the only |
5153 | things aside from REG and MEM that should appear in a | |
5154 | SET_DEST. */ | |
d328ebdf | 5155 | new_rtx = subst (XEXP (x, i), from, to, |
590b7e80 | 5156 | (((in_dest |
5157 | && (code == SUBREG || code == STRICT_LOW_PART | |
5158 | || code == ZERO_EXTRACT)) | |
5159 | || code == SET) | |
34dd021c | 5160 | && i == 0), |
5161 | code == IF_THEN_ELSE && i == 0, | |
5162 | unique_copy); | |
590b7e80 | 5163 | |
5164 | /* If we found that we will have to reject this combination, | |
5165 | indicate that by returning the CLOBBER ourselves, rather than | |
5166 | an expression containing it. This will speed things up as | |
5167 | well as prevent accidents where two CLOBBERs are considered | |
5168 | to be equal, thus producing an incorrect simplification. */ | |
5169 | ||
d328ebdf | 5170 | if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx) |
5171 | return new_rtx; | |
590b7e80 | 5172 | |
efa08fc2 | 5173 | if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx)) |
bd72d0ee | 5174 | { |
ae065618 | 5175 | enum machine_mode mode = GET_MODE (x); |
ba06212f | 5176 | |
d328ebdf | 5177 | x = simplify_subreg (GET_MODE (x), new_rtx, |
bd72d0ee | 5178 | GET_MODE (SUBREG_REG (x)), |
5179 | SUBREG_BYTE (x)); | |
5180 | if (! x) | |
ae065618 | 5181 | x = gen_rtx_CLOBBER (mode, const0_rtx); |
bd72d0ee | 5182 | } |
e913b5cd | 5183 | else if (CONST_SCALAR_INT_P (new_rtx) |
bd72d0ee | 5184 | && GET_CODE (x) == ZERO_EXTEND) |
5185 | { | |
5186 | x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
d328ebdf | 5187 | new_rtx, GET_MODE (XEXP (x, 0))); |
cc636d56 | 5188 | gcc_assert (x); |
bd72d0ee | 5189 | } |
5190 | else | |
d328ebdf | 5191 | SUBST (XEXP (x, i), new_rtx); |
ccfa01f5 | 5192 | } |
ccfa01f5 | 5193 | } |
5194 | } | |
5195 | ||
aa70f65e | 5196 | /* Check if we are loading something from the constant pool via float |
5197 | extension; in this case we would undo compress_float_constant | |
5198 | optimization and degenerate constant load to an immediate value. */ | |
5199 | if (GET_CODE (x) == FLOAT_EXTEND | |
5200 | && MEM_P (XEXP (x, 0)) | |
5201 | && MEM_READONLY_P (XEXP (x, 0))) | |
5202 | { | |
5203 | rtx tmp = avoid_constant_pool_reference (x); | |
5204 | if (x != tmp) | |
5205 | return x; | |
5206 | } | |
5207 | ||
2b0f64f9 | 5208 | /* Try to simplify X. If the simplification changed the code, it is likely |
5209 | that further simplification will help, so loop, but limit the number | |
5210 | of repetitions that will be performed. */ | |
5211 | ||
5212 | for (i = 0; i < 4; i++) | |
5213 | { | |
5214 | /* If X is sufficiently simple, don't bother trying to do anything | |
5215 | with it. */ | |
5216 | if (code != CONST_INT && code != REG && code != CLOBBER) | |
34dd021c | 5217 | x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond); |
ec90760f | 5218 | |
2b0f64f9 | 5219 | if (GET_CODE (x) == code) |
5220 | break; | |
ec90760f | 5221 | |
2b0f64f9 | 5222 | code = GET_CODE (x); |
bb713f36 | 5223 | |
2b0f64f9 | 5224 | /* We no longer know the original mode of operand 0 since we |
5225 | have changed the form of X) */ | |
5226 | op0_mode = VOIDmode; | |
5227 | } | |
bb713f36 | 5228 | |
2b0f64f9 | 5229 | return x; |
5230 | } | |
5231 | \f | |
5232 | /* Simplify X, a piece of RTL. We just operate on the expression at the | |
5233 | outer level; call `subst' to simplify recursively. Return the new | |
5234 | expression. | |
5235 | ||
d7ef6792 | 5236 | OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero |
34dd021c | 5237 | if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level |
5238 | of a condition. */ | |
bb713f36 | 5239 | |
2b0f64f9 | 5240 | static rtx |
34dd021c | 5241 | combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest, |
5242 | int in_cond) | |
2b0f64f9 | 5243 | { |
5244 | enum rtx_code code = GET_CODE (x); | |
5245 | enum machine_mode mode = GET_MODE (x); | |
5246 | rtx temp; | |
5247 | int i; | |
ec90760f | 5248 | |
ccfa01f5 | 5249 | /* If this is a commutative operation, put a constant last and a complex |
5250 | expression first. We don't need to do this for comparisons here. */ | |
6720e96c | 5251 | if (COMMUTATIVE_ARITH_P (x) |
09f800b9 | 5252 | && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) |
ccfa01f5 | 5253 | { |
5254 | temp = XEXP (x, 0); | |
5255 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
5256 | SUBST (XEXP (x, 1), temp); | |
5257 | } | |
5258 | ||
510f7125 | 5259 | /* If this is a simple operation applied to an IF_THEN_ELSE, try |
ec90760f | 5260 | applying it to the arms of the IF_THEN_ELSE. This often simplifies |
862e4898 | 5261 | things. Check for cases where both arms are testing the same |
5262 | condition. | |
5263 | ||
5264 | Don't do anything if all operands are very simple. */ | |
5265 | ||
6720e96c | 5266 | if ((BINARY_P (x) |
5267 | && ((!OBJECT_P (XEXP (x, 0)) | |
862e4898 | 5268 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
6720e96c | 5269 | && OBJECT_P (SUBREG_REG (XEXP (x, 0))))) |
5270 | || (!OBJECT_P (XEXP (x, 1)) | |
862e4898 | 5271 | && ! (GET_CODE (XEXP (x, 1)) == SUBREG |
6720e96c | 5272 | && OBJECT_P (SUBREG_REG (XEXP (x, 1))))))) |
5273 | || (UNARY_P (x) | |
a0c938f0 | 5274 | && (!OBJECT_P (XEXP (x, 0)) |
862e4898 | 5275 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
6720e96c | 5276 | && OBJECT_P (SUBREG_REG (XEXP (x, 0))))))) |
ec90760f | 5277 | { |
9c811526 | 5278 | rtx cond, true_rtx, false_rtx; |
862e4898 | 5279 | |
9c811526 | 5280 | cond = if_then_else_cond (x, &true_rtx, &false_rtx); |
7feddf73 | 5281 | if (cond != 0 |
5282 | /* If everything is a comparison, what we have is highly unlikely | |
5283 | to be simpler, so don't use it. */ | |
6720e96c | 5284 | && ! (COMPARISON_P (x) |
5285 | && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))) | |
862e4898 | 5286 | { |
5287 | rtx cop1 = const0_rtx; | |
5288 | enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); | |
5289 | ||
6720e96c | 5290 | if (cond_code == NE && COMPARISON_P (cond)) |
04310098 | 5291 | return x; |
5292 | ||
510f7125 | 5293 | /* Simplify the alternative arms; this may collapse the true and |
6b34f88c | 5294 | false arms to store-flag values. Be careful to use copy_rtx |
5295 | here since true_rtx or false_rtx might share RTL with x as a | |
5296 | result of the if_then_else_cond call above. */ | |
34dd021c | 5297 | true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0); |
5298 | false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0); | |
5056f17b | 5299 | |
9c811526 | 5300 | /* If true_rtx and false_rtx are not general_operands, an if_then_else |
6587e23e | 5301 | is unlikely to be simpler. */ |
9c811526 | 5302 | if (general_operand (true_rtx, VOIDmode) |
5303 | && general_operand (false_rtx, VOIDmode)) | |
6587e23e | 5304 | { |
b0bb7395 | 5305 | enum rtx_code reversed; |
5306 | ||
6587e23e | 5307 | /* Restarting if we generate a store-flag expression will cause |
5308 | us to loop. Just drop through in this case. */ | |
5309 | ||
5310 | /* If the result values are STORE_FLAG_VALUE and zero, we can | |
5311 | just make the comparison operation. */ | |
9c811526 | 5312 | if (true_rtx == const_true_rtx && false_rtx == const0_rtx) |
800a7def | 5313 | x = simplify_gen_relational (cond_code, mode, VOIDmode, |
5314 | cond, cop1); | |
8e74bbdf | 5315 | else if (true_rtx == const0_rtx && false_rtx == const_true_rtx |
b0bb7395 | 5316 | && ((reversed = reversed_comparison_code_parts |
d598ad0d | 5317 | (cond_code, cond, cop1, NULL)) |
a0c938f0 | 5318 | != UNKNOWN)) |
800a7def | 5319 | x = simplify_gen_relational (reversed, mode, VOIDmode, |
5320 | cond, cop1); | |
6587e23e | 5321 | |
5322 | /* Likewise, we can make the negate of a comparison operation | |
5323 | if the result values are - STORE_FLAG_VALUE and zero. */ | |
971ba038 | 5324 | else if (CONST_INT_P (true_rtx) |
9c811526 | 5325 | && INTVAL (true_rtx) == - STORE_FLAG_VALUE |
5326 | && false_rtx == const0_rtx) | |
3380b197 | 5327 | x = simplify_gen_unary (NEG, mode, |
800a7def | 5328 | simplify_gen_relational (cond_code, |
5329 | mode, VOIDmode, | |
5330 | cond, cop1), | |
3380b197 | 5331 | mode); |
971ba038 | 5332 | else if (CONST_INT_P (false_rtx) |
9c811526 | 5333 | && INTVAL (false_rtx) == - STORE_FLAG_VALUE |
b0bb7395 | 5334 | && true_rtx == const0_rtx |
5335 | && ((reversed = reversed_comparison_code_parts | |
d598ad0d | 5336 | (cond_code, cond, cop1, NULL)) |
a0c938f0 | 5337 | != UNKNOWN)) |
3380b197 | 5338 | x = simplify_gen_unary (NEG, mode, |
800a7def | 5339 | simplify_gen_relational (reversed, |
5340 | mode, VOIDmode, | |
5341 | cond, cop1), | |
3380b197 | 5342 | mode); |
6587e23e | 5343 | else |
5344 | return gen_rtx_IF_THEN_ELSE (mode, | |
800a7def | 5345 | simplify_gen_relational (cond_code, |
5346 | mode, | |
5347 | VOIDmode, | |
5348 | cond, | |
5349 | cop1), | |
9c811526 | 5350 | true_rtx, false_rtx); |
9bab13ca | 5351 | |
6587e23e | 5352 | code = GET_CODE (x); |
5353 | op0_mode = VOIDmode; | |
5354 | } | |
862e4898 | 5355 | } |
ec90760f | 5356 | } |
5357 | ||
ccfa01f5 | 5358 | /* Try to fold this expression in case we have constants that weren't |
5359 | present before. */ | |
5360 | temp = 0; | |
5361 | switch (GET_RTX_CLASS (code)) | |
5362 | { | |
6720e96c | 5363 | case RTX_UNARY: |
115addd6 | 5364 | if (op0_mode == VOIDmode) |
5365 | op0_mode = GET_MODE (XEXP (x, 0)); | |
ccfa01f5 | 5366 | temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); |
5367 | break; | |
6720e96c | 5368 | case RTX_COMPARE: |
5369 | case RTX_COMM_COMPARE: | |
67405ba4 | 5370 | { |
5371 | enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); | |
5372 | if (cmp_mode == VOIDmode) | |
ec68004d | 5373 | { |
5374 | cmp_mode = GET_MODE (XEXP (x, 1)); | |
5375 | if (cmp_mode == VOIDmode) | |
5376 | cmp_mode = op0_mode; | |
5377 | } | |
089b4730 | 5378 | temp = simplify_relational_operation (code, mode, cmp_mode, |
67405ba4 | 5379 | XEXP (x, 0), XEXP (x, 1)); |
5380 | } | |
ccfa01f5 | 5381 | break; |
6720e96c | 5382 | case RTX_COMM_ARITH: |
5383 | case RTX_BIN_ARITH: | |
ccfa01f5 | 5384 | temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); |
5385 | break; | |
6720e96c | 5386 | case RTX_BITFIELD_OPS: |
5387 | case RTX_TERNARY: | |
ccfa01f5 | 5388 | temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), |
5389 | XEXP (x, 1), XEXP (x, 2)); | |
5390 | break; | |
6720e96c | 5391 | default: |
5392 | break; | |
ccfa01f5 | 5393 | } |
5394 | ||
5395 | if (temp) | |
b94b03fb | 5396 | { |
5397 | x = temp; | |
5398 | code = GET_CODE (temp); | |
5399 | op0_mode = VOIDmode; | |
5400 | mode = GET_MODE (temp); | |
5401 | } | |
ccfa01f5 | 5402 | |
ccfa01f5 | 5403 | /* First see if we can apply the inverse distributive law. */ |
98a1ef9c | 5404 | if (code == PLUS || code == MINUS |
5405 | || code == AND || code == IOR || code == XOR) | |
ccfa01f5 | 5406 | { |
5407 | x = apply_distributive_law (x); | |
5408 | code = GET_CODE (x); | |
cc566b64 | 5409 | op0_mode = VOIDmode; |
ccfa01f5 | 5410 | } |
5411 | ||
5412 | /* If CODE is an associative operation not otherwise handled, see if we | |
5413 | can associate some operands. This can win if they are constants or | |
81802af6 | 5414 | if they are logically related (i.e. (a & b) & a). */ |
a0fd8a81 | 5415 | if ((code == PLUS || code == MINUS || code == MULT || code == DIV |
5416 | || code == AND || code == IOR || code == XOR | |
ccfa01f5 | 5417 | || code == SMAX || code == SMIN || code == UMAX || code == UMIN) |
a0fd8a81 | 5418 | && ((INTEGRAL_MODE_P (mode) && code != DIV) |
49d060d7 | 5419 | || (flag_associative_math && FLOAT_MODE_P (mode)))) |
ccfa01f5 | 5420 | { |
5421 | if (GET_CODE (XEXP (x, 0)) == code) | |
5422 | { | |
5423 | rtx other = XEXP (XEXP (x, 0), 0); | |
5424 | rtx inner_op0 = XEXP (XEXP (x, 0), 1); | |
5425 | rtx inner_op1 = XEXP (x, 1); | |
5426 | rtx inner; | |
510f7125 | 5427 | |
ccfa01f5 | 5428 | /* Make sure we pass the constant operand if any as the second |
5429 | one if this is a commutative operation. */ | |
6720e96c | 5430 | if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x)) |
ccfa01f5 | 5431 | { |
5432 | rtx tem = inner_op0; | |
5433 | inner_op0 = inner_op1; | |
5434 | inner_op1 = tem; | |
5435 | } | |
5436 | inner = simplify_binary_operation (code == MINUS ? PLUS | |
5437 | : code == DIV ? MULT | |
ccfa01f5 | 5438 | : code, |
5439 | mode, inner_op0, inner_op1); | |
5440 | ||
5441 | /* For commutative operations, try the other pair if that one | |
5442 | didn't simplify. */ | |
6720e96c | 5443 | if (inner == 0 && COMMUTATIVE_ARITH_P (x)) |
ccfa01f5 | 5444 | { |
5445 | other = XEXP (XEXP (x, 0), 1); | |
5446 | inner = simplify_binary_operation (code, mode, | |
5447 | XEXP (XEXP (x, 0), 0), | |
5448 | XEXP (x, 1)); | |
5449 | } | |
5450 | ||
5451 | if (inner) | |
800a7def | 5452 | return simplify_gen_binary (code, mode, other, inner); |
ccfa01f5 | 5453 | } |
5454 | } | |
5455 | ||
5456 | /* A little bit of algebraic simplification here. */ | |
5457 | switch (code) | |
5458 | { | |
5459 | case MEM: | |
5460 | /* Ensure that our address has any ASHIFTs converted to MULT in case | |
5461 | address-recognizing predicates are called later. */ | |
5462 | temp = make_compound_operation (XEXP (x, 0), MEM); | |
5463 | SUBST (XEXP (x, 0), temp); | |
5464 | break; | |
5465 | ||
5466 | case SUBREG: | |
64ab453f | 5467 | if (op0_mode == VOIDmode) |
5468 | op0_mode = GET_MODE (SUBREG_REG (x)); | |
ccfa01f5 | 5469 | |
316f48ea | 5470 | /* See if this can be moved to simplify_subreg. */ |
c3e7c35d | 5471 | if (CONSTANT_P (SUBREG_REG (x)) |
d20ef498 | 5472 | && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) |
316f48ea | 5473 | /* Don't call gen_lowpart if the inner mode |
d20ef498 | 5474 | is VOIDmode and we cannot simplify it, as SUBREG without |
5475 | inner mode is invalid. */ | |
5476 | && (GET_MODE (SUBREG_REG (x)) != VOIDmode | |
5477 | || gen_lowpart_common (mode, SUBREG_REG (x)))) | |
316f48ea | 5478 | return gen_lowpart (mode, SUBREG_REG (x)); |
ccfa01f5 | 5479 | |
808b87dc | 5480 | if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) |
a0c938f0 | 5481 | break; |
64ab453f | 5482 | { |
5483 | rtx temp; | |
5484 | temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, | |
87e97de6 | 5485 | SUBREG_BYTE (x)); |
64ab453f | 5486 | if (temp) |
5487 | return temp; | |
fd304a93 | 5488 | |
5489 | /* If op is known to have all lower bits zero, the result is zero. */ | |
5490 | if (!in_dest | |
5491 | && SCALAR_INT_MODE_P (mode) | |
5492 | && SCALAR_INT_MODE_P (op0_mode) | |
5493 | && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode) | |
5494 | && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) | |
5495 | && HWI_COMPUTABLE_MODE_P (op0_mode) | |
5496 | && (nonzero_bits (SUBREG_REG (x), op0_mode) | |
5497 | & GET_MODE_MASK (mode)) == 0) | |
5498 | return CONST0_RTX (mode); | |
64ab453f | 5499 | } |
90bfe841 | 5500 | |
8fb100fd | 5501 | /* Don't change the mode of the MEM if that would change the meaning |
9e9ce32b | 5502 | of the address. */ |
e16ceb8e | 5503 | if (MEM_P (SUBREG_REG (x)) |
8fb100fd | 5504 | && (MEM_VOLATILE_P (SUBREG_REG (x)) |
4e27ffd0 | 5505 | || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0), |
5506 | MEM_ADDR_SPACE (SUBREG_REG (x))))) | |
8fb100fd | 5507 | return gen_rtx_CLOBBER (mode, const0_rtx); |
5508 | ||
7f77fd3f | 5509 | /* Note that we cannot do any narrowing for non-constants since |
5510 | we might have been counting on using the fact that some bits were | |
5511 | zero. We now do this in the SET. */ | |
5512 | ||
ccfa01f5 | 5513 | break; |
5514 | ||
ccfa01f5 | 5515 | case NEG: |
ccfa01f5 | 5516 | temp = expand_compound_operation (XEXP (x, 0)); |
5517 | ||
5518 | /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be | |
87e97de6 | 5519 | replaced by (lshiftrt X C). This will convert |
ccfa01f5 | 5520 | (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ |
5521 | ||
5522 | if (GET_CODE (temp) == ASHIFTRT | |
971ba038 | 5523 | && CONST_INT_P (XEXP (temp, 1)) |
ded805e6 | 5524 | && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1) |
2a66066b | 5525 | return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0), |
2b0f64f9 | 5526 | INTVAL (XEXP (temp, 1))); |
ccfa01f5 | 5527 | |
3d882a35 | 5528 | /* If X has only a single bit that might be nonzero, say, bit I, convert |
ccfa01f5 | 5529 | (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of |
5530 | MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to | |
5531 | (sign_extract X 1 Y). But only do this if TEMP isn't a register | |
5532 | or a SUBREG of one since we'd be making the expression more | |
5533 | complex if it was just a register. */ | |
5534 | ||
8ad4c111 | 5535 | if (!REG_P (temp) |
ccfa01f5 | 5536 | && ! (GET_CODE (temp) == SUBREG |
8ad4c111 | 5537 | && REG_P (SUBREG_REG (temp))) |
3d882a35 | 5538 | && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) |
ccfa01f5 | 5539 | { |
5540 | rtx temp1 = simplify_shift_const | |
1bb04728 | 5541 | (NULL_RTX, ASHIFTRT, mode, |
5542 | simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, | |
ded805e6 | 5543 | GET_MODE_PRECISION (mode) - 1 - i), |
5544 | GET_MODE_PRECISION (mode) - 1 - i); | |
ccfa01f5 | 5545 | |
5546 | /* If all we did was surround TEMP with the two shifts, we | |
5547 | haven't improved anything, so don't use it. Otherwise, | |
5548 | we are better off with TEMP1. */ | |
5549 | if (GET_CODE (temp1) != ASHIFTRT | |
5550 | || GET_CODE (XEXP (temp1, 0)) != ASHIFT | |
5551 | || XEXP (XEXP (temp1, 0), 0) != temp) | |
2b0f64f9 | 5552 | return temp1; |
ccfa01f5 | 5553 | } |
5554 | break; | |
5555 | ||
d5229fd0 | 5556 | case TRUNCATE: |
d616995c | 5557 | /* We can't handle truncation to a partial integer mode here |
5558 | because we don't know the real bitsize of the partial | |
5559 | integer mode. */ | |
5560 | if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
5561 | break; | |
5562 | ||
f179ee60 | 5563 | if (HWI_COMPUTABLE_MODE_P (mode)) |
d5229fd0 | 5564 | SUBST (XEXP (x, 0), |
5565 | force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), | |
b92e2e43 | 5566 | GET_MODE_MASK (mode), 0)); |
0a3894c2 | 5567 | |
b572c3c9 | 5568 | /* We can truncate a constant value and return it. */ |
5569 | if (CONST_INT_P (XEXP (x, 0))) | |
5570 | return gen_int_mode (INTVAL (XEXP (x, 0)), mode); | |
5571 | ||
6516cbaf | 5572 | /* Similarly to what we do in simplify-rtx.c, a truncate of a register |
5573 | whose value is a comparison can be replaced with a subreg if | |
5574 | STORE_FLAG_VALUE permits. */ | |
f179ee60 | 5575 | if (HWI_COMPUTABLE_MODE_P (mode) |
897c6c81 | 5576 | && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 |
0a3894c2 | 5577 | && (temp = get_last_value (XEXP (x, 0))) |
6720e96c | 5578 | && COMPARISON_P (temp)) |
316f48ea | 5579 | return gen_lowpart (mode, XEXP (x, 0)); |
d5229fd0 | 5580 | break; |
5581 | ||
ccfa01f5 | 5582 | case CONST: |
5583 | /* (const (const X)) can become (const X). Do it this way rather than | |
5584 | returning the inner CONST since CONST can be shared with a | |
5585 | REG_EQUAL note. */ | |
5586 | if (GET_CODE (XEXP (x, 0)) == CONST) | |
5587 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
5588 | break; | |
5589 | ||
5590 | #ifdef HAVE_lo_sum | |
5591 | case LO_SUM: | |
5592 | /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we | |
5593 | can add in an offset. find_split_point will split this address up | |
5594 | again if it doesn't match. */ | |
5595 | if (GET_CODE (XEXP (x, 0)) == HIGH | |
5596 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) | |
5597 | return XEXP (x, 1); | |
5598 | break; | |
5599 | #endif | |
5600 | ||
5601 | case PLUS: | |
ccfa01f5 | 5602 | /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) |
5603 | when c is (const_int (pow2 + 1) / 2) is a sign extension of a | |
5604 | bit-field and can be replaced by either a sign_extend or a | |
cef718c1 | 5605 | sign_extract. The `and' may be a zero_extend and the two |
5606 | <c>, -<c> constants may be reversed. */ | |
ccfa01f5 | 5607 | if (GET_CODE (XEXP (x, 0)) == XOR |
971ba038 | 5608 | && CONST_INT_P (XEXP (x, 1)) |
5609 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
510f7125 | 5610 | && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) |
897c6c81 | 5611 | && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 |
5612 | || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0) | |
f179ee60 | 5613 | && HWI_COMPUTABLE_MODE_P (mode) |
ccfa01f5 | 5614 | && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND |
971ba038 | 5615 | && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1)) |
897c6c81 | 5616 | && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) |
5617 | == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1)) | |
ccfa01f5 | 5618 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND |
ded805e6 | 5619 | && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) |
02e7a332 | 5620 | == (unsigned int) i + 1)))) |
2b0f64f9 | 5621 | return simplify_shift_const |
5622 | (NULL_RTX, ASHIFTRT, mode, | |
5623 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
5624 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
ded805e6 | 5625 | GET_MODE_PRECISION (mode) - (i + 1)), |
5626 | GET_MODE_PRECISION (mode) - (i + 1)); | |
ccfa01f5 | 5627 | |
8056031f | 5628 | /* If only the low-order bit of X is possibly nonzero, (plus x -1) |
ccfa01f5 | 5629 | can become (ashiftrt (ashift (xor x 1) C) C) where C is |
5630 | the bitsize of the mode - 1. This allows simplification of | |
5631 | "a = (b & 8) == 0;" */ | |
5632 | if (XEXP (x, 1) == constm1_rtx | |
8ad4c111 | 5633 | && !REG_P (XEXP (x, 0)) |
77676a31 | 5634 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
8ad4c111 | 5635 | && REG_P (SUBREG_REG (XEXP (x, 0)))) |
3d882a35 | 5636 | && nonzero_bits (XEXP (x, 0), mode) == 1) |
2b0f64f9 | 5637 | return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, |
5638 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
3380b197 | 5639 | gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), |
ded805e6 | 5640 | GET_MODE_PRECISION (mode) - 1), |
5641 | GET_MODE_PRECISION (mode) - 1); | |
13e5f45b | 5642 | |
5643 | /* If we are adding two things that have no bits in common, convert | |
5644 | the addition into an IOR. This will often be further simplified, | |
5645 | for example in cases like ((a & 1) + (a & 2)), which can | |
5646 | become a & 3. */ | |
5647 | ||
f179ee60 | 5648 | if (HWI_COMPUTABLE_MODE_P (mode) |
3d882a35 | 5649 | && (nonzero_bits (XEXP (x, 0), mode) |
5650 | & nonzero_bits (XEXP (x, 1), mode)) == 0) | |
6587e23e | 5651 | { |
5652 | /* Try to simplify the expression further. */ | |
800a7def | 5653 | rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); |
9a1ba33e | 5654 | temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0); |
6587e23e | 5655 | |
5656 | /* If we could, great. If not, do not go ahead with the IOR | |
5657 | replacement, since PLUS appears in many special purpose | |
5658 | address arithmetic instructions. */ | |
9a1ba33e | 5659 | if (GET_CODE (temp) != CLOBBER |
5660 | && (GET_CODE (temp) != IOR | |
5661 | || ((XEXP (temp, 0) != XEXP (x, 0) | |
5662 | || XEXP (temp, 1) != XEXP (x, 1)) | |
5663 | && (XEXP (temp, 0) != XEXP (x, 1) | |
5664 | || XEXP (temp, 1) != XEXP (x, 0))))) | |
6587e23e | 5665 | return temp; |
5666 | } | |
ccfa01f5 | 5667 | break; |
5668 | ||
5669 | case MINUS: | |
5670 | /* (minus <foo> (and <foo> (const_int -pow2))) becomes | |
5671 | (and <foo> (const_int pow2-1)) */ | |
5672 | if (GET_CODE (XEXP (x, 1)) == AND | |
971ba038 | 5673 | && CONST_INT_P (XEXP (XEXP (x, 1), 1)) |
897c6c81 | 5674 | && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0 |
ccfa01f5 | 5675 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
2b0f64f9 | 5676 | return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), |
510f7125 | 5677 | -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); |
ccfa01f5 | 5678 | break; |
5679 | ||
5680 | case MULT: | |
5681 | /* If we have (mult (plus A B) C), apply the distributive law and then | |
5682 | the inverse distributive law to see if things simplify. This | |
5683 | occurs mostly in addresses, often when unrolling loops. */ | |
5684 | ||
5685 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
5686 | { | |
800a7def | 5687 | rtx result = distribute_and_simplify_rtx (x, 0); |
5688 | if (result) | |
5689 | return result; | |
ccfa01f5 | 5690 | } |
800a7def | 5691 | |
02cd84cd | 5692 | /* Try simplify a*(b/c) as (a*b)/c. */ |
48e1416a | 5693 | if (FLOAT_MODE_P (mode) && flag_associative_math |
02cd84cd | 5694 | && GET_CODE (XEXP (x, 0)) == DIV) |
5695 | { | |
5696 | rtx tem = simplify_binary_operation (MULT, mode, | |
5697 | XEXP (XEXP (x, 0), 0), | |
5698 | XEXP (x, 1)); | |
5699 | if (tem) | |
800a7def | 5700 | return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); |
02cd84cd | 5701 | } |
ccfa01f5 | 5702 | break; |
5703 | ||
5704 | case UDIV: | |
5705 | /* If this is a divide by a power of two, treat it as a shift if | |
5706 | its first operand is a shift. */ | |
971ba038 | 5707 | if (CONST_INT_P (XEXP (x, 1)) |
897c6c81 | 5708 | && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0 |
ccfa01f5 | 5709 | && (GET_CODE (XEXP (x, 0)) == ASHIFT |
5710 | || GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
5711 | || GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
5712 | || GET_CODE (XEXP (x, 0)) == ROTATE | |
5713 | || GET_CODE (XEXP (x, 0)) == ROTATERT)) | |
2b0f64f9 | 5714 | return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); |
ccfa01f5 | 5715 | break; |
5716 | ||
5717 | case EQ: case NE: | |
5718 | case GT: case GTU: case GE: case GEU: | |
5719 | case LT: case LTU: case LE: case LEU: | |
b467856b | 5720 | case UNEQ: case LTGT: |
87e97de6 | 5721 | case UNGT: case UNGE: |
5722 | case UNLT: case UNLE: | |
b467856b | 5723 | case UNORDERED: case ORDERED: |
ccfa01f5 | 5724 | /* If the first operand is a condition code, we can't do anything |
5725 | with it. */ | |
5726 | if (GET_CODE (XEXP (x, 0)) == COMPARE | |
5727 | || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC | |
a4589b78 | 5728 | && ! CC0_P (XEXP (x, 0)))) |
ccfa01f5 | 5729 | { |
5730 | rtx op0 = XEXP (x, 0); | |
5731 | rtx op1 = XEXP (x, 1); | |
5732 | enum rtx_code new_code; | |
5733 | ||
5734 | if (GET_CODE (op0) == COMPARE) | |
5735 | op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
5736 | ||
5737 | /* Simplify our comparison, if possible. */ | |
5738 | new_code = simplify_comparison (code, &op0, &op1); | |
5739 | ||
ccfa01f5 | 5740 | /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X |
3d882a35 | 5741 | if only the low-order bit is possibly nonzero in X (such as when |
9bab13ca | 5742 | X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to |
5743 | (xor X 1) or (minus 1 X); we use the former. Finally, if X is | |
5744 | known to be either 0 or -1, NE becomes a NEG and EQ becomes | |
5745 | (plus X 1). | |
5746 | ||
5747 | Remove any ZERO_EXTRACT we made when thinking this was a | |
5748 | comparison. It may now be simpler to use, e.g., an AND. If a | |
5749 | ZERO_EXTRACT is indeed appropriate, it will be placed back by | |
34dd021c | 5750 | the call to make_compound_operation in the SET case. |
5751 | ||
5752 | Don't apply these optimizations if the caller would | |
5753 | prefer a comparison rather than a value. | |
5754 | E.g., for the condition in an IF_THEN_ELSE most targets need | |
5755 | an explicit comparison. */ | |
9bab13ca | 5756 | |
34dd021c | 5757 | if (in_cond) |
5758 | ; | |
5759 | ||
5760 | else if (STORE_FLAG_VALUE == 1 | |
7feddf73 | 5761 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
3573fd04 | 5762 | && op1 == const0_rtx |
5763 | && mode == GET_MODE (op0) | |
5764 | && nonzero_bits (op0, mode) == 1) | |
316f48ea | 5765 | return gen_lowpart (mode, |
5766 | expand_compound_operation (op0)); | |
9bab13ca | 5767 | |
7feddf73 | 5768 | else if (STORE_FLAG_VALUE == 1 |
5769 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
9bab13ca | 5770 | && op1 == const0_rtx |
3573fd04 | 5771 | && mode == GET_MODE (op0) |
9bab13ca | 5772 | && (num_sign_bit_copies (op0, mode) |
ded805e6 | 5773 | == GET_MODE_PRECISION (mode))) |
9bab13ca | 5774 | { |
5775 | op0 = expand_compound_operation (op0); | |
3380b197 | 5776 | return simplify_gen_unary (NEG, mode, |
316f48ea | 5777 | gen_lowpart (mode, op0), |
3380b197 | 5778 | mode); |
9bab13ca | 5779 | } |
5780 | ||
7feddf73 | 5781 | else if (STORE_FLAG_VALUE == 1 |
5782 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
ccfa01f5 | 5783 | && op1 == const0_rtx |
3573fd04 | 5784 | && mode == GET_MODE (op0) |
9bab13ca | 5785 | && nonzero_bits (op0, mode) == 1) |
4b6e4fea | 5786 | { |
5787 | op0 = expand_compound_operation (op0); | |
800a7def | 5788 | return simplify_gen_binary (XOR, mode, |
5789 | gen_lowpart (mode, op0), | |
5790 | const1_rtx); | |
9bab13ca | 5791 | } |
4b6e4fea | 5792 | |
7feddf73 | 5793 | else if (STORE_FLAG_VALUE == 1 |
5794 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
9bab13ca | 5795 | && op1 == const0_rtx |
3573fd04 | 5796 | && mode == GET_MODE (op0) |
9bab13ca | 5797 | && (num_sign_bit_copies (op0, mode) |
ded805e6 | 5798 | == GET_MODE_PRECISION (mode))) |
9bab13ca | 5799 | { |
5800 | op0 = expand_compound_operation (op0); | |
29c05e22 | 5801 | return plus_constant (mode, gen_lowpart (mode, op0), 1); |
4b6e4fea | 5802 | } |
ccfa01f5 | 5803 | |
9bab13ca | 5804 | /* If STORE_FLAG_VALUE is -1, we have cases similar to |
5805 | those above. */ | |
8ebe31d6 | 5806 | if (in_cond) |
5807 | ; | |
5808 | ||
5809 | else if (STORE_FLAG_VALUE == -1 | |
7feddf73 | 5810 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
ccfa01f5 | 5811 | && op1 == const0_rtx |
9bab13ca | 5812 | && (num_sign_bit_copies (op0, mode) |
ded805e6 | 5813 | == GET_MODE_PRECISION (mode))) |
316f48ea | 5814 | return gen_lowpart (mode, |
5815 | expand_compound_operation (op0)); | |
9bab13ca | 5816 | |
7feddf73 | 5817 | else if (STORE_FLAG_VALUE == -1 |
5818 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
9bab13ca | 5819 | && op1 == const0_rtx |
3573fd04 | 5820 | && mode == GET_MODE (op0) |
9bab13ca | 5821 | && nonzero_bits (op0, mode) == 1) |
5822 | { | |
5823 | op0 = expand_compound_operation (op0); | |
3380b197 | 5824 | return simplify_gen_unary (NEG, mode, |
316f48ea | 5825 | gen_lowpart (mode, op0), |
3380b197 | 5826 | mode); |
9bab13ca | 5827 | } |
5828 | ||
7feddf73 | 5829 | else if (STORE_FLAG_VALUE == -1 |
5830 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
9bab13ca | 5831 | && op1 == const0_rtx |
3573fd04 | 5832 | && mode == GET_MODE (op0) |
9bab13ca | 5833 | && (num_sign_bit_copies (op0, mode) |
ded805e6 | 5834 | == GET_MODE_PRECISION (mode))) |
ccfa01f5 | 5835 | { |
4b6e4fea | 5836 | op0 = expand_compound_operation (op0); |
3380b197 | 5837 | return simplify_gen_unary (NOT, mode, |
316f48ea | 5838 | gen_lowpart (mode, op0), |
3380b197 | 5839 | mode); |
9bab13ca | 5840 | } |
5841 | ||
5842 | /* If X is 0/1, (eq X 0) is X-1. */ | |
7feddf73 | 5843 | else if (STORE_FLAG_VALUE == -1 |
5844 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
9bab13ca | 5845 | && op1 == const0_rtx |
3573fd04 | 5846 | && mode == GET_MODE (op0) |
9bab13ca | 5847 | && nonzero_bits (op0, mode) == 1) |
5848 | { | |
5849 | op0 = expand_compound_operation (op0); | |
29c05e22 | 5850 | return plus_constant (mode, gen_lowpart (mode, op0), -1); |
ccfa01f5 | 5851 | } |
ccfa01f5 | 5852 | |
5853 | /* If STORE_FLAG_VALUE says to just test the sign bit and X has just | |
3d882a35 | 5854 | one bit that might be nonzero, we can convert (ne x 0) to |
5855 | (ashift x c) where C puts the bit in the sign bit. Remove any | |
5856 | AND with STORE_FLAG_VALUE when we are done, since we are only | |
5857 | going to test the sign bit. */ | |
ded4a97a | 5858 | if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
f179ee60 | 5859 | && HWI_COMPUTABLE_MODE_P (mode) |
f92430e0 | 5860 | && val_signbit_p (mode, STORE_FLAG_VALUE) |
ccfa01f5 | 5861 | && op1 == const0_rtx |
5862 | && mode == GET_MODE (op0) | |
9bab13ca | 5863 | && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) |
ccfa01f5 | 5864 | { |
4b6e4fea | 5865 | x = simplify_shift_const (NULL_RTX, ASHIFT, mode, |
5866 | expand_compound_operation (op0), | |
ded805e6 | 5867 | GET_MODE_PRECISION (mode) - 1 - i); |
ccfa01f5 | 5868 | if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) |
5869 | return XEXP (x, 0); | |
5870 | else | |
5871 | return x; | |
5872 | } | |
5873 | ||
48d6412b | 5874 | /* If the code changed, return a whole new comparison. |
5875 | We also need to avoid using SUBST in cases where | |
5876 | simplify_comparison has widened a comparison with a CONST_INT, | |
5877 | since in that case the wider CONST_INT may fail the sanity | |
5878 | checks in do_SUBST. */ | |
5879 | if (new_code != code | |
5880 | || (CONST_INT_P (op1) | |
5881 | && GET_MODE (op0) != GET_MODE (XEXP (x, 0)) | |
5882 | && GET_MODE (op0) != GET_MODE (XEXP (x, 1)))) | |
3380b197 | 5883 | return gen_rtx_fmt_ee (new_code, mode, op0, op1); |
ccfa01f5 | 5884 | |
510f7125 | 5885 | /* Otherwise, keep this operation, but maybe change its operands. |
ccfa01f5 | 5886 | This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ |
5887 | SUBST (XEXP (x, 0), op0); | |
5888 | SUBST (XEXP (x, 1), op1); | |
5889 | } | |
5890 | break; | |
510f7125 | 5891 | |
ccfa01f5 | 5892 | case IF_THEN_ELSE: |
2b0f64f9 | 5893 | return simplify_if_then_else (x); |
5056f17b | 5894 | |
2b0f64f9 | 5895 | case ZERO_EXTRACT: |
5896 | case SIGN_EXTRACT: | |
5897 | case ZERO_EXTEND: | |
5898 | case SIGN_EXTEND: | |
a92771b8 | 5899 | /* If we are processing SET_DEST, we are done. */ |
2b0f64f9 | 5900 | if (in_dest) |
5901 | return x; | |
ec90760f | 5902 | |
2b0f64f9 | 5903 | return expand_compound_operation (x); |
ec90760f | 5904 | |
2b0f64f9 | 5905 | case SET: |
5906 | return simplify_set (x); | |
1f1c8c5a | 5907 | |
2b0f64f9 | 5908 | case AND: |
5909 | case IOR: | |
d7ef6792 | 5910 | return simplify_logical (x); |
ec90760f | 5911 | |
2b0f64f9 | 5912 | case ASHIFT: |
5913 | case LSHIFTRT: | |
5914 | case ASHIFTRT: | |
5915 | case ROTATE: | |
5916 | case ROTATERT: | |
5917 | /* If this is a shift by a constant amount, simplify it. */ | |
971ba038 | 5918 | if (CONST_INT_P (XEXP (x, 1))) |
510f7125 | 5919 | return simplify_shift_const (x, code, mode, XEXP (x, 0), |
2b0f64f9 | 5920 | INTVAL (XEXP (x, 1))); |
5921 | ||
8ad4c111 | 5922 | else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1))) |
2b0f64f9 | 5923 | SUBST (XEXP (x, 1), |
99c8af92 | 5924 | force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), |
b3003238 | 5925 | ((unsigned HOST_WIDE_INT) 1 |
5926 | << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) | |
5927 | - 1, | |
b92e2e43 | 5928 | 0)); |
2b0f64f9 | 5929 | break; |
0dbd1c74 | 5930 | |
5931 | default: | |
5932 | break; | |
2b0f64f9 | 5933 | } |
5934 | ||
5935 | return x; | |
5936 | } | |
5937 | \f | |
5938 | /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ | |
9bab13ca | 5939 | |
2b0f64f9 | 5940 | static rtx |
d598ad0d | 5941 | simplify_if_then_else (rtx x) |
2b0f64f9 | 5942 | { |
5943 | enum machine_mode mode = GET_MODE (x); | |
5944 | rtx cond = XEXP (x, 0); | |
9c811526 | 5945 | rtx true_rtx = XEXP (x, 1); |
5946 | rtx false_rtx = XEXP (x, 2); | |
2b0f64f9 | 5947 | enum rtx_code true_code = GET_CODE (cond); |
6720e96c | 5948 | int comparison_p = COMPARISON_P (cond); |
2b0f64f9 | 5949 | rtx temp; |
5950 | int i; | |
1b796f12 | 5951 | enum rtx_code false_code; |
5952 | rtx reversed; | |
2b0f64f9 | 5953 | |
a92771b8 | 5954 | /* Simplify storing of the truth value. */ |
9c811526 | 5955 | if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) |
800a7def | 5956 | return simplify_gen_relational (true_code, mode, VOIDmode, |
5957 | XEXP (cond, 0), XEXP (cond, 1)); | |
510f7125 | 5958 | |
a92771b8 | 5959 | /* Also when the truth value has to be reversed. */ |
1b796f12 | 5960 | if (comparison_p |
9c811526 | 5961 | && true_rtx == const0_rtx && false_rtx == const_true_rtx |
0fc1e6fa | 5962 | && (reversed = reversed_comparison (cond, mode))) |
1b796f12 | 5963 | return reversed; |
2b0f64f9 | 5964 | |
5965 | /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used | |
5966 | in it is being compared against certain values. Get the true and false | |
5967 | comparisons and see if that says anything about the value of each arm. */ | |
5968 | ||
1b796f12 | 5969 | if (comparison_p |
0fc1e6fa | 5970 | && ((false_code = reversed_comparison_code (cond, NULL)) |
1b796f12 | 5971 | != UNKNOWN) |
8ad4c111 | 5972 | && REG_P (XEXP (cond, 0))) |
2b0f64f9 | 5973 | { |
5974 | HOST_WIDE_INT nzb; | |
5975 | rtx from = XEXP (cond, 0); | |
2b0f64f9 | 5976 | rtx true_val = XEXP (cond, 1); |
5977 | rtx false_val = true_val; | |
5978 | int swapped = 0; | |
5056f17b | 5979 | |
2b0f64f9 | 5980 | /* If FALSE_CODE is EQ, swap the codes and arms. */ |
9bab13ca | 5981 | |
2b0f64f9 | 5982 | if (false_code == EQ) |
1f1c8c5a | 5983 | { |
2b0f64f9 | 5984 | swapped = 1, true_code = EQ, false_code = NE; |
9c811526 | 5985 | temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; |
2b0f64f9 | 5986 | } |
9bab13ca | 5987 | |
2b0f64f9 | 5988 | /* If we are comparing against zero and the expression being tested has |
5989 | only a single bit that might be nonzero, that is its value when it is | |
5990 | not equal to zero. Similarly if it is known to be -1 or 0. */ | |
5991 | ||
5992 | if (true_code == EQ && true_val == const0_rtx | |
5993 | && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) | |
bf6a5269 | 5994 | { |
5995 | false_code = EQ; | |
f62058c3 | 5996 | false_val = gen_int_mode (nzb, GET_MODE (from)); |
bf6a5269 | 5997 | } |
2b0f64f9 | 5998 | else if (true_code == EQ && true_val == const0_rtx |
5999 | && (num_sign_bit_copies (from, GET_MODE (from)) | |
ded805e6 | 6000 | == GET_MODE_PRECISION (GET_MODE (from)))) |
bf6a5269 | 6001 | { |
6002 | false_code = EQ; | |
6003 | false_val = constm1_rtx; | |
6004 | } | |
2b0f64f9 | 6005 | |
6006 | /* Now simplify an arm if we know the value of the register in the | |
6007 | branch and it is used in the arm. Be careful due to the potential | |
6008 | of locally-shared RTL. */ | |
6009 | ||
9c811526 | 6010 | if (reg_mentioned_p (from, true_rtx)) |
6011 | true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, | |
6012 | from, true_val), | |
34dd021c | 6013 | pc_rtx, pc_rtx, 0, 0, 0); |
9c811526 | 6014 | if (reg_mentioned_p (from, false_rtx)) |
6015 | false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, | |
2b0f64f9 | 6016 | from, false_val), |
34dd021c | 6017 | pc_rtx, pc_rtx, 0, 0, 0); |
2b0f64f9 | 6018 | |
9c811526 | 6019 | SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); |
6020 | SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); | |
2b0f64f9 | 6021 | |
9c811526 | 6022 | true_rtx = XEXP (x, 1); |
6023 | false_rtx = XEXP (x, 2); | |
6024 | true_code = GET_CODE (cond); | |
2b0f64f9 | 6025 | } |
9bab13ca | 6026 | |
2b0f64f9 | 6027 | /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be |
6028 | reversed, do so to avoid needing two sets of patterns for | |
6029 | subtract-and-branch insns. Similarly if we have a constant in the true | |
6030 | arm, the false arm is the same as the first operand of the comparison, or | |
6031 | the false arm is more complicated than the true arm. */ | |
6032 | ||
1b796f12 | 6033 | if (comparison_p |
0fc1e6fa | 6034 | && reversed_comparison_code (cond, NULL) != UNKNOWN |
9c811526 | 6035 | && (true_rtx == pc_rtx |
6036 | || (CONSTANT_P (true_rtx) | |
971ba038 | 6037 | && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx) |
9c811526 | 6038 | || true_rtx == const0_rtx |
6720e96c | 6039 | || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx)) |
6040 | || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx)) | |
6041 | && !OBJECT_P (false_rtx)) | |
9c811526 | 6042 | || reg_mentioned_p (true_rtx, false_rtx) |
6043 | || rtx_equal_p (false_rtx, XEXP (cond, 0)))) | |
2b0f64f9 | 6044 | { |
1b796f12 | 6045 | true_code = reversed_comparison_code (cond, NULL); |
0fc1e6fa | 6046 | SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond))); |
9c811526 | 6047 | SUBST (XEXP (x, 1), false_rtx); |
6048 | SUBST (XEXP (x, 2), true_rtx); | |
1f1c8c5a | 6049 | |
9c811526 | 6050 | temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; |
6051 | cond = XEXP (x, 0); | |
aec8f9c4 | 6052 | |
a92771b8 | 6053 | /* It is possible that the conditional has been simplified out. */ |
aec8f9c4 | 6054 | true_code = GET_CODE (cond); |
6720e96c | 6055 | comparison_p = COMPARISON_P (cond); |
2b0f64f9 | 6056 | } |
862e4898 | 6057 | |
2b0f64f9 | 6058 | /* If the two arms are identical, we don't need the comparison. */ |
1f1c8c5a | 6059 | |
9c811526 | 6060 | if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) |
6061 | return true_rtx; | |
1f1c8c5a | 6062 | |
aa0f8df3 | 6063 | /* Convert a == b ? b : a to "a". */ |
6064 | if (true_code == EQ && ! side_effects_p (cond) | |
af8d63dd | 6065 | && !HONOR_NANS (mode) |
9c811526 | 6066 | && rtx_equal_p (XEXP (cond, 0), false_rtx) |
6067 | && rtx_equal_p (XEXP (cond, 1), true_rtx)) | |
6068 | return false_rtx; | |
aa0f8df3 | 6069 | else if (true_code == NE && ! side_effects_p (cond) |
af8d63dd | 6070 | && !HONOR_NANS (mode) |
9c811526 | 6071 | && rtx_equal_p (XEXP (cond, 0), true_rtx) |
6072 | && rtx_equal_p (XEXP (cond, 1), false_rtx)) | |
6073 | return true_rtx; | |
aa0f8df3 | 6074 | |
2b0f64f9 | 6075 | /* Look for cases where we have (abs x) or (neg (abs X)). */ |
6076 | ||
6077 | if (GET_MODE_CLASS (mode) == MODE_INT | |
76d5115a | 6078 | && comparison_p |
6079 | && XEXP (cond, 1) == const0_rtx | |
9c811526 | 6080 | && GET_CODE (false_rtx) == NEG |
6081 | && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) | |
9c811526 | 6082 | && rtx_equal_p (true_rtx, XEXP (cond, 0)) |
6083 | && ! side_effects_p (true_rtx)) | |
2b0f64f9 | 6084 | switch (true_code) |
6085 | { | |
6086 | case GT: | |
6087 | case GE: | |
3380b197 | 6088 | return simplify_gen_unary (ABS, mode, true_rtx, mode); |
2b0f64f9 | 6089 | case LT: |
6090 | case LE: | |
3380b197 | 6091 | return |
6092 | simplify_gen_unary (NEG, mode, | |
6093 | simplify_gen_unary (ABS, mode, true_rtx, mode), | |
6094 | mode); | |
ea913091 | 6095 | default: |
6096 | break; | |
2b0f64f9 | 6097 | } |
6098 | ||
6099 | /* Look for MIN or MAX. */ | |
6100 | ||
7f3be425 | 6101 | if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) |
2b0f64f9 | 6102 | && comparison_p |
9c811526 | 6103 | && rtx_equal_p (XEXP (cond, 0), true_rtx) |
6104 | && rtx_equal_p (XEXP (cond, 1), false_rtx) | |
2b0f64f9 | 6105 | && ! side_effects_p (cond)) |
6106 | switch (true_code) | |
6107 | { | |
6108 | case GE: | |
6109 | case GT: | |
800a7def | 6110 | return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx); |
2b0f64f9 | 6111 | case LE: |
6112 | case LT: | |
800a7def | 6113 | return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx); |
2b0f64f9 | 6114 | case GEU: |
6115 | case GTU: | |
800a7def | 6116 | return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx); |
2b0f64f9 | 6117 | case LEU: |
6118 | case LTU: | |
800a7def | 6119 | return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx); |
0dbd1c74 | 6120 | default: |
6121 | break; | |
2b0f64f9 | 6122 | } |
510f7125 | 6123 | |
2b0f64f9 | 6124 | /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its |
6125 | second operand is zero, this can be done as (OP Z (mult COND C2)) where | |
6126 | C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or | |
6127 | SIGN_EXTEND as long as Z is already extended (so we don't destroy it). | |
6128 | We can do this kind of thing in some cases when STORE_FLAG_VALUE is | |
7feddf73 | 6129 | neither 1 or -1, but it isn't worth checking for. */ |
2b0f64f9 | 6130 | |
7feddf73 | 6131 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
692e0f79 | 6132 | && comparison_p |
6133 | && GET_MODE_CLASS (mode) == MODE_INT | |
6134 | && ! side_effects_p (x)) | |
2b0f64f9 | 6135 | { |
9c811526 | 6136 | rtx t = make_compound_operation (true_rtx, SET); |
6137 | rtx f = make_compound_operation (false_rtx, SET); | |
2b0f64f9 | 6138 | rtx cond_op0 = XEXP (cond, 0); |
6139 | rtx cond_op1 = XEXP (cond, 1); | |
21f1e711 | 6140 | enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; |
2b0f64f9 | 6141 | enum machine_mode m = mode; |
df9f2bb6 | 6142 | rtx z = 0, c1 = NULL_RTX; |
2b0f64f9 | 6143 | |
2b0f64f9 | 6144 | if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS |
6145 | || GET_CODE (t) == IOR || GET_CODE (t) == XOR | |
6146 | || GET_CODE (t) == ASHIFT | |
6147 | || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) | |
6148 | && rtx_equal_p (XEXP (t, 0), f)) | |
6149 | c1 = XEXP (t, 1), op = GET_CODE (t), z = f; | |
6150 | ||
6151 | /* If an identity-zero op is commutative, check whether there | |
a92771b8 | 6152 | would be a match if we swapped the operands. */ |
2b0f64f9 | 6153 | else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR |
6154 | || GET_CODE (t) == XOR) | |
6155 | && rtx_equal_p (XEXP (t, 1), f)) | |
6156 | c1 = XEXP (t, 0), op = GET_CODE (t), z = f; | |
6157 | else if (GET_CODE (t) == SIGN_EXTEND | |
6158 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
6159 | || GET_CODE (XEXP (t, 0)) == MINUS | |
6160 | || GET_CODE (XEXP (t, 0)) == IOR | |
6161 | || GET_CODE (XEXP (t, 0)) == XOR | |
6162 | || GET_CODE (XEXP (t, 0)) == ASHIFT | |
6163 | || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
6164 | || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
6165 | && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
6166 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
6167 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
6168 | && (num_sign_bit_copies (f, GET_MODE (f)) | |
13883914 | 6169 | > (unsigned int) |
ded805e6 | 6170 | (GET_MODE_PRECISION (mode) |
6171 | - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0)))))) | |
2b0f64f9 | 6172 | { |
6173 | c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
6174 | extend_op = SIGN_EXTEND; | |
6175 | m = GET_MODE (XEXP (t, 0)); | |
1f1c8c5a | 6176 | } |
2b0f64f9 | 6177 | else if (GET_CODE (t) == SIGN_EXTEND |
6178 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
6179 | || GET_CODE (XEXP (t, 0)) == IOR | |
6180 | || GET_CODE (XEXP (t, 0)) == XOR) | |
6181 | && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
6182 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
6183 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
6184 | && (num_sign_bit_copies (f, GET_MODE (f)) | |
13883914 | 6185 | > (unsigned int) |
ded805e6 | 6186 | (GET_MODE_PRECISION (mode) |
6187 | - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1)))))) | |
2b0f64f9 | 6188 | { |
6189 | c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
6190 | extend_op = SIGN_EXTEND; | |
6191 | m = GET_MODE (XEXP (t, 0)); | |
6192 | } | |
6193 | else if (GET_CODE (t) == ZERO_EXTEND | |
6194 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
6195 | || GET_CODE (XEXP (t, 0)) == MINUS | |
6196 | || GET_CODE (XEXP (t, 0)) == IOR | |
6197 | || GET_CODE (XEXP (t, 0)) == XOR | |
6198 | || GET_CODE (XEXP (t, 0)) == ASHIFT | |
6199 | || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
6200 | || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
6201 | && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
f179ee60 | 6202 | && HWI_COMPUTABLE_MODE_P (mode) |
2b0f64f9 | 6203 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) |
6204 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
6205 | && ((nonzero_bits (f, GET_MODE (f)) | |
510f7125 | 6206 | & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) |
2b0f64f9 | 6207 | == 0)) |
6208 | { | |
6209 | c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
6210 | extend_op = ZERO_EXTEND; | |
6211 | m = GET_MODE (XEXP (t, 0)); | |
6212 | } | |
6213 | else if (GET_CODE (t) == ZERO_EXTEND | |
6214 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
6215 | || GET_CODE (XEXP (t, 0)) == IOR | |
6216 | || GET_CODE (XEXP (t, 0)) == XOR) | |
6217 | && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
f179ee60 | 6218 | && HWI_COMPUTABLE_MODE_P (mode) |
2b0f64f9 | 6219 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) |
6220 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
6221 | && ((nonzero_bits (f, GET_MODE (f)) | |
510f7125 | 6222 | & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) |
2b0f64f9 | 6223 | == 0)) |
6224 | { | |
6225 | c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
6226 | extend_op = ZERO_EXTEND; | |
6227 | m = GET_MODE (XEXP (t, 0)); | |
6228 | } | |
510f7125 | 6229 | |
2b0f64f9 | 6230 | if (z) |
6231 | { | |
800a7def | 6232 | temp = subst (simplify_gen_relational (true_code, m, VOIDmode, |
6233 | cond_op0, cond_op1), | |
34dd021c | 6234 | pc_rtx, pc_rtx, 0, 0, 0); |
800a7def | 6235 | temp = simplify_gen_binary (MULT, m, temp, |
6236 | simplify_gen_binary (MULT, m, c1, | |
6237 | const_true_rtx)); | |
34dd021c | 6238 | temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0); |
800a7def | 6239 | temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); |
2b0f64f9 | 6240 | |
21f1e711 | 6241 | if (extend_op != UNKNOWN) |
3380b197 | 6242 | temp = simplify_gen_unary (extend_op, mode, temp, m); |
2b0f64f9 | 6243 | |
6244 | return temp; | |
6245 | } | |
6246 | } | |
98a1ef9c | 6247 | |
2b0f64f9 | 6248 | /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or |
6249 | 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the | |
6250 | negation of a single bit, we can convert this operation to a shift. We | |
6251 | can actually do this more generally, but it doesn't seem worth it. */ | |
6252 | ||
6253 | if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
971ba038 | 6254 | && false_rtx == const0_rtx && CONST_INT_P (true_rtx) |
2b0f64f9 | 6255 | && ((1 == nonzero_bits (XEXP (cond, 0), mode) |
897c6c81 | 6256 | && (i = exact_log2 (UINTVAL (true_rtx))) >= 0) |
2b0f64f9 | 6257 | || ((num_sign_bit_copies (XEXP (cond, 0), mode) |
ded805e6 | 6258 | == GET_MODE_PRECISION (mode)) |
897c6c81 | 6259 | && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0))) |
2b0f64f9 | 6260 | return |
6261 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
316f48ea | 6262 | gen_lowpart (mode, XEXP (cond, 0)), i); |
ccfa01f5 | 6263 | |
3d2a8deb | 6264 | /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */ |
6265 | if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
971ba038 | 6266 | && false_rtx == const0_rtx && CONST_INT_P (true_rtx) |
ed869d65 | 6267 | && GET_MODE (XEXP (cond, 0)) == mode |
897c6c81 | 6268 | && (UINTVAL (true_rtx) & GET_MODE_MASK (mode)) |
3d2a8deb | 6269 | == nonzero_bits (XEXP (cond, 0), mode) |
897c6c81 | 6270 | && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0) |
3d2a8deb | 6271 | return XEXP (cond, 0); |
6272 | ||
2b0f64f9 | 6273 | return x; |
6274 | } | |
6275 | \f | |
6276 | /* Simplify X, a SET expression. Return the new expression. */ | |
ccfa01f5 | 6277 | |
2b0f64f9 | 6278 | static rtx |
d598ad0d | 6279 | simplify_set (rtx x) |
2b0f64f9 | 6280 | { |
6281 | rtx src = SET_SRC (x); | |
6282 | rtx dest = SET_DEST (x); | |
6283 | enum machine_mode mode | |
6284 | = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); | |
35330d19 | 6285 | rtx_insn *other_insn; |
2b0f64f9 | 6286 | rtx *cc_use; |
6287 | ||
6288 | /* (set (pc) (return)) gets written as (return). */ | |
9cb2517e | 6289 | if (GET_CODE (dest) == PC && ANY_RETURN_P (src)) |
2b0f64f9 | 6290 | return src; |
ccfa01f5 | 6291 | |
7f77fd3f | 6292 | /* Now that we know for sure which bits of SRC we are using, see if we can |
6293 | simplify the expression for the object knowing that we only need the | |
6294 | low-order bits. */ | |
6295 | ||
f179ee60 | 6296 | if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode)) |
7014838c | 6297 | { |
897c6c81 | 6298 | src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0); |
7014838c | 6299 | SUBST (SET_SRC (x), src); |
6300 | } | |
7f77fd3f | 6301 | |
2b0f64f9 | 6302 | /* If we are setting CC0 or if the source is a COMPARE, look for the use of |
6303 | the comparison result and try to simplify it unless we already have used | |
6304 | undobuf.other_insn. */ | |
0e9aa9fe | 6305 | if ((GET_MODE_CLASS (mode) == MODE_CC |
6306 | || GET_CODE (src) == COMPARE | |
6307 | || CC0_P (dest)) | |
2b0f64f9 | 6308 | && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 |
6309 | && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) | |
6720e96c | 6310 | && COMPARISON_P (*cc_use) |
eee391de | 6311 | && rtx_equal_p (XEXP (*cc_use, 0), dest)) |
2b0f64f9 | 6312 | { |
6313 | enum rtx_code old_code = GET_CODE (*cc_use); | |
6314 | enum rtx_code new_code; | |
a6e85413 | 6315 | rtx op0, op1, tmp; |
2b0f64f9 | 6316 | int other_changed = 0; |
e4ffbd30 | 6317 | rtx inner_compare = NULL_RTX; |
2b0f64f9 | 6318 | enum machine_mode compare_mode = GET_MODE (dest); |
6319 | ||
6320 | if (GET_CODE (src) == COMPARE) | |
e4ffbd30 | 6321 | { |
6322 | op0 = XEXP (src, 0), op1 = XEXP (src, 1); | |
6323 | if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) | |
6324 | { | |
6325 | inner_compare = op0; | |
6326 | op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1); | |
6327 | } | |
6328 | } | |
2b0f64f9 | 6329 | else |
04d809cb | 6330 | op0 = src, op1 = CONST0_RTX (GET_MODE (src)); |
ccfa01f5 | 6331 | |
ac503e50 | 6332 | tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode, |
6333 | op0, op1); | |
6334 | if (!tmp) | |
a0c938f0 | 6335 | new_code = old_code; |
ac503e50 | 6336 | else if (!CONSTANT_P (tmp)) |
a0c938f0 | 6337 | { |
6338 | new_code = GET_CODE (tmp); | |
6339 | op0 = XEXP (tmp, 0); | |
6340 | op1 = XEXP (tmp, 1); | |
6341 | } | |
a6e85413 | 6342 | else |
a6e85413 | 6343 | { |
6344 | rtx pat = PATTERN (other_insn); | |
6345 | undobuf.other_insn = other_insn; | |
6346 | SUBST (*cc_use, tmp); | |
6347 | ||
6348 | /* Attempt to simplify CC user. */ | |
6349 | if (GET_CODE (pat) == SET) | |
6350 | { | |
d328ebdf | 6351 | rtx new_rtx = simplify_rtx (SET_SRC (pat)); |
6352 | if (new_rtx != NULL_RTX) | |
6353 | SUBST (SET_SRC (pat), new_rtx); | |
a6e85413 | 6354 | } |
6355 | ||
6356 | /* Convert X into a no-op move. */ | |
6357 | SUBST (SET_DEST (x), pc_rtx); | |
6358 | SUBST (SET_SRC (x), pc_rtx); | |
6359 | return x; | |
6360 | } | |
6361 | ||
2b0f64f9 | 6362 | /* Simplify our comparison, if possible. */ |
ac503e50 | 6363 | new_code = simplify_comparison (new_code, &op0, &op1); |
ccfa01f5 | 6364 | |
15460c97 | 6365 | #ifdef SELECT_CC_MODE |
2b0f64f9 | 6366 | /* If this machine has CC modes other than CCmode, check to see if we |
6367 | need to use a different CC mode here. */ | |
ac503e50 | 6368 | if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) |
6369 | compare_mode = GET_MODE (op0); | |
e4ffbd30 | 6370 | else if (inner_compare |
6371 | && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC | |
6372 | && new_code == old_code | |
6373 | && op0 == XEXP (inner_compare, 0) | |
6374 | && op1 == XEXP (inner_compare, 1)) | |
6375 | compare_mode = GET_MODE (inner_compare); | |
ac503e50 | 6376 | else |
6377 | compare_mode = SELECT_CC_MODE (new_code, op0, op1); | |
ccfa01f5 | 6378 | |
15460c97 | 6379 | #ifndef HAVE_cc0 |
2b0f64f9 | 6380 | /* If the mode changed, we have to change SET_DEST, the mode in the |
6381 | compare, and the mode in the place SET_DEST is used. If SET_DEST is | |
6382 | a hard register, just build new versions with the proper mode. If it | |
6383 | is a pseudo, we lose unless it is only time we set the pseudo, in | |
6384 | which case we can safely change its mode. */ | |
6385 | if (compare_mode != GET_MODE (dest)) | |
6386 | { | |
136305f4 | 6387 | if (can_change_dest_mode (dest, 0, compare_mode)) |
ccfa01f5 | 6388 | { |
136305f4 | 6389 | unsigned int regno = REGNO (dest); |
df738c1f | 6390 | rtx new_dest; |
136305f4 | 6391 | |
df738c1f | 6392 | if (regno < FIRST_PSEUDO_REGISTER) |
6393 | new_dest = gen_rtx_REG (compare_mode, regno); | |
6394 | else | |
6395 | { | |
6396 | SUBST_MODE (regno_reg_rtx[regno], compare_mode); | |
6397 | new_dest = regno_reg_rtx[regno]; | |
6398 | } | |
ccfa01f5 | 6399 | |
2b0f64f9 | 6400 | SUBST (SET_DEST (x), new_dest); |
6401 | SUBST (XEXP (*cc_use, 0), new_dest); | |
6402 | other_changed = 1; | |
ccfa01f5 | 6403 | |
2b0f64f9 | 6404 | dest = new_dest; |
ccfa01f5 | 6405 | } |
2b0f64f9 | 6406 | } |
15460c97 | 6407 | #endif /* cc0 */ |
6408 | #endif /* SELECT_CC_MODE */ | |
ccfa01f5 | 6409 | |
2b0f64f9 | 6410 | /* If the code changed, we have to build a new comparison in |
6411 | undobuf.other_insn. */ | |
6412 | if (new_code != old_code) | |
6413 | { | |
ae1b4595 | 6414 | int other_changed_previously = other_changed; |
2b0f64f9 | 6415 | unsigned HOST_WIDE_INT mask; |
cac5cd08 | 6416 | rtx old_cc_use = *cc_use; |
2b0f64f9 | 6417 | |
3380b197 | 6418 | SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), |
6419 | dest, const0_rtx)); | |
ae1b4595 | 6420 | other_changed = 1; |
2b0f64f9 | 6421 | |
6422 | /* If the only change we made was to change an EQ into an NE or | |
6423 | vice versa, OP0 has only one bit that might be nonzero, and OP1 | |
6424 | is zero, check if changing the user of the condition code will | |
6425 | produce a valid insn. If it won't, we can keep the original code | |
6426 | in that insn by surrounding our operation with an XOR. */ | |
6427 | ||
6428 | if (((old_code == NE && new_code == EQ) | |
6429 | || (old_code == EQ && new_code == NE)) | |
ae1b4595 | 6430 | && ! other_changed_previously && op1 == const0_rtx |
f179ee60 | 6431 | && HWI_COMPUTABLE_MODE_P (GET_MODE (op0)) |
2b0f64f9 | 6432 | && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) |
ccfa01f5 | 6433 | { |
2b0f64f9 | 6434 | rtx pat = PATTERN (other_insn), note = 0; |
ccfa01f5 | 6435 | |
d9943040 | 6436 | if ((recog_for_combine (&pat, other_insn, ¬e) < 0 |
2b0f64f9 | 6437 | && ! check_asm_operands (pat))) |
6438 | { | |
cac5cd08 | 6439 | *cc_use = old_cc_use; |
ae1b4595 | 6440 | other_changed = 0; |
ccfa01f5 | 6441 | |
5d5ee71f | 6442 | op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0, |
6443 | gen_int_mode (mask, | |
6444 | GET_MODE (op0))); | |
ccfa01f5 | 6445 | } |
ccfa01f5 | 6446 | } |
2b0f64f9 | 6447 | } |
6448 | ||
6449 | if (other_changed) | |
6450 | undobuf.other_insn = other_insn; | |
ccfa01f5 | 6451 | |
2b0f64f9 | 6452 | /* Otherwise, if we didn't previously have a COMPARE in the |
6453 | correct mode, we need one. */ | |
6454 | if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) | |
6455 | { | |
3380b197 | 6456 | SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); |
2b0f64f9 | 6457 | src = SET_SRC (x); |
ccfa01f5 | 6458 | } |
eba9b5f1 | 6459 | else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx) |
6460 | { | |
61e138d0 | 6461 | SUBST (SET_SRC (x), op0); |
eba9b5f1 | 6462 | src = SET_SRC (x); |
a0c938f0 | 6463 | } |
61e138d0 | 6464 | /* Otherwise, update the COMPARE if needed. */ |
6465 | else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1) | |
ccfa01f5 | 6466 | { |
61e138d0 | 6467 | SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); |
6468 | src = SET_SRC (x); | |
ccfa01f5 | 6469 | } |
2b0f64f9 | 6470 | } |
6471 | else | |
6472 | { | |
6473 | /* Get SET_SRC in a form where we have placed back any | |
6474 | compound expressions. Then do the checks below. */ | |
6475 | src = make_compound_operation (src, SET); | |
6476 | SUBST (SET_SRC (x), src); | |
6477 | } | |
ccfa01f5 | 6478 | |
2b0f64f9 | 6479 | /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, |
6480 | and X being a REG or (subreg (reg)), we may be able to convert this to | |
510f7125 | 6481 | (set (subreg:m2 x) (op)). |
a77b65e2 | 6482 | |
08eb940c | 6483 | We can always do this if M1 is narrower than M2 because that means that |
6484 | we only care about the low bits of the result. | |
a77b65e2 | 6485 | |
08eb940c | 6486 | However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot |
6487 | perform a narrower operation than requested since the high-order bits will | |
6488 | be undefined. On machine where it is defined, this transformation is safe | |
6489 | as long as M1 and M2 have the same number of words. */ | |
510f7125 | 6490 | |
2b0f64f9 | 6491 | if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) |
6720e96c | 6492 | && !OBJECT_P (SUBREG_REG (src)) |
2b0f64f9 | 6493 | && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) |
6494 | / UNITS_PER_WORD) | |
6495 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) | |
6496 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
08eb940c | 6497 | #ifndef WORD_REGISTER_OPERATIONS |
6498 | && (GET_MODE_SIZE (GET_MODE (src)) | |
a0c938f0 | 6499 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) |
08eb940c | 6500 | #endif |
897118e8 | 6501 | #ifdef CANNOT_CHANGE_MODE_CLASS |
8ad4c111 | 6502 | && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER |
897118e8 | 6503 | && REG_CANNOT_CHANGE_MODE_P (REGNO (dest), |
f65c89fb | 6504 | GET_MODE (SUBREG_REG (src)), |
22aae821 | 6505 | GET_MODE (src))) |
510f7125 | 6506 | #endif |
8ad4c111 | 6507 | && (REG_P (dest) |
2b0f64f9 | 6508 | || (GET_CODE (dest) == SUBREG |
8ad4c111 | 6509 | && REG_P (SUBREG_REG (dest))))) |
2b0f64f9 | 6510 | { |
6511 | SUBST (SET_DEST (x), | |
316f48ea | 6512 | gen_lowpart (GET_MODE (SUBREG_REG (src)), |
2b0f64f9 | 6513 | dest)); |
6514 | SUBST (SET_SRC (x), SUBREG_REG (src)); | |
6515 | ||
6516 | src = SET_SRC (x), dest = SET_DEST (x); | |
6517 | } | |
a77b65e2 | 6518 | |
fe4ca37c | 6519 | #ifdef HAVE_cc0 |
6520 | /* If we have (set (cc0) (subreg ...)), we try to remove the subreg | |
6521 | in SRC. */ | |
6522 | if (dest == cc0_rtx | |
6523 | && GET_CODE (src) == SUBREG | |
6524 | && subreg_lowpart_p (src) | |
ded805e6 | 6525 | && (GET_MODE_PRECISION (GET_MODE (src)) |
6526 | < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src))))) | |
fe4ca37c | 6527 | { |
6528 | rtx inner = SUBREG_REG (src); | |
6529 | enum machine_mode inner_mode = GET_MODE (inner); | |
6530 | ||
6531 | /* Here we make sure that we don't have a sign bit on. */ | |
f92430e0 | 6532 | if (val_signbit_known_clear_p (GET_MODE (src), |
6533 | nonzero_bits (inner, inner_mode))) | |
fe4ca37c | 6534 | { |
6535 | SUBST (SET_SRC (x), inner); | |
6536 | src = SET_SRC (x); | |
6537 | } | |
6538 | } | |
6539 | #endif | |
6540 | ||
8bf08534 | 6541 | #ifdef LOAD_EXTEND_OP |
2b0f64f9 | 6542 | /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this |
6543 | would require a paradoxical subreg. Replace the subreg with a | |
a92771b8 | 6544 | zero_extend to avoid the reload that would otherwise be required. */ |
2b0f64f9 | 6545 | |
6546 | if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) | |
65b45ec0 | 6547 | && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src))) |
21f1e711 | 6548 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN |
701e46d0 | 6549 | && SUBREG_BYTE (src) == 0 |
b537bfdb | 6550 | && paradoxical_subreg_p (src) |
e16ceb8e | 6551 | && MEM_P (SUBREG_REG (src))) |
2b0f64f9 | 6552 | { |
6553 | SUBST (SET_SRC (x), | |
27a9551b | 6554 | gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), |
6555 | GET_MODE (src), SUBREG_REG (src))); | |
2b0f64f9 | 6556 | |
6557 | src = SET_SRC (x); | |
6558 | } | |
ccfa01f5 | 6559 | #endif |
6560 | ||
2b0f64f9 | 6561 | /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we |
6562 | are comparing an item known to be 0 or -1 against 0, use a logical | |
6563 | operation instead. Check for one of the arms being an IOR of the other | |
6564 | arm with some value. We compute three terms to be IOR'ed together. In | |
6565 | practice, at most two will be nonzero. Then we do the IOR's. */ | |
6566 | ||
6567 | if (GET_CODE (dest) != PC | |
6568 | && GET_CODE (src) == IF_THEN_ELSE | |
082f40c3 | 6569 | && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT |
2b0f64f9 | 6570 | && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) |
6571 | && XEXP (XEXP (src, 0), 1) == const0_rtx | |
10e98608 | 6572 | && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) |
25b28391 | 6573 | #ifdef HAVE_conditional_move |
6574 | && ! can_conditionally_move_p (GET_MODE (src)) | |
6575 | #endif | |
2b0f64f9 | 6576 | && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), |
6577 | GET_MODE (XEXP (XEXP (src, 0), 0))) | |
ded805e6 | 6578 | == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0)))) |
2b0f64f9 | 6579 | && ! side_effects_p (src)) |
6580 | { | |
9c811526 | 6581 | rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE |
2b0f64f9 | 6582 | ? XEXP (src, 1) : XEXP (src, 2)); |
9c811526 | 6583 | rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE |
2b0f64f9 | 6584 | ? XEXP (src, 2) : XEXP (src, 1)); |
6585 | rtx term1 = const0_rtx, term2, term3; | |
6586 | ||
9c811526 | 6587 | if (GET_CODE (true_rtx) == IOR |
6588 | && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) | |
77676a31 | 6589 | term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx; |
9c811526 | 6590 | else if (GET_CODE (true_rtx) == IOR |
6591 | && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) | |
77676a31 | 6592 | term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx; |
9c811526 | 6593 | else if (GET_CODE (false_rtx) == IOR |
6594 | && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) | |
77676a31 | 6595 | term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx; |
9c811526 | 6596 | else if (GET_CODE (false_rtx) == IOR |
6597 | && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) | |
77676a31 | 6598 | term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx; |
9c811526 | 6599 | |
800a7def | 6600 | term2 = simplify_gen_binary (AND, GET_MODE (src), |
6601 | XEXP (XEXP (src, 0), 0), true_rtx); | |
6602 | term3 = simplify_gen_binary (AND, GET_MODE (src), | |
6603 | simplify_gen_unary (NOT, GET_MODE (src), | |
6604 | XEXP (XEXP (src, 0), 0), | |
6605 | GET_MODE (src)), | |
6606 | false_rtx); | |
2b0f64f9 | 6607 | |
6608 | SUBST (SET_SRC (x), | |
800a7def | 6609 | simplify_gen_binary (IOR, GET_MODE (src), |
6610 | simplify_gen_binary (IOR, GET_MODE (src), | |
6611 | term1, term2), | |
6612 | term3)); | |
2b0f64f9 | 6613 | |
6614 | src = SET_SRC (x); | |
6615 | } | |
ccfa01f5 | 6616 | |
c5c878e8 | 6617 | /* If either SRC or DEST is a CLOBBER of (const_int 0), make this |
6618 | whole thing fail. */ | |
6619 | if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) | |
6620 | return src; | |
6621 | else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) | |
6622 | return dest; | |
6623 | else | |
6624 | /* Convert this into a field assignment operation, if possible. */ | |
6625 | return make_field_assignment (x); | |
2b0f64f9 | 6626 | } |
6627 | \f | |
6628 | /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified | |
d7ef6792 | 6629 | result. */ |
2b0f64f9 | 6630 | |
6631 | static rtx | |
d7ef6792 | 6632 | simplify_logical (rtx x) |
2b0f64f9 | 6633 | { |
6634 | enum machine_mode mode = GET_MODE (x); | |
6635 | rtx op0 = XEXP (x, 0); | |
6636 | rtx op1 = XEXP (x, 1); | |
6637 | ||
6638 | switch (GET_CODE (x)) | |
6639 | { | |
ccfa01f5 | 6640 | case AND: |
cfb14220 | 6641 | /* We can call simplify_and_const_int only if we don't lose |
6642 | any (sign) bits when converting INTVAL (op1) to | |
6643 | "unsigned HOST_WIDE_INT". */ | |
971ba038 | 6644 | if (CONST_INT_P (op1) |
f179ee60 | 6645 | && (HWI_COMPUTABLE_MODE_P (mode) |
cfb14220 | 6646 | || INTVAL (op1) > 0)) |
ccfa01f5 | 6647 | { |
2b0f64f9 | 6648 | x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); |
ccfa01f5 | 6649 | if (GET_CODE (x) != AND) |
2b0f64f9 | 6650 | return x; |
0ecfc2c7 | 6651 | |
6720e96c | 6652 | op0 = XEXP (x, 0); |
6653 | op1 = XEXP (x, 1); | |
ccfa01f5 | 6654 | } |
6655 | ||
800a7def | 6656 | /* If we have any of (and (ior A B) C) or (and (xor A B) C), |
6657 | apply the distributive law and then the inverse distributive | |
6658 | law to see if things simplify. */ | |
8b0f9265 | 6659 | if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) |
ccfa01f5 | 6660 | { |
800a7def | 6661 | rtx result = distribute_and_simplify_rtx (x, 0); |
6662 | if (result) | |
6663 | return result; | |
ccfa01f5 | 6664 | } |
8b0f9265 | 6665 | if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) |
800a7def | 6666 | { |
6667 | rtx result = distribute_and_simplify_rtx (x, 1); | |
6668 | if (result) | |
6669 | return result; | |
6670 | } | |
ccfa01f5 | 6671 | break; |
6672 | ||
6673 | case IOR: | |
ccfa01f5 | 6674 | /* If we have (ior (and A B) C), apply the distributive law and then |
6675 | the inverse distributive law to see if things simplify. */ | |
6676 | ||
8b0f9265 | 6677 | if (GET_CODE (op0) == AND) |
6678 | { | |
800a7def | 6679 | rtx result = distribute_and_simplify_rtx (x, 0); |
6680 | if (result) | |
6681 | return result; | |
8b0f9265 | 6682 | } |
6683 | ||
6684 | if (GET_CODE (op1) == AND) | |
ccfa01f5 | 6685 | { |
800a7def | 6686 | rtx result = distribute_and_simplify_rtx (x, 1); |
6687 | if (result) | |
6688 | return result; | |
ccfa01f5 | 6689 | } |
ccfa01f5 | 6690 | break; |
0dbd1c74 | 6691 | |
6692 | default: | |
cc636d56 | 6693 | gcc_unreachable (); |
ccfa01f5 | 6694 | } |
6695 | ||
6696 | return x; | |
6697 | } | |
6698 | \f | |
6699 | /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound | |
6700 | operations" because they can be replaced with two more basic operations. | |
6701 | ZERO_EXTEND is also considered "compound" because it can be replaced with | |
6702 | an AND operation, which is simpler, though only one operation. | |
6703 | ||
6704 | The function expand_compound_operation is called with an rtx expression | |
510f7125 | 6705 | and will convert it to the appropriate shifts and AND operations, |
ccfa01f5 | 6706 | simplifying at each stage. |
6707 | ||
6708 | The function make_compound_operation is called to convert an expression | |
6709 | consisting of shifts and ANDs into the equivalent compound expression. | |
6710 | It is the inverse of this function, loosely speaking. */ | |
6711 | ||
6712 | static rtx | |
d598ad0d | 6713 | expand_compound_operation (rtx x) |
ccfa01f5 | 6714 | { |
02e7a332 | 6715 | unsigned HOST_WIDE_INT pos = 0, len; |
ccfa01f5 | 6716 | int unsignedp = 0; |
02e7a332 | 6717 | unsigned int modewidth; |
ccfa01f5 | 6718 | rtx tem; |
6719 | ||
6720 | switch (GET_CODE (x)) | |
6721 | { | |
6722 | case ZERO_EXTEND: | |
6723 | unsignedp = 1; | |
6724 | case SIGN_EXTEND: | |
afe723c2 | 6725 | /* We can't necessarily use a const_int for a multiword mode; |
6726 | it depends on implicitly extending the value. | |
6727 | Since we don't know the right way to extend it, | |
6728 | we can't tell whether the implicit way is right. | |
6729 | ||
6730 | Even for a mode that is no wider than a const_int, | |
6731 | we can't win, because we need to sign extend one of its bits through | |
6732 | the rest of it, and we don't know which bit. */ | |
971ba038 | 6733 | if (CONST_INT_P (XEXP (x, 0))) |
afe723c2 | 6734 | return x; |
ccfa01f5 | 6735 | |
2b0f64f9 | 6736 | /* Return if (subreg:MODE FROM 0) is not a safe replacement for |
6737 | (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM | |
6738 | because (SUBREG (MEM...)) is guaranteed to cause the MEM to be | |
6739 | reloaded. If not for that, MEM's would very rarely be safe. | |
6740 | ||
6741 | Reject MODEs bigger than a word, because we might not be able | |
6742 | to reference a two-register group starting with an arbitrary register | |
6743 | (and currently gen_lowpart might crash for a SUBREG). */ | |
510f7125 | 6744 | |
2b0f64f9 | 6745 | if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) |
ccfa01f5 | 6746 | return x; |
6747 | ||
dd067362 | 6748 | /* Reject MODEs that aren't scalar integers because turning vector |
6749 | or complex modes into shifts causes problems. */ | |
6750 | ||
6751 | if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
6752 | return x; | |
6753 | ||
ded805e6 | 6754 | len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))); |
ccfa01f5 | 6755 | /* If the inner object has VOIDmode (the only way this can happen |
dafdd1c8 | 6756 | is if it is an ASM_OPERANDS), we can't do anything since we don't |
ccfa01f5 | 6757 | know how much masking to do. */ |
6758 | if (len == 0) | |
6759 | return x; | |
6760 | ||
6761 | break; | |
6762 | ||
6763 | case ZERO_EXTRACT: | |
6764 | unsignedp = 1; | |
476d094d | 6765 | |
6766 | /* ... fall through ... */ | |
6767 | ||
ccfa01f5 | 6768 | case SIGN_EXTRACT: |
6769 | /* If the operand is a CLOBBER, just return it. */ | |
6770 | if (GET_CODE (XEXP (x, 0)) == CLOBBER) | |
6771 | return XEXP (x, 0); | |
6772 | ||
971ba038 | 6773 | if (!CONST_INT_P (XEXP (x, 1)) |
6774 | || !CONST_INT_P (XEXP (x, 2)) | |
ccfa01f5 | 6775 | || GET_MODE (XEXP (x, 0)) == VOIDmode) |
6776 | return x; | |
6777 | ||
dd067362 | 6778 | /* Reject MODEs that aren't scalar integers because turning vector |
6779 | or complex modes into shifts causes problems. */ | |
6780 | ||
6781 | if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
6782 | return x; | |
6783 | ||
ccfa01f5 | 6784 | len = INTVAL (XEXP (x, 1)); |
6785 | pos = INTVAL (XEXP (x, 2)); | |
6786 | ||
2854ce58 | 6787 | /* This should stay within the object being extracted, fail otherwise. */ |
ded805e6 | 6788 | if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))) |
2854ce58 | 6789 | return x; |
ccfa01f5 | 6790 | |
51356f86 | 6791 | if (BITS_BIG_ENDIAN) |
ded805e6 | 6792 | pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos; |
51356f86 | 6793 | |
ccfa01f5 | 6794 | break; |
6795 | ||
6796 | default: | |
6797 | return x; | |
6798 | } | |
0f177ed3 | 6799 | /* Convert sign extension to zero extension, if we know that the high |
6800 | bit is not set, as this is easier to optimize. It will be converted | |
6801 | back to cheaper alternative in make_extraction. */ | |
6802 | if (GET_CODE (x) == SIGN_EXTEND | |
f179ee60 | 6803 | && (HWI_COMPUTABLE_MODE_P (GET_MODE (x)) |
0f177ed3 | 6804 | && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) |
510f7125 | 6805 | & ~(((unsigned HOST_WIDE_INT) |
0f177ed3 | 6806 | GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) |
6807 | >> 1)) | |
6808 | == 0))) | |
6809 | { | |
6810 | rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); | |
195a9d8b | 6811 | rtx temp2 = expand_compound_operation (temp); |
6812 | ||
6813 | /* Make sure this is a profitable operation. */ | |
7013e87c | 6814 | if (set_src_cost (x, optimize_this_for_speed_p) |
6815 | > set_src_cost (temp2, optimize_this_for_speed_p)) | |
195a9d8b | 6816 | return temp2; |
7013e87c | 6817 | else if (set_src_cost (x, optimize_this_for_speed_p) |
6818 | > set_src_cost (temp, optimize_this_for_speed_p)) | |
195a9d8b | 6819 | return temp; |
6820 | else | |
6821 | return x; | |
0f177ed3 | 6822 | } |
ccfa01f5 | 6823 | |
0a3894c2 | 6824 | /* We can optimize some special cases of ZERO_EXTEND. */ |
6825 | if (GET_CODE (x) == ZERO_EXTEND) | |
6826 | { | |
6827 | /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we | |
a0c938f0 | 6828 | know that the last value didn't have any inappropriate bits |
6829 | set. */ | |
0a3894c2 | 6830 | if (GET_CODE (XEXP (x, 0)) == TRUNCATE |
6831 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
f179ee60 | 6832 | && HWI_COMPUTABLE_MODE_P (GET_MODE (x)) |
0a3894c2 | 6833 | && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) |
510f7125 | 6834 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0a3894c2 | 6835 | return XEXP (XEXP (x, 0), 0); |
6836 | ||
6837 | /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
6838 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6839 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
6840 | && subreg_lowpart_p (XEXP (x, 0)) | |
f179ee60 | 6841 | && HWI_COMPUTABLE_MODE_P (GET_MODE (x)) |
0a3894c2 | 6842 | && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) |
510f7125 | 6843 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0a3894c2 | 6844 | return SUBREG_REG (XEXP (x, 0)); |
6845 | ||
6846 | /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo | |
a0c938f0 | 6847 | is a comparison and STORE_FLAG_VALUE permits. This is like |
6848 | the first case, but it works even when GET_MODE (x) is larger | |
6849 | than HOST_WIDE_INT. */ | |
0a3894c2 | 6850 | if (GET_CODE (XEXP (x, 0)) == TRUNCATE |
6851 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
6720e96c | 6852 | && COMPARISON_P (XEXP (XEXP (x, 0), 0)) |
ded805e6 | 6853 | && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) |
0a3894c2 | 6854 | <= HOST_BITS_PER_WIDE_INT) |
897c6c81 | 6855 | && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0a3894c2 | 6856 | return XEXP (XEXP (x, 0), 0); |
6857 | ||
6858 | /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
6859 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6860 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
6861 | && subreg_lowpart_p (XEXP (x, 0)) | |
6720e96c | 6862 | && COMPARISON_P (SUBREG_REG (XEXP (x, 0))) |
ded805e6 | 6863 | && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) |
0a3894c2 | 6864 | <= HOST_BITS_PER_WIDE_INT) |
897c6c81 | 6865 | && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0a3894c2 | 6866 | return SUBREG_REG (XEXP (x, 0)); |
6867 | ||
0a3894c2 | 6868 | } |
6869 | ||
ccfa01f5 | 6870 | /* If we reach here, we want to return a pair of shifts. The inner |
6871 | shift is a left shift of BITSIZE - POS - LEN bits. The outer | |
6872 | shift is a right shift of BITSIZE - LEN bits. It is arithmetic or | |
6873 | logical depending on the value of UNSIGNEDP. | |
6874 | ||
6875 | If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be | |
6876 | converted into an AND of a shift. | |
6877 | ||
6878 | We must check for the case where the left shift would have a negative | |
6879 | count. This can happen in a case like (x >> 31) & 255 on machines | |
6880 | that can't shift by a constant. On those machines, we would first | |
510f7125 | 6881 | combine the shift with the AND to produce a variable-position |
d306bc62 | 6882 | extraction. Then the constant of 31 would be substituted in |
6883 | to produce such a position. */ | |
ccfa01f5 | 6884 | |
ded805e6 | 6885 | modewidth = GET_MODE_PRECISION (GET_MODE (x)); |
d306bc62 | 6886 | if (modewidth >= pos + len) |
dcfc98c1 | 6887 | { |
6888 | enum machine_mode mode = GET_MODE (x); | |
6889 | tem = gen_lowpart (mode, XEXP (x, 0)); | |
6890 | if (!tem || GET_CODE (tem) == CLOBBER) | |
6891 | return x; | |
6892 | tem = simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
6893 | tem, modewidth - pos - len); | |
6894 | tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, | |
6895 | mode, tem, modewidth - len); | |
6896 | } | |
1bb04728 | 6897 | else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) |
6898 | tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), | |
6899 | simplify_shift_const (NULL_RTX, LSHIFTRT, | |
ccfa01f5 | 6900 | GET_MODE (x), |
6901 | XEXP (x, 0), pos), | |
897c6c81 | 6902 | ((unsigned HOST_WIDE_INT) 1 << len) - 1); |
ccfa01f5 | 6903 | else |
6904 | /* Any other cases we can't handle. */ | |
6905 | return x; | |
ccfa01f5 | 6906 | |
6907 | /* If we couldn't do this for some reason, return the original | |
6908 | expression. */ | |
6909 | if (GET_CODE (tem) == CLOBBER) | |
6910 | return x; | |
6911 | ||
6912 | return tem; | |
6913 | } | |
6914 | \f | |
6915 | /* X is a SET which contains an assignment of one object into | |
6916 | a part of another (such as a bit-field assignment, STRICT_LOW_PART, | |
6917 | or certain SUBREGS). If possible, convert it into a series of | |
6918 | logical operations. | |
6919 | ||
6920 | We half-heartedly support variable positions, but do not at all | |
6921 | support variable lengths. */ | |
6922 | ||
81a410b1 | 6923 | static const_rtx |
6924 | expand_field_assignment (const_rtx x) | |
ccfa01f5 | 6925 | { |
6926 | rtx inner; | |
a92771b8 | 6927 | rtx pos; /* Always counts from low bit. */ |
ccfa01f5 | 6928 | int len; |
800a7def | 6929 | rtx mask, cleared, masked; |
ccfa01f5 | 6930 | enum machine_mode compute_mode; |
6931 | ||
6932 | /* Loop until we find something we can't simplify. */ | |
6933 | while (1) | |
6934 | { | |
6935 | if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART | |
6936 | && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) | |
6937 | { | |
6938 | inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); | |
ded805e6 | 6939 | len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))); |
b3a976d8 | 6940 | pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); |
ccfa01f5 | 6941 | } |
6942 | else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
971ba038 | 6943 | && CONST_INT_P (XEXP (SET_DEST (x), 1))) |
ccfa01f5 | 6944 | { |
6945 | inner = XEXP (SET_DEST (x), 0); | |
6946 | len = INTVAL (XEXP (SET_DEST (x), 1)); | |
6947 | pos = XEXP (SET_DEST (x), 2); | |
6948 | ||
89370a1e | 6949 | /* A constant position should stay within the width of INNER. */ |
971ba038 | 6950 | if (CONST_INT_P (pos) |
ded805e6 | 6951 | && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner))) |
2854ce58 | 6952 | break; |
ccfa01f5 | 6953 | |
51356f86 | 6954 | if (BITS_BIG_ENDIAN) |
6955 | { | |
971ba038 | 6956 | if (CONST_INT_P (pos)) |
ded805e6 | 6957 | pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len |
51356f86 | 6958 | - INTVAL (pos)); |
6959 | else if (GET_CODE (pos) == MINUS | |
971ba038 | 6960 | && CONST_INT_P (XEXP (pos, 1)) |
51356f86 | 6961 | && (INTVAL (XEXP (pos, 1)) |
ded805e6 | 6962 | == GET_MODE_PRECISION (GET_MODE (inner)) - len)) |
51356f86 | 6963 | /* If position is ADJUST - X, new position is X. */ |
6964 | pos = XEXP (pos, 0); | |
6965 | else | |
5d5ee71f | 6966 | { |
6967 | HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner)); | |
6968 | pos = simplify_gen_binary (MINUS, GET_MODE (pos), | |
6969 | gen_int_mode (prec - len, | |
6970 | GET_MODE (pos)), | |
6971 | pos); | |
6972 | } | |
51356f86 | 6973 | } |
ccfa01f5 | 6974 | } |
6975 | ||
6976 | /* A SUBREG between two modes that occupy the same numbers of words | |
6977 | can be done by moving the SUBREG to the source. */ | |
6978 | else if (GET_CODE (SET_DEST (x)) == SUBREG | |
b8667333 | 6979 | /* We need SUBREGs to compute nonzero_bits properly. */ |
6980 | && nonzero_sign_valid | |
ccfa01f5 | 6981 | && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) |
6982 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
6983 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
6984 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
6985 | { | |
941522d6 | 6986 | x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), |
316f48ea | 6987 | gen_lowpart |
7014838c | 6988 | (GET_MODE (SUBREG_REG (SET_DEST (x))), |
6989 | SET_SRC (x))); | |
ccfa01f5 | 6990 | continue; |
6991 | } | |
6992 | else | |
6993 | break; | |
6994 | ||
6995 | while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
6996 | inner = SUBREG_REG (inner); | |
6997 | ||
6998 | compute_mode = GET_MODE (inner); | |
6999 | ||
dd067362 | 7000 | /* Don't attempt bitwise arithmetic on non scalar integer modes. */ |
7001 | if (! SCALAR_INT_MODE_P (compute_mode)) | |
a976c13c | 7002 | { |
7003 | enum machine_mode imode; | |
7004 | ||
dd067362 | 7005 | /* Don't do anything for vector or complex integral types. */ |
a976c13c | 7006 | if (! FLOAT_MODE_P (compute_mode)) |
7007 | break; | |
7008 | ||
7009 | /* Try to find an integral mode to pun with. */ | |
7010 | imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); | |
7011 | if (imode == BLKmode) | |
7012 | break; | |
7013 | ||
7014 | compute_mode = imode; | |
316f48ea | 7015 | inner = gen_lowpart (imode, inner); |
a976c13c | 7016 | } |
7017 | ||
ccfa01f5 | 7018 | /* Compute a mask of LEN bits, if we can do this on the host machine. */ |
800a7def | 7019 | if (len >= HOST_BITS_PER_WIDE_INT) |
ccfa01f5 | 7020 | break; |
7021 | ||
7022 | /* Now compute the equivalent expression. Make a copy of INNER | |
7023 | for the SET_DEST in case it is a MEM into which we will substitute; | |
7024 | we don't want shared RTL in that case. */ | |
5d5ee71f | 7025 | mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1, |
7026 | compute_mode); | |
800a7def | 7027 | cleared = simplify_gen_binary (AND, compute_mode, |
7028 | simplify_gen_unary (NOT, compute_mode, | |
7029 | simplify_gen_binary (ASHIFT, | |
7030 | compute_mode, | |
7031 | mask, pos), | |
7032 | compute_mode), | |
7033 | inner); | |
7034 | masked = simplify_gen_binary (ASHIFT, compute_mode, | |
7035 | simplify_gen_binary ( | |
7036 | AND, compute_mode, | |
7037 | gen_lowpart (compute_mode, SET_SRC (x)), | |
7038 | mask), | |
7039 | pos); | |
7040 | ||
7041 | x = gen_rtx_SET (VOIDmode, copy_rtx (inner), | |
7042 | simplify_gen_binary (IOR, compute_mode, | |
7043 | cleared, masked)); | |
ccfa01f5 | 7044 | } |
7045 | ||
7046 | return x; | |
7047 | } | |
7048 | \f | |
f017138e | 7049 | /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, |
139a6a2b | 7050 | it is an RTX that represents the (variable) starting position; otherwise, |
7051 | POS is the (constant) starting bit position. Both are counted from the LSB. | |
ccfa01f5 | 7052 | |
139a6a2b | 7053 | UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one. |
ccfa01f5 | 7054 | |
139a6a2b | 7055 | IN_DEST is nonzero if this is a reference in the destination of a SET. |
7056 | This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, | |
ccfa01f5 | 7057 | a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will |
7058 | be used. | |
7059 | ||
d10cfa8d | 7060 | IN_COMPARE is nonzero if we are in a COMPARE. This means that a |
ccfa01f5 | 7061 | ZERO_EXTRACT should be built even for bits starting at bit 0. |
7062 | ||
4dad978c | 7063 | MODE is the desired mode of the result (if IN_DEST == 0). |
7064 | ||
7065 | The result is an RTX for the extraction or NULL_RTX if the target | |
7066 | can't handle it. */ | |
ccfa01f5 | 7067 | |
7068 | static rtx | |
d598ad0d | 7069 | make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos, |
7070 | rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp, | |
7071 | int in_dest, int in_compare) | |
ccfa01f5 | 7072 | { |
5e8b3c5a | 7073 | /* This mode describes the size of the storage area |
7074 | to fetch the overall value from. Within that, we | |
7075 | ignore the POS lowest bits, etc. */ | |
ccfa01f5 | 7076 | enum machine_mode is_mode = GET_MODE (inner); |
7077 | enum machine_mode inner_mode; | |
89370a1e | 7078 | enum machine_mode wanted_inner_mode; |
e2595aa1 | 7079 | enum machine_mode wanted_inner_reg_mode = word_mode; |
ccfa01f5 | 7080 | enum machine_mode pos_mode = word_mode; |
7081 | enum machine_mode extraction_mode = word_mode; | |
7082 | enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); | |
d328ebdf | 7083 | rtx new_rtx = 0; |
f017138e | 7084 | rtx orig_pos_rtx = pos_rtx; |
02e7a332 | 7085 | HOST_WIDE_INT orig_pos; |
ccfa01f5 | 7086 | |
139a6a2b | 7087 | if (pos_rtx && CONST_INT_P (pos_rtx)) |
7088 | pos = INTVAL (pos_rtx), pos_rtx = 0; | |
7089 | ||
89370a1e | 7090 | if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) |
5e8b3c5a | 7091 | { |
7092 | /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), | |
7093 | consider just the QI as the memory to extract from. | |
7094 | The subreg adds or removes high bits; its mode is | |
7095 | irrelevant to the meaning of this extraction, | |
7096 | since POS and LEN count from the lsb. */ | |
e16ceb8e | 7097 | if (MEM_P (SUBREG_REG (inner))) |
5e8b3c5a | 7098 | is_mode = GET_MODE (SUBREG_REG (inner)); |
7099 | inner = SUBREG_REG (inner); | |
7100 | } | |
0ecae535 | 7101 | else if (GET_CODE (inner) == ASHIFT |
971ba038 | 7102 | && CONST_INT_P (XEXP (inner, 1)) |
0ecae535 | 7103 | && pos_rtx == 0 && pos == 0 |
897c6c81 | 7104 | && len > UINTVAL (XEXP (inner, 1))) |
0ecae535 | 7105 | { |
7106 | /* We're extracting the least significant bits of an rtx | |
7107 | (ashift X (const_int C)), where LEN > C. Extract the | |
7108 | least significant (LEN - C) bits of X, giving an rtx | |
7109 | whose mode is MODE, then shift it left C times. */ | |
d328ebdf | 7110 | new_rtx = make_extraction (mode, XEXP (inner, 0), |
0ecae535 | 7111 | 0, 0, len - INTVAL (XEXP (inner, 1)), |
7112 | unsignedp, in_dest, in_compare); | |
d328ebdf | 7113 | if (new_rtx != 0) |
7114 | return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1)); | |
0ecae535 | 7115 | } |
50c95104 | 7116 | else if (GET_CODE (inner) == TRUNCATE) |
7117 | inner = XEXP (inner, 0); | |
ccfa01f5 | 7118 | |
7119 | inner_mode = GET_MODE (inner); | |
7120 | ||
ccfa01f5 | 7121 | /* See if this can be done without an extraction. We never can if the |
7122 | width of the field is not the same as that of some integer mode. For | |
7123 | registers, we can only avoid the extraction if the position is at the | |
7124 | low-order bit and this is either not in the destination or we have the | |
7125 | appropriate STRICT_LOW_PART operation available. | |
7126 | ||
7127 | For MEM, we can avoid an extract if the field starts on an appropriate | |
89370a1e | 7128 | boundary and we can change the mode of the memory reference. */ |
ccfa01f5 | 7129 | |
7130 | if (tmode != BLKmode | |
db321fd6 | 7131 | && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 |
e16ceb8e | 7132 | && !MEM_P (inner) |
4c199243 | 7133 | && (inner_mode == tmode |
7134 | || !REG_P (inner) | |
396f2130 | 7135 | || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode) |
4c199243 | 7136 | || reg_truncated_to_mode (tmode, inner)) |
ccfa01f5 | 7137 | && (! in_dest |
8ad4c111 | 7138 | || (REG_P (inner) |
ad99e708 | 7139 | && have_insn_for (STRICT_LOW_PART, tmode)))) |
e16ceb8e | 7140 | || (MEM_P (inner) && pos_rtx == 0 |
9efc0f8e | 7141 | && (pos |
7142 | % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) | |
7143 | : BITS_PER_UNIT)) == 0 | |
ccfa01f5 | 7144 | /* We can't do this if we are widening INNER_MODE (it |
7145 | may not be aligned, for one thing). */ | |
ded805e6 | 7146 | && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode) |
ccfa01f5 | 7147 | && (inner_mode == tmode |
4e27ffd0 | 7148 | || (! mode_dependent_address_p (XEXP (inner, 0), |
7149 | MEM_ADDR_SPACE (inner)) | |
ccfa01f5 | 7150 | && ! MEM_VOLATILE_P (inner)))))) |
7151 | { | |
ccfa01f5 | 7152 | /* If INNER is a MEM, make a new MEM that encompasses just the desired |
7153 | field. If the original and current mode are the same, we need not | |
510f7125 | 7154 | adjust the offset. Otherwise, we do if bytes big endian. |
ccfa01f5 | 7155 | |
db321fd6 | 7156 | If INNER is not a MEM, get a piece consisting of just the field |
7157 | of interest (in this case POS % BITS_PER_WORD must be 0). */ | |
ccfa01f5 | 7158 | |
e16ceb8e | 7159 | if (MEM_P (inner)) |
ccfa01f5 | 7160 | { |
e4e86ec5 | 7161 | HOST_WIDE_INT offset; |
7162 | ||
5e8b3c5a | 7163 | /* POS counts from lsb, but make OFFSET count in memory order. */ |
7164 | if (BYTES_BIG_ENDIAN) | |
ded805e6 | 7165 | offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT; |
5e8b3c5a | 7166 | else |
7167 | offset = pos / BITS_PER_UNIT; | |
ccfa01f5 | 7168 | |
d328ebdf | 7169 | new_rtx = adjust_address_nv (inner, tmode, offset); |
ccfa01f5 | 7170 | } |
8ad4c111 | 7171 | else if (REG_P (inner)) |
eee391de | 7172 | { |
eee391de | 7173 | if (tmode != inner_mode) |
701e46d0 | 7174 | { |
316f48ea | 7175 | /* We can't call gen_lowpart in a DEST since we |
6432e7e4 | 7176 | always want a SUBREG (see below) and it would sometimes |
7177 | return a new hard register. */ | |
7178 | if (pos || in_dest) | |
ac9db7eb | 7179 | { |
ac9db7eb | 7180 | HOST_WIDE_INT final_word = pos / BITS_PER_WORD; |
7181 | ||
7182 | if (WORDS_BIG_ENDIAN | |
7183 | && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) | |
7184 | final_word = ((GET_MODE_SIZE (inner_mode) | |
7185 | - GET_MODE_SIZE (tmode)) | |
7186 | / UNITS_PER_WORD) - final_word; | |
7187 | ||
7188 | final_word *= UNITS_PER_WORD; | |
7189 | if (BYTES_BIG_ENDIAN && | |
7190 | GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) | |
7191 | final_word += (GET_MODE_SIZE (inner_mode) | |
7192 | - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; | |
7193 | ||
7194 | /* Avoid creating invalid subregs, for example when | |
7195 | simplifying (x>>32)&255. */ | |
432ef5b7 | 7196 | if (!validate_subreg (tmode, inner_mode, inner, final_word)) |
ac9db7eb | 7197 | return NULL_RTX; |
7198 | ||
d328ebdf | 7199 | new_rtx = gen_rtx_SUBREG (tmode, inner, final_word); |
ac9db7eb | 7200 | } |
7201 | else | |
d328ebdf | 7202 | new_rtx = gen_lowpart (tmode, inner); |
701e46d0 | 7203 | } |
87e97de6 | 7204 | else |
d328ebdf | 7205 | new_rtx = inner; |
87e97de6 | 7206 | } |
ccfa01f5 | 7207 | else |
d328ebdf | 7208 | new_rtx = force_to_mode (inner, tmode, |
390fc1d2 | 7209 | len >= HOST_BITS_PER_WIDE_INT |
b5d326b3 | 7210 | ? ~(unsigned HOST_WIDE_INT) 0 |
fe352cf1 | 7211 | : ((unsigned HOST_WIDE_INT) 1 << len) - 1, |
b92e2e43 | 7212 | 0); |
ccfa01f5 | 7213 | |
510f7125 | 7214 | /* If this extraction is going into the destination of a SET, |
ccfa01f5 | 7215 | make a STRICT_LOW_PART unless we made a MEM. */ |
7216 | ||
7217 | if (in_dest) | |
d328ebdf | 7218 | return (MEM_P (new_rtx) ? new_rtx |
7219 | : (GET_CODE (new_rtx) != SUBREG | |
941522d6 | 7220 | ? gen_rtx_CLOBBER (tmode, const0_rtx) |
d328ebdf | 7221 | : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx))); |
ccfa01f5 | 7222 | |
0f177ed3 | 7223 | if (mode == tmode) |
d328ebdf | 7224 | return new_rtx; |
0f177ed3 | 7225 | |
efa08fc2 | 7226 | if (CONST_SCALAR_INT_P (new_rtx)) |
0895c53c | 7227 | return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, |
7228 | mode, new_rtx, tmode); | |
dbd8525d | 7229 | |
0f177ed3 | 7230 | /* If we know that no extraneous bits are set, and that the high |
7231 | bit is not set, convert the extraction to the cheaper of | |
7232 | sign and zero extension, that are equivalent in these cases. */ | |
7233 | if (flag_expensive_optimizations | |
f179ee60 | 7234 | && (HWI_COMPUTABLE_MODE_P (tmode) |
d328ebdf | 7235 | && ((nonzero_bits (new_rtx, tmode) |
f179ee60 | 7236 | & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1)) |
0f177ed3 | 7237 | == 0))) |
7238 | { | |
d328ebdf | 7239 | rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx); |
7240 | rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx); | |
0f177ed3 | 7241 | |
7242 | /* Prefer ZERO_EXTENSION, since it gives more information to | |
7243 | backends. */ | |
7013e87c | 7244 | if (set_src_cost (temp, optimize_this_for_speed_p) |
7245 | <= set_src_cost (temp1, optimize_this_for_speed_p)) | |
0f177ed3 | 7246 | return temp; |
7247 | return temp1; | |
7248 | } | |
7249 | ||
ccfa01f5 | 7250 | /* Otherwise, sign- or zero-extend unless we already are in the |
7251 | proper mode. */ | |
7252 | ||
3380b197 | 7253 | return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, |
d328ebdf | 7254 | mode, new_rtx)); |
ccfa01f5 | 7255 | } |
7256 | ||
4dcbb8c3 | 7257 | /* Unless this is a COMPARE or we have a funny memory reference, |
7258 | don't do anything with zero-extending field extracts starting at | |
7259 | the low-order bit since they are simple AND operations. */ | |
f017138e | 7260 | if (pos_rtx == 0 && pos == 0 && ! in_dest |
89370a1e | 7261 | && ! in_compare && unsignedp) |
ccfa01f5 | 7262 | return 0; |
7263 | ||
89370a1e | 7264 | /* Unless INNER is not MEM, reject this if we would be spanning bytes or |
7265 | if the position is not a constant and the length is not 1. In all | |
7266 | other cases, we would only be going outside our object in cases when | |
7267 | an original shift would have been undefined. */ | |
7268 | if (MEM_P (inner) | |
ded805e6 | 7269 | && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode)) |
b6006adf | 7270 | || (pos_rtx != 0 && len != 1))) |
7271 | return 0; | |
7272 | ||
26427966 | 7273 | enum extraction_pattern pattern = (in_dest ? EP_insv |
7274 | : unsignedp ? EP_extzv : EP_extv); | |
7275 | ||
7276 | /* If INNER is not from memory, we want it to have the mode of a register | |
7277 | extraction pattern's structure operand, or word_mode if there is no | |
7278 | such pattern. The same applies to extraction_mode and pos_mode | |
7279 | and their respective operands. | |
7280 | ||
7281 | For memory, assume that the desired extraction_mode and pos_mode | |
7282 | are the same as for a register operation, since at present we don't | |
7283 | have named patterns for aligned memory structures. */ | |
7284 | struct extraction_insn insn; | |
7285 | if (get_best_reg_extraction_insn (&insn, pattern, | |
7286 | GET_MODE_BITSIZE (inner_mode), mode)) | |
ccfa01f5 | 7287 | { |
26427966 | 7288 | wanted_inner_reg_mode = insn.struct_mode; |
7289 | pos_mode = insn.pos_mode; | |
7290 | extraction_mode = insn.field_mode; | |
ccfa01f5 | 7291 | } |
ccfa01f5 | 7292 | |
7293 | /* Never narrow an object, since that might not be safe. */ | |
7294 | ||
7295 | if (mode != VOIDmode | |
7296 | && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) | |
7297 | extraction_mode = mode; | |
7298 | ||
e16ceb8e | 7299 | if (!MEM_P (inner)) |
e2595aa1 | 7300 | wanted_inner_mode = wanted_inner_reg_mode; |
89370a1e | 7301 | else |
7302 | { | |
7303 | /* Be careful not to go beyond the extracted object and maintain the | |
a0c938f0 | 7304 | natural alignment of the memory. */ |
89370a1e | 7305 | wanted_inner_mode = smallest_mode_for_size (len, MODE_INT); |
7306 | while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len | |
7307 | > GET_MODE_BITSIZE (wanted_inner_mode)) | |
7308 | { | |
7309 | wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode); | |
7310 | gcc_assert (wanted_inner_mode != VOIDmode); | |
7311 | } | |
89370a1e | 7312 | } |
ccfa01f5 | 7313 | |
390fc1d2 | 7314 | orig_pos = pos; |
7315 | ||
51356f86 | 7316 | if (BITS_BIG_ENDIAN) |
7317 | { | |
3a92d1a4 | 7318 | /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to |
7319 | BITS_BIG_ENDIAN style. If position is constant, compute new | |
7320 | position. Otherwise, build subtraction. | |
7321 | Note that POS is relative to the mode of the original argument. | |
7322 | If it's a MEM we need to recompute POS relative to that. | |
7323 | However, if we're extracting from (or inserting into) a register, | |
7324 | we want to recompute POS relative to wanted_inner_mode. */ | |
e16ceb8e | 7325 | int width = (MEM_P (inner) |
3a92d1a4 | 7326 | ? GET_MODE_BITSIZE (is_mode) |
7327 | : GET_MODE_BITSIZE (wanted_inner_mode)); | |
7328 | ||
51356f86 | 7329 | if (pos_rtx == 0) |
3a92d1a4 | 7330 | pos = width - len - pos; |
51356f86 | 7331 | else |
7332 | pos_rtx | |
c338f2e3 | 7333 | = gen_rtx_MINUS (GET_MODE (pos_rtx), |
7334 | gen_int_mode (width - len, GET_MODE (pos_rtx)), | |
7335 | pos_rtx); | |
3a92d1a4 | 7336 | /* POS may be less than 0 now, but we check for that below. |
e16ceb8e | 7337 | Note that it can only be less than 0 if !MEM_P (inner). */ |
51356f86 | 7338 | } |
ccfa01f5 | 7339 | |
89370a1e | 7340 | /* If INNER has a wider mode, and this is a constant extraction, try to |
7341 | make it smaller and adjust the byte to point to the byte containing | |
ccfa01f5 | 7342 | the value. */ |
e2595aa1 | 7343 | if (wanted_inner_mode != VOIDmode |
89370a1e | 7344 | && inner_mode != wanted_inner_mode |
7345 | && ! pos_rtx | |
e2595aa1 | 7346 | && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) |
89370a1e | 7347 | && MEM_P (inner) |
4e27ffd0 | 7348 | && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner)) |
89370a1e | 7349 | && ! MEM_VOLATILE_P (inner)) |
ccfa01f5 | 7350 | { |
7351 | int offset = 0; | |
7352 | ||
7353 | /* The computations below will be correct if the machine is big | |
7354 | endian in both bits and bytes or little endian in bits and bytes. | |
7355 | If it is mixed, we must adjust. */ | |
510f7125 | 7356 | |
ccfa01f5 | 7357 | /* If bytes are big endian and we had a paradoxical SUBREG, we must |
a92771b8 | 7358 | adjust OFFSET to compensate. */ |
51356f86 | 7359 | if (BYTES_BIG_ENDIAN |
ccfa01f5 | 7360 | && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) |
7361 | offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); | |
ccfa01f5 | 7362 | |
89370a1e | 7363 | /* We can now move to the desired byte. */ |
7364 | offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode)) | |
7365 | * GET_MODE_SIZE (wanted_inner_mode); | |
7366 | pos %= GET_MODE_BITSIZE (wanted_inner_mode); | |
ccfa01f5 | 7367 | |
51356f86 | 7368 | if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN |
e2595aa1 | 7369 | && is_mode != wanted_inner_mode) |
a6db14c0 | 7370 | offset = (GET_MODE_SIZE (is_mode) |
e2595aa1 | 7371 | - GET_MODE_SIZE (wanted_inner_mode) - offset); |
a6db14c0 | 7372 | |
89370a1e | 7373 | inner = adjust_address_nv (inner, wanted_inner_mode, offset); |
ccfa01f5 | 7374 | } |
7375 | ||
658e1523 | 7376 | /* If INNER is not memory, get it into the proper mode. If we are changing |
7377 | its mode, POS must be a constant and smaller than the size of the new | |
7378 | mode. */ | |
e16ceb8e | 7379 | else if (!MEM_P (inner)) |
86f13df2 | 7380 | { |
658e1523 | 7381 | /* On the LHS, don't create paradoxical subregs implicitely truncating |
7382 | the register unless TRULY_NOOP_TRUNCATION. */ | |
7383 | if (in_dest | |
396f2130 | 7384 | && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner), |
7385 | wanted_inner_mode)) | |
658e1523 | 7386 | return NULL_RTX; |
7387 | ||
86f13df2 | 7388 | if (GET_MODE (inner) != wanted_inner_mode |
7389 | && (pos_rtx != 0 | |
7390 | || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) | |
658e1523 | 7391 | return NULL_RTX; |
86f13df2 | 7392 | |
f8eca087 | 7393 | if (orig_pos < 0) |
658e1523 | 7394 | return NULL_RTX; |
f8eca087 | 7395 | |
86f13df2 | 7396 | inner = force_to_mode (inner, wanted_inner_mode, |
7397 | pos_rtx | |
7398 | || len + orig_pos >= HOST_BITS_PER_WIDE_INT | |
b5d326b3 | 7399 | ? ~(unsigned HOST_WIDE_INT) 0 |
fe352cf1 | 7400 | : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) |
7401 | << orig_pos), | |
b92e2e43 | 7402 | 0); |
86f13df2 | 7403 | } |
ccfa01f5 | 7404 | |
7405 | /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we | |
7406 | have to zero extend. Otherwise, we can just use a SUBREG. */ | |
f017138e | 7407 | if (pos_rtx != 0 |
ccfa01f5 | 7408 | && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) |
0f177ed3 | 7409 | { |
1bf020d9 | 7410 | rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx, |
7411 | GET_MODE (pos_rtx)); | |
0f177ed3 | 7412 | |
7413 | /* If we know that no extraneous bits are set, and that the high | |
4a82352a | 7414 | bit is not set, convert extraction to cheaper one - either |
0f177ed3 | 7415 | SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these |
7416 | cases. */ | |
7417 | if (flag_expensive_optimizations | |
f179ee60 | 7418 | && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx)) |
0f177ed3 | 7419 | && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) |
510f7125 | 7420 | & ~(((unsigned HOST_WIDE_INT) |
7421 | GET_MODE_MASK (GET_MODE (pos_rtx))) | |
7422 | >> 1)) | |
0f177ed3 | 7423 | == 0))) |
7424 | { | |
1bf020d9 | 7425 | rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx, |
7426 | GET_MODE (pos_rtx)); | |
0f177ed3 | 7427 | |
0032d72b | 7428 | /* Prefer ZERO_EXTENSION, since it gives more information to |
0f177ed3 | 7429 | backends. */ |
7013e87c | 7430 | if (set_src_cost (temp1, optimize_this_for_speed_p) |
7431 | < set_src_cost (temp, optimize_this_for_speed_p)) | |
0f177ed3 | 7432 | temp = temp1; |
7433 | } | |
7434 | pos_rtx = temp; | |
7435 | } | |
ccfa01f5 | 7436 | |
f017138e | 7437 | /* Make POS_RTX unless we already have it and it is correct. If we don't |
7438 | have a POS_RTX but we do have an ORIG_POS_RTX, the latter must | |
a92771b8 | 7439 | be a CONST_INT. */ |
f017138e | 7440 | if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) |
7441 | pos_rtx = orig_pos_rtx; | |
7442 | ||
7443 | else if (pos_rtx == 0) | |
1bb04728 | 7444 | pos_rtx = GEN_INT (pos); |
ccfa01f5 | 7445 | |
7446 | /* Make the required operation. See if we can use existing rtx. */ | |
d328ebdf | 7447 | new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, |
1bb04728 | 7448 | extraction_mode, inner, GEN_INT (len), pos_rtx); |
ccfa01f5 | 7449 | if (! in_dest) |
d328ebdf | 7450 | new_rtx = gen_lowpart (mode, new_rtx); |
ccfa01f5 | 7451 | |
d328ebdf | 7452 | return new_rtx; |
ccfa01f5 | 7453 | } |
7454 | \f | |
8c7ee42a | 7455 | /* See if X contains an ASHIFT of COUNT or more bits that can be commuted |
7456 | with any other operations in X. Return X without that shift if so. */ | |
7457 | ||
7458 | static rtx | |
d598ad0d | 7459 | extract_left_shift (rtx x, int count) |
8c7ee42a | 7460 | { |
7461 | enum rtx_code code = GET_CODE (x); | |
7462 | enum machine_mode mode = GET_MODE (x); | |
7463 | rtx tem; | |
7464 | ||
7465 | switch (code) | |
7466 | { | |
7467 | case ASHIFT: | |
7468 | /* This is the shift itself. If it is wide enough, we will return | |
7469 | either the value being shifted if the shift count is equal to | |
7470 | COUNT or a shift for the difference. */ | |
971ba038 | 7471 | if (CONST_INT_P (XEXP (x, 1)) |
8c7ee42a | 7472 | && INTVAL (XEXP (x, 1)) >= count) |
7473 | return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), | |
7474 | INTVAL (XEXP (x, 1)) - count); | |
7475 | break; | |
7476 | ||
7477 | case NEG: case NOT: | |
7478 | if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) | |
3380b197 | 7479 | return simplify_gen_unary (code, mode, tem, mode); |
8c7ee42a | 7480 | |
7481 | break; | |
7482 | ||
7483 | case PLUS: case IOR: case XOR: case AND: | |
7484 | /* If we can safely shift this constant and we find the inner shift, | |
7485 | make a new operation. */ | |
971ba038 | 7486 | if (CONST_INT_P (XEXP (x, 1)) |
897c6c81 | 7487 | && (UINTVAL (XEXP (x, 1)) |
7488 | & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0 | |
8c7ee42a | 7489 | && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) |
5d5ee71f | 7490 | { |
7491 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count; | |
7492 | return simplify_gen_binary (code, mode, tem, | |
7493 | gen_int_mode (val, mode)); | |
7494 | } | |
8c7ee42a | 7495 | break; |
510f7125 | 7496 | |
0dbd1c74 | 7497 | default: |
7498 | break; | |
8c7ee42a | 7499 | } |
7500 | ||
7501 | return 0; | |
7502 | } | |
7503 | \f | |
ccfa01f5 | 7504 | /* Look at the expression rooted at X. Look for expressions |
7505 | equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. | |
7506 | Form these expressions. | |
7507 | ||
7508 | Return the new rtx, usually just X. | |
7509 | ||
6c842310 | 7510 | Also, for machines like the VAX that don't have logical shift insns, |
ccfa01f5 | 7511 | try to convert logical to arithmetic shift operations in cases where |
7512 | they are equivalent. This undoes the canonicalizations to logical | |
7513 | shifts done elsewhere. | |
7514 | ||
7515 | We try, as much as possible, to re-use rtl expressions to save memory. | |
7516 | ||
7517 | IN_CODE says what kind of expression we are processing. Normally, it is | |
c3a052b1 | 7518 | SET. In a memory address (inside a MEM, PLUS or minus, the latter two |
7519 | being kludges), it is MEM. When processing the arguments of a comparison | |
ccfa01f5 | 7520 | or a COMPARE against zero, it is COMPARE. */ |
7521 | ||
e6637753 | 7522 | rtx |
d598ad0d | 7523 | make_compound_operation (rtx x, enum rtx_code in_code) |
ccfa01f5 | 7524 | { |
7525 | enum rtx_code code = GET_CODE (x); | |
7526 | enum machine_mode mode = GET_MODE (x); | |
ded805e6 | 7527 | int mode_width = GET_MODE_PRECISION (mode); |
8c7ee42a | 7528 | rtx rhs, lhs; |
ccfa01f5 | 7529 | enum rtx_code next_code; |
d34f4b40 | 7530 | int i, j; |
d328ebdf | 7531 | rtx new_rtx = 0; |
2929d68d | 7532 | rtx tem; |
d2ca078f | 7533 | const char *fmt; |
ccfa01f5 | 7534 | |
7535 | /* Select the code to be used in recursive calls. Once we are inside an | |
7536 | address, we stay there. If we have a comparison, set to COMPARE, | |
7537 | but once inside, go back to our default of SET. */ | |
7538 | ||
3fc0a3f1 | 7539 | next_code = (code == MEM ? MEM |
7540 | : ((code == PLUS || code == MINUS) | |
7541 | && SCALAR_INT_MODE_P (mode)) ? MEM | |
6720e96c | 7542 | : ((code == COMPARE || COMPARISON_P (x)) |
ccfa01f5 | 7543 | && XEXP (x, 1) == const0_rtx) ? COMPARE |
7544 | : in_code == COMPARE ? SET : in_code); | |
7545 | ||
7546 | /* Process depending on the code of this operation. If NEW is set | |
d10cfa8d | 7547 | nonzero, it will be returned. */ |
ccfa01f5 | 7548 | |
7549 | switch (code) | |
7550 | { | |
7551 | case ASHIFT: | |
ccfa01f5 | 7552 | /* Convert shifts by constants into multiplications if inside |
7553 | an address. */ | |
971ba038 | 7554 | if (in_code == MEM && CONST_INT_P (XEXP (x, 1)) |
1bb04728 | 7555 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
952f9aab | 7556 | && INTVAL (XEXP (x, 1)) >= 0 |
7557 | && SCALAR_INT_MODE_P (mode)) | |
2929d68d | 7558 | { |
422101e8 | 7559 | HOST_WIDE_INT count = INTVAL (XEXP (x, 1)); |
7560 | HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count; | |
7561 | ||
d328ebdf | 7562 | new_rtx = make_compound_operation (XEXP (x, 0), next_code); |
422101e8 | 7563 | if (GET_CODE (new_rtx) == NEG) |
7564 | { | |
7565 | new_rtx = XEXP (new_rtx, 0); | |
7566 | multval = -multval; | |
7567 | } | |
7568 | multval = trunc_int_for_mode (multval, mode); | |
c338f2e3 | 7569 | new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode)); |
2929d68d | 7570 | } |
ccfa01f5 | 7571 | break; |
7572 | ||
422101e8 | 7573 | case PLUS: |
7574 | lhs = XEXP (x, 0); | |
7575 | rhs = XEXP (x, 1); | |
3fc0a3f1 | 7576 | lhs = make_compound_operation (lhs, next_code); |
7577 | rhs = make_compound_operation (rhs, next_code); | |
422101e8 | 7578 | if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG |
7579 | && SCALAR_INT_MODE_P (mode)) | |
7580 | { | |
7581 | tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0), | |
7582 | XEXP (lhs, 1)); | |
7583 | new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem); | |
7584 | } | |
7585 | else if (GET_CODE (lhs) == MULT | |
7586 | && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0)) | |
7587 | { | |
7588 | tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0), | |
7589 | simplify_gen_unary (NEG, mode, | |
7590 | XEXP (lhs, 1), | |
7591 | mode)); | |
7592 | new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem); | |
7593 | } | |
7594 | else | |
7595 | { | |
7596 | SUBST (XEXP (x, 0), lhs); | |
7597 | SUBST (XEXP (x, 1), rhs); | |
7598 | goto maybe_swap; | |
7599 | } | |
7600 | x = gen_lowpart (mode, new_rtx); | |
7601 | goto maybe_swap; | |
7602 | ||
7603 | case MINUS: | |
7604 | lhs = XEXP (x, 0); | |
7605 | rhs = XEXP (x, 1); | |
3fc0a3f1 | 7606 | lhs = make_compound_operation (lhs, next_code); |
7607 | rhs = make_compound_operation (rhs, next_code); | |
422101e8 | 7608 | if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG |
7609 | && SCALAR_INT_MODE_P (mode)) | |
7610 | { | |
7611 | tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0), | |
7612 | XEXP (rhs, 1)); | |
7613 | new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs); | |
7614 | } | |
7615 | else if (GET_CODE (rhs) == MULT | |
7616 | && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0)) | |
7617 | { | |
7618 | tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0), | |
7619 | simplify_gen_unary (NEG, mode, | |
7620 | XEXP (rhs, 1), | |
7621 | mode)); | |
7622 | new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs); | |
7623 | } | |
7624 | else | |
7625 | { | |
7626 | SUBST (XEXP (x, 0), lhs); | |
7627 | SUBST (XEXP (x, 1), rhs); | |
7628 | return x; | |
7629 | } | |
7630 | return gen_lowpart (mode, new_rtx); | |
7631 | ||
ccfa01f5 | 7632 | case AND: |
7633 | /* If the second operand is not a constant, we can't do anything | |
7634 | with it. */ | |
971ba038 | 7635 | if (!CONST_INT_P (XEXP (x, 1))) |
ccfa01f5 | 7636 | break; |
7637 | ||
7638 | /* If the constant is a power of two minus one and the first operand | |
7639 | is a logical right shift, make an extraction. */ | |
7640 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
897c6c81 | 7641 | && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) |
2929d68d | 7642 | { |
d328ebdf | 7643 | new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); |
7644 | new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1, | |
2929d68d | 7645 | 0, in_code == COMPARE); |
7646 | } | |
9efc0f8e | 7647 | |
ccfa01f5 | 7648 | /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ |
7649 | else if (GET_CODE (XEXP (x, 0)) == SUBREG | |
7650 | && subreg_lowpart_p (XEXP (x, 0)) | |
7651 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT | |
897c6c81 | 7652 | && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) |
2929d68d | 7653 | { |
d328ebdf | 7654 | new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), |
2929d68d | 7655 | next_code); |
d328ebdf | 7656 | new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0, |
2929d68d | 7657 | XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, |
7658 | 0, in_code == COMPARE); | |
7659 | } | |
6503f782 | 7660 | /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ |
febf430c | 7661 | else if ((GET_CODE (XEXP (x, 0)) == XOR |
7662 | || GET_CODE (XEXP (x, 0)) == IOR) | |
7663 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT | |
7664 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT | |
897c6c81 | 7665 | && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) |
febf430c | 7666 | { |
7667 | /* Apply the distributive law, and then try to make extractions. */ | |
d328ebdf | 7668 | new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, |
3380b197 | 7669 | gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), |
7670 | XEXP (x, 1)), | |
7671 | gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), | |
7672 | XEXP (x, 1))); | |
d328ebdf | 7673 | new_rtx = make_compound_operation (new_rtx, in_code); |
febf430c | 7674 | } |
d976ad75 | 7675 | |
7676 | /* If we are have (and (rotate X C) M) and C is larger than the number | |
7677 | of bits in M, this is an extraction. */ | |
7678 | ||
7679 | else if (GET_CODE (XEXP (x, 0)) == ROTATE | |
971ba038 | 7680 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) |
897c6c81 | 7681 | && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0 |
d976ad75 | 7682 | && i <= INTVAL (XEXP (XEXP (x, 0), 1))) |
2929d68d | 7683 | { |
d328ebdf | 7684 | new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); |
7685 | new_rtx = make_extraction (mode, new_rtx, | |
ded805e6 | 7686 | (GET_MODE_PRECISION (mode) |
2929d68d | 7687 | - INTVAL (XEXP (XEXP (x, 0), 1))), |
7688 | NULL_RTX, i, 1, 0, in_code == COMPARE); | |
7689 | } | |
d976ad75 | 7690 | |
7691 | /* On machines without logical shifts, if the operand of the AND is | |
ccfa01f5 | 7692 | a logical shift and our mask turns off all the propagated sign |
7693 | bits, we can replace the logical shift with an arithmetic shift. */ | |
ad99e708 | 7694 | else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT |
7695 | && !have_insn_for (LSHIFTRT, mode) | |
7696 | && have_insn_for (ASHIFTRT, mode) | |
971ba038 | 7697 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) |
ccfa01f5 | 7698 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 |
1bb04728 | 7699 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT |
7700 | && mode_width <= HOST_BITS_PER_WIDE_INT) | |
ccfa01f5 | 7701 | { |
1bb04728 | 7702 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
ccfa01f5 | 7703 | |
7704 | mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); | |
7705 | if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) | |
7706 | SUBST (XEXP (x, 0), | |
3380b197 | 7707 | gen_rtx_ASHIFTRT (mode, |
7708 | make_compound_operation | |
7709 | (XEXP (XEXP (x, 0), 0), next_code), | |
7710 | XEXP (XEXP (x, 0), 1))); | |
ccfa01f5 | 7711 | } |
7712 | ||
7713 | /* If the constant is one less than a power of two, this might be | |
7714 | representable by an extraction even if no shift is present. | |
7715 | If it doesn't end up being a ZERO_EXTEND, we will ignore it unless | |
7716 | we are in a COMPARE. */ | |
897c6c81 | 7717 | else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) |
d328ebdf | 7718 | new_rtx = make_extraction (mode, |
2929d68d | 7719 | make_compound_operation (XEXP (x, 0), |
7720 | next_code), | |
7721 | 0, NULL_RTX, i, 1, 0, in_code == COMPARE); | |
ccfa01f5 | 7722 | |
7723 | /* If we are in a comparison and this is an AND with a power of two, | |
7724 | convert this into the appropriate bit extract. */ | |
7725 | else if (in_code == COMPARE | |
897c6c81 | 7726 | && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0) |
d328ebdf | 7727 | new_rtx = make_extraction (mode, |
2929d68d | 7728 | make_compound_operation (XEXP (x, 0), |
7729 | next_code), | |
7730 | i, NULL_RTX, 1, 1, 0, 1); | |
ccfa01f5 | 7731 | |
7732 | break; | |
7733 | ||
7734 | case LSHIFTRT: | |
7735 | /* If the sign bit is known to be zero, replace this with an | |
7736 | arithmetic shift. */ | |
ad99e708 | 7737 | if (have_insn_for (ASHIFTRT, mode) |
7738 | && ! have_insn_for (LSHIFTRT, mode) | |
1bb04728 | 7739 | && mode_width <= HOST_BITS_PER_WIDE_INT |
3d882a35 | 7740 | && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) |
ccfa01f5 | 7741 | { |
d328ebdf | 7742 | new_rtx = gen_rtx_ASHIFTRT (mode, |
3380b197 | 7743 | make_compound_operation (XEXP (x, 0), |
7744 | next_code), | |
7745 | XEXP (x, 1)); | |
ccfa01f5 | 7746 | break; |
7747 | } | |
7748 | ||
a92771b8 | 7749 | /* ... fall through ... */ |
ccfa01f5 | 7750 | |
7751 | case ASHIFTRT: | |
8c7ee42a | 7752 | lhs = XEXP (x, 0); |
7753 | rhs = XEXP (x, 1); | |
7754 | ||
ccfa01f5 | 7755 | /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, |
7756 | this is a SIGN_EXTRACT. */ | |
971ba038 | 7757 | if (CONST_INT_P (rhs) |
8c7ee42a | 7758 | && GET_CODE (lhs) == ASHIFT |
971ba038 | 7759 | && CONST_INT_P (XEXP (lhs, 1)) |
ff2f572b | 7760 | && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)) |
690dd636 | 7761 | && INTVAL (XEXP (lhs, 1)) >= 0 |
ff2f572b | 7762 | && INTVAL (rhs) < mode_width) |
2929d68d | 7763 | { |
d328ebdf | 7764 | new_rtx = make_compound_operation (XEXP (lhs, 0), next_code); |
7765 | new_rtx = make_extraction (mode, new_rtx, | |
8c7ee42a | 7766 | INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), |
7767 | NULL_RTX, mode_width - INTVAL (rhs), | |
ec90760f | 7768 | code == LSHIFTRT, 0, in_code == COMPARE); |
ad967a2b | 7769 | break; |
ec90760f | 7770 | } |
7771 | ||
8c7ee42a | 7772 | /* See if we have operations between an ASHIFTRT and an ASHIFT. |
7773 | If so, try to merge the shifts into a SIGN_EXTEND. We could | |
7774 | also do this for some cases of SIGN_EXTRACT, but it doesn't | |
7775 | seem worth the effort; the case checked for occurs on Alpha. */ | |
510f7125 | 7776 | |
6720e96c | 7777 | if (!OBJECT_P (lhs) |
8c7ee42a | 7778 | && ! (GET_CODE (lhs) == SUBREG |
6720e96c | 7779 | && (OBJECT_P (SUBREG_REG (lhs)))) |
971ba038 | 7780 | && CONST_INT_P (rhs) |
8c7ee42a | 7781 | && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT |
ff2f572b | 7782 | && INTVAL (rhs) < mode_width |
d328ebdf | 7783 | && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0) |
7784 | new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code), | |
8c7ee42a | 7785 | 0, NULL_RTX, mode_width - INTVAL (rhs), |
7786 | code == LSHIFTRT, 0, in_code == COMPARE); | |
510f7125 | 7787 | |
ccfa01f5 | 7788 | break; |
2929d68d | 7789 | |
7790 | case SUBREG: | |
7791 | /* Call ourselves recursively on the inner expression. If we are | |
7792 | narrowing the object and it has a different RTL code from | |
7793 | what it originally did, do this SUBREG as a force_to_mode. */ | |
f72b241d | 7794 | { |
b4b21cd0 | 7795 | rtx inner = SUBREG_REG (x), simplified; |
cea05f44 | 7796 | enum rtx_code subreg_code = in_code; |
7797 | ||
7798 | /* If in_code is COMPARE, it isn't always safe to pass it through | |
7799 | to the recursive make_compound_operation call. */ | |
7800 | if (subreg_code == COMPARE | |
7801 | && (!subreg_lowpart_p (x) | |
7802 | || GET_CODE (inner) == SUBREG | |
7803 | /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0) | |
7804 | is (const_int 0), rather than | |
7805 | (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */ | |
7806 | || (GET_CODE (inner) == AND | |
7807 | && CONST_INT_P (XEXP (inner, 1)) | |
7808 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner)) | |
7809 | && exact_log2 (UINTVAL (XEXP (inner, 1))) | |
7810 | >= GET_MODE_BITSIZE (mode)))) | |
7811 | subreg_code = SET; | |
7812 | ||
7813 | tem = make_compound_operation (inner, subreg_code); | |
d58ffe10 | 7814 | |
b4b21cd0 | 7815 | simplified |
7816 | = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x)); | |
f72b241d | 7817 | if (simplified) |
7818 | tem = simplified; | |
0d79d92d | 7819 | |
b4b21cd0 | 7820 | if (GET_CODE (tem) != GET_CODE (inner) |
7821 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner)) | |
f72b241d | 7822 | && subreg_lowpart_p (x)) |
7823 | { | |
897c6c81 | 7824 | rtx newer |
7825 | = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0); | |
a0c938f0 | 7826 | |
f72b241d | 7827 | /* If we have something other than a SUBREG, we might have |
7828 | done an expansion, so rerun ourselves. */ | |
7829 | if (GET_CODE (newer) != SUBREG) | |
7830 | newer = make_compound_operation (newer, in_code); | |
a0c938f0 | 7831 | |
dce31f46 | 7832 | /* force_to_mode can expand compounds. If it just re-expanded the |
b4b21cd0 | 7833 | compound, use gen_lowpart to convert to the desired mode. */ |
7834 | if (rtx_equal_p (newer, x) | |
7835 | /* Likewise if it re-expanded the compound only partially. | |
7836 | This happens for SUBREG of ZERO_EXTRACT if they extract | |
7837 | the same number of bits. */ | |
7838 | || (GET_CODE (newer) == SUBREG | |
7839 | && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT | |
7840 | || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT) | |
7841 | && GET_CODE (inner) == AND | |
7842 | && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0)))) | |
dce31f46 | 7843 | return gen_lowpart (GET_MODE (x), tem); |
7844 | ||
f72b241d | 7845 | return newer; |
7846 | } | |
7847 | ||
7848 | if (simplified) | |
0d79d92d | 7849 | return tem; |
f72b241d | 7850 | } |
0dbd1c74 | 7851 | break; |
510f7125 | 7852 | |
0dbd1c74 | 7853 | default: |
7854 | break; | |
ccfa01f5 | 7855 | } |
7856 | ||
d328ebdf | 7857 | if (new_rtx) |
ccfa01f5 | 7858 | { |
d328ebdf | 7859 | x = gen_lowpart (mode, new_rtx); |
ccfa01f5 | 7860 | code = GET_CODE (x); |
7861 | } | |
7862 | ||
17748811 | 7863 | /* Now recursively process each operand of this operation. We need to |
7864 | handle ZERO_EXTEND specially so that we don't lose track of the | |
7865 | inner mode. */ | |
7866 | if (GET_CODE (x) == ZERO_EXTEND) | |
7867 | { | |
7868 | new_rtx = make_compound_operation (XEXP (x, 0), next_code); | |
7869 | tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
7870 | new_rtx, GET_MODE (XEXP (x, 0))); | |
7871 | if (tem) | |
7872 | return tem; | |
7873 | SUBST (XEXP (x, 0), new_rtx); | |
7874 | return x; | |
7875 | } | |
7876 | ||
ccfa01f5 | 7877 | fmt = GET_RTX_FORMAT (code); |
7878 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
7879 | if (fmt[i] == 'e') | |
7880 | { | |
d328ebdf | 7881 | new_rtx = make_compound_operation (XEXP (x, i), next_code); |
7882 | SUBST (XEXP (x, i), new_rtx); | |
ccfa01f5 | 7883 | } |
d34f4b40 | 7884 | else if (fmt[i] == 'E') |
7885 | for (j = 0; j < XVECLEN (x, i); j++) | |
7886 | { | |
7887 | new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code); | |
7888 | SUBST (XVECEXP (x, i, j), new_rtx); | |
7889 | } | |
ccfa01f5 | 7890 | |
422101e8 | 7891 | maybe_swap: |
3f43639e | 7892 | /* If this is a commutative operation, the changes to the operands |
7893 | may have made it noncanonical. */ | |
7894 | if (COMMUTATIVE_ARITH_P (x) | |
7895 | && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) | |
7896 | { | |
7897 | tem = XEXP (x, 0); | |
7898 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
7899 | SUBST (XEXP (x, 1), tem); | |
7900 | } | |
7901 | ||
ccfa01f5 | 7902 | return x; |
7903 | } | |
7904 | \f | |
7905 | /* Given M see if it is a value that would select a field of bits | |
510f7125 | 7906 | within an item, but not the entire word. Return -1 if not. |
7907 | Otherwise, return the starting position of the field, where 0 is the | |
7908 | low-order bit. | |
ccfa01f5 | 7909 | |
7910 | *PLEN is set to the length of the field. */ | |
7911 | ||
7912 | static int | |
d598ad0d | 7913 | get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen) |
ccfa01f5 | 7914 | { |
7915 | /* Get the bit number of the first 1 bit from the right, -1 if none. */ | |
7e8d812e | 7916 | int pos = m ? ctz_hwi (m) : -1; |
4ee9c684 | 7917 | int len = 0; |
ccfa01f5 | 7918 | |
4ee9c684 | 7919 | if (pos >= 0) |
7920 | /* Now shift off the low-order zero bits and see if we have a | |
7921 | power of two minus 1. */ | |
7922 | len = exact_log2 ((m >> pos) + 1); | |
ccfa01f5 | 7923 | |
40e46041 | 7924 | if (len <= 0) |
4ee9c684 | 7925 | pos = -1; |
ccfa01f5 | 7926 | |
40e46041 | 7927 | *plen = len; |
ccfa01f5 | 7928 | return pos; |
7929 | } | |
7930 | \f | |
b92e2e43 | 7931 | /* If X refers to a register that equals REG in value, replace these |
7932 | references with REG. */ | |
7933 | static rtx | |
7934 | canon_reg_for_combine (rtx x, rtx reg) | |
7935 | { | |
7936 | rtx op0, op1, op2; | |
7937 | const char *fmt; | |
7938 | int i; | |
7939 | bool copied; | |
7940 | ||
7941 | enum rtx_code code = GET_CODE (x); | |
7942 | switch (GET_RTX_CLASS (code)) | |
7943 | { | |
7944 | case RTX_UNARY: | |
7945 | op0 = canon_reg_for_combine (XEXP (x, 0), reg); | |
7946 | if (op0 != XEXP (x, 0)) | |
7947 | return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0, | |
7948 | GET_MODE (reg)); | |
7949 | break; | |
7950 | ||
7951 | case RTX_BIN_ARITH: | |
7952 | case RTX_COMM_ARITH: | |
7953 | op0 = canon_reg_for_combine (XEXP (x, 0), reg); | |
7954 | op1 = canon_reg_for_combine (XEXP (x, 1), reg); | |
7955 | if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
7956 | return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); | |
7957 | break; | |
7958 | ||
7959 | case RTX_COMPARE: | |
7960 | case RTX_COMM_COMPARE: | |
7961 | op0 = canon_reg_for_combine (XEXP (x, 0), reg); | |
7962 | op1 = canon_reg_for_combine (XEXP (x, 1), reg); | |
7963 | if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
7964 | return simplify_gen_relational (GET_CODE (x), GET_MODE (x), | |
7965 | GET_MODE (op0), op0, op1); | |
7966 | break; | |
7967 | ||
7968 | case RTX_TERNARY: | |
7969 | case RTX_BITFIELD_OPS: | |
7970 | op0 = canon_reg_for_combine (XEXP (x, 0), reg); | |
7971 | op1 = canon_reg_for_combine (XEXP (x, 1), reg); | |
7972 | op2 = canon_reg_for_combine (XEXP (x, 2), reg); | |
7973 | if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2)) | |
7974 | return simplify_gen_ternary (GET_CODE (x), GET_MODE (x), | |
7975 | GET_MODE (op0), op0, op1, op2); | |
7976 | ||
7977 | case RTX_OBJ: | |
7978 | if (REG_P (x)) | |
7979 | { | |
7980 | if (rtx_equal_p (get_last_value (reg), x) | |
7981 | || rtx_equal_p (reg, get_last_value (x))) | |
7982 | return reg; | |
7983 | else | |
7984 | break; | |
7985 | } | |
7986 | ||
7987 | /* fall through */ | |
7988 | ||
7989 | default: | |
7990 | fmt = GET_RTX_FORMAT (code); | |
7991 | copied = false; | |
7992 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
a0c938f0 | 7993 | if (fmt[i] == 'e') |
7994 | { | |
7995 | rtx op = canon_reg_for_combine (XEXP (x, i), reg); | |
b92e2e43 | 7996 | if (op != XEXP (x, i)) |
7997 | { | |
7998 | if (!copied) | |
7999 | { | |
8000 | copied = true; | |
8001 | x = copy_rtx (x); | |
8002 | } | |
8003 | XEXP (x, i) = op; | |
a0c938f0 | 8004 | } |
8005 | } | |
8006 | else if (fmt[i] == 'E') | |
8007 | { | |
8008 | int j; | |
8009 | for (j = 0; j < XVECLEN (x, i); j++) | |
b92e2e43 | 8010 | { |
a0c938f0 | 8011 | rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg); |
8012 | if (op != XVECEXP (x, i, j)) | |
b92e2e43 | 8013 | { |
8014 | if (!copied) | |
8015 | { | |
8016 | copied = true; | |
8017 | x = copy_rtx (x); | |
8018 | } | |
8019 | XVECEXP (x, i, j) = op; | |
a0c938f0 | 8020 | } |
b92e2e43 | 8021 | } |
8022 | } | |
8023 | ||
8024 | break; | |
8025 | } | |
8026 | ||
8027 | return x; | |
8028 | } | |
8029 | ||
4c199243 | 8030 | /* Return X converted to MODE. If the value is already truncated to |
8031 | MODE we can just return a subreg even though in the general case we | |
8032 | would need an explicit truncation. */ | |
8033 | ||
8034 | static rtx | |
8035 | gen_lowpart_or_truncate (enum machine_mode mode, rtx x) | |
8036 | { | |
ef9384f3 | 8037 | if (!CONST_INT_P (x) |
8038 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)) | |
396f2130 | 8039 | && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x)) |
ef9384f3 | 8040 | && !(REG_P (x) && reg_truncated_to_mode (mode, x))) |
8041 | { | |
8042 | /* Bit-cast X into an integer mode. */ | |
8043 | if (!SCALAR_INT_MODE_P (GET_MODE (x))) | |
8044 | x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x); | |
8045 | x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode), | |
8046 | x, GET_MODE (x)); | |
8047 | } | |
8048 | ||
8049 | return gen_lowpart (mode, x); | |
4c199243 | 8050 | } |
8051 | ||
390fc1d2 | 8052 | /* See if X can be simplified knowing that we will only refer to it in |
8053 | MODE and will only refer to those bits that are nonzero in MASK. | |
8054 | If other bits are being computed or if masking operations are done | |
8055 | that select a superset of the bits in MASK, they can sometimes be | |
8056 | ignored. | |
8057 | ||
8058 | Return a possibly simplified expression, but always convert X to | |
8059 | MODE. If X is a CONST_INT, AND the CONST_INT with MASK. | |
9efc0f8e | 8060 | |
ffb2de56 | 8061 | If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK |
8062 | are all off in X. This is used when X will be complemented, by either | |
8a4e096c | 8063 | NOT, NEG, or XOR. */ |
9efc0f8e | 8064 | |
8065 | static rtx | |
d598ad0d | 8066 | force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask, |
b92e2e43 | 8067 | int just_select) |
9efc0f8e | 8068 | { |
8069 | enum rtx_code code = GET_CODE (x); | |
8a4e096c | 8070 | int next_select = just_select || code == XOR || code == NOT || code == NEG; |
e647dd3a | 8071 | enum machine_mode op_mode; |
8072 | unsigned HOST_WIDE_INT fuller_mask, nonzero; | |
390fc1d2 | 8073 | rtx op0, op1, temp; |
8074 | ||
831aa830 | 8075 | /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the |
8076 | code below will do the wrong thing since the mode of such an | |
510f7125 | 8077 | expression is VOIDmode. |
43a36bab | 8078 | |
8079 | Also do nothing if X is a CLOBBER; this can happen if X was | |
316f48ea | 8080 | the return value from a call to gen_lowpart. */ |
43a36bab | 8081 | if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) |
c5c878e8 | 8082 | return x; |
8083 | ||
aaaaacd4 | 8084 | /* We want to perform the operation in its present mode unless we know |
390fc1d2 | 8085 | that the operation is valid in MODE, in which case we do the operation |
8086 | in MODE. */ | |
a59e2317 | 8087 | op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) |
ad99e708 | 8088 | && have_insn_for (code, mode)) |
e647dd3a | 8089 | ? mode : GET_MODE (x)); |
ffb2de56 | 8090 | |
5a0824bc | 8091 | /* It is not valid to do a right-shift in a narrower mode |
8092 | than the one it came in with. */ | |
8093 | if ((code == LSHIFTRT || code == ASHIFTRT) | |
ded805e6 | 8094 | && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x))) |
5a0824bc | 8095 | op_mode = GET_MODE (x); |
e647dd3a | 8096 | |
8097 | /* Truncate MASK to fit OP_MODE. */ | |
8098 | if (op_mode) | |
8099 | mask &= GET_MODE_MASK (op_mode); | |
390fc1d2 | 8100 | |
8101 | /* When we have an arithmetic operation, or a shift whose count we | |
bfac37b2 | 8102 | do not know, we need to assume that all bits up to the highest-order |
390fc1d2 | 8103 | bit in MASK will be needed. This is how we form such a mask. */ |
bfac37b2 | 8104 | if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) |
8105 | fuller_mask = ~(unsigned HOST_WIDE_INT) 0; | |
e647dd3a | 8106 | else |
bfac37b2 | 8107 | fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) |
8108 | - 1); | |
e647dd3a | 8109 | |
8110 | /* Determine what bits of X are guaranteed to be (non)zero. */ | |
8111 | nonzero = nonzero_bits (x, mode); | |
390fc1d2 | 8112 | |
8113 | /* If none of the bits in X are needed, return a zero. */ | |
7bb0bd01 | 8114 | if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x)) |
62f6cb56 | 8115 | x = const0_rtx; |
9efc0f8e | 8116 | |
390fc1d2 | 8117 | /* If X is a CONST_INT, return a new one. Do this here since the |
8118 | test below will fail. */ | |
971ba038 | 8119 | if (CONST_INT_P (x)) |
62f6cb56 | 8120 | { |
8121 | if (SCALAR_INT_MODE_P (mode)) | |
a0c938f0 | 8122 | return gen_int_mode (INTVAL (x) & mask, mode); |
62f6cb56 | 8123 | else |
8124 | { | |
8125 | x = GEN_INT (INTVAL (x) & mask); | |
8126 | return gen_lowpart_common (mode, x); | |
8127 | } | |
8128 | } | |
9efc0f8e | 8129 | |
8a4e096c | 8130 | /* If X is narrower than MODE and we want all the bits in X's mode, just |
8131 | get X in the proper mode. */ | |
8132 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) | |
510f7125 | 8133 | && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) |
316f48ea | 8134 | return gen_lowpart (mode, x); |
9efc0f8e | 8135 | |
ef9384f3 | 8136 | /* We can ignore the effect of a SUBREG if it narrows the mode or |
8137 | if the constant masks to zero all the bits the mode doesn't have. */ | |
8138 | if (GET_CODE (x) == SUBREG | |
8139 | && subreg_lowpart_p (x) | |
8140 | && ((GET_MODE_SIZE (GET_MODE (x)) | |
8141 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
8142 | || (0 == (mask | |
8143 | & GET_MODE_MASK (GET_MODE (x)) | |
8144 | & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) | |
8145 | return force_to_mode (SUBREG_REG (x), mode, mask, next_select); | |
8146 | ||
8147 | /* The arithmetic simplifications here only work for scalar integer modes. */ | |
8148 | if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x))) | |
8149 | return gen_lowpart_or_truncate (mode, x); | |
6d5136ab | 8150 | |
9efc0f8e | 8151 | switch (code) |
8152 | { | |
390fc1d2 | 8153 | case CLOBBER: |
8154 | /* If X is a (clobber (const_int)), return it since we know we are | |
a92771b8 | 8155 | generating something that won't match. */ |
390fc1d2 | 8156 | return x; |
8157 | ||
9efc0f8e | 8158 | case SIGN_EXTEND: |
8159 | case ZERO_EXTEND: | |
8160 | case ZERO_EXTRACT: | |
8161 | case SIGN_EXTRACT: | |
8162 | x = expand_compound_operation (x); | |
8163 | if (GET_CODE (x) != code) | |
b92e2e43 | 8164 | return force_to_mode (x, mode, mask, next_select); |
9efc0f8e | 8165 | break; |
8166 | ||
3f03d2db | 8167 | case TRUNCATE: |
8168 | /* Similarly for a truncate. */ | |
8169 | return force_to_mode (XEXP (x, 0), mode, mask, next_select); | |
8170 | ||
9efc0f8e | 8171 | case AND: |
390fc1d2 | 8172 | /* If this is an AND with a constant, convert it into an AND |
8173 | whose constant is the AND of that constant with MASK. If it | |
8174 | remains an AND of MASK, delete it since it is redundant. */ | |
9efc0f8e | 8175 | |
971ba038 | 8176 | if (CONST_INT_P (XEXP (x, 1))) |
9efc0f8e | 8177 | { |
390fc1d2 | 8178 | x = simplify_and_const_int (x, op_mode, XEXP (x, 0), |
8179 | mask & INTVAL (XEXP (x, 1))); | |
9efc0f8e | 8180 | |
8181 | /* If X is still an AND, see if it is an AND with a mask that | |
8c7ee42a | 8182 | is just some low-order bits. If so, and it is MASK, we don't |
8183 | need it. */ | |
9efc0f8e | 8184 | |
971ba038 | 8185 | if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1)) |
ec00a5f6 | 8186 | && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) |
c1131678 | 8187 | == mask)) |
9efc0f8e | 8188 | x = XEXP (x, 0); |
ec90760f | 8189 | |
8c7ee42a | 8190 | /* If it remains an AND, try making another AND with the bits |
8191 | in the mode mask that aren't in MASK turned on. If the | |
8192 | constant in the AND is wide enough, this might make a | |
8193 | cheaper constant. */ | |
8194 | ||
971ba038 | 8195 | if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1)) |
d5229fd0 | 8196 | && GET_MODE_MASK (GET_MODE (x)) != mask |
f179ee60 | 8197 | && HWI_COMPUTABLE_MODE_P (GET_MODE (x))) |
8c7ee42a | 8198 | { |
897c6c81 | 8199 | unsigned HOST_WIDE_INT cval |
8200 | = UINTVAL (XEXP (x, 1)) | |
8201 | | (GET_MODE_MASK (GET_MODE (x)) & ~mask); | |
8c7ee42a | 8202 | rtx y; |
8203 | ||
5d5ee71f | 8204 | y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0), |
8205 | gen_int_mode (cval, GET_MODE (x))); | |
7013e87c | 8206 | if (set_src_cost (y, optimize_this_for_speed_p) |
8207 | < set_src_cost (x, optimize_this_for_speed_p)) | |
8c7ee42a | 8208 | x = y; |
8209 | } | |
8210 | ||
ec90760f | 8211 | break; |
9efc0f8e | 8212 | } |
8213 | ||
390fc1d2 | 8214 | goto binop; |
9efc0f8e | 8215 | |
8216 | case PLUS: | |
390fc1d2 | 8217 | /* In (and (plus FOO C1) M), if M is a mask that just turns off |
8218 | low-order bits (as in an alignment operation) and FOO is already | |
8219 | aligned to that boundary, mask C1 to that boundary as well. | |
8220 | This may eliminate that PLUS and, later, the AND. */ | |
e1b1d556 | 8221 | |
8222 | { | |
ded805e6 | 8223 | unsigned int width = GET_MODE_PRECISION (mode); |
e1b1d556 | 8224 | unsigned HOST_WIDE_INT smask = mask; |
8225 | ||
8226 | /* If MODE is narrower than HOST_WIDE_INT and mask is a negative | |
8227 | number, sign extend it. */ | |
8228 | ||
8229 | if (width < HOST_BITS_PER_WIDE_INT | |
561f0ec8 | 8230 | && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0) |
8231 | smask |= HOST_WIDE_INT_M1U << width; | |
e1b1d556 | 8232 | |
971ba038 | 8233 | if (CONST_INT_P (XEXP (x, 1)) |
04a917bf | 8234 | && exact_log2 (- smask) >= 0 |
8235 | && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 | |
8236 | && (INTVAL (XEXP (x, 1)) & ~smask) != 0) | |
29c05e22 | 8237 | return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0), |
04a917bf | 8238 | (INTVAL (XEXP (x, 1)) & smask)), |
b92e2e43 | 8239 | mode, smask, next_select); |
e1b1d556 | 8240 | } |
390fc1d2 | 8241 | |
a92771b8 | 8242 | /* ... fall through ... */ |
390fc1d2 | 8243 | |
9efc0f8e | 8244 | case MULT: |
390fc1d2 | 8245 | /* For PLUS, MINUS and MULT, we need any bits less significant than the |
8246 | most significant bit in MASK since carries from those bits will | |
8247 | affect the bits we are interested in. */ | |
8248 | mask = fuller_mask; | |
8249 | goto binop; | |
8250 | ||
732fc2b4 | 8251 | case MINUS: |
8252 | /* If X is (minus C Y) where C's least set bit is larger than any bit | |
8253 | in the mask, then we may replace with (neg Y). */ | |
971ba038 | 8254 | if (CONST_INT_P (XEXP (x, 0)) |
60141df0 | 8255 | && ((UINTVAL (XEXP (x, 0)) & -UINTVAL (XEXP (x, 0))) > mask)) |
732fc2b4 | 8256 | { |
3380b197 | 8257 | x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), |
8258 | GET_MODE (x)); | |
b92e2e43 | 8259 | return force_to_mode (x, mode, mask, next_select); |
732fc2b4 | 8260 | } |
8261 | ||
4c286961 | 8262 | /* Similarly, if C contains every bit in the fuller_mask, then we may |
732fc2b4 | 8263 | replace with (not Y). */ |
971ba038 | 8264 | if (CONST_INT_P (XEXP (x, 0)) |
897c6c81 | 8265 | && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0)))) |
732fc2b4 | 8266 | { |
3380b197 | 8267 | x = simplify_gen_unary (NOT, GET_MODE (x), |
8268 | XEXP (x, 1), GET_MODE (x)); | |
b92e2e43 | 8269 | return force_to_mode (x, mode, mask, next_select); |
732fc2b4 | 8270 | } |
8271 | ||
8272 | mask = fuller_mask; | |
8273 | goto binop; | |
8274 | ||
9efc0f8e | 8275 | case IOR: |
8276 | case XOR: | |
390fc1d2 | 8277 | /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and |
8278 | LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) | |
8279 | operation which may be a bitfield extraction. Ensure that the | |
8280 | constant we form is not wider than the mode of X. */ | |
8281 | ||
8282 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
971ba038 | 8283 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) |
390fc1d2 | 8284 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 |
8285 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT | |
971ba038 | 8286 | && CONST_INT_P (XEXP (x, 1)) |
390fc1d2 | 8287 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) |
8288 | + floor_log2 (INTVAL (XEXP (x, 1)))) | |
ded805e6 | 8289 | < GET_MODE_PRECISION (GET_MODE (x))) |
897c6c81 | 8290 | && (UINTVAL (XEXP (x, 1)) |
510f7125 | 8291 | & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) |
390fc1d2 | 8292 | { |
5d5ee71f | 8293 | temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask) |
8294 | << INTVAL (XEXP (XEXP (x, 0), 1)), | |
8295 | GET_MODE (x)); | |
800a7def | 8296 | temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x), |
8297 | XEXP (XEXP (x, 0), 0), temp); | |
8298 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp, | |
8299 | XEXP (XEXP (x, 0), 1)); | |
b92e2e43 | 8300 | return force_to_mode (x, mode, mask, next_select); |
390fc1d2 | 8301 | } |
8302 | ||
8303 | binop: | |
9efc0f8e | 8304 | /* For most binary operations, just propagate into the operation and |
1e625a2e | 8305 | change the mode if we have an operation of that mode. */ |
390fc1d2 | 8306 | |
3f03d2db | 8307 | op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select); |
8308 | op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select); | |
8309 | ||
8310 | /* If we ended up truncating both operands, truncate the result of the | |
8311 | operation instead. */ | |
8312 | if (GET_CODE (op0) == TRUNCATE | |
8313 | && GET_CODE (op1) == TRUNCATE) | |
8314 | { | |
8315 | op0 = XEXP (op0, 0); | |
8316 | op1 = XEXP (op1, 0); | |
8317 | } | |
8318 | ||
8319 | op0 = gen_lowpart_or_truncate (op_mode, op0); | |
8320 | op1 = gen_lowpart_or_truncate (op_mode, op1); | |
390fc1d2 | 8321 | |
8322 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
800a7def | 8323 | x = simplify_gen_binary (code, op_mode, op0, op1); |
ec90760f | 8324 | break; |
9efc0f8e | 8325 | |
8326 | case ASHIFT: | |
9efc0f8e | 8327 | /* For left shifts, do the same, but just for the first operand. |
129e5354 | 8328 | However, we cannot do anything with shifts where we cannot |
8329 | guarantee that the counts are smaller than the size of the mode | |
8330 | because such a count will have a different meaning in a | |
390fc1d2 | 8331 | wider mode. */ |
129e5354 | 8332 | |
971ba038 | 8333 | if (! (CONST_INT_P (XEXP (x, 1)) |
390fc1d2 | 8334 | && INTVAL (XEXP (x, 1)) >= 0 |
ded805e6 | 8335 | && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode)) |
129e5354 | 8336 | && ! (GET_MODE (XEXP (x, 1)) != VOIDmode |
8337 | && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) | |
ded805e6 | 8338 | < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode)))) |
129e5354 | 8339 | break; |
510f7125 | 8340 | |
390fc1d2 | 8341 | /* If the shift count is a constant and we can do arithmetic in |
8342 | the mode of the shift, refine which bits we need. Otherwise, use the | |
8343 | conservative form of the mask. */ | |
971ba038 | 8344 | if (CONST_INT_P (XEXP (x, 1)) |
390fc1d2 | 8345 | && INTVAL (XEXP (x, 1)) >= 0 |
ded805e6 | 8346 | && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode) |
f179ee60 | 8347 | && HWI_COMPUTABLE_MODE_P (op_mode)) |
390fc1d2 | 8348 | mask >>= INTVAL (XEXP (x, 1)); |
8349 | else | |
8350 | mask = fuller_mask; | |
8351 | ||
4c199243 | 8352 | op0 = gen_lowpart_or_truncate (op_mode, |
8353 | force_to_mode (XEXP (x, 0), op_mode, | |
8354 | mask, next_select)); | |
390fc1d2 | 8355 | |
8356 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) | |
800a7def | 8357 | x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1)); |
ec90760f | 8358 | break; |
9efc0f8e | 8359 | |
8360 | case LSHIFTRT: | |
deb3096c | 8361 | /* Here we can only do something if the shift count is a constant, |
8362 | this shift constant is valid for the host, and we can do arithmetic | |
8363 | in OP_MODE. */ | |
9efc0f8e | 8364 | |
971ba038 | 8365 | if (CONST_INT_P (XEXP (x, 1)) |
7c4d4cbb | 8366 | && INTVAL (XEXP (x, 1)) >= 0 |
deb3096c | 8367 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
f179ee60 | 8368 | && HWI_COMPUTABLE_MODE_P (op_mode)) |
ec90760f | 8369 | { |
390fc1d2 | 8370 | rtx inner = XEXP (x, 0); |
439b8569 | 8371 | unsigned HOST_WIDE_INT inner_mask; |
390fc1d2 | 8372 | |
8373 | /* Select the mask of the bits we need for the shift operand. */ | |
439b8569 | 8374 | inner_mask = mask << INTVAL (XEXP (x, 1)); |
ec90760f | 8375 | |
390fc1d2 | 8376 | /* We can only change the mode of the shift if we can do arithmetic |
439b8569 | 8377 | in the mode of the shift and INNER_MASK is no wider than the |
17c7352a | 8378 | width of X's mode. */ |
8379 | if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0) | |
ec90760f | 8380 | op_mode = GET_MODE (x); |
8381 | ||
b92e2e43 | 8382 | inner = force_to_mode (inner, op_mode, inner_mask, next_select); |
390fc1d2 | 8383 | |
8384 | if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) | |
800a7def | 8385 | x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); |
ec90760f | 8386 | } |
390fc1d2 | 8387 | |
8388 | /* If we have (and (lshiftrt FOO C1) C2) where the combination of the | |
8389 | shift and AND produces only copies of the sign bit (C2 is one less | |
8390 | than a power of two), we can do this with just a shift. */ | |
8391 | ||
8392 | if (GET_CODE (x) == LSHIFTRT | |
971ba038 | 8393 | && CONST_INT_P (XEXP (x, 1)) |
f8d937be | 8394 | /* The shift puts one of the sign bit copies in the least significant |
8395 | bit. */ | |
390fc1d2 | 8396 | && ((INTVAL (XEXP (x, 1)) |
8397 | + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) | |
ded805e6 | 8398 | >= GET_MODE_PRECISION (GET_MODE (x))) |
390fc1d2 | 8399 | && exact_log2 (mask + 1) >= 0 |
f8d937be | 8400 | /* Number of bits left after the shift must be more than the mask |
8401 | needs. */ | |
8402 | && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) | |
ded805e6 | 8403 | <= GET_MODE_PRECISION (GET_MODE (x))) |
f8d937be | 8404 | /* Must be more sign bit copies than the mask needs. */ |
02e7a332 | 8405 | && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) |
390fc1d2 | 8406 | >= exact_log2 (mask + 1))) |
800a7def | 8407 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), |
ded805e6 | 8408 | GEN_INT (GET_MODE_PRECISION (GET_MODE (x)) |
800a7def | 8409 | - exact_log2 (mask + 1))); |
b03b2fbb | 8410 | |
8411 | goto shiftrt; | |
ec90760f | 8412 | |
8413 | case ASHIFTRT: | |
390fc1d2 | 8414 | /* If we are just looking for the sign bit, we don't need this shift at |
8415 | all, even if it has a variable count. */ | |
f92430e0 | 8416 | if (val_signbit_p (GET_MODE (x), mask)) |
b92e2e43 | 8417 | return force_to_mode (XEXP (x, 0), mode, mask, next_select); |
390fc1d2 | 8418 | |
8419 | /* If this is a shift by a constant, get a mask that contains those bits | |
8420 | that are not copies of the sign bit. We then have two cases: If | |
8421 | MASK only includes those bits, this can be a logical shift, which may | |
8422 | allow simplifications. If MASK is a single-bit field not within | |
8423 | those bits, we are requesting a copy of the sign bit and hence can | |
8424 | shift the sign bit to the appropriate location. */ | |
8425 | ||
971ba038 | 8426 | if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0 |
390fc1d2 | 8427 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) |
8428 | { | |
1282ed8f | 8429 | int i; |
390fc1d2 | 8430 | |
78eda270 | 8431 | /* If the considered data is wider than HOST_WIDE_INT, we can't |
e2ea89e5 | 8432 | represent a mask for all its bits in a single scalar. |
8433 | But we only care about the lower bits, so calculate these. */ | |
8434 | ||
ded805e6 | 8435 | if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) |
e2ea89e5 | 8436 | { |
897c6c81 | 8437 | nonzero = ~(unsigned HOST_WIDE_INT) 0; |
e2ea89e5 | 8438 | |
ded805e6 | 8439 | /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1)) |
e2ea89e5 | 8440 | is the number of bits a full-width mask would have set. |
8441 | We need only shift if these are fewer than nonzero can | |
8442 | hold. If not, we must keep all bits set in nonzero. */ | |
8443 | ||
ded805e6 | 8444 | if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1)) |
e2ea89e5 | 8445 | < HOST_BITS_PER_WIDE_INT) |
8446 | nonzero >>= INTVAL (XEXP (x, 1)) | |
8447 | + HOST_BITS_PER_WIDE_INT | |
ded805e6 | 8448 | - GET_MODE_PRECISION (GET_MODE (x)) ; |
e2ea89e5 | 8449 | } |
8450 | else | |
8451 | { | |
8452 | nonzero = GET_MODE_MASK (GET_MODE (x)); | |
8453 | nonzero >>= INTVAL (XEXP (x, 1)); | |
8454 | } | |
390fc1d2 | 8455 | |
1282ed8f | 8456 | if ((mask & ~nonzero) == 0) |
8457 | { | |
2a66066b | 8458 | x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x), |
1282ed8f | 8459 | XEXP (x, 0), INTVAL (XEXP (x, 1))); |
8460 | if (GET_CODE (x) != ASHIFTRT) | |
8461 | return force_to_mode (x, mode, mask, next_select); | |
8462 | } | |
8463 | ||
8464 | else if ((i = exact_log2 (mask)) >= 0) | |
390fc1d2 | 8465 | { |
8466 | x = simplify_shift_const | |
1282ed8f | 8467 | (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0), |
ded805e6 | 8468 | GET_MODE_PRECISION (GET_MODE (x)) - 1 - i); |
390fc1d2 | 8469 | |
8470 | if (GET_CODE (x) != ASHIFTRT) | |
b92e2e43 | 8471 | return force_to_mode (x, mode, mask, next_select); |
390fc1d2 | 8472 | } |
8473 | } | |
8474 | ||
dafdd1c8 | 8475 | /* If MASK is 1, convert this to an LSHIFTRT. This can be done |
390fc1d2 | 8476 | even if the shift count isn't a constant. */ |
8477 | if (mask == 1) | |
800a7def | 8478 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), |
8479 | XEXP (x, 0), XEXP (x, 1)); | |
390fc1d2 | 8480 | |
b03b2fbb | 8481 | shiftrt: |
8482 | ||
8483 | /* If this is a zero- or sign-extension operation that just affects bits | |
a90bc44a | 8484 | we don't care about, remove it. Be sure the call above returned |
8485 | something that is still a shift. */ | |
ec90760f | 8486 | |
a90bc44a | 8487 | if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) |
971ba038 | 8488 | && CONST_INT_P (XEXP (x, 1)) |
ec90760f | 8489 | && INTVAL (XEXP (x, 1)) >= 0 |
390fc1d2 | 8490 | && (INTVAL (XEXP (x, 1)) |
ded805e6 | 8491 | <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1)) |
ec90760f | 8492 | && GET_CODE (XEXP (x, 0)) == ASHIFT |
f9af8fcd | 8493 | && XEXP (XEXP (x, 0), 1) == XEXP (x, 1)) |
ffb2de56 | 8494 | return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, |
b92e2e43 | 8495 | next_select); |
390fc1d2 | 8496 | |
9efc0f8e | 8497 | break; |
8498 | ||
390fc1d2 | 8499 | case ROTATE: |
8500 | case ROTATERT: | |
8501 | /* If the shift count is constant and we can do computations | |
8502 | in the mode of X, compute where the bits we care about are. | |
8503 | Otherwise, we can't do anything. Don't change the mode of | |
8504 | the shift or propagate MODE into the shift, though. */ | |
971ba038 | 8505 | if (CONST_INT_P (XEXP (x, 1)) |
390fc1d2 | 8506 | && INTVAL (XEXP (x, 1)) >= 0) |
8507 | { | |
8508 | temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, | |
5d5ee71f | 8509 | GET_MODE (x), |
8510 | gen_int_mode (mask, GET_MODE (x)), | |
390fc1d2 | 8511 | XEXP (x, 1)); |
971ba038 | 8512 | if (temp && CONST_INT_P (temp)) |
aaaaacd4 | 8513 | x = simplify_gen_binary (code, GET_MODE (x), |
8514 | force_to_mode (XEXP (x, 0), GET_MODE (x), | |
8515 | INTVAL (temp), next_select), | |
8516 | XEXP (x, 1)); | |
390fc1d2 | 8517 | } |
8518 | break; | |
510f7125 | 8519 | |
9efc0f8e | 8520 | case NEG: |
8a4e096c | 8521 | /* If we just want the low-order bit, the NEG isn't needed since it |
04641143 | 8522 | won't change the low-order bit. */ |
8a4e096c | 8523 | if (mask == 1) |
b92e2e43 | 8524 | return force_to_mode (XEXP (x, 0), mode, mask, just_select); |
8a4e096c | 8525 | |
390fc1d2 | 8526 | /* We need any bits less significant than the most significant bit in |
8527 | MASK since carries from those bits will affect the bits we are | |
8528 | interested in. */ | |
8529 | mask = fuller_mask; | |
8530 | goto unop; | |
8531 | ||
9efc0f8e | 8532 | case NOT: |
390fc1d2 | 8533 | /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the |
8534 | same as the XOR case above. Ensure that the constant we form is not | |
8535 | wider than the mode of X. */ | |
8536 | ||
8537 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
971ba038 | 8538 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) |
390fc1d2 | 8539 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 |
8540 | && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) | |
ded805e6 | 8541 | < GET_MODE_PRECISION (GET_MODE (x))) |
390fc1d2 | 8542 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) |
8543 | { | |
6d7ddaae | 8544 | temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), |
8545 | GET_MODE (x)); | |
800a7def | 8546 | temp = simplify_gen_binary (XOR, GET_MODE (x), |
8547 | XEXP (XEXP (x, 0), 0), temp); | |
8548 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), | |
8549 | temp, XEXP (XEXP (x, 0), 1)); | |
390fc1d2 | 8550 | |
b92e2e43 | 8551 | return force_to_mode (x, mode, mask, next_select); |
390fc1d2 | 8552 | } |
8553 | ||
f5622cbf | 8554 | /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must |
8555 | use the full mask inside the NOT. */ | |
8556 | mask = fuller_mask; | |
8557 | ||
390fc1d2 | 8558 | unop: |
4c199243 | 8559 | op0 = gen_lowpart_or_truncate (op_mode, |
8560 | force_to_mode (XEXP (x, 0), mode, mask, | |
8561 | next_select)); | |
390fc1d2 | 8562 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) |
3380b197 | 8563 | x = simplify_gen_unary (code, op_mode, op0, op_mode); |
390fc1d2 | 8564 | break; |
8565 | ||
8566 | case NE: | |
8567 | /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included | |
45895109 | 8568 | in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, |
648c610e | 8569 | which is equal to STORE_FLAG_VALUE. */ |
897c6c81 | 8570 | if ((mask & ~STORE_FLAG_VALUE) == 0 |
8571 | && XEXP (x, 1) == const0_rtx | |
1b3407b1 | 8572 | && GET_MODE (XEXP (x, 0)) == mode |
45895109 | 8573 | && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 |
451e72c2 | 8574 | && (nonzero_bits (XEXP (x, 0), mode) |
8575 | == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE)) | |
b92e2e43 | 8576 | return force_to_mode (XEXP (x, 0), mode, mask, next_select); |
390fc1d2 | 8577 | |
ec90760f | 8578 | break; |
8579 | ||
8580 | case IF_THEN_ELSE: | |
8581 | /* We have no way of knowing if the IF_THEN_ELSE can itself be | |
8582 | written in a narrower mode. We play it safe and do not do so. */ | |
8583 | ||
aaaaacd4 | 8584 | op0 = gen_lowpart_or_truncate (GET_MODE (x), |
8585 | force_to_mode (XEXP (x, 1), mode, | |
8586 | mask, next_select)); | |
8587 | op1 = gen_lowpart_or_truncate (GET_MODE (x), | |
8588 | force_to_mode (XEXP (x, 2), mode, | |
8589 | mask, next_select)); | |
8590 | if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2)) | |
8591 | x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x), | |
8592 | GET_MODE (XEXP (x, 0)), XEXP (x, 0), | |
8593 | op0, op1); | |
ec90760f | 8594 | break; |
510f7125 | 8595 | |
0dbd1c74 | 8596 | default: |
8597 | break; | |
9efc0f8e | 8598 | } |
8599 | ||
ec90760f | 8600 | /* Ensure we return a value of the proper mode. */ |
4c199243 | 8601 | return gen_lowpart_or_truncate (mode, x); |
9efc0f8e | 8602 | } |
8603 | \f | |
862e4898 | 8604 | /* Return nonzero if X is an expression that has one of two values depending on |
8605 | whether some other value is zero or nonzero. In that case, we return the | |
8606 | value that is being tested, *PTRUE is set to the value if the rtx being | |
8607 | returned has a nonzero value, and *PFALSE is set to the other alternative. | |
8608 | ||
8609 | If we return zero, we set *PTRUE and *PFALSE to X. */ | |
8610 | ||
8611 | static rtx | |
d598ad0d | 8612 | if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse) |
862e4898 | 8613 | { |
8614 | enum machine_mode mode = GET_MODE (x); | |
8615 | enum rtx_code code = GET_CODE (x); | |
862e4898 | 8616 | rtx cond0, cond1, true0, true1, false0, false1; |
8617 | unsigned HOST_WIDE_INT nz; | |
8618 | ||
155b05dc | 8619 | /* If we are comparing a value against zero, we are done. */ |
8620 | if ((code == NE || code == EQ) | |
9a1ec826 | 8621 | && XEXP (x, 1) == const0_rtx) |
155b05dc | 8622 | { |
91599c6e | 8623 | *ptrue = (code == NE) ? const_true_rtx : const0_rtx; |
8624 | *pfalse = (code == NE) ? const0_rtx : const_true_rtx; | |
155b05dc | 8625 | return XEXP (x, 0); |
8626 | } | |
8627 | ||
862e4898 | 8628 | /* If this is a unary operation whose operand has one of two values, apply |
8629 | our opcode to compute those values. */ | |
6720e96c | 8630 | else if (UNARY_P (x) |
155b05dc | 8631 | && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) |
862e4898 | 8632 | { |
3380b197 | 8633 | *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); |
8634 | *pfalse = simplify_gen_unary (code, mode, false0, | |
8635 | GET_MODE (XEXP (x, 0))); | |
862e4898 | 8636 | return cond0; |
8637 | } | |
8638 | ||
751dd1c5 | 8639 | /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would |
01cc3b75 | 8640 | make can't possibly match and would suppress other optimizations. */ |
751dd1c5 | 8641 | else if (code == COMPARE) |
8642 | ; | |
8643 | ||
862e4898 | 8644 | /* If this is a binary operation, see if either side has only one of two |
8645 | values. If either one does or if both do and they are conditional on | |
8646 | the same value, compute the new true and false values. */ | |
6720e96c | 8647 | else if (BINARY_P (x)) |
862e4898 | 8648 | { |
8649 | cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); | |
8650 | cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); | |
8651 | ||
8652 | if ((cond0 != 0 || cond1 != 0) | |
8653 | && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) | |
8654 | { | |
9fd67677 | 8655 | /* If if_then_else_cond returned zero, then true/false are the |
8656 | same rtl. We must copy one of them to prevent invalid rtl | |
8657 | sharing. */ | |
8658 | if (cond0 == 0) | |
8659 | true0 = copy_rtx (true0); | |
8660 | else if (cond1 == 0) | |
8661 | true1 = copy_rtx (true1); | |
8662 | ||
800a7def | 8663 | if (COMPARISON_P (x)) |
8664 | { | |
8665 | *ptrue = simplify_gen_relational (code, mode, VOIDmode, | |
8666 | true0, true1); | |
8667 | *pfalse = simplify_gen_relational (code, mode, VOIDmode, | |
a0c938f0 | 8668 | false0, false1); |
800a7def | 8669 | } |
8670 | else | |
8671 | { | |
8672 | *ptrue = simplify_gen_binary (code, mode, true0, true1); | |
8673 | *pfalse = simplify_gen_binary (code, mode, false0, false1); | |
8674 | } | |
8675 | ||
862e4898 | 8676 | return cond0 ? cond0 : cond1; |
8677 | } | |
5056f17b | 8678 | |
5056f17b | 8679 | /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the |
d10cfa8d | 8680 | operands is zero when the other is nonzero, and vice-versa, |
7feddf73 | 8681 | and STORE_FLAG_VALUE is 1 or -1. */ |
5056f17b | 8682 | |
7feddf73 | 8683 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
8684 | && (code == PLUS || code == IOR || code == XOR || code == MINUS | |
510f7125 | 8685 | || code == UMAX) |
5056f17b | 8686 | && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) |
8687 | { | |
8688 | rtx op0 = XEXP (XEXP (x, 0), 1); | |
8689 | rtx op1 = XEXP (XEXP (x, 1), 1); | |
8690 | ||
8691 | cond0 = XEXP (XEXP (x, 0), 0); | |
8692 | cond1 = XEXP (XEXP (x, 1), 0); | |
8693 | ||
6720e96c | 8694 | if (COMPARISON_P (cond0) |
8695 | && COMPARISON_P (cond1) | |
0fc1e6fa | 8696 | && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) |
5056f17b | 8697 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) |
8698 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
8699 | || ((swap_condition (GET_CODE (cond0)) | |
0fc1e6fa | 8700 | == reversed_comparison_code (cond1, NULL)) |
5056f17b | 8701 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) |
8702 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
8703 | && ! side_effects_p (x)) | |
8704 | { | |
800a7def | 8705 | *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx); |
8706 | *pfalse = simplify_gen_binary (MULT, mode, | |
8707 | (code == MINUS | |
8708 | ? simplify_gen_unary (NEG, mode, | |
8709 | op1, mode) | |
8710 | : op1), | |
8711 | const_true_rtx); | |
5056f17b | 8712 | return cond0; |
8713 | } | |
8714 | } | |
8715 | ||
4a82352a | 8716 | /* Similarly for MULT, AND and UMIN, except that for these the result |
5056f17b | 8717 | is always zero. */ |
7feddf73 | 8718 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
8719 | && (code == MULT || code == AND || code == UMIN) | |
5056f17b | 8720 | && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) |
8721 | { | |
8722 | cond0 = XEXP (XEXP (x, 0), 0); | |
8723 | cond1 = XEXP (XEXP (x, 1), 0); | |
8724 | ||
6720e96c | 8725 | if (COMPARISON_P (cond0) |
8726 | && COMPARISON_P (cond1) | |
0fc1e6fa | 8727 | && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) |
5056f17b | 8728 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) |
8729 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
8730 | || ((swap_condition (GET_CODE (cond0)) | |
0fc1e6fa | 8731 | == reversed_comparison_code (cond1, NULL)) |
5056f17b | 8732 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) |
8733 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
8734 | && ! side_effects_p (x)) | |
8735 | { | |
8736 | *ptrue = *pfalse = const0_rtx; | |
8737 | return cond0; | |
8738 | } | |
8739 | } | |
862e4898 | 8740 | } |
8741 | ||
8742 | else if (code == IF_THEN_ELSE) | |
8743 | { | |
8744 | /* If we have IF_THEN_ELSE already, extract the condition and | |
8745 | canonicalize it if it is NE or EQ. */ | |
8746 | cond0 = XEXP (x, 0); | |
8747 | *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); | |
8748 | if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) | |
8749 | return XEXP (cond0, 0); | |
8750 | else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) | |
8751 | { | |
8752 | *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); | |
8753 | return XEXP (cond0, 0); | |
8754 | } | |
8755 | else | |
8756 | return cond0; | |
8757 | } | |
8758 | ||
84e81e84 | 8759 | /* If X is a SUBREG, we can narrow both the true and false values |
8760 | if the inner expression, if there is a condition. */ | |
8761 | else if (code == SUBREG | |
862e4898 | 8762 | && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), |
8763 | &true0, &false0))) | |
8764 | { | |
cbe81417 | 8765 | true0 = simplify_gen_subreg (mode, true0, |
8766 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
8767 | false0 = simplify_gen_subreg (mode, false0, | |
84e81e84 | 8768 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); |
cbe81417 | 8769 | if (true0 && false0) |
8770 | { | |
8771 | *ptrue = true0; | |
8772 | *pfalse = false0; | |
8773 | return cond0; | |
8774 | } | |
862e4898 | 8775 | } |
8776 | ||
8777 | /* If X is a constant, this isn't special and will cause confusions | |
8778 | if we treat it as such. Likewise if it is equivalent to a constant. */ | |
8779 | else if (CONSTANT_P (x) | |
8780 | || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) | |
8781 | ; | |
8782 | ||
dea049dc | 8783 | /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that |
8784 | will be least confusing to the rest of the compiler. */ | |
8785 | else if (mode == BImode) | |
8786 | { | |
8787 | *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; | |
8788 | return x; | |
8789 | } | |
8790 | ||
510f7125 | 8791 | /* If X is known to be either 0 or -1, those are the true and |
862e4898 | 8792 | false values when testing X. */ |
29743b4b | 8793 | else if (x == constm1_rtx || x == const0_rtx |
8794 | || (mode != VOIDmode | |
ded805e6 | 8795 | && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode))) |
862e4898 | 8796 | { |
8797 | *ptrue = constm1_rtx, *pfalse = const0_rtx; | |
8798 | return x; | |
8799 | } | |
8800 | ||
8801 | /* Likewise for 0 or a single bit. */ | |
f179ee60 | 8802 | else if (HWI_COMPUTABLE_MODE_P (mode) |
29743b4b | 8803 | && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) |
862e4898 | 8804 | { |
886bca0a | 8805 | *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; |
862e4898 | 8806 | return x; |
8807 | } | |
8808 | ||
8809 | /* Otherwise fail; show no condition with true and false values the same. */ | |
8810 | *ptrue = *pfalse = x; | |
8811 | return 0; | |
8812 | } | |
8813 | \f | |
1f1c8c5a | 8814 | /* Return the value of expression X given the fact that condition COND |
8815 | is known to be true when applied to REG as its first operand and VAL | |
8816 | as its second. X is known to not be shared and so can be modified in | |
8817 | place. | |
8818 | ||
8819 | We only handle the simplest cases, and specifically those cases that | |
8820 | arise with IF_THEN_ELSE expressions. */ | |
8821 | ||
8822 | static rtx | |
d598ad0d | 8823 | known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val) |
1f1c8c5a | 8824 | { |
8825 | enum rtx_code code = GET_CODE (x); | |
17ebeabc | 8826 | rtx temp; |
d2ca078f | 8827 | const char *fmt; |
1f1c8c5a | 8828 | int i, j; |
8829 | ||
8830 | if (side_effects_p (x)) | |
8831 | return x; | |
8832 | ||
46fa144f | 8833 | /* If either operand of the condition is a floating point value, |
8834 | then we have to avoid collapsing an EQ comparison. */ | |
8835 | if (cond == EQ | |
8836 | && rtx_equal_p (x, reg) | |
8837 | && ! FLOAT_MODE_P (GET_MODE (x)) | |
8838 | && ! FLOAT_MODE_P (GET_MODE (val))) | |
b467856b | 8839 | return val; |
46fa144f | 8840 | |
b467856b | 8841 | if (cond == UNEQ && rtx_equal_p (x, reg)) |
1f1c8c5a | 8842 | return val; |
8843 | ||
8844 | /* If X is (abs REG) and we know something about REG's relationship | |
8845 | with zero, we may be able to simplify this. */ | |
8846 | ||
8847 | if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) | |
8848 | switch (cond) | |
8849 | { | |
8850 | case GE: case GT: case EQ: | |
8851 | return XEXP (x, 0); | |
8852 | case LT: case LE: | |
3380b197 | 8853 | return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), |
8854 | XEXP (x, 0), | |
8855 | GET_MODE (XEXP (x, 0))); | |
0dbd1c74 | 8856 | default: |
8857 | break; | |
1f1c8c5a | 8858 | } |
8859 | ||
8860 | /* The only other cases we handle are MIN, MAX, and comparisons if the | |
8861 | operands are the same as REG and VAL. */ | |
8862 | ||
6720e96c | 8863 | else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x)) |
1f1c8c5a | 8864 | { |
8865 | if (rtx_equal_p (XEXP (x, 0), val)) | |
8866 | cond = swap_condition (cond), temp = val, val = reg, reg = temp; | |
8867 | ||
8868 | if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) | |
8869 | { | |
6720e96c | 8870 | if (COMPARISON_P (x)) |
a4110d9a | 8871 | { |
8872 | if (comparison_dominates_p (cond, code)) | |
8873 | return const_true_rtx; | |
1f1c8c5a | 8874 | |
0fc1e6fa | 8875 | code = reversed_comparison_code (x, NULL); |
a4110d9a | 8876 | if (code != UNKNOWN |
8877 | && comparison_dominates_p (cond, code)) | |
8878 | return const0_rtx; | |
8879 | else | |
8880 | return x; | |
8881 | } | |
1f1c8c5a | 8882 | else if (code == SMAX || code == SMIN |
8883 | || code == UMIN || code == UMAX) | |
8884 | { | |
8885 | int unsignedp = (code == UMIN || code == UMAX); | |
8886 | ||
e6bec3e3 | 8887 | /* Do not reverse the condition when it is NE or EQ. |
8888 | This is because we cannot conclude anything about | |
8889 | the value of 'SMAX (x, y)' when x is not equal to y, | |
87e97de6 | 8890 | but we can when x equals y. */ |
e6bec3e3 | 8891 | if ((code == SMAX || code == UMAX) |
8892 | && ! (cond == EQ || cond == NE)) | |
1f1c8c5a | 8893 | cond = reverse_condition (cond); |
8894 | ||
8895 | switch (cond) | |
8896 | { | |
8897 | case GE: case GT: | |
8898 | return unsignedp ? x : XEXP (x, 1); | |
8899 | case LE: case LT: | |
8900 | return unsignedp ? x : XEXP (x, 0); | |
8901 | case GEU: case GTU: | |
8902 | return unsignedp ? XEXP (x, 1) : x; | |
8903 | case LEU: case LTU: | |
8904 | return unsignedp ? XEXP (x, 0) : x; | |
0dbd1c74 | 8905 | default: |
8906 | break; | |
1f1c8c5a | 8907 | } |
8908 | } | |
8909 | } | |
8910 | } | |
826402d7 | 8911 | else if (code == SUBREG) |
8912 | { | |
8913 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); | |
d328ebdf | 8914 | rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val); |
826402d7 | 8915 | |
8916 | if (SUBREG_REG (x) != r) | |
8917 | { | |
8918 | /* We must simplify subreg here, before we lose track of the | |
8919 | original inner_mode. */ | |
d328ebdf | 8920 | new_rtx = simplify_subreg (GET_MODE (x), r, |
826402d7 | 8921 | inner_mode, SUBREG_BYTE (x)); |
d328ebdf | 8922 | if (new_rtx) |
8923 | return new_rtx; | |
826402d7 | 8924 | else |
8925 | SUBST (SUBREG_REG (x), r); | |
8926 | } | |
8927 | ||
8928 | return x; | |
8929 | } | |
bd72d0ee | 8930 | /* We don't have to handle SIGN_EXTEND here, because even in the |
8931 | case of replacing something with a modeless CONST_INT, a | |
8932 | CONST_INT is already (supposed to be) a valid sign extension for | |
8933 | its narrower mode, which implies it's already properly | |
8934 | sign-extended for the wider mode. Now, for ZERO_EXTEND, the | |
8935 | story is different. */ | |
8936 | else if (code == ZERO_EXTEND) | |
8937 | { | |
8938 | enum machine_mode inner_mode = GET_MODE (XEXP (x, 0)); | |
d328ebdf | 8939 | rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val); |
bd72d0ee | 8940 | |
8941 | if (XEXP (x, 0) != r) | |
8942 | { | |
8943 | /* We must simplify the zero_extend here, before we lose | |
a0c938f0 | 8944 | track of the original inner_mode. */ |
d328ebdf | 8945 | new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), |
bd72d0ee | 8946 | r, inner_mode); |
d328ebdf | 8947 | if (new_rtx) |
8948 | return new_rtx; | |
bd72d0ee | 8949 | else |
8950 | SUBST (XEXP (x, 0), r); | |
8951 | } | |
8952 | ||
8953 | return x; | |
8954 | } | |
1f1c8c5a | 8955 | |
8956 | fmt = GET_RTX_FORMAT (code); | |
8957 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8958 | { | |
8959 | if (fmt[i] == 'e') | |
8960 | SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); | |
8961 | else if (fmt[i] == 'E') | |
8962 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8963 | SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), | |
8964 | cond, reg, val)); | |
8965 | } | |
8966 | ||
8967 | return x; | |
8968 | } | |
8969 | \f | |
ea95063a | 8970 | /* See if X and Y are equal for the purposes of seeing if we can rewrite an |
8971 | assignment as a field assignment. */ | |
8972 | ||
8973 | static int | |
d598ad0d | 8974 | rtx_equal_for_field_assignment_p (rtx x, rtx y) |
ea95063a | 8975 | { |
ea95063a | 8976 | if (x == y || rtx_equal_p (x, y)) |
8977 | return 1; | |
8978 | ||
8979 | if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) | |
8980 | return 0; | |
8981 | ||
8982 | /* Check for a paradoxical SUBREG of a MEM compared with the MEM. | |
8983 | Note that all SUBREGs of MEM are paradoxical; otherwise they | |
8984 | would have been rewritten. */ | |
e16ceb8e | 8985 | if (MEM_P (x) && GET_CODE (y) == SUBREG |
8986 | && MEM_P (SUBREG_REG (y)) | |
ea95063a | 8987 | && rtx_equal_p (SUBREG_REG (y), |
316f48ea | 8988 | gen_lowpart (GET_MODE (SUBREG_REG (y)), x))) |
ea95063a | 8989 | return 1; |
8990 | ||
e16ceb8e | 8991 | if (MEM_P (y) && GET_CODE (x) == SUBREG |
8992 | && MEM_P (SUBREG_REG (x)) | |
ea95063a | 8993 | && rtx_equal_p (SUBREG_REG (x), |
316f48ea | 8994 | gen_lowpart (GET_MODE (SUBREG_REG (x)), y))) |
ea95063a | 8995 | return 1; |
8996 | ||
9e042f31 | 8997 | /* We used to see if get_last_value of X and Y were the same but that's |
8998 | not correct. In one direction, we'll cause the assignment to have | |
8999 | the wrong destination and in the case, we'll import a register into this | |
9000 | insn that might have already have been dead. So fail if none of the | |
9001 | above cases are true. */ | |
9002 | return 0; | |
ea95063a | 9003 | } |
9004 | \f | |
ccfa01f5 | 9005 | /* See if X, a SET operation, can be rewritten as a bit-field assignment. |
9006 | Return that assignment if so. | |
9007 | ||
9008 | We only handle the most common cases. */ | |
9009 | ||
9010 | static rtx | |
d598ad0d | 9011 | make_field_assignment (rtx x) |
ccfa01f5 | 9012 | { |
9013 | rtx dest = SET_DEST (x); | |
9014 | rtx src = SET_SRC (x); | |
9efc0f8e | 9015 | rtx assign; |
ea95063a | 9016 | rtx rhs, lhs; |
1bb04728 | 9017 | HOST_WIDE_INT c1; |
02e7a332 | 9018 | HOST_WIDE_INT pos; |
9019 | unsigned HOST_WIDE_INT len; | |
9efc0f8e | 9020 | rtx other; |
9021 | enum machine_mode mode; | |
ccfa01f5 | 9022 | |
9023 | /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is | |
9024 | a clear of a one-bit field. We will have changed it to | |
9025 | (and (rotate (const_int -2) POS) DEST), so check for that. Also check | |
9026 | for a SUBREG. */ | |
9027 | ||
9028 | if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE | |
971ba038 | 9029 | && CONST_INT_P (XEXP (XEXP (src, 0), 0)) |
ccfa01f5 | 9030 | && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 |
ea95063a | 9031 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) |
ccfa01f5 | 9032 | { |
f017138e | 9033 | assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), |
ccfa01f5 | 9034 | 1, 1, 1, 0); |
4dad978c | 9035 | if (assign != 0) |
941522d6 | 9036 | return gen_rtx_SET (VOIDmode, assign, const0_rtx); |
4dad978c | 9037 | return x; |
ccfa01f5 | 9038 | } |
9039 | ||
6b2c69ce | 9040 | if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG |
9041 | && subreg_lowpart_p (XEXP (src, 0)) | |
9042 | && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) | |
9043 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) | |
9044 | && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE | |
971ba038 | 9045 | && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) |
6b2c69ce | 9046 | && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 |
9047 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
ccfa01f5 | 9048 | { |
f017138e | 9049 | assign = make_extraction (VOIDmode, dest, 0, |
ccfa01f5 | 9050 | XEXP (SUBREG_REG (XEXP (src, 0)), 1), |
9051 | 1, 1, 1, 0); | |
4dad978c | 9052 | if (assign != 0) |
941522d6 | 9053 | return gen_rtx_SET (VOIDmode, assign, const0_rtx); |
4dad978c | 9054 | return x; |
ccfa01f5 | 9055 | } |
9056 | ||
1159eaa1 | 9057 | /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a |
ccfa01f5 | 9058 | one-bit field. */ |
6b2c69ce | 9059 | if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT |
9060 | && XEXP (XEXP (src, 0), 0) == const1_rtx | |
9061 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
ccfa01f5 | 9062 | { |
f017138e | 9063 | assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), |
ccfa01f5 | 9064 | 1, 1, 1, 0); |
4dad978c | 9065 | if (assign != 0) |
941522d6 | 9066 | return gen_rtx_SET (VOIDmode, assign, const1_rtx); |
4dad978c | 9067 | return x; |
ccfa01f5 | 9068 | } |
9069 | ||
6b2c69ce | 9070 | /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the |
9071 | SRC is an AND with all bits of that field set, then we can discard | |
9072 | the AND. */ | |
9073 | if (GET_CODE (dest) == ZERO_EXTRACT | |
971ba038 | 9074 | && CONST_INT_P (XEXP (dest, 1)) |
6b2c69ce | 9075 | && GET_CODE (src) == AND |
971ba038 | 9076 | && CONST_INT_P (XEXP (src, 1))) |
6b2c69ce | 9077 | { |
9078 | HOST_WIDE_INT width = INTVAL (XEXP (dest, 1)); | |
9079 | unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1)); | |
9080 | unsigned HOST_WIDE_INT ze_mask; | |
9081 | ||
9082 | if (width >= HOST_BITS_PER_WIDE_INT) | |
9083 | ze_mask = -1; | |
9084 | else | |
9085 | ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; | |
9086 | ||
9087 | /* Complete overlap. We can remove the source AND. */ | |
9088 | if ((and_mask & ze_mask) == ze_mask) | |
9089 | return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0)); | |
9090 | ||
9091 | /* Partial overlap. We can reduce the source AND. */ | |
9092 | if ((and_mask & ze_mask) != and_mask) | |
9093 | { | |
9094 | mode = GET_MODE (src); | |
9095 | src = gen_rtx_AND (mode, XEXP (src, 0), | |
af8e5e26 | 9096 | gen_int_mode (and_mask & ze_mask, mode)); |
6b2c69ce | 9097 | return gen_rtx_SET (VOIDmode, dest, src); |
9098 | } | |
9099 | } | |
9100 | ||
9efc0f8e | 9101 | /* The other case we handle is assignments into a constant-position |
1159eaa1 | 9102 | field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents |
9efc0f8e | 9103 | a mask that has all one bits except for a group of zero bits and |
9104 | OTHER is known to have zeros where C1 has ones, this is such an | |
9105 | assignment. Compute the position and length from C1. Shift OTHER | |
9106 | to the appropriate position, force it to the required mode, and | |
9107 | make the extraction. Check for the AND in both operands. */ | |
9108 | ||
1159eaa1 | 9109 | if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) |
ea95063a | 9110 | return x; |
9111 | ||
9112 | rhs = expand_compound_operation (XEXP (src, 0)); | |
9113 | lhs = expand_compound_operation (XEXP (src, 1)); | |
9114 | ||
9115 | if (GET_CODE (rhs) == AND | |
971ba038 | 9116 | && CONST_INT_P (XEXP (rhs, 1)) |
ea95063a | 9117 | && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) |
9118 | c1 = INTVAL (XEXP (rhs, 1)), other = lhs; | |
9119 | else if (GET_CODE (lhs) == AND | |
971ba038 | 9120 | && CONST_INT_P (XEXP (lhs, 1)) |
ea95063a | 9121 | && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) |
9122 | c1 = INTVAL (XEXP (lhs, 1)), other = rhs; | |
9efc0f8e | 9123 | else |
9124 | return x; | |
ccfa01f5 | 9125 | |
510f7125 | 9126 | pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); |
ded805e6 | 9127 | if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest)) |
9128 | || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT | |
997d68fe | 9129 | || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) |
9efc0f8e | 9130 | return x; |
ccfa01f5 | 9131 | |
1bb04728 | 9132 | assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); |
4dad978c | 9133 | if (assign == 0) |
9134 | return x; | |
ccfa01f5 | 9135 | |
9efc0f8e | 9136 | /* The mode to use for the source is the mode of the assignment, or of |
9137 | what is inside a possible STRICT_LOW_PART. */ | |
510f7125 | 9138 | mode = (GET_CODE (assign) == STRICT_LOW_PART |
9efc0f8e | 9139 | ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); |
ccfa01f5 | 9140 | |
9efc0f8e | 9141 | /* Shift OTHER right POS places and make it the source, restricting it |
9142 | to the proper length and mode. */ | |
ccfa01f5 | 9143 | |
b92e2e43 | 9144 | src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT, |
9145 | GET_MODE (src), | |
9146 | other, pos), | |
9147 | dest); | |
9148 | src = force_to_mode (src, mode, | |
ded805e6 | 9149 | GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT |
b5d326b3 | 9150 | ? ~(unsigned HOST_WIDE_INT) 0 |
fe352cf1 | 9151 | : ((unsigned HOST_WIDE_INT) 1 << len) - 1, |
b92e2e43 | 9152 | 0); |
ccfa01f5 | 9153 | |
a63f1b8f | 9154 | /* If SRC is masked by an AND that does not make a difference in |
9155 | the value being stored, strip it. */ | |
9156 | if (GET_CODE (assign) == ZERO_EXTRACT | |
971ba038 | 9157 | && CONST_INT_P (XEXP (assign, 1)) |
a63f1b8f | 9158 | && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT |
9159 | && GET_CODE (src) == AND | |
971ba038 | 9160 | && CONST_INT_P (XEXP (src, 1)) |
897c6c81 | 9161 | && UINTVAL (XEXP (src, 1)) |
9162 | == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1) | |
a63f1b8f | 9163 | src = XEXP (src, 0); |
9164 | ||
3380b197 | 9165 | return gen_rtx_SET (VOIDmode, assign, src); |
ccfa01f5 | 9166 | } |
9167 | \f | |
9168 | /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) | |
9169 | if so. */ | |
9170 | ||
9171 | static rtx | |
d598ad0d | 9172 | apply_distributive_law (rtx x) |
ccfa01f5 | 9173 | { |
9174 | enum rtx_code code = GET_CODE (x); | |
f58bb90b | 9175 | enum rtx_code inner_code; |
ccfa01f5 | 9176 | rtx lhs, rhs, other; |
9177 | rtx tem; | |
ccfa01f5 | 9178 | |
f58bb90b | 9179 | /* Distributivity is not true for floating point as it can change the |
9180 | value. So we don't do it unless -funsafe-math-optimizations. */ | |
9181 | if (FLOAT_MODE_P (GET_MODE (x)) | |
9182 | && ! flag_unsafe_math_optimizations) | |
b77a8efd | 9183 | return x; |
9184 | ||
ccfa01f5 | 9185 | /* The outer operation can only be one of the following: */ |
9186 | if (code != IOR && code != AND && code != XOR | |
9187 | && code != PLUS && code != MINUS) | |
9188 | return x; | |
9189 | ||
f58bb90b | 9190 | lhs = XEXP (x, 0); |
9191 | rhs = XEXP (x, 1); | |
ccfa01f5 | 9192 | |
a92771b8 | 9193 | /* If either operand is a primitive we can't do anything, so get out |
9194 | fast. */ | |
6720e96c | 9195 | if (OBJECT_P (lhs) || OBJECT_P (rhs)) |
ccfa01f5 | 9196 | return x; |
9197 | ||
9198 | lhs = expand_compound_operation (lhs); | |
9199 | rhs = expand_compound_operation (rhs); | |
9200 | inner_code = GET_CODE (lhs); | |
9201 | if (inner_code != GET_CODE (rhs)) | |
9202 | return x; | |
9203 | ||
9204 | /* See if the inner and outer operations distribute. */ | |
9205 | switch (inner_code) | |
9206 | { | |
9207 | case LSHIFTRT: | |
9208 | case ASHIFTRT: | |
9209 | case AND: | |
9210 | case IOR: | |
9211 | /* These all distribute except over PLUS. */ | |
9212 | if (code == PLUS || code == MINUS) | |
9213 | return x; | |
9214 | break; | |
9215 | ||
9216 | case MULT: | |
9217 | if (code != PLUS && code != MINUS) | |
9218 | return x; | |
9219 | break; | |
9220 | ||
9221 | case ASHIFT: | |
6503f782 | 9222 | /* This is also a multiply, so it distributes over everything. */ |
ccfa01f5 | 9223 | break; |
9224 | ||
2ef72921 | 9225 | /* This used to handle SUBREG, but this turned out to be counter- |
9226 | productive, since (subreg (op ...)) usually is not handled by | |
9227 | insn patterns, and this "optimization" therefore transformed | |
9228 | recognizable patterns into unrecognizable ones. Therefore the | |
9229 | SUBREG case was removed from here. | |
9230 | ||
9231 | It is possible that distributing SUBREG over arithmetic operations | |
9232 | leads to an intermediate result than can then be optimized further, | |
9233 | e.g. by moving the outer SUBREG to the other side of a SET as done | |
9234 | in simplify_set. This seems to have been the original intent of | |
9235 | handling SUBREGs here. | |
9236 | ||
9237 | However, with current GCC this does not appear to actually happen, | |
9238 | at least on major platforms. If some case is found where removing | |
9239 | the SUBREG case here prevents follow-on optimizations, distributing | |
9240 | SUBREGs ought to be re-added at that place, e.g. in simplify_set. */ | |
ccfa01f5 | 9241 | |
9242 | default: | |
9243 | return x; | |
9244 | } | |
9245 | ||
9246 | /* Set LHS and RHS to the inner operands (A and B in the example | |
9247 | above) and set OTHER to the common operand (C in the example). | |
6720e96c | 9248 | There is only one way to do this unless the inner operation is |
ccfa01f5 | 9249 | commutative. */ |
6720e96c | 9250 | if (COMMUTATIVE_ARITH_P (lhs) |
ccfa01f5 | 9251 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) |
9252 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); | |
6720e96c | 9253 | else if (COMMUTATIVE_ARITH_P (lhs) |
ccfa01f5 | 9254 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) |
9255 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); | |
6720e96c | 9256 | else if (COMMUTATIVE_ARITH_P (lhs) |
ccfa01f5 | 9257 | && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) |
9258 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); | |
9259 | else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) | |
9260 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); | |
9261 | else | |
9262 | return x; | |
9263 | ||
9264 | /* Form the new inner operation, seeing if it simplifies first. */ | |
800a7def | 9265 | tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs); |
ccfa01f5 | 9266 | |
9267 | /* There is one exception to the general way of distributing: | |
18f2b54c | 9268 | (a | c) ^ (b | c) -> (a ^ b) & ~c */ |
ccfa01f5 | 9269 | if (code == XOR && inner_code == IOR) |
9270 | { | |
9271 | inner_code = AND; | |
3380b197 | 9272 | other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); |
ccfa01f5 | 9273 | } |
9274 | ||
9275 | /* We may be able to continuing distributing the result, so call | |
9276 | ourselves recursively on the inner operation before forming the | |
9277 | outer operation, which we return. */ | |
800a7def | 9278 | return simplify_gen_binary (inner_code, GET_MODE (x), |
9279 | apply_distributive_law (tem), other); | |
9280 | } | |
9281 | ||
9282 | /* See if X is of the form (* (+ A B) C), and if so convert to | |
9283 | (+ (* A C) (* B C)) and try to simplify. | |
9284 | ||
9285 | Most of the time, this results in no change. However, if some of | |
9286 | the operands are the same or inverses of each other, simplifications | |
9287 | will result. | |
9288 | ||
9289 | For example, (and (ior A B) (not B)) can occur as the result of | |
9290 | expanding a bit field assignment. When we apply the distributive | |
9291 | law to this, we get (ior (and (A (not B))) (and (B (not B)))), | |
9292 | which then simplifies to (and (A (not B))). | |
a0c938f0 | 9293 | |
800a7def | 9294 | Note that no checks happen on the validity of applying the inverse |
9295 | distributive law. This is pointless since we can do it in the | |
9296 | few places where this routine is called. | |
9297 | ||
9298 | N is the index of the term that is decomposed (the arithmetic operation, | |
9299 | i.e. (+ A B) in the first example above). !N is the index of the term that | |
9300 | is distributed, i.e. of C in the first example above. */ | |
9301 | static rtx | |
9302 | distribute_and_simplify_rtx (rtx x, int n) | |
9303 | { | |
9304 | enum machine_mode mode; | |
9305 | enum rtx_code outer_code, inner_code; | |
9306 | rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp; | |
9307 | ||
359a1bd5 | 9308 | /* Distributivity is not true for floating point as it can change the |
9309 | value. So we don't do it unless -funsafe-math-optimizations. */ | |
9310 | if (FLOAT_MODE_P (GET_MODE (x)) | |
9311 | && ! flag_unsafe_math_optimizations) | |
9312 | return NULL_RTX; | |
9313 | ||
800a7def | 9314 | decomposed = XEXP (x, n); |
9315 | if (!ARITHMETIC_P (decomposed)) | |
9316 | return NULL_RTX; | |
9317 | ||
9318 | mode = GET_MODE (x); | |
9319 | outer_code = GET_CODE (x); | |
9320 | distributed = XEXP (x, !n); | |
9321 | ||
9322 | inner_code = GET_CODE (decomposed); | |
9323 | inner_op0 = XEXP (decomposed, 0); | |
9324 | inner_op1 = XEXP (decomposed, 1); | |
9325 | ||
9326 | /* Special case (and (xor B C) (not A)), which is equivalent to | |
9327 | (xor (ior A B) (ior A C)) */ | |
9328 | if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT) | |
9329 | { | |
9330 | distributed = XEXP (distributed, 0); | |
9331 | outer_code = IOR; | |
9332 | } | |
9333 | ||
9334 | if (n == 0) | |
9335 | { | |
9336 | /* Distribute the second term. */ | |
9337 | new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed); | |
9338 | new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed); | |
9339 | } | |
9340 | else | |
9341 | { | |
9342 | /* Distribute the first term. */ | |
9343 | new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0); | |
9344 | new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1); | |
9345 | } | |
9346 | ||
9347 | tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode, | |
9348 | new_op0, new_op1)); | |
9349 | if (GET_CODE (tmp) != outer_code | |
7013e87c | 9350 | && (set_src_cost (tmp, optimize_this_for_speed_p) |
9351 | < set_src_cost (x, optimize_this_for_speed_p))) | |
800a7def | 9352 | return tmp; |
9353 | ||
9354 | return NULL_RTX; | |
ccfa01f5 | 9355 | } |
9356 | \f | |
1282ed8f | 9357 | /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done |
9358 | in MODE. Return an equivalent form, if different from (and VAROP | |
9359 | (const_int CONSTOP)). Otherwise, return NULL_RTX. */ | |
ccfa01f5 | 9360 | |
9361 | static rtx | |
1282ed8f | 9362 | simplify_and_const_int_1 (enum machine_mode mode, rtx varop, |
9363 | unsigned HOST_WIDE_INT constop) | |
ccfa01f5 | 9364 | { |
3d882a35 | 9365 | unsigned HOST_WIDE_INT nonzero; |
1282ed8f | 9366 | unsigned HOST_WIDE_INT orig_constop; |
9367 | rtx orig_varop; | |
5563ada6 | 9368 | int i; |
ccfa01f5 | 9369 | |
1282ed8f | 9370 | orig_varop = varop; |
9371 | orig_constop = constop; | |
9372 | if (GET_CODE (varop) == CLOBBER) | |
9373 | return NULL_RTX; | |
9374 | ||
390fc1d2 | 9375 | /* Simplify VAROP knowing that we will be only looking at some of the |
6ee1791f | 9376 | bits in it. |
9377 | ||
9378 | Note by passing in CONSTOP, we guarantee that the bits not set in | |
9379 | CONSTOP are not significant and will never be examined. We must | |
9380 | ensure that is the case by explicitly masking out those bits | |
9381 | before returning. */ | |
b92e2e43 | 9382 | varop = force_to_mode (varop, mode, constop, 0); |
ccfa01f5 | 9383 | |
6ee1791f | 9384 | /* If VAROP is a CLOBBER, we will fail so return it. */ |
9385 | if (GET_CODE (varop) == CLOBBER) | |
390fc1d2 | 9386 | return varop; |
ccfa01f5 | 9387 | |
6ee1791f | 9388 | /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP |
9389 | to VAROP and return the new constant. */ | |
971ba038 | 9390 | if (CONST_INT_P (varop)) |
69e41517 | 9391 | return gen_int_mode (INTVAL (varop) & constop, mode); |
6ee1791f | 9392 | |
4a2b3ef8 | 9393 | /* See what bits may be nonzero in VAROP. Unlike the general case of |
9394 | a call to nonzero_bits, here we don't care about bits outside | |
9395 | MODE. */ | |
9396 | ||
9397 | nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); | |
e1b1d556 | 9398 | |
ccfa01f5 | 9399 | /* Turn off all bits in the constant that are known to already be zero. |
3d882a35 | 9400 | Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS |
ccfa01f5 | 9401 | which is tested below. */ |
9402 | ||
3d882a35 | 9403 | constop &= nonzero; |
ccfa01f5 | 9404 | |
9405 | /* If we don't have any bits left, return zero. */ | |
9406 | if (constop == 0) | |
9407 | return const0_rtx; | |
9408 | ||
5563ada6 | 9409 | /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is |
dafdd1c8 | 9410 | a power of two, we can replace this with an ASHIFT. */ |
5563ada6 | 9411 | if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 |
9412 | && (i = exact_log2 (constop)) >= 0) | |
9413 | return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); | |
510f7125 | 9414 | |
390fc1d2 | 9415 | /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR |
9416 | or XOR, then try to apply the distributive law. This may eliminate | |
9417 | operations if either branch can be simplified because of the AND. | |
9418 | It may also make some cases more complex, but those cases probably | |
9419 | won't match a pattern either with or without this. */ | |
9420 | ||
9421 | if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) | |
9422 | return | |
316f48ea | 9423 | gen_lowpart |
390fc1d2 | 9424 | (mode, |
9425 | apply_distributive_law | |
800a7def | 9426 | (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop), |
9427 | simplify_and_const_int (NULL_RTX, | |
9428 | GET_MODE (varop), | |
9429 | XEXP (varop, 0), | |
9430 | constop), | |
9431 | simplify_and_const_int (NULL_RTX, | |
9432 | GET_MODE (varop), | |
9433 | XEXP (varop, 1), | |
9434 | constop)))); | |
390fc1d2 | 9435 | |
b92e2e43 | 9436 | /* If VAROP is PLUS, and the constant is a mask of low bits, distribute |
0af94772 | 9437 | the AND and see if one of the operands simplifies to zero. If so, we |
9438 | may eliminate it. */ | |
9439 | ||
9440 | if (GET_CODE (varop) == PLUS | |
9441 | && exact_log2 (constop + 1) >= 0) | |
9442 | { | |
9443 | rtx o0, o1; | |
9444 | ||
9445 | o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); | |
9446 | o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); | |
9447 | if (o0 == const0_rtx) | |
9448 | return o1; | |
9449 | if (o1 == const0_rtx) | |
9450 | return o0; | |
9451 | } | |
9452 | ||
1282ed8f | 9453 | /* Make a SUBREG if necessary. If we can't make it, fail. */ |
9454 | varop = gen_lowpart (mode, varop); | |
9455 | if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) | |
9456 | return NULL_RTX; | |
ccfa01f5 | 9457 | |
9458 | /* If we are only masking insignificant bits, return VAROP. */ | |
3d882a35 | 9459 | if (constop == nonzero) |
1282ed8f | 9460 | return varop; |
ccfa01f5 | 9461 | |
1282ed8f | 9462 | if (varop == orig_varop && constop == orig_constop) |
9463 | return NULL_RTX; | |
ec00a5f6 | 9464 | |
1282ed8f | 9465 | /* Otherwise, return an AND. */ |
91bc4142 | 9466 | return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode)); |
1282ed8f | 9467 | } |
9468 | ||
9469 | ||
9470 | /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done | |
9471 | in MODE. | |
9472 | ||
9473 | Return an equivalent form, if different from X. Otherwise, return X. If | |
9474 | X is zero, we are to always construct the equivalent form. */ | |
9475 | ||
9476 | static rtx | |
9477 | simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop, | |
9478 | unsigned HOST_WIDE_INT constop) | |
9479 | { | |
9480 | rtx tem = simplify_and_const_int_1 (mode, varop, constop); | |
9481 | if (tem) | |
9482 | return tem; | |
ccfa01f5 | 9483 | |
1282ed8f | 9484 | if (!x) |
91bc4142 | 9485 | x = simplify_gen_binary (AND, GET_MODE (varop), varop, |
9486 | gen_int_mode (constop, mode)); | |
1282ed8f | 9487 | if (GET_MODE (x) != mode) |
9488 | x = gen_lowpart (mode, x); | |
ccfa01f5 | 9489 | return x; |
9490 | } | |
9491 | \f | |
d263732c | 9492 | /* Given a REG, X, compute which bits in X can be nonzero. |
ccfa01f5 | 9493 | We don't care about bits outside of those defined in MODE. |
9494 | ||
9495 | For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is | |
9496 | a shift, AND, or zero_extract, we can do better. */ | |
9497 | ||
d263732c | 9498 | static rtx |
b7bf20db | 9499 | reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode, |
9500 | const_rtx known_x ATTRIBUTE_UNUSED, | |
d263732c | 9501 | enum machine_mode known_mode ATTRIBUTE_UNUSED, |
9502 | unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED, | |
9503 | unsigned HOST_WIDE_INT *nonzero) | |
ccfa01f5 | 9504 | { |
ccfa01f5 | 9505 | rtx tem; |
7ed1bb71 | 9506 | reg_stat_type *rsp; |
ccfa01f5 | 9507 | |
d263732c | 9508 | /* If X is a register whose nonzero bits value is current, use it. |
9509 | Otherwise, if X is a register whose value we can find, use that | |
9510 | value. Otherwise, use the previously-computed global nonzero bits | |
9511 | for this register. */ | |
9512 | ||
f1f41a6c | 9513 | rsp = ®_stat[REGNO (x)]; |
7ed1bb71 | 9514 | if (rsp->last_set_value != 0 |
9515 | && (rsp->last_set_mode == mode | |
9516 | || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT | |
d263732c | 9517 | && GET_MODE_CLASS (mode) == MODE_INT)) |
7ed1bb71 | 9518 | && ((rsp->last_set_label >= label_tick_ebb_start |
9519 | && rsp->last_set_label < label_tick) | |
9520 | || (rsp->last_set_label == label_tick | |
9521 | && DF_INSN_LUID (rsp->last_set) < subst_low_luid) | |
d263732c | 9522 | || (REGNO (x) >= FIRST_PSEUDO_REGISTER |
9523 | && REG_N_SETS (REGNO (x)) == 1 | |
3072d30e | 9524 | && !REGNO_REG_SET_P |
34154e27 | 9525 | (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), |
9526 | REGNO (x))))) | |
ccfa01f5 | 9527 | { |
8487161b | 9528 | unsigned HOST_WIDE_INT mask = rsp->last_set_nonzero_bits; |
9529 | ||
9530 | if (GET_MODE_PRECISION (rsp->last_set_mode) < GET_MODE_PRECISION (mode)) | |
9531 | /* We don't know anything about the upper bits. */ | |
9532 | mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (rsp->last_set_mode); | |
9533 | ||
9534 | *nonzero &= mask; | |
d263732c | 9535 | return NULL; |
ccfa01f5 | 9536 | } |
9537 | ||
d263732c | 9538 | tem = get_last_value (x); |
ccfa01f5 | 9539 | |
d263732c | 9540 | if (tem) |
78e20271 | 9541 | { |
f53963df | 9542 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND |
d263732c | 9543 | /* If X is narrower than MODE and TEM is a non-negative |
a0c938f0 | 9544 | constant that would appear negative in the mode of X, |
9545 | sign-extend it for use in reg_nonzero_bits because some | |
9546 | machines (maybe most) will actually do the sign-extension | |
9547 | and this is the conservative approach. | |
d263732c | 9548 | |
a0c938f0 | 9549 | ??? For 2.5, try to tighten up the MD files in this regard |
9550 | instead of this kludge. */ | |
d263732c | 9551 | |
f92430e0 | 9552 | if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode) |
971ba038 | 9553 | && CONST_INT_P (tem) |
d263732c | 9554 | && INTVAL (tem) > 0 |
f92430e0 | 9555 | && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem))) |
9556 | tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x))); | |
ccfa01f5 | 9557 | #endif |
d263732c | 9558 | return tem; |
ccfa01f5 | 9559 | } |
7ed1bb71 | 9560 | else if (nonzero_sign_valid && rsp->nonzero_bits) |
0defd243 | 9561 | { |
7ed1bb71 | 9562 | unsigned HOST_WIDE_INT mask = rsp->nonzero_bits; |
0defd243 | 9563 | |
ded805e6 | 9564 | if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)) |
a0c938f0 | 9565 | /* We don't know anything about the upper bits. */ |
9566 | mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); | |
8487161b | 9567 | |
d263732c | 9568 | *nonzero &= mask; |
0defd243 | 9569 | } |
9570 | ||
d263732c | 9571 | return NULL; |
0defd243 | 9572 | } |
9573 | ||
ec90760f | 9574 | /* Return the number of bits at the high-order end of X that are known to |
9bab13ca | 9575 | be equal to the sign bit. X will be used in mode MODE; if MODE is |
9576 | VOIDmode, X will be used in its own mode. The returned value will always | |
9577 | be between 1 and the number of bits in MODE. */ | |
ec90760f | 9578 | |
d263732c | 9579 | static rtx |
b7bf20db | 9580 | reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode, |
9581 | const_rtx known_x ATTRIBUTE_UNUSED, | |
d263732c | 9582 | enum machine_mode known_mode |
9583 | ATTRIBUTE_UNUSED, | |
9584 | unsigned int known_ret ATTRIBUTE_UNUSED, | |
9585 | unsigned int *result) | |
ec90760f | 9586 | { |
ec90760f | 9587 | rtx tem; |
7ed1bb71 | 9588 | reg_stat_type *rsp; |
9589 | ||
f1f41a6c | 9590 | rsp = ®_stat[REGNO (x)]; |
7ed1bb71 | 9591 | if (rsp->last_set_value != 0 |
9592 | && rsp->last_set_mode == mode | |
9593 | && ((rsp->last_set_label >= label_tick_ebb_start | |
9594 | && rsp->last_set_label < label_tick) | |
9595 | || (rsp->last_set_label == label_tick | |
9596 | && DF_INSN_LUID (rsp->last_set) < subst_low_luid) | |
a0c938f0 | 9597 | || (REGNO (x) >= FIRST_PSEUDO_REGISTER |
d263732c | 9598 | && REG_N_SETS (REGNO (x)) == 1 |
3072d30e | 9599 | && !REGNO_REG_SET_P |
34154e27 | 9600 | (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), |
9601 | REGNO (x))))) | |
02e7a332 | 9602 | { |
7ed1bb71 | 9603 | *result = rsp->last_set_sign_bit_copies; |
d263732c | 9604 | return NULL; |
ec90760f | 9605 | } |
9606 | ||
d263732c | 9607 | tem = get_last_value (x); |
9608 | if (tem != 0) | |
9609 | return tem; | |
ec90760f | 9610 | |
7ed1bb71 | 9611 | if (nonzero_sign_valid && rsp->sign_bit_copies != 0 |
ded805e6 | 9612 | && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode)) |
7ed1bb71 | 9613 | *result = rsp->sign_bit_copies; |
a0c938f0 | 9614 | |
d263732c | 9615 | return NULL; |
ec90760f | 9616 | } |
9617 | \f | |
8bbbe2b5 | 9618 | /* Return the number of "extended" bits there are in X, when interpreted |
9619 | as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For | |
9620 | unsigned quantities, this is the number of high-order zero bits. | |
9621 | For signed quantities, this is the number of copies of the sign bit | |
9622 | minus 1. In both case, this function returns the number of "spare" | |
9623 | bits. For example, if two quantities for which this function returns | |
9624 | at least 1 are added, the addition is known not to overflow. | |
9625 | ||
9626 | This function will always return 0 unless called during combine, which | |
9627 | implies that it must be called from a define_split. */ | |
9628 | ||
9629 | unsigned int | |
9630 | extended_count (const_rtx x, enum machine_mode mode, int unsignedp) | |
9631 | { | |
9632 | if (nonzero_sign_valid == 0) | |
9633 | return 0; | |
9634 | ||
9635 | return (unsignedp | |
9636 | ? (HWI_COMPUTABLE_MODE_P (mode) | |
9637 | ? (unsigned int) (GET_MODE_PRECISION (mode) - 1 | |
9638 | - floor_log2 (nonzero_bits (x, mode))) | |
9639 | : 0) | |
9640 | : num_sign_bit_copies (x, mode) - 1); | |
9641 | } | |
9642 | ||
ccfa01f5 | 9643 | /* This function is called from `simplify_shift_const' to merge two |
9644 | outer operations. Specifically, we have already found that we need | |
9645 | to perform operation *POP0 with constant *PCONST0 at the outermost | |
9646 | position. We would now like to also perform OP1 with constant CONST1 | |
9647 | (with *POP0 being done last). | |
9648 | ||
9649 | Return 1 if we can do the operation and update *POP0 and *PCONST0 with | |
510f7125 | 9650 | the resulting operation. *PCOMP_P is set to 1 if we would need to |
ccfa01f5 | 9651 | complement the innermost operand, otherwise it is unchanged. |
9652 | ||
9653 | MODE is the mode in which the operation will be done. No bits outside | |
9654 | the width of this mode matter. It is assumed that the width of this mode | |
1bb04728 | 9655 | is smaller than or equal to HOST_BITS_PER_WIDE_INT. |
ccfa01f5 | 9656 | |
21f1e711 | 9657 | If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, |
ccfa01f5 | 9658 | IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper |
9659 | result is simply *PCONST0. | |
9660 | ||
9661 | If the resulting operation cannot be expressed as one operation, we | |
9662 | return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ | |
9663 | ||
9664 | static int | |
d598ad0d | 9665 | merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p) |
ccfa01f5 | 9666 | { |
9667 | enum rtx_code op0 = *pop0; | |
1bb04728 | 9668 | HOST_WIDE_INT const0 = *pconst0; |
ccfa01f5 | 9669 | |
9670 | const0 &= GET_MODE_MASK (mode); | |
9671 | const1 &= GET_MODE_MASK (mode); | |
9672 | ||
9673 | /* If OP0 is an AND, clear unimportant bits in CONST1. */ | |
9674 | if (op0 == AND) | |
9675 | const1 &= const0; | |
9676 | ||
21f1e711 | 9677 | /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or |
ccfa01f5 | 9678 | if OP0 is SET. */ |
9679 | ||
21f1e711 | 9680 | if (op1 == UNKNOWN || op0 == SET) |
ccfa01f5 | 9681 | return 1; |
9682 | ||
21f1e711 | 9683 | else if (op0 == UNKNOWN) |
ccfa01f5 | 9684 | op0 = op1, const0 = const1; |
9685 | ||
9686 | else if (op0 == op1) | |
9687 | { | |
9688 | switch (op0) | |
9689 | { | |
9690 | case AND: | |
9691 | const0 &= const1; | |
9692 | break; | |
9693 | case IOR: | |
9694 | const0 |= const1; | |
9695 | break; | |
9696 | case XOR: | |
9697 | const0 ^= const1; | |
9698 | break; | |
9699 | case PLUS: | |
9700 | const0 += const1; | |
9701 | break; | |
9702 | case NEG: | |
21f1e711 | 9703 | op0 = UNKNOWN; |
ccfa01f5 | 9704 | break; |
0dbd1c74 | 9705 | default: |
9706 | break; | |
ccfa01f5 | 9707 | } |
9708 | } | |
9709 | ||
9710 | /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ | |
9711 | else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) | |
9712 | return 0; | |
9713 | ||
9714 | /* If the two constants aren't the same, we can't do anything. The | |
9715 | remaining six cases can all be done. */ | |
9716 | else if (const0 != const1) | |
9717 | return 0; | |
9718 | ||
9719 | else | |
9720 | switch (op0) | |
9721 | { | |
9722 | case IOR: | |
9723 | if (op1 == AND) | |
9724 | /* (a & b) | b == b */ | |
9725 | op0 = SET; | |
9726 | else /* op1 == XOR */ | |
9727 | /* (a ^ b) | b == a | b */ | |
6536bc06 | 9728 | {;} |
ccfa01f5 | 9729 | break; |
9730 | ||
9731 | case XOR: | |
9732 | if (op1 == AND) | |
9733 | /* (a & b) ^ b == (~a) & b */ | |
9734 | op0 = AND, *pcomp_p = 1; | |
9735 | else /* op1 == IOR */ | |
9736 | /* (a | b) ^ b == a & ~b */ | |
882ba07d | 9737 | op0 = AND, const0 = ~const0; |
ccfa01f5 | 9738 | break; |
9739 | ||
9740 | case AND: | |
9741 | if (op1 == IOR) | |
9742 | /* (a | b) & b == b */ | |
9743 | op0 = SET; | |
9744 | else /* op1 == XOR */ | |
9745 | /* (a ^ b) & b) == (~a) & b */ | |
9746 | *pcomp_p = 1; | |
9747 | break; | |
0dbd1c74 | 9748 | default: |
9749 | break; | |
ccfa01f5 | 9750 | } |
9751 | ||
9752 | /* Check for NO-OP cases. */ | |
9753 | const0 &= GET_MODE_MASK (mode); | |
9754 | if (const0 == 0 | |
9755 | && (op0 == IOR || op0 == XOR || op0 == PLUS)) | |
21f1e711 | 9756 | op0 = UNKNOWN; |
ccfa01f5 | 9757 | else if (const0 == 0 && op0 == AND) |
9758 | op0 = SET; | |
274c11d8 | 9759 | else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) |
9760 | && op0 == AND) | |
21f1e711 | 9761 | op0 = UNKNOWN; |
ccfa01f5 | 9762 | |
959aa063 | 9763 | *pop0 = op0; |
9764 | ||
b2345915 | 9765 | /* ??? Slightly redundant with the above mask, but not entirely. |
9766 | Moving this above means we'd have to sign-extend the mode mask | |
9767 | for the final test. */ | |
959aa063 | 9768 | if (op0 != UNKNOWN && op0 != NEG) |
9769 | *pconst0 = trunc_int_for_mode (const0, mode); | |
ccfa01f5 | 9770 | |
9771 | return 1; | |
9772 | } | |
9773 | \f | |
5b46cc62 | 9774 | /* A helper to simplify_shift_const_1 to determine the mode we can perform |
9775 | the shift in. The original shift operation CODE is performed on OP in | |
9776 | ORIG_MODE. Return the wider mode MODE if we can perform the operation | |
4e0ce2fb | 9777 | in that mode. Return ORIG_MODE otherwise. We can also assume that the |
9778 | result of the shift is subject to operation OUTER_CODE with operand | |
9779 | OUTER_CONST. */ | |
5b46cc62 | 9780 | |
9781 | static enum machine_mode | |
4e0ce2fb | 9782 | try_widen_shift_mode (enum rtx_code code, rtx op, int count, |
9783 | enum machine_mode orig_mode, enum machine_mode mode, | |
9784 | enum rtx_code outer_code, HOST_WIDE_INT outer_const) | |
5b46cc62 | 9785 | { |
9786 | if (orig_mode == mode) | |
9787 | return mode; | |
ded805e6 | 9788 | gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode)); |
5b46cc62 | 9789 | |
9790 | /* In general we can't perform in wider mode for right shift and rotate. */ | |
9791 | switch (code) | |
9792 | { | |
9793 | case ASHIFTRT: | |
9794 | /* We can still widen if the bits brought in from the left are identical | |
9795 | to the sign bit of ORIG_MODE. */ | |
9796 | if (num_sign_bit_copies (op, mode) | |
ded805e6 | 9797 | > (unsigned) (GET_MODE_PRECISION (mode) |
9798 | - GET_MODE_PRECISION (orig_mode))) | |
5b46cc62 | 9799 | return mode; |
be26a489 | 9800 | return orig_mode; |
9801 | ||
5b46cc62 | 9802 | case LSHIFTRT: |
be26a489 | 9803 | /* Similarly here but with zero bits. */ |
f179ee60 | 9804 | if (HWI_COMPUTABLE_MODE_P (mode) |
be26a489 | 9805 | && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0) |
9806 | return mode; | |
4e0ce2fb | 9807 | |
9808 | /* We can also widen if the bits brought in will be masked off. This | |
9809 | operation is performed in ORIG_MODE. */ | |
d16b48d5 | 9810 | if (outer_code == AND) |
4e0ce2fb | 9811 | { |
d16b48d5 | 9812 | int care_bits = low_bitmask_len (orig_mode, outer_const); |
4e0ce2fb | 9813 | |
9814 | if (care_bits >= 0 | |
ded805e6 | 9815 | && GET_MODE_PRECISION (orig_mode) - care_bits >= count) |
4e0ce2fb | 9816 | return mode; |
9817 | } | |
be26a489 | 9818 | /* fall through */ |
9819 | ||
5b46cc62 | 9820 | case ROTATE: |
9821 | return orig_mode; | |
9822 | ||
9823 | case ROTATERT: | |
9824 | gcc_unreachable (); | |
9825 | ||
9826 | default: | |
9827 | return mode; | |
9828 | } | |
9829 | } | |
9830 | ||
ded805e6 | 9831 | /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind |
9832 | of shift. The result of the shift is RESULT_MODE. Return NULL_RTX | |
9833 | if we cannot simplify it. Otherwise, return a simplified value. | |
ccfa01f5 | 9834 | |
9835 | The shift is normally computed in the widest mode we find in VAROP, as | |
9836 | long as it isn't a different number of words than RESULT_MODE. Exceptions | |
1282ed8f | 9837 | are ASHIFTRT and ROTATE, which are always done in their original mode. */ |
ccfa01f5 | 9838 | |
9839 | static rtx | |
1282ed8f | 9840 | simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode, |
9841 | rtx varop, int orig_count) | |
ccfa01f5 | 9842 | { |
9843 | enum rtx_code orig_code = code; | |
1282ed8f | 9844 | rtx orig_varop = varop; |
9845 | int count; | |
ccfa01f5 | 9846 | enum machine_mode mode = result_mode; |
9847 | enum machine_mode shift_mode, tmode; | |
02e7a332 | 9848 | unsigned int mode_words |
ccfa01f5 | 9849 | = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; |
9850 | /* We form (outer_op (code varop count) (outer_const)). */ | |
21f1e711 | 9851 | enum rtx_code outer_op = UNKNOWN; |
a66086da | 9852 | HOST_WIDE_INT outer_const = 0; |
ccfa01f5 | 9853 | int complement_p = 0; |
d328ebdf | 9854 | rtx new_rtx, x; |
ccfa01f5 | 9855 | |
f095ddef | 9856 | /* Make sure and truncate the "natural" shift on the way in. We don't |
9857 | want to do this inside the loop as it makes it more difficult to | |
9858 | combine shifts. */ | |
f095ddef | 9859 | if (SHIFT_COUNT_TRUNCATED) |
b3003238 | 9860 | orig_count &= GET_MODE_BITSIZE (mode) - 1; |
f095ddef | 9861 | |
ccfa01f5 | 9862 | /* If we were given an invalid count, don't do anything except exactly |
9863 | what was requested. */ | |
9864 | ||
ded805e6 | 9865 | if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode)) |
1282ed8f | 9866 | return NULL_RTX; |
ccfa01f5 | 9867 | |
f095ddef | 9868 | count = orig_count; |
59b24b5b | 9869 | |
ccfa01f5 | 9870 | /* Unless one of the branches of the `if' in this loop does a `continue', |
9871 | we will `break' the loop after the `if'. */ | |
9872 | ||
9873 | while (count != 0) | |
9874 | { | |
1282ed8f | 9875 | /* If we have an operand of (clobber (const_int 0)), fail. */ |
ccfa01f5 | 9876 | if (GET_CODE (varop) == CLOBBER) |
1282ed8f | 9877 | return NULL_RTX; |
ccfa01f5 | 9878 | |
b090827b | 9879 | /* Convert ROTATERT to ROTATE. */ |
ccfa01f5 | 9880 | if (code == ROTATERT) |
77f1f7c1 | 9881 | { |
ded805e6 | 9882 | unsigned int bitsize = GET_MODE_PRECISION (result_mode); |
77f1f7c1 | 9883 | code = ROTATE; |
9884 | if (VECTOR_MODE_P (result_mode)) | |
9885 | count = bitsize / GET_MODE_NUNITS (result_mode) - count; | |
9886 | else | |
9887 | count = bitsize - count; | |
9888 | } | |
ccfa01f5 | 9889 | |
4e0ce2fb | 9890 | shift_mode = try_widen_shift_mode (code, varop, count, result_mode, |
9891 | mode, outer_op, outer_const); | |
ccfa01f5 | 9892 | |
9893 | /* Handle cases where the count is greater than the size of the mode | |
59b24b5b | 9894 | minus 1. For ASHIFT, use the size minus one as the count (this can |
9895 | occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, | |
9896 | take the count modulo the size. For other shifts, the result is | |
9897 | zero. | |
ccfa01f5 | 9898 | |
9899 | Since these shifts are being produced by the compiler by combining | |
9900 | multiple operations, each of which are defined, we know what the | |
9901 | result is supposed to be. */ | |
510f7125 | 9902 | |
ded805e6 | 9903 | if (count > (GET_MODE_PRECISION (shift_mode) - 1)) |
ccfa01f5 | 9904 | { |
9905 | if (code == ASHIFTRT) | |
ded805e6 | 9906 | count = GET_MODE_PRECISION (shift_mode) - 1; |
ccfa01f5 | 9907 | else if (code == ROTATE || code == ROTATERT) |
ded805e6 | 9908 | count %= GET_MODE_PRECISION (shift_mode); |
ccfa01f5 | 9909 | else |
9910 | { | |
9911 | /* We can't simply return zero because there may be an | |
9912 | outer op. */ | |
9913 | varop = const0_rtx; | |
9914 | count = 0; | |
9915 | break; | |
9916 | } | |
9917 | } | |
9918 | ||
ff2f572b | 9919 | /* If we discovered we had to complement VAROP, leave. Making a NOT |
9920 | here would cause an infinite loop. */ | |
9921 | if (complement_p) | |
9922 | break; | |
9923 | ||
ce62335a | 9924 | /* An arithmetic right shift of a quantity known to be -1 or 0 |
9925 | is a no-op. */ | |
9926 | if (code == ASHIFTRT | |
9927 | && (num_sign_bit_copies (varop, shift_mode) | |
ded805e6 | 9928 | == GET_MODE_PRECISION (shift_mode))) |
ec90760f | 9929 | { |
ce62335a | 9930 | count = 0; |
9931 | break; | |
9932 | } | |
ec90760f | 9933 | |
ce62335a | 9934 | /* If we are doing an arithmetic right shift and discarding all but |
9935 | the sign bit copies, this is equivalent to doing a shift by the | |
9936 | bitsize minus one. Convert it into that shift because it will often | |
9937 | allow other simplifications. */ | |
52e3b5a6 | 9938 | |
ce62335a | 9939 | if (code == ASHIFTRT |
9940 | && (count + num_sign_bit_copies (varop, shift_mode) | |
ded805e6 | 9941 | >= GET_MODE_PRECISION (shift_mode))) |
9942 | count = GET_MODE_PRECISION (shift_mode) - 1; | |
52e3b5a6 | 9943 | |
ccfa01f5 | 9944 | /* We simplify the tests below and elsewhere by converting |
9945 | ASHIFTRT to LSHIFTRT if we know the sign bit is clear. | |
dafdd1c8 | 9946 | `make_compound_operation' will convert it to an ASHIFTRT for |
9947 | those machines (such as VAX) that don't have an LSHIFTRT. */ | |
f92430e0 | 9948 | if (code == ASHIFTRT |
9949 | && val_signbit_known_clear_p (shift_mode, | |
9950 | nonzero_bits (varop, shift_mode))) | |
ccfa01f5 | 9951 | code = LSHIFTRT; |
9952 | ||
7bb0bd01 | 9953 | if (((code == LSHIFTRT |
f179ee60 | 9954 | && HWI_COMPUTABLE_MODE_P (shift_mode) |
7bb0bd01 | 9955 | && !(nonzero_bits (varop, shift_mode) >> count)) |
9956 | || (code == ASHIFT | |
f179ee60 | 9957 | && HWI_COMPUTABLE_MODE_P (shift_mode) |
7bb0bd01 | 9958 | && !((nonzero_bits (varop, shift_mode) << count) |
9959 | & GET_MODE_MASK (shift_mode)))) | |
9960 | && !side_effects_p (varop)) | |
a1043dde | 9961 | varop = const0_rtx; |
38099b6a | 9962 | |
ccfa01f5 | 9963 | switch (GET_CODE (varop)) |
9964 | { | |
9965 | case SIGN_EXTEND: | |
9966 | case ZERO_EXTEND: | |
9967 | case SIGN_EXTRACT: | |
9968 | case ZERO_EXTRACT: | |
d328ebdf | 9969 | new_rtx = expand_compound_operation (varop); |
9970 | if (new_rtx != varop) | |
ccfa01f5 | 9971 | { |
d328ebdf | 9972 | varop = new_rtx; |
ccfa01f5 | 9973 | continue; |
9974 | } | |
9975 | break; | |
9976 | ||
9977 | case MEM: | |
9978 | /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH | |
9979 | minus the width of a smaller mode, we can do this with a | |
9980 | SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ | |
9981 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
4e27ffd0 | 9982 | && ! mode_dependent_address_p (XEXP (varop, 0), |
9983 | MEM_ADDR_SPACE (varop)) | |
ccfa01f5 | 9984 | && ! MEM_VOLATILE_P (varop) |
9985 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
9986 | MODE_INT, 1)) != BLKmode) | |
9987 | { | |
d328ebdf | 9988 | new_rtx = adjust_address_nv (varop, tmode, |
e4e86ec5 | 9989 | BYTES_BIG_ENDIAN ? 0 |
9990 | : count / BITS_PER_UNIT); | |
63c906ce | 9991 | |
3380b197 | 9992 | varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND |
d328ebdf | 9993 | : ZERO_EXTEND, mode, new_rtx); |
ccfa01f5 | 9994 | count = 0; |
9995 | continue; | |
9996 | } | |
9997 | break; | |
9998 | ||
ccfa01f5 | 9999 | case SUBREG: |
10000 | /* If VAROP is a SUBREG, strip it as long as the inner operand has | |
10001 | the same number of words as what we've seen so far. Then store | |
10002 | the widest mode in MODE. */ | |
0bd5060c | 10003 | if (subreg_lowpart_p (varop) |
10004 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) | |
10005 | > GET_MODE_SIZE (GET_MODE (varop))) | |
13883914 | 10006 | && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) |
10007 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
4ec7d822 | 10008 | == mode_words |
10009 | && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT | |
10010 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT) | |
ccfa01f5 | 10011 | { |
10012 | varop = SUBREG_REG (varop); | |
10013 | if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) | |
10014 | mode = GET_MODE (varop); | |
10015 | continue; | |
10016 | } | |
10017 | break; | |
10018 | ||
10019 | case MULT: | |
10020 | /* Some machines use MULT instead of ASHIFT because MULT | |
10021 | is cheaper. But it is still better on those machines to | |
10022 | merge two shifts into one. */ | |
971ba038 | 10023 | if (CONST_INT_P (XEXP (varop, 1)) |
897c6c81 | 10024 | && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0) |
ccfa01f5 | 10025 | { |
02e7a332 | 10026 | varop |
800a7def | 10027 | = simplify_gen_binary (ASHIFT, GET_MODE (varop), |
10028 | XEXP (varop, 0), | |
10029 | GEN_INT (exact_log2 ( | |
897c6c81 | 10030 | UINTVAL (XEXP (varop, 1))))); |
ccfa01f5 | 10031 | continue; |
10032 | } | |
10033 | break; | |
10034 | ||
10035 | case UDIV: | |
10036 | /* Similar, for when divides are cheaper. */ | |
971ba038 | 10037 | if (CONST_INT_P (XEXP (varop, 1)) |
897c6c81 | 10038 | && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0) |
ccfa01f5 | 10039 | { |
02e7a332 | 10040 | varop |
800a7def | 10041 | = simplify_gen_binary (LSHIFTRT, GET_MODE (varop), |
10042 | XEXP (varop, 0), | |
10043 | GEN_INT (exact_log2 ( | |
897c6c81 | 10044 | UINTVAL (XEXP (varop, 1))))); |
ccfa01f5 | 10045 | continue; |
10046 | } | |
10047 | break; | |
10048 | ||
10049 | case ASHIFTRT: | |
010eeb12 | 10050 | /* If we are extracting just the sign bit of an arithmetic |
10051 | right shift, that shift is not needed. However, the sign | |
10052 | bit of a wider mode may be different from what would be | |
10053 | interpreted as the sign bit in a narrower mode, so, if | |
10054 | the result is narrower, don't discard the shift. */ | |
13883914 | 10055 | if (code == LSHIFTRT |
1282ed8f | 10056 | && count == (GET_MODE_BITSIZE (result_mode) - 1) |
010eeb12 | 10057 | && (GET_MODE_BITSIZE (result_mode) |
10058 | >= GET_MODE_BITSIZE (GET_MODE (varop)))) | |
ccfa01f5 | 10059 | { |
10060 | varop = XEXP (varop, 0); | |
10061 | continue; | |
10062 | } | |
10063 | ||
a92771b8 | 10064 | /* ... fall through ... */ |
ccfa01f5 | 10065 | |
10066 | case LSHIFTRT: | |
10067 | case ASHIFT: | |
ccfa01f5 | 10068 | case ROTATE: |
10069 | /* Here we have two nested shifts. The result is usually the | |
10070 | AND of a new shift with a mask. We compute the result below. */ | |
971ba038 | 10071 | if (CONST_INT_P (XEXP (varop, 1)) |
ccfa01f5 | 10072 | && INTVAL (XEXP (varop, 1)) >= 0 |
ded805e6 | 10073 | && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop)) |
f179ee60 | 10074 | && HWI_COMPUTABLE_MODE_P (result_mode) |
10075 | && HWI_COMPUTABLE_MODE_P (mode) | |
ad4ecfda | 10076 | && !VECTOR_MODE_P (result_mode)) |
ccfa01f5 | 10077 | { |
10078 | enum rtx_code first_code = GET_CODE (varop); | |
02e7a332 | 10079 | unsigned int first_count = INTVAL (XEXP (varop, 1)); |
1bb04728 | 10080 | unsigned HOST_WIDE_INT mask; |
ccfa01f5 | 10081 | rtx mask_rtx; |
ccfa01f5 | 10082 | |
ccfa01f5 | 10083 | /* We have one common special case. We can't do any merging if |
10084 | the inner code is an ASHIFTRT of a smaller mode. However, if | |
10085 | we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) | |
10086 | with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), | |
10087 | we can convert it to | |
ded805e6 | 10088 | (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1). |
ccfa01f5 | 10089 | This simplifies certain SIGN_EXTEND operations. */ |
10090 | if (code == ASHIFT && first_code == ASHIFTRT | |
ded805e6 | 10091 | && count == (GET_MODE_PRECISION (result_mode) |
10092 | - GET_MODE_PRECISION (GET_MODE (varop)))) | |
ccfa01f5 | 10093 | { |
10094 | /* C3 has the low-order C1 bits zero. */ | |
510f7125 | 10095 | |
897c6c81 | 10096 | mask = GET_MODE_MASK (mode) |
10097 | & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1); | |
ccfa01f5 | 10098 | |
1bb04728 | 10099 | varop = simplify_and_const_int (NULL_RTX, result_mode, |
ccfa01f5 | 10100 | XEXP (varop, 0), mask); |
1bb04728 | 10101 | varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, |
ccfa01f5 | 10102 | varop, count); |
10103 | count = first_count; | |
10104 | code = ASHIFTRT; | |
10105 | continue; | |
10106 | } | |
510f7125 | 10107 | |
ec90760f | 10108 | /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more |
10109 | than C1 high-order bits equal to the sign bit, we can convert | |
dafdd1c8 | 10110 | this to either an ASHIFT or an ASHIFTRT depending on the |
510f7125 | 10111 | two counts. |
ccfa01f5 | 10112 | |
10113 | We cannot do this if VAROP's mode is not SHIFT_MODE. */ | |
10114 | ||
10115 | if (code == ASHIFTRT && first_code == ASHIFT | |
10116 | && GET_MODE (varop) == shift_mode | |
ec90760f | 10117 | && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) |
10118 | > first_count)) | |
ccfa01f5 | 10119 | { |
ec90760f | 10120 | varop = XEXP (varop, 0); |
1282ed8f | 10121 | count -= first_count; |
10122 | if (count < 0) | |
10123 | { | |
10124 | count = -count; | |
10125 | code = ASHIFT; | |
10126 | } | |
02e7a332 | 10127 | |
ec90760f | 10128 | continue; |
ccfa01f5 | 10129 | } |
10130 | ||
10131 | /* There are some cases we can't do. If CODE is ASHIFTRT, | |
10132 | we can only do this if FIRST_CODE is also ASHIFTRT. | |
10133 | ||
10134 | We can't do the case when CODE is ROTATE and FIRST_CODE is | |
10135 | ASHIFTRT. | |
10136 | ||
10137 | If the mode of this shift is not the mode of the outer shift, | |
d8b993a0 | 10138 | we can't do this if either shift is a right shift or ROTATE. |
ccfa01f5 | 10139 | |
10140 | Finally, we can't do any of these if the mode is too wide | |
10141 | unless the codes are the same. | |
10142 | ||
10143 | Handle the case where the shift codes are the same | |
10144 | first. */ | |
10145 | ||
10146 | if (code == first_code) | |
10147 | { | |
10148 | if (GET_MODE (varop) != result_mode | |
d8b993a0 | 10149 | && (code == ASHIFTRT || code == LSHIFTRT |
10150 | || code == ROTATE)) | |
ccfa01f5 | 10151 | break; |
10152 | ||
10153 | count += first_count; | |
10154 | varop = XEXP (varop, 0); | |
10155 | continue; | |
10156 | } | |
10157 | ||
10158 | if (code == ASHIFTRT | |
10159 | || (code == ROTATE && first_code == ASHIFTRT) | |
ded805e6 | 10160 | || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT |
ccfa01f5 | 10161 | || (GET_MODE (varop) != result_mode |
d8b993a0 | 10162 | && (first_code == ASHIFTRT || first_code == LSHIFTRT |
10163 | || first_code == ROTATE | |
ccfa01f5 | 10164 | || code == ROTATE))) |
10165 | break; | |
10166 | ||
10167 | /* To compute the mask to apply after the shift, shift the | |
510f7125 | 10168 | nonzero bits of the inner shift the same way the |
ccfa01f5 | 10169 | outer shift will. */ |
10170 | ||
5d5ee71f | 10171 | mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)), |
10172 | result_mode); | |
ccfa01f5 | 10173 | |
10174 | mask_rtx | |
1282ed8f | 10175 | = simplify_const_binary_operation (code, result_mode, mask_rtx, |
10176 | GEN_INT (count)); | |
510f7125 | 10177 | |
ccfa01f5 | 10178 | /* Give up if we can't compute an outer operation to use. */ |
10179 | if (mask_rtx == 0 | |
971ba038 | 10180 | || !CONST_INT_P (mask_rtx) |
ccfa01f5 | 10181 | || ! merge_outer_ops (&outer_op, &outer_const, AND, |
10182 | INTVAL (mask_rtx), | |
10183 | result_mode, &complement_p)) | |
10184 | break; | |
10185 | ||
10186 | /* If the shifts are in the same direction, we add the | |
10187 | counts. Otherwise, we subtract them. */ | |
10188 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
10189 | == (first_code == ASHIFTRT || first_code == LSHIFTRT)) | |
1282ed8f | 10190 | count += first_count; |
ccfa01f5 | 10191 | else |
1282ed8f | 10192 | count -= first_count; |
ccfa01f5 | 10193 | |
510f7125 | 10194 | /* If COUNT is positive, the new shift is usually CODE, |
ccfa01f5 | 10195 | except for the two exceptions below, in which case it is |
10196 | FIRST_CODE. If the count is negative, FIRST_CODE should | |
10197 | always be used */ | |
1282ed8f | 10198 | if (count > 0 |
ccfa01f5 | 10199 | && ((first_code == ROTATE && code == ASHIFT) |
10200 | || (first_code == ASHIFTRT && code == LSHIFTRT))) | |
1282ed8f | 10201 | code = first_code; |
10202 | else if (count < 0) | |
10203 | code = first_code, count = -count; | |
ccfa01f5 | 10204 | |
10205 | varop = XEXP (varop, 0); | |
10206 | continue; | |
10207 | } | |
10208 | ||
10209 | /* If we have (A << B << C) for any shift, we can convert this to | |
10210 | (A << C << B). This wins if A is a constant. Only try this if | |
10211 | B is not a constant. */ | |
10212 | ||
10213 | else if (GET_CODE (varop) == code | |
971ba038 | 10214 | && CONST_INT_P (XEXP (varop, 0)) |
10215 | && !CONST_INT_P (XEXP (varop, 1))) | |
ccfa01f5 | 10216 | { |
d328ebdf | 10217 | rtx new_rtx = simplify_const_binary_operation (code, mode, |
1282ed8f | 10218 | XEXP (varop, 0), |
10219 | GEN_INT (count)); | |
d328ebdf | 10220 | varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1)); |
ccfa01f5 | 10221 | count = 0; |
10222 | continue; | |
10223 | } | |
10224 | break; | |
10225 | ||
10226 | case NOT: | |
26573c33 | 10227 | if (VECTOR_MODE_P (mode)) |
10228 | break; | |
10229 | ||
ccfa01f5 | 10230 | /* Make this fit the case below. */ |
77b4556a | 10231 | varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx); |
ccfa01f5 | 10232 | continue; |
10233 | ||
10234 | case IOR: | |
10235 | case AND: | |
10236 | case XOR: | |
10237 | /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) | |
10238 | with C the size of VAROP - 1 and the shift is logical if | |
10239 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
10240 | we have an (le X 0) operation. If we have an arithmetic shift | |
10241 | and STORE_FLAG_VALUE is 1 or we have a logical shift with | |
10242 | STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ | |
10243 | ||
10244 | if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS | |
10245 | && XEXP (XEXP (varop, 0), 1) == constm1_rtx | |
10246 | && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
10247 | && (code == LSHIFTRT || code == ASHIFTRT) | |
ded805e6 | 10248 | && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1) |
ccfa01f5 | 10249 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) |
10250 | { | |
10251 | count = 0; | |
3380b197 | 10252 | varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), |
10253 | const0_rtx); | |
ccfa01f5 | 10254 | |
10255 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
3380b197 | 10256 | varop = gen_rtx_NEG (GET_MODE (varop), varop); |
ccfa01f5 | 10257 | |
10258 | continue; | |
10259 | } | |
10260 | ||
10261 | /* If we have (shift (logical)), move the logical to the outside | |
10262 | to allow it to possibly combine with another logical and the | |
10263 | shift to combine with another shift. This also canonicalizes to | |
10264 | what a ZERO_EXTRACT looks like. Also, some machines have | |
10265 | (and (shift)) insns. */ | |
10266 | ||
971ba038 | 10267 | if (CONST_INT_P (XEXP (varop, 1)) |
ea1ac559 | 10268 | /* We can't do this if we have (ashiftrt (xor)) and the |
8bf684df | 10269 | constant has its sign bit set in shift_mode with shift_mode |
10270 | wider than result_mode. */ | |
ea1ac559 | 10271 | && !(code == ASHIFTRT && GET_CODE (varop) == XOR |
8bf684df | 10272 | && result_mode != shift_mode |
ea1ac559 | 10273 | && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), |
10274 | shift_mode)) | |
5d5ee71f | 10275 | && (new_rtx = simplify_const_binary_operation |
10276 | (code, result_mode, | |
10277 | gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), | |
10278 | GEN_INT (count))) != 0 | |
971ba038 | 10279 | && CONST_INT_P (new_rtx) |
ccfa01f5 | 10280 | && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), |
d328ebdf | 10281 | INTVAL (new_rtx), result_mode, &complement_p)) |
ccfa01f5 | 10282 | { |
10283 | varop = XEXP (varop, 0); | |
10284 | continue; | |
10285 | } | |
10286 | ||
10287 | /* If we can't do that, try to simplify the shift in each arm of the | |
10288 | logical expression, make a new logical expression, and apply | |
8bf684df | 10289 | the inverse distributive law. This also can't be done for |
10290 | (ashiftrt (xor)) where we've widened the shift and the constant | |
10291 | changes the sign bit. */ | |
971ba038 | 10292 | if (CONST_INT_P (XEXP (varop, 1)) |
79277589 | 10293 | && !(code == ASHIFTRT && GET_CODE (varop) == XOR |
8bf684df | 10294 | && result_mode != shift_mode |
a0c938f0 | 10295 | && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), |
79277589 | 10296 | shift_mode))) |
ea1ac559 | 10297 | { |
10298 | rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, | |
10299 | XEXP (varop, 0), count); | |
10300 | rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, | |
10301 | XEXP (varop, 1), count); | |
ccfa01f5 | 10302 | |
800a7def | 10303 | varop = simplify_gen_binary (GET_CODE (varop), shift_mode, |
10304 | lhs, rhs); | |
ea1ac559 | 10305 | varop = apply_distributive_law (varop); |
ccfa01f5 | 10306 | |
ea1ac559 | 10307 | count = 0; |
a0c938f0 | 10308 | continue; |
ea1ac559 | 10309 | } |
ccfa01f5 | 10310 | break; |
10311 | ||
10312 | case EQ: | |
139c3f48 | 10313 | /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE |
ccfa01f5 | 10314 | says that the sign bit can be tested, FOO has mode MODE, C is |
ded805e6 | 10315 | GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit |
6503f782 | 10316 | that may be nonzero. */ |
10317 | if (code == LSHIFTRT | |
ccfa01f5 | 10318 | && XEXP (varop, 1) == const0_rtx |
10319 | && GET_MODE (XEXP (varop, 0)) == result_mode | |
ded805e6 | 10320 | && count == (GET_MODE_PRECISION (result_mode) - 1) |
f179ee60 | 10321 | && HWI_COMPUTABLE_MODE_P (result_mode) |
1282ed8f | 10322 | && STORE_FLAG_VALUE == -1 |
3d882a35 | 10323 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1 |
897c6c81 | 10324 | && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode, |
1bb04728 | 10325 | &complement_p)) |
ccfa01f5 | 10326 | { |
10327 | varop = XEXP (varop, 0); | |
10328 | count = 0; | |
10329 | continue; | |
10330 | } | |
10331 | break; | |
10332 | ||
10333 | case NEG: | |
ec90760f | 10334 | /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less |
10335 | than the number of bits in the mode is equivalent to A. */ | |
13883914 | 10336 | if (code == LSHIFTRT |
ded805e6 | 10337 | && count == (GET_MODE_PRECISION (result_mode) - 1) |
3d882a35 | 10338 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1) |
ccfa01f5 | 10339 | { |
ec90760f | 10340 | varop = XEXP (varop, 0); |
ccfa01f5 | 10341 | count = 0; |
10342 | continue; | |
10343 | } | |
10344 | ||
10345 | /* NEG commutes with ASHIFT since it is multiplication. Move the | |
10346 | NEG outside to allow shifts to combine. */ | |
10347 | if (code == ASHIFT | |
897c6c81 | 10348 | && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode, |
1bb04728 | 10349 | &complement_p)) |
ccfa01f5 | 10350 | { |
10351 | varop = XEXP (varop, 0); | |
10352 | continue; | |
10353 | } | |
10354 | break; | |
10355 | ||
10356 | case PLUS: | |
ec90760f | 10357 | /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C |
10358 | is one less than the number of bits in the mode is | |
10359 | equivalent to (xor A 1). */ | |
13883914 | 10360 | if (code == LSHIFTRT |
ded805e6 | 10361 | && count == (GET_MODE_PRECISION (result_mode) - 1) |
ccfa01f5 | 10362 | && XEXP (varop, 1) == constm1_rtx |
3d882a35 | 10363 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1 |
897c6c81 | 10364 | && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode, |
1bb04728 | 10365 | &complement_p)) |
ccfa01f5 | 10366 | { |
10367 | count = 0; | |
10368 | varop = XEXP (varop, 0); | |
10369 | continue; | |
10370 | } | |
10371 | ||
ded4a97a | 10372 | /* If we have (xshiftrt (plus FOO BAR) C), and the only bits |
3d882a35 | 10373 | that might be nonzero in BAR are those being shifted out and those |
ded4a97a | 10374 | bits are known zero in FOO, we can replace the PLUS with FOO. |
10375 | Similarly in the other operand order. This code occurs when | |
10376 | we are computing the size of a variable-size array. */ | |
10377 | ||
10378 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
1bb04728 | 10379 | && count < HOST_BITS_PER_WIDE_INT |
3d882a35 | 10380 | && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 |
10381 | && (nonzero_bits (XEXP (varop, 1), result_mode) | |
10382 | & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) | |
ded4a97a | 10383 | { |
10384 | varop = XEXP (varop, 0); | |
10385 | continue; | |
10386 | } | |
10387 | else if ((code == ASHIFTRT || code == LSHIFTRT) | |
1bb04728 | 10388 | && count < HOST_BITS_PER_WIDE_INT |
f179ee60 | 10389 | && HWI_COMPUTABLE_MODE_P (result_mode) |
3d882a35 | 10390 | && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) |
ded4a97a | 10391 | >> count) |
3d882a35 | 10392 | && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) |
10393 | & nonzero_bits (XEXP (varop, 1), | |
ded4a97a | 10394 | result_mode))) |
10395 | { | |
10396 | varop = XEXP (varop, 1); | |
10397 | continue; | |
10398 | } | |
10399 | ||
ccfa01f5 | 10400 | /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ |
10401 | if (code == ASHIFT | |
971ba038 | 10402 | && CONST_INT_P (XEXP (varop, 1)) |
b704209e | 10403 | && (new_rtx = simplify_const_binary_operation |
10404 | (ASHIFT, result_mode, | |
10405 | gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), | |
10406 | GEN_INT (count))) != 0 | |
971ba038 | 10407 | && CONST_INT_P (new_rtx) |
ccfa01f5 | 10408 | && merge_outer_ops (&outer_op, &outer_const, PLUS, |
d328ebdf | 10409 | INTVAL (new_rtx), result_mode, &complement_p)) |
ccfa01f5 | 10410 | { |
10411 | varop = XEXP (varop, 0); | |
10412 | continue; | |
10413 | } | |
0b4b6aaa | 10414 | |
10415 | /* Check for 'PLUS signbit', which is the canonical form of 'XOR | |
10416 | signbit', and attempt to change the PLUS to an XOR and move it to | |
10417 | the outer operation as is done above in the AND/IOR/XOR case | |
10418 | leg for shift(logical). See details in logical handling above | |
dac49aa5 | 10419 | for reasoning in doing so. */ |
0b4b6aaa | 10420 | if (code == LSHIFTRT |
971ba038 | 10421 | && CONST_INT_P (XEXP (varop, 1)) |
0b4b6aaa | 10422 | && mode_signbit_p (result_mode, XEXP (varop, 1)) |
b704209e | 10423 | && (new_rtx = simplify_const_binary_operation |
10424 | (code, result_mode, | |
10425 | gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), | |
10426 | GEN_INT (count))) != 0 | |
971ba038 | 10427 | && CONST_INT_P (new_rtx) |
0b4b6aaa | 10428 | && merge_outer_ops (&outer_op, &outer_const, XOR, |
d328ebdf | 10429 | INTVAL (new_rtx), result_mode, &complement_p)) |
0b4b6aaa | 10430 | { |
10431 | varop = XEXP (varop, 0); | |
10432 | continue; | |
10433 | } | |
10434 | ||
ccfa01f5 | 10435 | break; |
10436 | ||
10437 | case MINUS: | |
10438 | /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) | |
10439 | with C the size of VAROP - 1 and the shift is logical if | |
10440 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
10441 | we have a (gt X 0) operation. If the shift is arithmetic with | |
10442 | STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, | |
10443 | we have a (neg (gt X 0)) operation. */ | |
10444 | ||
7feddf73 | 10445 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
10446 | && GET_CODE (XEXP (varop, 0)) == ASHIFTRT | |
ded805e6 | 10447 | && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1) |
ccfa01f5 | 10448 | && (code == LSHIFTRT || code == ASHIFTRT) |
971ba038 | 10449 | && CONST_INT_P (XEXP (XEXP (varop, 0), 1)) |
1282ed8f | 10450 | && INTVAL (XEXP (XEXP (varop, 0), 1)) == count |
ccfa01f5 | 10451 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) |
10452 | { | |
10453 | count = 0; | |
3380b197 | 10454 | varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), |
10455 | const0_rtx); | |
ccfa01f5 | 10456 | |
10457 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
3380b197 | 10458 | varop = gen_rtx_NEG (GET_MODE (varop), varop); |
ccfa01f5 | 10459 | |
10460 | continue; | |
10461 | } | |
10462 | break; | |
1ecdc043 | 10463 | |
10464 | case TRUNCATE: | |
10465 | /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) | |
10466 | if the truncate does not affect the value. */ | |
10467 | if (code == LSHIFTRT | |
10468 | && GET_CODE (XEXP (varop, 0)) == LSHIFTRT | |
971ba038 | 10469 | && CONST_INT_P (XEXP (XEXP (varop, 0), 1)) |
1ecdc043 | 10470 | && (INTVAL (XEXP (XEXP (varop, 0), 1)) |
ded805e6 | 10471 | >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0))) |
10472 | - GET_MODE_PRECISION (GET_MODE (varop))))) | |
1ecdc043 | 10473 | { |
10474 | rtx varop_inner = XEXP (varop, 0); | |
10475 | ||
02e7a332 | 10476 | varop_inner |
3380b197 | 10477 | = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), |
10478 | XEXP (varop_inner, 0), | |
10479 | GEN_INT | |
10480 | (count + INTVAL (XEXP (varop_inner, 1)))); | |
10481 | varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); | |
1ecdc043 | 10482 | count = 0; |
10483 | continue; | |
10484 | } | |
10485 | break; | |
510f7125 | 10486 | |
0dbd1c74 | 10487 | default: |
10488 | break; | |
ccfa01f5 | 10489 | } |
10490 | ||
10491 | break; | |
10492 | } | |
10493 | ||
4e0ce2fb | 10494 | shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode, |
10495 | outer_op, outer_const); | |
ccfa01f5 | 10496 | |
10497 | /* We have now finished analyzing the shift. The result should be | |
10498 | a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If | |
21f1e711 | 10499 | OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied |
ccfa01f5 | 10500 | to the result of the shift. OUTER_CONST is the relevant constant, |
1282ed8f | 10501 | but we must turn off all bits turned off in the shift. */ |
ccfa01f5 | 10502 | |
1282ed8f | 10503 | if (outer_op == UNKNOWN |
10504 | && orig_code == code && orig_count == count | |
10505 | && varop == orig_varop | |
10506 | && shift_mode == GET_MODE (varop)) | |
10507 | return NULL_RTX; | |
ccfa01f5 | 10508 | |
1282ed8f | 10509 | /* Make a SUBREG if necessary. If we can't make it, fail. */ |
10510 | varop = gen_lowpart (shift_mode, varop); | |
10511 | if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) | |
10512 | return NULL_RTX; | |
ccfa01f5 | 10513 | |
98a1ef9c | 10514 | /* If we have an outer operation and we just made a shift, it is |
10515 | possible that we could have simplified the shift were it not | |
10516 | for the outer operation. So try to do the simplification | |
10517 | recursively. */ | |
10518 | ||
1282ed8f | 10519 | if (outer_op != UNKNOWN) |
10520 | x = simplify_shift_const_1 (code, shift_mode, varop, count); | |
10521 | else | |
10522 | x = NULL_RTX; | |
10523 | ||
10524 | if (x == NULL_RTX) | |
10525 | x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count)); | |
98a1ef9c | 10526 | |
dafdd1c8 | 10527 | /* If we were doing an LSHIFTRT in a wider mode than it was originally, |
ccfa01f5 | 10528 | turn off all the bits that the shift would have turned off. */ |
10529 | if (orig_code == LSHIFTRT && result_mode != shift_mode) | |
1bb04728 | 10530 | x = simplify_and_const_int (NULL_RTX, shift_mode, x, |
ccfa01f5 | 10531 | GET_MODE_MASK (result_mode) >> orig_count); |
510f7125 | 10532 | |
ccfa01f5 | 10533 | /* Do the remainder of the processing in RESULT_MODE. */ |
6b84145c | 10534 | x = gen_lowpart_or_truncate (result_mode, x); |
ccfa01f5 | 10535 | |
10536 | /* If COMPLEMENT_P is set, we have to complement X before doing the outer | |
10537 | operation. */ | |
10538 | if (complement_p) | |
77676a31 | 10539 | x = simplify_gen_unary (NOT, result_mode, x, result_mode); |
ccfa01f5 | 10540 | |
21f1e711 | 10541 | if (outer_op != UNKNOWN) |
ccfa01f5 | 10542 | { |
959aa063 | 10543 | if (GET_RTX_CLASS (outer_op) != RTX_UNARY |
ded805e6 | 10544 | && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT) |
b2345915 | 10545 | outer_const = trunc_int_for_mode (outer_const, result_mode); |
ccfa01f5 | 10546 | |
10547 | if (outer_op == AND) | |
1bb04728 | 10548 | x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); |
ccfa01f5 | 10549 | else if (outer_op == SET) |
7bb0bd01 | 10550 | { |
10551 | /* This means that we have determined that the result is | |
10552 | equivalent to a constant. This should be rare. */ | |
10553 | if (!side_effects_p (x)) | |
10554 | x = GEN_INT (outer_const); | |
10555 | } | |
6720e96c | 10556 | else if (GET_RTX_CLASS (outer_op) == RTX_UNARY) |
3380b197 | 10557 | x = simplify_gen_unary (outer_op, result_mode, x, result_mode); |
ccfa01f5 | 10558 | else |
800a7def | 10559 | x = simplify_gen_binary (outer_op, result_mode, x, |
10560 | GEN_INT (outer_const)); | |
ccfa01f5 | 10561 | } |
10562 | ||
10563 | return x; | |
510f7125 | 10564 | } |
1282ed8f | 10565 | |
10566 | /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. | |
10567 | The result of the shift is RESULT_MODE. If we cannot simplify it, | |
10568 | return X or, if it is NULL, synthesize the expression with | |
10569 | simplify_gen_binary. Otherwise, return a simplified value. | |
10570 | ||
10571 | The shift is normally computed in the widest mode we find in VAROP, as | |
10572 | long as it isn't a different number of words than RESULT_MODE. Exceptions | |
10573 | are ASHIFTRT and ROTATE, which are always done in their original mode. */ | |
10574 | ||
10575 | static rtx | |
10576 | simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode, | |
10577 | rtx varop, int count) | |
10578 | { | |
10579 | rtx tem = simplify_shift_const_1 (code, result_mode, varop, count); | |
10580 | if (tem) | |
10581 | return tem; | |
10582 | ||
10583 | if (!x) | |
10584 | x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count)); | |
10585 | if (GET_MODE (x) != result_mode) | |
10586 | x = gen_lowpart (result_mode, x); | |
10587 | return x; | |
10588 | } | |
10589 | ||
ccfa01f5 | 10590 | \f |
10591 | /* Like recog, but we receive the address of a pointer to a new pattern. | |
10592 | We try to match the rtx that the pointer points to. | |
10593 | If that fails, we may try to modify or replace the pattern, | |
10594 | storing the replacement into the same pointer object. | |
10595 | ||
10596 | Modifications include deletion or addition of CLOBBERs. | |
10597 | ||
10598 | PNOTES is a pointer to a location where any REG_UNUSED notes added for | |
10599 | the CLOBBERs are placed. | |
10600 | ||
10601 | The value is the final insn code from the pattern ultimately matched, | |
10602 | or -1. */ | |
10603 | ||
10604 | static int | |
35330d19 | 10605 | recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) |
ccfa01f5 | 10606 | { |
19cb6b50 | 10607 | rtx pat = *pnewpat; |
2a29bc01 | 10608 | rtx pat_without_clobbers; |
ccfa01f5 | 10609 | int insn_code_number; |
10610 | int num_clobbers_to_add = 0; | |
10611 | int i; | |
2a29bc01 | 10612 | rtx notes = NULL_RTX; |
7f518aaf | 10613 | rtx old_notes, old_pat; |
2a29bc01 | 10614 | int old_icode; |
ccfa01f5 | 10615 | |
804f49cd | 10616 | /* If PAT is a PARALLEL, check to see if it contains the CLOBBER |
10617 | we use to indicate that something didn't match. If we find such a | |
10618 | thing, force rejection. */ | |
8fec938c | 10619 | if (GET_CODE (pat) == PARALLEL) |
804f49cd | 10620 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) |
8fec938c | 10621 | if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER |
10622 | && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) | |
804f49cd | 10623 | return -1; |
10624 | ||
7f518aaf | 10625 | old_pat = PATTERN (insn); |
10626 | old_notes = REG_NOTES (insn); | |
10627 | PATTERN (insn) = pat; | |
2a29bc01 | 10628 | REG_NOTES (insn) = NULL_RTX; |
323f7906 | 10629 | |
7f518aaf | 10630 | insn_code_number = recog (pat, insn, &num_clobbers_to_add); |
0f975d00 | 10631 | if (dump_file && (dump_flags & TDF_DETAILS)) |
10632 | { | |
10633 | if (insn_code_number < 0) | |
10634 | fputs ("Failed to match this instruction:\n", dump_file); | |
10635 | else | |
10636 | fputs ("Successfully matched this instruction:\n", dump_file); | |
10637 | print_rtl_single (dump_file, pat); | |
10638 | } | |
ccfa01f5 | 10639 | |
10640 | /* If it isn't, there is the possibility that we previously had an insn | |
10641 | that clobbered some register as a side effect, but the combined | |
10642 | insn doesn't need to do that. So try once more without the clobbers | |
10643 | unless this represents an ASM insn. */ | |
10644 | ||
10645 | if (insn_code_number < 0 && ! check_asm_operands (pat) | |
10646 | && GET_CODE (pat) == PARALLEL) | |
10647 | { | |
10648 | int pos; | |
10649 | ||
10650 | for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) | |
10651 | if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) | |
10652 | { | |
10653 | if (i != pos) | |
10654 | SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); | |
10655 | pos++; | |
10656 | } | |
10657 | ||
10658 | SUBST_INT (XVECLEN (pat, 0), pos); | |
10659 | ||
10660 | if (pos == 1) | |
10661 | pat = XVECEXP (pat, 0, 0); | |
10662 | ||
7f518aaf | 10663 | PATTERN (insn) = pat; |
10664 | insn_code_number = recog (pat, insn, &num_clobbers_to_add); | |
0f975d00 | 10665 | if (dump_file && (dump_flags & TDF_DETAILS)) |
10666 | { | |
10667 | if (insn_code_number < 0) | |
10668 | fputs ("Failed to match this instruction:\n", dump_file); | |
10669 | else | |
10670 | fputs ("Successfully matched this instruction:\n", dump_file); | |
10671 | print_rtl_single (dump_file, pat); | |
10672 | } | |
ccfa01f5 | 10673 | } |
2a29bc01 | 10674 | |
10675 | pat_without_clobbers = pat; | |
10676 | ||
7f518aaf | 10677 | PATTERN (insn) = old_pat; |
10678 | REG_NOTES (insn) = old_notes; | |
ccfa01f5 | 10679 | |
1805c35c | 10680 | /* Recognize all noop sets, these will be killed by followup pass. */ |
10681 | if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) | |
10682 | insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; | |
10683 | ||
ccfa01f5 | 10684 | /* If we had any clobbers to add, make a new pattern than contains |
10685 | them. Then check to make sure that all of them are dead. */ | |
10686 | if (num_clobbers_to_add) | |
10687 | { | |
941522d6 | 10688 | rtx newpat = gen_rtx_PARALLEL (VOIDmode, |
7fbebc11 | 10689 | rtvec_alloc (GET_CODE (pat) == PARALLEL |
10690 | ? (XVECLEN (pat, 0) | |
10691 | + num_clobbers_to_add) | |
10692 | : num_clobbers_to_add + 1)); | |
ccfa01f5 | 10693 | |
10694 | if (GET_CODE (pat) == PARALLEL) | |
10695 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
10696 | XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); | |
10697 | else | |
10698 | XVECEXP (newpat, 0, 0) = pat; | |
10699 | ||
10700 | add_clobbers (newpat, insn_code_number); | |
10701 | ||
10702 | for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; | |
10703 | i < XVECLEN (newpat, 0); i++) | |
10704 | { | |
8ad4c111 | 10705 | if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)) |
ccfa01f5 | 10706 | && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) |
10707 | return -1; | |
48e1416a | 10708 | if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH) |
3072d30e | 10709 | { |
10710 | gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))); | |
5859ee98 | 10711 | notes = alloc_reg_note (REG_UNUSED, |
10712 | XEXP (XVECEXP (newpat, 0, i), 0), notes); | |
3072d30e | 10713 | } |
ccfa01f5 | 10714 | } |
10715 | pat = newpat; | |
10716 | } | |
10717 | ||
2a29bc01 | 10718 | if (insn_code_number >= 0 |
10719 | && insn_code_number != NOOP_MOVE_INSN_CODE) | |
10720 | { | |
10721 | old_pat = PATTERN (insn); | |
10722 | old_notes = REG_NOTES (insn); | |
10723 | old_icode = INSN_CODE (insn); | |
10724 | PATTERN (insn) = pat; | |
10725 | REG_NOTES (insn) = notes; | |
10726 | ||
10727 | /* Allow targets to reject combined insn. */ | |
10728 | if (!targetm.legitimate_combined_insn (insn)) | |
10729 | { | |
10730 | if (dump_file && (dump_flags & TDF_DETAILS)) | |
10731 | fputs ("Instruction not appropriate for target.", | |
10732 | dump_file); | |
10733 | ||
10734 | /* Callers expect recog_for_combine to strip | |
10735 | clobbers from the pattern on failure. */ | |
10736 | pat = pat_without_clobbers; | |
10737 | notes = NULL_RTX; | |
10738 | ||
10739 | insn_code_number = -1; | |
10740 | } | |
10741 | ||
10742 | PATTERN (insn) = old_pat; | |
10743 | REG_NOTES (insn) = old_notes; | |
10744 | INSN_CODE (insn) = old_icode; | |
10745 | } | |
10746 | ||
ccfa01f5 | 10747 | *pnewpat = pat; |
10748 | *pnotes = notes; | |
10749 | ||
10750 | return insn_code_number; | |
10751 | } | |
10752 | \f | |
316f48ea | 10753 | /* Like gen_lowpart_general but for use by combine. In combine it |
10754 | is not possible to create any new pseudoregs. However, it is | |
10755 | safe to create invalid memory addresses, because combine will | |
10756 | try to recognize them and all they will do is make the combine | |
10757 | attempt fail. | |
ccfa01f5 | 10758 | |
10759 | If for some reason this cannot do its job, an rtx | |
10760 | (clobber (const_int 0)) is returned. | |
10761 | An insn containing that will not be recognized. */ | |
10762 | ||
ccfa01f5 | 10763 | static rtx |
fec27df5 | 10764 | gen_lowpart_for_combine (enum machine_mode omode, rtx x) |
ccfa01f5 | 10765 | { |
fec27df5 | 10766 | enum machine_mode imode = GET_MODE (x); |
10767 | unsigned int osize = GET_MODE_SIZE (omode); | |
10768 | unsigned int isize = GET_MODE_SIZE (imode); | |
ccfa01f5 | 10769 | rtx result; |
10770 | ||
fec27df5 | 10771 | if (omode == imode) |
ccfa01f5 | 10772 | return x; |
10773 | ||
8e397331 | 10774 | /* We can only support MODE being wider than a word if X is a |
10775 | constant integer or has a mode the same size. */ | |
fec27df5 | 10776 | if (GET_MODE_SIZE (omode) > UNITS_PER_WORD |
efa08fc2 | 10777 | && ! (CONST_SCALAR_INT_P (x) || isize == osize)) |
fec27df5 | 10778 | goto fail; |
ccfa01f5 | 10779 | |
10780 | /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart | |
10781 | won't know what to do. So we will strip off the SUBREG here and | |
10782 | process normally. */ | |
e16ceb8e | 10783 | if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) |
ccfa01f5 | 10784 | { |
10785 | x = SUBREG_REG (x); | |
9c61a71b | 10786 | |
10787 | /* For use in case we fall down into the address adjustments | |
10788 | further below, we need to adjust the known mode and size of | |
10789 | x; imode and isize, since we just adjusted x. */ | |
10790 | imode = GET_MODE (x); | |
10791 | ||
10792 | if (imode == omode) | |
ccfa01f5 | 10793 | return x; |
9c61a71b | 10794 | |
10795 | isize = GET_MODE_SIZE (imode); | |
ccfa01f5 | 10796 | } |
10797 | ||
fec27df5 | 10798 | result = gen_lowpart_common (omode, x); |
10799 | ||
ccfa01f5 | 10800 | if (result) |
10801 | return result; | |
10802 | ||
e16ceb8e | 10803 | if (MEM_P (x)) |
ccfa01f5 | 10804 | { |
19cb6b50 | 10805 | int offset = 0; |
ccfa01f5 | 10806 | |
10807 | /* Refuse to work on a volatile memory ref or one with a mode-dependent | |
10808 | address. */ | |
4e27ffd0 | 10809 | if (MEM_VOLATILE_P (x) |
10810 | || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x))) | |
fec27df5 | 10811 | goto fail; |
ccfa01f5 | 10812 | |
10813 | /* If we want to refer to something bigger than the original memref, | |
5f3447b0 | 10814 | generate a paradoxical subreg instead. That will force a reload |
ccfa01f5 | 10815 | of the original memref X. */ |
fec27df5 | 10816 | if (isize < osize) |
10817 | return gen_rtx_SUBREG (omode, x, 0); | |
ccfa01f5 | 10818 | |
51356f86 | 10819 | if (WORDS_BIG_ENDIAN) |
fec27df5 | 10820 | offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD); |
7014838c | 10821 | |
f7f07c95 | 10822 | /* Adjust the address so that the address-after-the-data is |
10823 | unchanged. */ | |
51356f86 | 10824 | if (BYTES_BIG_ENDIAN) |
fec27df5 | 10825 | offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize); |
e4e86ec5 | 10826 | |
fec27df5 | 10827 | return adjust_address_nv (x, omode, offset); |
ccfa01f5 | 10828 | } |
10829 | ||
10830 | /* If X is a comparison operator, rewrite it in a new mode. This | |
10831 | probably won't match, but may allow further simplifications. */ | |
6720e96c | 10832 | else if (COMPARISON_P (x)) |
fec27df5 | 10833 | return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1)); |
ccfa01f5 | 10834 | |
10835 | /* If we couldn't simplify X any other way, just enclose it in a | |
10836 | SUBREG. Normally, this SUBREG won't match, but some patterns may | |
d976ad75 | 10837 | include an explicit SUBREG or we may simplify it further in combine. */ |
ccfa01f5 | 10838 | else |
9efc0f8e | 10839 | { |
701e46d0 | 10840 | int offset = 0; |
81802af6 | 10841 | rtx res; |
9efc0f8e | 10842 | |
fec27df5 | 10843 | offset = subreg_lowpart_offset (omode, imode); |
10844 | if (imode == VOIDmode) | |
621a189c | 10845 | { |
fec27df5 | 10846 | imode = int_mode_for_mode (omode); |
10847 | x = gen_lowpart_common (imode, x); | |
10848 | if (x == NULL) | |
10849 | goto fail; | |
621a189c | 10850 | } |
fec27df5 | 10851 | res = simplify_gen_subreg (omode, x, imode, offset); |
81802af6 | 10852 | if (res) |
10853 | return res; | |
9efc0f8e | 10854 | } |
fec27df5 | 10855 | |
10856 | fail: | |
ea138c98 | 10857 | return gen_rtx_CLOBBER (omode, const0_rtx); |
ccfa01f5 | 10858 | } |
10859 | \f | |
9a86832e | 10860 | /* Try to simplify a comparison between OP0 and a constant OP1, |
10861 | where CODE is the comparison code that will be tested, into a | |
10862 | (CODE OP0 const0_rtx) form. | |
10863 | ||
10864 | The result is a possibly different comparison code to use. | |
10865 | *POP1 may be updated. */ | |
10866 | ||
10867 | static enum rtx_code | |
9ec27261 | 10868 | simplify_compare_const (enum rtx_code code, enum machine_mode mode, |
10869 | rtx op0, rtx *pop1) | |
9a86832e | 10870 | { |
ded805e6 | 10871 | unsigned int mode_width = GET_MODE_PRECISION (mode); |
9a86832e | 10872 | HOST_WIDE_INT const_op = INTVAL (*pop1); |
10873 | ||
10874 | /* Get the constant we are comparing against and turn off all bits | |
10875 | not on in our mode. */ | |
10876 | if (mode != VOIDmode) | |
10877 | const_op = trunc_int_for_mode (const_op, mode); | |
10878 | ||
10879 | /* If we are comparing against a constant power of two and the value | |
10880 | being compared can only have that single bit nonzero (e.g., it was | |
10881 | `and'ed with that bit), we can replace this with a comparison | |
10882 | with zero. */ | |
10883 | if (const_op | |
10884 | && (code == EQ || code == NE || code == GE || code == GEU | |
10885 | || code == LT || code == LTU) | |
9ec27261 | 10886 | && mode_width - 1 < HOST_BITS_PER_WIDE_INT |
241f5399 | 10887 | && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0 |
10888 | && (nonzero_bits (op0, mode) | |
10889 | == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode)))) | |
9a86832e | 10890 | { |
10891 | code = (code == EQ || code == GE || code == GEU ? NE : EQ); | |
10892 | const_op = 0; | |
10893 | } | |
10894 | ||
10895 | /* Similarly, if we are comparing a value known to be either -1 or | |
10896 | 0 with -1, change it to the opposite comparison against zero. */ | |
10897 | if (const_op == -1 | |
10898 | && (code == EQ || code == NE || code == GT || code == LE | |
10899 | || code == GEU || code == LTU) | |
10900 | && num_sign_bit_copies (op0, mode) == mode_width) | |
10901 | { | |
10902 | code = (code == EQ || code == LE || code == GEU ? NE : EQ); | |
10903 | const_op = 0; | |
10904 | } | |
10905 | ||
10906 | /* Do some canonicalizations based on the comparison code. We prefer | |
10907 | comparisons against zero and then prefer equality comparisons. | |
10908 | If we can reduce the size of a constant, we will do that too. */ | |
10909 | switch (code) | |
10910 | { | |
10911 | case LT: | |
10912 | /* < C is equivalent to <= (C - 1) */ | |
10913 | if (const_op > 0) | |
10914 | { | |
10915 | const_op -= 1; | |
10916 | code = LE; | |
10917 | /* ... fall through to LE case below. */ | |
10918 | } | |
10919 | else | |
10920 | break; | |
10921 | ||
10922 | case LE: | |
10923 | /* <= C is equivalent to < (C + 1); we do this for C < 0 */ | |
10924 | if (const_op < 0) | |
10925 | { | |
10926 | const_op += 1; | |
10927 | code = LT; | |
10928 | } | |
10929 | ||
10930 | /* If we are doing a <= 0 comparison on a value known to have | |
10931 | a zero sign bit, we can replace this with == 0. */ | |
10932 | else if (const_op == 0 | |
9ec27261 | 10933 | && mode_width - 1 < HOST_BITS_PER_WIDE_INT |
9a86832e | 10934 | && (nonzero_bits (op0, mode) |
10935 | & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) | |
10936 | == 0) | |
10937 | code = EQ; | |
10938 | break; | |
10939 | ||
10940 | case GE: | |
10941 | /* >= C is equivalent to > (C - 1). */ | |
10942 | if (const_op > 0) | |
10943 | { | |
10944 | const_op -= 1; | |
10945 | code = GT; | |
10946 | /* ... fall through to GT below. */ | |
10947 | } | |
10948 | else | |
10949 | break; | |
10950 | ||
10951 | case GT: | |
10952 | /* > C is equivalent to >= (C + 1); we do this for C < 0. */ | |
10953 | if (const_op < 0) | |
10954 | { | |
10955 | const_op += 1; | |
10956 | code = GE; | |
10957 | } | |
10958 | ||
10959 | /* If we are doing a > 0 comparison on a value known to have | |
10960 | a zero sign bit, we can replace this with != 0. */ | |
10961 | else if (const_op == 0 | |
9ec27261 | 10962 | && mode_width - 1 < HOST_BITS_PER_WIDE_INT |
9a86832e | 10963 | && (nonzero_bits (op0, mode) |
10964 | & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) | |
10965 | == 0) | |
10966 | code = NE; | |
10967 | break; | |
10968 | ||
10969 | case LTU: | |
10970 | /* < C is equivalent to <= (C - 1). */ | |
10971 | if (const_op > 0) | |
10972 | { | |
10973 | const_op -= 1; | |
10974 | code = LEU; | |
10975 | /* ... fall through ... */ | |
10976 | } | |
10977 | /* (unsigned) < 0x80000000 is equivalent to >= 0. */ | |
9ec27261 | 10978 | else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT |
9a86832e | 10979 | && (unsigned HOST_WIDE_INT) const_op |
10980 | == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) | |
10981 | { | |
10982 | const_op = 0; | |
10983 | code = GE; | |
10984 | break; | |
10985 | } | |
10986 | else | |
10987 | break; | |
10988 | ||
10989 | case LEU: | |
10990 | /* unsigned <= 0 is equivalent to == 0 */ | |
10991 | if (const_op == 0) | |
10992 | code = EQ; | |
10993 | /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ | |
9ec27261 | 10994 | else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT |
9a86832e | 10995 | && (unsigned HOST_WIDE_INT) const_op |
10996 | == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1) | |
10997 | { | |
10998 | const_op = 0; | |
10999 | code = GE; | |
11000 | } | |
11001 | break; | |
11002 | ||
11003 | case GEU: | |
11004 | /* >= C is equivalent to > (C - 1). */ | |
11005 | if (const_op > 1) | |
11006 | { | |
11007 | const_op -= 1; | |
11008 | code = GTU; | |
11009 | /* ... fall through ... */ | |
11010 | } | |
11011 | ||
11012 | /* (unsigned) >= 0x80000000 is equivalent to < 0. */ | |
9ec27261 | 11013 | else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT |
9a86832e | 11014 | && (unsigned HOST_WIDE_INT) const_op |
11015 | == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) | |
11016 | { | |
11017 | const_op = 0; | |
11018 | code = LT; | |
11019 | break; | |
11020 | } | |
11021 | else | |
11022 | break; | |
11023 | ||
11024 | case GTU: | |
11025 | /* unsigned > 0 is equivalent to != 0 */ | |
11026 | if (const_op == 0) | |
11027 | code = NE; | |
11028 | /* (unsigned) > 0x7fffffff is equivalent to < 0. */ | |
9ec27261 | 11029 | else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT |
9a86832e | 11030 | && (unsigned HOST_WIDE_INT) const_op |
11031 | == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1) | |
11032 | { | |
11033 | const_op = 0; | |
11034 | code = LT; | |
11035 | } | |
11036 | break; | |
11037 | ||
11038 | default: | |
11039 | break; | |
11040 | } | |
11041 | ||
11042 | *pop1 = GEN_INT (const_op); | |
11043 | return code; | |
11044 | } | |
11045 | \f | |
ccfa01f5 | 11046 | /* Simplify a comparison between *POP0 and *POP1 where CODE is the |
11047 | comparison code that will be tested. | |
11048 | ||
11049 | The result is a possibly different comparison code to use. *POP0 and | |
11050 | *POP1 may be updated. | |
11051 | ||
11052 | It is possible that we might detect that a comparison is either always | |
11053 | true or always false. However, we do not perform general constant | |
88355298 | 11054 | folding in combine, so this knowledge isn't useful. Such tautologies |
ccfa01f5 | 11055 | should have been detected earlier. Hence we ignore all such cases. */ |
11056 | ||
11057 | static enum rtx_code | |
d598ad0d | 11058 | simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) |
ccfa01f5 | 11059 | { |
11060 | rtx op0 = *pop0; | |
11061 | rtx op1 = *pop1; | |
11062 | rtx tem, tem1; | |
11063 | int i; | |
11064 | enum machine_mode mode, tmode; | |
11065 | ||
11066 | /* Try a few ways of applying the same transformation to both operands. */ | |
11067 | while (1) | |
11068 | { | |
751dd1c5 | 11069 | #ifndef WORD_REGISTER_OPERATIONS |
11070 | /* The test below this one won't handle SIGN_EXTENDs on these machines, | |
11071 | so check specially. */ | |
11072 | if (code != GTU && code != GEU && code != LTU && code != LEU | |
11073 | && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT | |
11074 | && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
11075 | && GET_CODE (XEXP (op1, 0)) == ASHIFT | |
11076 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG | |
11077 | && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG | |
11078 | && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) | |
93db3f92 | 11079 | == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) |
971ba038 | 11080 | && CONST_INT_P (XEXP (op0, 1)) |
f9af8fcd | 11081 | && XEXP (op0, 1) == XEXP (op1, 1) |
11082 | && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
11083 | && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1) | |
751dd1c5 | 11084 | && (INTVAL (XEXP (op0, 1)) |
ded805e6 | 11085 | == (GET_MODE_PRECISION (GET_MODE (op0)) |
11086 | - (GET_MODE_PRECISION | |
751dd1c5 | 11087 | (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) |
11088 | { | |
11089 | op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); | |
11090 | op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); | |
11091 | } | |
11092 | #endif | |
11093 | ||
ccfa01f5 | 11094 | /* If both operands are the same constant shift, see if we can ignore the |
11095 | shift. We can if the shift is a rotate or if the bits shifted out of | |
3d882a35 | 11096 | this shift are known to be zero for both inputs and if the type of |
ccfa01f5 | 11097 | comparison is compatible with the shift. */ |
fb668ded | 11098 | if (GET_CODE (op0) == GET_CODE (op1) |
9af5ce0c | 11099 | && HWI_COMPUTABLE_MODE_P (GET_MODE (op0)) |
fb668ded | 11100 | && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) |
6503f782 | 11101 | || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) |
fb668ded | 11102 | && (code != GT && code != LT && code != GE && code != LE)) |
11103 | || (GET_CODE (op0) == ASHIFTRT | |
11104 | && (code != GTU && code != LTU | |
af618804 | 11105 | && code != GEU && code != LEU))) |
971ba038 | 11106 | && CONST_INT_P (XEXP (op0, 1)) |
fb668ded | 11107 | && INTVAL (XEXP (op0, 1)) >= 0 |
11108 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT | |
11109 | && XEXP (op0, 1) == XEXP (op1, 1)) | |
ccfa01f5 | 11110 | { |
11111 | enum machine_mode mode = GET_MODE (op0); | |
1bb04728 | 11112 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
ccfa01f5 | 11113 | int shift_count = INTVAL (XEXP (op0, 1)); |
11114 | ||
11115 | if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) | |
11116 | mask &= (mask >> shift_count) << shift_count; | |
6503f782 | 11117 | else if (GET_CODE (op0) == ASHIFT) |
ccfa01f5 | 11118 | mask = (mask & (mask << shift_count)) >> shift_count; |
11119 | ||
510f7125 | 11120 | if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 |
11121 | && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) | |
ccfa01f5 | 11122 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); |
11123 | else | |
11124 | break; | |
11125 | } | |
11126 | ||
11127 | /* If both operands are AND's of a paradoxical SUBREG by constant, the | |
11128 | SUBREGs are of the same mode, and, in both cases, the AND would | |
11129 | be redundant if the comparison was done in the narrower mode, | |
11130 | do the comparison in the narrower mode (e.g., we are AND'ing with 1 | |
3d882a35 | 11131 | and the operand's possibly nonzero bits are 0xffffff01; in that case |
11132 | if we only care about QImode, we don't need the AND). This case | |
11133 | occurs if the output mode of an scc insn is not SImode and | |
7995bb82 | 11134 | STORE_FLAG_VALUE == 1 (e.g., the 386). |
11135 | ||
11136 | Similarly, check for a case where the AND's are ZERO_EXTEND | |
11137 | operations from some narrower mode even though a SUBREG is not | |
11138 | present. */ | |
ccfa01f5 | 11139 | |
510f7125 | 11140 | else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND |
971ba038 | 11141 | && CONST_INT_P (XEXP (op0, 1)) |
11142 | && CONST_INT_P (XEXP (op1, 1))) | |
ccfa01f5 | 11143 | { |
7995bb82 | 11144 | rtx inner_op0 = XEXP (op0, 0); |
11145 | rtx inner_op1 = XEXP (op1, 0); | |
11146 | HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); | |
11147 | HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); | |
11148 | int changed = 0; | |
510f7125 | 11149 | |
b537bfdb | 11150 | if (paradoxical_subreg_p (inner_op0) |
11151 | && GET_CODE (inner_op1) == SUBREG | |
7995bb82 | 11152 | && (GET_MODE (SUBREG_REG (inner_op0)) |
11153 | == GET_MODE (SUBREG_REG (inner_op1))) | |
ded805e6 | 11154 | && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0))) |
7995bb82 | 11155 | <= HOST_BITS_PER_WIDE_INT) |
76b75367 | 11156 | && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), |
571fc94e | 11157 | GET_MODE (SUBREG_REG (inner_op0))))) |
76b75367 | 11158 | && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), |
11159 | GET_MODE (SUBREG_REG (inner_op1)))))) | |
7995bb82 | 11160 | { |
11161 | op0 = SUBREG_REG (inner_op0); | |
11162 | op1 = SUBREG_REG (inner_op1); | |
11163 | ||
11164 | /* The resulting comparison is always unsigned since we masked | |
a92771b8 | 11165 | off the original sign bit. */ |
7995bb82 | 11166 | code = unsigned_condition (code); |
11167 | ||
11168 | changed = 1; | |
11169 | } | |
ccfa01f5 | 11170 | |
7995bb82 | 11171 | else if (c0 == c1) |
11172 | for (tmode = GET_CLASS_NARROWEST_MODE | |
11173 | (GET_MODE_CLASS (GET_MODE (op0))); | |
11174 | tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) | |
274c11d8 | 11175 | if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) |
7995bb82 | 11176 | { |
316f48ea | 11177 | op0 = gen_lowpart (tmode, inner_op0); |
11178 | op1 = gen_lowpart (tmode, inner_op1); | |
4ab49f1a | 11179 | code = unsigned_condition (code); |
7995bb82 | 11180 | changed = 1; |
11181 | break; | |
11182 | } | |
11183 | ||
11184 | if (! changed) | |
11185 | break; | |
ccfa01f5 | 11186 | } |
751dd1c5 | 11187 | |
93db3f92 | 11188 | /* If both operands are NOT, we can strip off the outer operation |
11189 | and adjust the comparison code for swapped operands; similarly for | |
11190 | NEG, except that this must be an equality comparison. */ | |
11191 | else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) | |
11192 | || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG | |
11193 | && (code == EQ || code == NE))) | |
11194 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); | |
751dd1c5 | 11195 | |
ccfa01f5 | 11196 | else |
11197 | break; | |
11198 | } | |
510f7125 | 11199 | |
ccfa01f5 | 11200 | /* If the first operand is a constant, swap the operands and adjust the |
45895109 | 11201 | comparison code appropriately, but don't do this if the second operand |
11202 | is already a constant integer. */ | |
f5ef1390 | 11203 | if (swap_commutative_operands_p (op0, op1)) |
ccfa01f5 | 11204 | { |
11205 | tem = op0, op0 = op1, op1 = tem; | |
11206 | code = swap_condition (code); | |
11207 | } | |
11208 | ||
11209 | /* We now enter a loop during which we will try to simplify the comparison. | |
11210 | For the most part, we only are concerned with comparisons with zero, | |
11211 | but some things may really be comparisons with zero but not start | |
11212 | out looking that way. */ | |
11213 | ||
971ba038 | 11214 | while (CONST_INT_P (op1)) |
ccfa01f5 | 11215 | { |
11216 | enum machine_mode mode = GET_MODE (op0); | |
ded805e6 | 11217 | unsigned int mode_width = GET_MODE_PRECISION (mode); |
1bb04728 | 11218 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
ccfa01f5 | 11219 | int equality_comparison_p; |
11220 | int sign_bit_comparison_p; | |
11221 | int unsigned_comparison_p; | |
1bb04728 | 11222 | HOST_WIDE_INT const_op; |
ccfa01f5 | 11223 | |
11224 | /* We only want to handle integral modes. This catches VOIDmode, | |
11225 | CCmode, and the floating-point modes. An exception is that we | |
11226 | can handle VOIDmode if OP0 is a COMPARE or a comparison | |
11227 | operation. */ | |
11228 | ||
11229 | if (GET_MODE_CLASS (mode) != MODE_INT | |
11230 | && ! (mode == VOIDmode | |
6720e96c | 11231 | && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0)))) |
ccfa01f5 | 11232 | break; |
11233 | ||
9a86832e | 11234 | /* Try to simplify the compare to constant, possibly changing the |
11235 | comparison op, and/or changing op1 to zero. */ | |
9ec27261 | 11236 | code = simplify_compare_const (code, mode, op0, &op1); |
dd067362 | 11237 | const_op = INTVAL (op1); |
ccfa01f5 | 11238 | |
11239 | /* Compute some predicates to simplify code below. */ | |
11240 | ||
11241 | equality_comparison_p = (code == EQ || code == NE); | |
11242 | sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); | |
11243 | unsigned_comparison_p = (code == LTU || code == LEU || code == GTU | |
e53624d0 | 11244 | || code == GEU); |
ccfa01f5 | 11245 | |
390fc1d2 | 11246 | /* If this is a sign bit comparison and we can do arithmetic in |
11247 | MODE, say that we will only be needing the sign bit of OP0. */ | |
f179ee60 | 11248 | if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode)) |
390fc1d2 | 11249 | op0 = force_to_mode (op0, mode, |
897c6c81 | 11250 | (unsigned HOST_WIDE_INT) 1 |
ded805e6 | 11251 | << (GET_MODE_PRECISION (mode) - 1), |
b92e2e43 | 11252 | 0); |
390fc1d2 | 11253 | |
ccfa01f5 | 11254 | /* Now try cases based on the opcode of OP0. If none of the cases |
11255 | does a "continue", we exit this loop immediately after the | |
11256 | switch. */ | |
11257 | ||
11258 | switch (GET_CODE (op0)) | |
11259 | { | |
11260 | case ZERO_EXTRACT: | |
11261 | /* If we are extracting a single bit from a variable position in | |
11262 | a constant that has only a single bit set and are comparing it | |
510f7125 | 11263 | with zero, we can convert this into an equality comparison |
e2595aa1 | 11264 | between the position and the location of the single bit. */ |
0c4f797f | 11265 | /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might |
11266 | have already reduced the shift count modulo the word size. */ | |
11267 | if (!SHIFT_COUNT_TRUNCATED | |
971ba038 | 11268 | && CONST_INT_P (XEXP (op0, 0)) |
ccfa01f5 | 11269 | && XEXP (op0, 1) == const1_rtx |
11270 | && equality_comparison_p && const_op == 0 | |
897c6c81 | 11271 | && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0) |
ccfa01f5 | 11272 | { |
51356f86 | 11273 | if (BITS_BIG_ENDIAN) |
44ecf428 | 11274 | i = BITS_PER_WORD - 1 - i; |
ccfa01f5 | 11275 | |
11276 | op0 = XEXP (op0, 2); | |
1bb04728 | 11277 | op1 = GEN_INT (i); |
ccfa01f5 | 11278 | const_op = i; |
11279 | ||
11280 | /* Result is nonzero iff shift count is equal to I. */ | |
11281 | code = reverse_condition (code); | |
11282 | continue; | |
11283 | } | |
ccfa01f5 | 11284 | |
a92771b8 | 11285 | /* ... fall through ... */ |
ccfa01f5 | 11286 | |
11287 | case SIGN_EXTRACT: | |
11288 | tem = expand_compound_operation (op0); | |
11289 | if (tem != op0) | |
11290 | { | |
11291 | op0 = tem; | |
11292 | continue; | |
11293 | } | |
11294 | break; | |
11295 | ||
11296 | case NOT: | |
11297 | /* If testing for equality, we can take the NOT of the constant. */ | |
11298 | if (equality_comparison_p | |
11299 | && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) | |
11300 | { | |
11301 | op0 = XEXP (op0, 0); | |
11302 | op1 = tem; | |
11303 | continue; | |
11304 | } | |
11305 | ||
11306 | /* If just looking at the sign bit, reverse the sense of the | |
11307 | comparison. */ | |
11308 | if (sign_bit_comparison_p) | |
11309 | { | |
11310 | op0 = XEXP (op0, 0); | |
11311 | code = (code == GE ? LT : GE); | |
11312 | continue; | |
11313 | } | |
11314 | break; | |
11315 | ||
11316 | case NEG: | |
11317 | /* If testing for equality, we can take the NEG of the constant. */ | |
11318 | if (equality_comparison_p | |
11319 | && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) | |
11320 | { | |
11321 | op0 = XEXP (op0, 0); | |
11322 | op1 = tem; | |
11323 | continue; | |
11324 | } | |
11325 | ||
11326 | /* The remaining cases only apply to comparisons with zero. */ | |
11327 | if (const_op != 0) | |
11328 | break; | |
11329 | ||
11330 | /* When X is ABS or is known positive, | |
11331 | (neg X) is < 0 if and only if X != 0. */ | |
11332 | ||
11333 | if (sign_bit_comparison_p | |
11334 | && (GET_CODE (XEXP (op0, 0)) == ABS | |
1bb04728 | 11335 | || (mode_width <= HOST_BITS_PER_WIDE_INT |
3d882a35 | 11336 | && (nonzero_bits (XEXP (op0, 0), mode) |
897c6c81 | 11337 | & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) |
11338 | == 0))) | |
ccfa01f5 | 11339 | { |
11340 | op0 = XEXP (op0, 0); | |
11341 | code = (code == LT ? NE : EQ); | |
11342 | continue; | |
11343 | } | |
11344 | ||
fb7f101b | 11345 | /* If we have NEG of something whose two high-order bits are the |
a92771b8 | 11346 | same, we know that "(-a) < 0" is equivalent to "a > 0". */ |
fb7f101b | 11347 | if (num_sign_bit_copies (op0, mode) >= 2) |
ccfa01f5 | 11348 | { |
11349 | op0 = XEXP (op0, 0); | |
11350 | code = swap_condition (code); | |
11351 | continue; | |
11352 | } | |
11353 | break; | |
11354 | ||
11355 | case ROTATE: | |
11356 | /* If we are testing equality and our count is a constant, we | |
11357 | can perform the inverse operation on our RHS. */ | |
971ba038 | 11358 | if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1)) |
ccfa01f5 | 11359 | && (tem = simplify_binary_operation (ROTATERT, mode, |
11360 | op1, XEXP (op0, 1))) != 0) | |
11361 | { | |
11362 | op0 = XEXP (op0, 0); | |
11363 | op1 = tem; | |
11364 | continue; | |
11365 | } | |
11366 | ||
11367 | /* If we are doing a < 0 or >= 0 comparison, it means we are testing | |
11368 | a particular bit. Convert it to an AND of a constant of that | |
11369 | bit. This will be converted into a ZERO_EXTRACT. */ | |
11370 | if (const_op == 0 && sign_bit_comparison_p | |
971ba038 | 11371 | && CONST_INT_P (XEXP (op0, 1)) |
1bb04728 | 11372 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
ccfa01f5 | 11373 | { |
1bb04728 | 11374 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
897c6c81 | 11375 | ((unsigned HOST_WIDE_INT) 1 |
1bb04728 | 11376 | << (mode_width - 1 |
11377 | - INTVAL (XEXP (op0, 1))))); | |
ccfa01f5 | 11378 | code = (code == LT ? NE : EQ); |
11379 | continue; | |
11380 | } | |
11381 | ||
510f7125 | 11382 | /* Fall through. */ |
ccfa01f5 | 11383 | |
11384 | case ABS: | |
11385 | /* ABS is ignorable inside an equality comparison with zero. */ | |
11386 | if (const_op == 0 && equality_comparison_p) | |
11387 | { | |
11388 | op0 = XEXP (op0, 0); | |
11389 | continue; | |
11390 | } | |
11391 | break; | |
ccfa01f5 | 11392 | |
11393 | case SIGN_EXTEND: | |
71b0614d | 11394 | /* Can simplify (compare (zero/sign_extend FOO) CONST) to |
11395 | (compare FOO CONST) if CONST fits in FOO's mode and we | |
11396 | are either testing inequality or have an unsigned | |
11397 | comparison with ZERO_EXTEND or a signed comparison with | |
11398 | SIGN_EXTEND. But don't do it if we don't have a compare | |
11399 | insn of the given mode, since we'd have to revert it | |
11400 | later on, and then we wouldn't know whether to sign- or | |
11401 | zero-extend. */ | |
11402 | mode = GET_MODE (XEXP (op0, 0)); | |
49f816eb | 11403 | if (GET_MODE_CLASS (mode) == MODE_INT |
71b0614d | 11404 | && ! unsigned_comparison_p |
49f816eb | 11405 | && HWI_COMPUTABLE_MODE_P (mode) |
11406 | && trunc_int_for_mode (const_op, mode) == const_op | |
0d79facf | 11407 | && have_insn_for (COMPARE, mode)) |
ccfa01f5 | 11408 | { |
11409 | op0 = XEXP (op0, 0); | |
11410 | continue; | |
11411 | } | |
11412 | break; | |
11413 | ||
11414 | case SUBREG: | |
18f18e6c | 11415 | /* Check for the case where we are comparing A - C1 with C2, that is |
11416 | ||
11417 | (subreg:MODE (plus (A) (-C1))) op (C2) | |
11418 | ||
11419 | with C1 a constant, and try to lift the SUBREG, i.e. to do the | |
11420 | comparison in the wider mode. One of the following two conditions | |
11421 | must be true in order for this to be valid: | |
11422 | ||
11423 | 1. The mode extension results in the same bit pattern being added | |
11424 | on both sides and the comparison is equality or unsigned. As | |
11425 | C2 has been truncated to fit in MODE, the pattern can only be | |
11426 | all 0s or all 1s. | |
11427 | ||
11428 | 2. The mode extension results in the sign bit being copied on | |
11429 | each side. | |
11430 | ||
11431 | The difficulty here is that we have predicates for A but not for | |
11432 | (A - C1) so we need to check that C1 is within proper bounds so | |
11433 | as to perturbate A as little as possible. */ | |
4cd6ac21 | 11434 | |
11435 | if (mode_width <= HOST_BITS_PER_WIDE_INT | |
11436 | && subreg_lowpart_p (op0) | |
ded805e6 | 11437 | && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width |
4cd6ac21 | 11438 | && GET_CODE (SUBREG_REG (op0)) == PLUS |
971ba038 | 11439 | && CONST_INT_P (XEXP (SUBREG_REG (op0), 1))) |
4cd6ac21 | 11440 | { |
18f18e6c | 11441 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); |
11442 | rtx a = XEXP (SUBREG_REG (op0), 0); | |
11443 | HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1)); | |
11444 | ||
11445 | if ((c1 > 0 | |
a0c938f0 | 11446 | && (unsigned HOST_WIDE_INT) c1 |
18f18e6c | 11447 | < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1) |
11448 | && (equality_comparison_p || unsigned_comparison_p) | |
11449 | /* (A - C1) zero-extends if it is positive and sign-extends | |
11450 | if it is negative, C2 both zero- and sign-extends. */ | |
11451 | && ((0 == (nonzero_bits (a, inner_mode) | |
11452 | & ~GET_MODE_MASK (mode)) | |
11453 | && const_op >= 0) | |
11454 | /* (A - C1) sign-extends if it is positive and 1-extends | |
11455 | if it is negative, C2 both sign- and 1-extends. */ | |
11456 | || (num_sign_bit_copies (a, inner_mode) | |
ded805e6 | 11457 | > (unsigned int) (GET_MODE_PRECISION (inner_mode) |
18f18e6c | 11458 | - mode_width) |
11459 | && const_op < 0))) | |
11460 | || ((unsigned HOST_WIDE_INT) c1 | |
11461 | < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2) | |
11462 | /* (A - C1) always sign-extends, like C2. */ | |
11463 | && num_sign_bit_copies (a, inner_mode) | |
ded805e6 | 11464 | > (unsigned int) (GET_MODE_PRECISION (inner_mode) |
0b7333de | 11465 | - (mode_width - 1)))) |
18f18e6c | 11466 | { |
11467 | op0 = SUBREG_REG (op0); | |
11468 | continue; | |
a0c938f0 | 11469 | } |
4cd6ac21 | 11470 | } |
11471 | ||
d1394e9c | 11472 | /* If the inner mode is narrower and we are extracting the low part, |
11473 | we can treat the SUBREG as if it were a ZERO_EXTEND. */ | |
11474 | if (subreg_lowpart_p (op0) | |
ded805e6 | 11475 | && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width) |
52d73c1b | 11476 | /* Fall through */ ; |
11477 | else | |
ccfa01f5 | 11478 | break; |
11479 | ||
a92771b8 | 11480 | /* ... fall through ... */ |
ccfa01f5 | 11481 | |
11482 | case ZERO_EXTEND: | |
71b0614d | 11483 | mode = GET_MODE (XEXP (op0, 0)); |
49f816eb | 11484 | if (GET_MODE_CLASS (mode) == MODE_INT |
71b0614d | 11485 | && (unsigned_comparison_p || equality_comparison_p) |
f179ee60 | 11486 | && HWI_COMPUTABLE_MODE_P (mode) |
49f816eb | 11487 | && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode) |
11488 | && const_op >= 0 | |
0d79facf | 11489 | && have_insn_for (COMPARE, mode)) |
ccfa01f5 | 11490 | { |
11491 | op0 = XEXP (op0, 0); | |
11492 | continue; | |
11493 | } | |
11494 | break; | |
11495 | ||
11496 | case PLUS: | |
c38a291f | 11497 | /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do |
88355298 | 11498 | this for equality comparisons due to pathological cases involving |
ccfa01f5 | 11499 | overflows. */ |
c38a291f | 11500 | if (equality_comparison_p |
11501 | && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
11502 | op1, XEXP (op0, 1)))) | |
ccfa01f5 | 11503 | { |
11504 | op0 = XEXP (op0, 0); | |
11505 | op1 = tem; | |
11506 | continue; | |
11507 | } | |
11508 | ||
11509 | /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ | |
11510 | if (const_op == 0 && XEXP (op0, 1) == constm1_rtx | |
11511 | && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) | |
11512 | { | |
11513 | op0 = XEXP (XEXP (op0, 0), 0); | |
11514 | code = (code == LT ? EQ : NE); | |
11515 | continue; | |
11516 | } | |
11517 | break; | |
11518 | ||
11519 | case MINUS: | |
3d837249 | 11520 | /* We used to optimize signed comparisons against zero, but that |
11521 | was incorrect. Unsigned comparisons against zero (GTU, LEU) | |
11522 | arrive here as equality comparisons, or (GEU, LTU) are | |
11523 | optimized away. No need to special-case them. */ | |
f9b38ae9 | 11524 | |
c38a291f | 11525 | /* (eq (minus A B) C) -> (eq A (plus B C)) or |
11526 | (eq B (minus A C)), whichever simplifies. We can only do | |
11527 | this for equality comparisons due to pathological cases involving | |
11528 | overflows. */ | |
11529 | if (equality_comparison_p | |
11530 | && 0 != (tem = simplify_binary_operation (PLUS, mode, | |
11531 | XEXP (op0, 1), op1))) | |
11532 | { | |
11533 | op0 = XEXP (op0, 0); | |
11534 | op1 = tem; | |
11535 | continue; | |
11536 | } | |
11537 | ||
11538 | if (equality_comparison_p | |
11539 | && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
11540 | XEXP (op0, 0), op1))) | |
11541 | { | |
11542 | op0 = XEXP (op0, 1); | |
11543 | op1 = tem; | |
11544 | continue; | |
11545 | } | |
11546 | ||
ccfa01f5 | 11547 | /* The sign bit of (minus (ashiftrt X C) X), where C is the number |
11548 | of bits in X minus 1, is one iff X > 0. */ | |
11549 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT | |
971ba038 | 11550 | && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) |
897c6c81 | 11551 | && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 |
ccfa01f5 | 11552 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) |
11553 | { | |
11554 | op0 = XEXP (op0, 1); | |
11555 | code = (code == GE ? LE : GT); | |
11556 | continue; | |
11557 | } | |
11558 | break; | |
11559 | ||
11560 | case XOR: | |
11561 | /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification | |
11562 | if C is zero or B is a constant. */ | |
11563 | if (equality_comparison_p | |
11564 | && 0 != (tem = simplify_binary_operation (XOR, mode, | |
11565 | XEXP (op0, 1), op1))) | |
11566 | { | |
11567 | op0 = XEXP (op0, 0); | |
11568 | op1 = tem; | |
11569 | continue; | |
11570 | } | |
11571 | break; | |
11572 | ||
11573 | case EQ: case NE: | |
b467856b | 11574 | case UNEQ: case LTGT: |
11575 | case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: | |
11576 | case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: | |
a0c938f0 | 11577 | case UNORDERED: case ORDERED: |
ccfa01f5 | 11578 | /* We can't do anything if OP0 is a condition code value, rather |
11579 | than an actual data value. */ | |
11580 | if (const_op != 0 | |
a4589b78 | 11581 | || CC0_P (XEXP (op0, 0)) |
ccfa01f5 | 11582 | || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) |
11583 | break; | |
11584 | ||
11585 | /* Get the two operands being compared. */ | |
11586 | if (GET_CODE (XEXP (op0, 0)) == COMPARE) | |
11587 | tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); | |
11588 | else | |
11589 | tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); | |
11590 | ||
11591 | /* Check for the cases where we simply want the result of the | |
11592 | earlier test or the opposite of that result. */ | |
1b796f12 | 11593 | if (code == NE || code == EQ |
f92430e0 | 11594 | || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE) |
4d90f0b2 | 11595 | && (code == LT || code == GE))) |
ccfa01f5 | 11596 | { |
4d90f0b2 | 11597 | enum rtx_code new_code; |
11598 | if (code == LT || code == NE) | |
11599 | new_code = GET_CODE (op0); | |
11600 | else | |
0fc1e6fa | 11601 | new_code = reversed_comparison_code (op0, NULL); |
87e97de6 | 11602 | |
4d90f0b2 | 11603 | if (new_code != UNKNOWN) |
1b796f12 | 11604 | { |
4d90f0b2 | 11605 | code = new_code; |
11606 | op0 = tem; | |
11607 | op1 = tem1; | |
1b796f12 | 11608 | continue; |
11609 | } | |
ccfa01f5 | 11610 | } |
11611 | break; | |
11612 | ||
11613 | case IOR: | |
d10cfa8d | 11614 | /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero |
ccfa01f5 | 11615 | iff X <= 0. */ |
11616 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS | |
11617 | && XEXP (XEXP (op0, 0), 1) == constm1_rtx | |
11618 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) | |
11619 | { | |
11620 | op0 = XEXP (op0, 1); | |
11621 | code = (code == GE ? GT : LE); | |
11622 | continue; | |
11623 | } | |
11624 | break; | |
11625 | ||
11626 | case AND: | |
11627 | /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This | |
11628 | will be converted to a ZERO_EXTRACT later. */ | |
11629 | if (const_op == 0 && equality_comparison_p | |
6503f782 | 11630 | && GET_CODE (XEXP (op0, 0)) == ASHIFT |
ccfa01f5 | 11631 | && XEXP (XEXP (op0, 0), 0) == const1_rtx) |
11632 | { | |
897c6c81 | 11633 | op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1), |
11634 | XEXP (XEXP (op0, 0), 1)); | |
11635 | op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1); | |
ccfa01f5 | 11636 | continue; |
11637 | } | |
11638 | ||
11639 | /* If we are comparing (and (lshiftrt X C1) C2) for equality with | |
11640 | zero and X is a comparison and C1 and C2 describe only bits set | |
11641 | in STORE_FLAG_VALUE, we can compare with X. */ | |
11642 | if (const_op == 0 && equality_comparison_p | |
1bb04728 | 11643 | && mode_width <= HOST_BITS_PER_WIDE_INT |
971ba038 | 11644 | && CONST_INT_P (XEXP (op0, 1)) |
ccfa01f5 | 11645 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT |
971ba038 | 11646 | && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) |
ccfa01f5 | 11647 | && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 |
1bb04728 | 11648 | && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) |
ccfa01f5 | 11649 | { |
11650 | mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) | |
11651 | << INTVAL (XEXP (XEXP (op0, 0), 1))); | |
510f7125 | 11652 | if ((~STORE_FLAG_VALUE & mask) == 0 |
6720e96c | 11653 | && (COMPARISON_P (XEXP (XEXP (op0, 0), 0)) |
ccfa01f5 | 11654 | || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 |
6720e96c | 11655 | && COMPARISON_P (tem)))) |
ccfa01f5 | 11656 | { |
11657 | op0 = XEXP (XEXP (op0, 0), 0); | |
11658 | continue; | |
11659 | } | |
11660 | } | |
11661 | ||
11662 | /* If we are doing an equality comparison of an AND of a bit equal | |
11663 | to the sign bit, replace this with a LT or GE comparison of | |
11664 | the underlying value. */ | |
11665 | if (equality_comparison_p | |
11666 | && const_op == 0 | |
971ba038 | 11667 | && CONST_INT_P (XEXP (op0, 1)) |
1bb04728 | 11668 | && mode_width <= HOST_BITS_PER_WIDE_INT |
ccfa01f5 | 11669 | && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) |
274c11d8 | 11670 | == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) |
ccfa01f5 | 11671 | { |
11672 | op0 = XEXP (op0, 0); | |
11673 | code = (code == EQ ? GE : LT); | |
11674 | continue; | |
11675 | } | |
11676 | ||
11677 | /* If this AND operation is really a ZERO_EXTEND from a narrower | |
11678 | mode, the constant fits within that mode, and this is either an | |
11679 | equality or unsigned comparison, try to do this comparison in | |
6d329589 | 11680 | the narrower mode. |
11681 | ||
11682 | Note that in: | |
11683 | ||
11684 | (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0)) | |
11685 | -> (ne:DI (reg:SI 4) (const_int 0)) | |
11686 | ||
11687 | unless TRULY_NOOP_TRUNCATION allows it or the register is | |
11688 | known to hold a value of the required mode the | |
11689 | transformation is invalid. */ | |
ccfa01f5 | 11690 | if ((equality_comparison_p || unsigned_comparison_p) |
971ba038 | 11691 | && CONST_INT_P (XEXP (op0, 1)) |
897c6c81 | 11692 | && (i = exact_log2 ((UINTVAL (XEXP (op0, 1)) |
ccfa01f5 | 11693 | & GET_MODE_MASK (mode)) |
11694 | + 1)) >= 0 | |
11695 | && const_op >> i == 0 | |
6d329589 | 11696 | && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode |
396f2130 | 11697 | && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0)) |
6d329589 | 11698 | || (REG_P (XEXP (op0, 0)) |
11699 | && reg_truncated_to_mode (tmode, XEXP (op0, 0))))) | |
ccfa01f5 | 11700 | { |
316f48ea | 11701 | op0 = gen_lowpart (tmode, XEXP (op0, 0)); |
ccfa01f5 | 11702 | continue; |
11703 | } | |
997d68fe | 11704 | |
1269aca3 | 11705 | /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 |
11706 | fits in both M1 and M2 and the SUBREG is either paradoxical | |
11707 | or represents the low part, permute the SUBREG and the AND | |
11708 | and try again. */ | |
11709 | if (GET_CODE (XEXP (op0, 0)) == SUBREG) | |
11710 | { | |
11711 | unsigned HOST_WIDE_INT c1; | |
11712 | tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0))); | |
da052aaf | 11713 | /* Require an integral mode, to avoid creating something like |
11714 | (AND:SF ...). */ | |
1269aca3 | 11715 | if (SCALAR_INT_MODE_P (tmode) |
11716 | /* It is unsafe to commute the AND into the SUBREG if the | |
11717 | SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is | |
11718 | not defined. As originally written the upper bits | |
11719 | have a defined value due to the AND operation. | |
11720 | However, if we commute the AND inside the SUBREG then | |
11721 | they no longer have defined values and the meaning of | |
11722 | the code has been changed. */ | |
11723 | && (0 | |
9e042f31 | 11724 | #ifdef WORD_REGISTER_OPERATIONS |
ded805e6 | 11725 | || (mode_width > GET_MODE_PRECISION (tmode) |
1269aca3 | 11726 | && mode_width <= BITS_PER_WORD) |
9e042f31 | 11727 | #endif |
ded805e6 | 11728 | || (mode_width <= GET_MODE_PRECISION (tmode) |
1269aca3 | 11729 | && subreg_lowpart_p (XEXP (op0, 0)))) |
971ba038 | 11730 | && CONST_INT_P (XEXP (op0, 1)) |
1269aca3 | 11731 | && mode_width <= HOST_BITS_PER_WIDE_INT |
f179ee60 | 11732 | && HWI_COMPUTABLE_MODE_P (tmode) |
1269aca3 | 11733 | && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0 |
11734 | && (c1 & ~GET_MODE_MASK (tmode)) == 0 | |
11735 | && c1 != mask | |
11736 | && c1 != GET_MODE_MASK (tmode)) | |
11737 | { | |
800a7def | 11738 | op0 = simplify_gen_binary (AND, tmode, |
11739 | SUBREG_REG (XEXP (op0, 0)), | |
11740 | gen_int_mode (c1, tmode)); | |
316f48ea | 11741 | op0 = gen_lowpart (mode, op0); |
1269aca3 | 11742 | continue; |
11743 | } | |
997d68fe | 11744 | } |
11745 | ||
fd4f87f4 | 11746 | /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */ |
11747 | if (const_op == 0 && equality_comparison_p | |
11748 | && XEXP (op0, 1) == const1_rtx | |
11749 | && GET_CODE (XEXP (op0, 0)) == NOT) | |
11750 | { | |
897c6c81 | 11751 | op0 = simplify_and_const_int (NULL_RTX, mode, |
11752 | XEXP (XEXP (op0, 0), 0), 1); | |
fd4f87f4 | 11753 | code = (code == NE ? EQ : NE); |
11754 | continue; | |
11755 | } | |
11756 | ||
7a5f56a5 | 11757 | /* Convert (ne (and (lshiftrt (not X)) 1) 0) to |
6fd65b76 | 11758 | (eq (and (lshiftrt X) 1) 0). |
11759 | Also handle the case where (not X) is expressed using xor. */ | |
7a5f56a5 | 11760 | if (const_op == 0 && equality_comparison_p |
11761 | && XEXP (op0, 1) == const1_rtx | |
6fd65b76 | 11762 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT) |
7a5f56a5 | 11763 | { |
6fd65b76 | 11764 | rtx shift_op = XEXP (XEXP (op0, 0), 0); |
11765 | rtx shift_count = XEXP (XEXP (op0, 0), 1); | |
11766 | ||
11767 | if (GET_CODE (shift_op) == NOT | |
11768 | || (GET_CODE (shift_op) == XOR | |
971ba038 | 11769 | && CONST_INT_P (XEXP (shift_op, 1)) |
11770 | && CONST_INT_P (shift_count) | |
f179ee60 | 11771 | && HWI_COMPUTABLE_MODE_P (mode) |
897c6c81 | 11772 | && (UINTVAL (XEXP (shift_op, 1)) |
11773 | == (unsigned HOST_WIDE_INT) 1 | |
11774 | << INTVAL (shift_count)))) | |
6fd65b76 | 11775 | { |
897c6c81 | 11776 | op0 |
11777 | = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count); | |
11778 | op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1); | |
6fd65b76 | 11779 | code = (code == NE ? EQ : NE); |
11780 | continue; | |
11781 | } | |
7a5f56a5 | 11782 | } |
ccfa01f5 | 11783 | break; |
11784 | ||
11785 | case ASHIFT: | |
6503f782 | 11786 | /* If we have (compare (ashift FOO N) (const_int C)) and |
ccfa01f5 | 11787 | the high order N bits of FOO (N+1 if an inequality comparison) |
3d882a35 | 11788 | are known to be zero, we can do this by comparing FOO with C |
ccfa01f5 | 11789 | shifted right N bits so long as the low-order N bits of C are |
11790 | zero. */ | |
971ba038 | 11791 | if (CONST_INT_P (XEXP (op0, 1)) |
ccfa01f5 | 11792 | && INTVAL (XEXP (op0, 1)) >= 0 |
11793 | && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) | |
1bb04728 | 11794 | < HOST_BITS_PER_WIDE_INT) |
897c6c81 | 11795 | && (((unsigned HOST_WIDE_INT) const_op |
11796 | & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) | |
11797 | - 1)) == 0) | |
1bb04728 | 11798 | && mode_width <= HOST_BITS_PER_WIDE_INT |
3d882a35 | 11799 | && (nonzero_bits (XEXP (op0, 0), mode) |
510f7125 | 11800 | & ~(mask >> (INTVAL (XEXP (op0, 1)) |
11801 | + ! equality_comparison_p))) == 0) | |
ccfa01f5 | 11802 | { |
b176b045 | 11803 | /* We must perform a logical shift, not an arithmetic one, |
11804 | as we want the top N bits of C to be zero. */ | |
b911bf3d | 11805 | unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); |
510f7125 | 11806 | |
b176b045 | 11807 | temp >>= INTVAL (XEXP (op0, 1)); |
2d232d05 | 11808 | op1 = gen_int_mode (temp, mode); |
ccfa01f5 | 11809 | op0 = XEXP (op0, 0); |
11810 | continue; | |
11811 | } | |
11812 | ||
9efc0f8e | 11813 | /* If we are doing a sign bit comparison, it means we are testing |
ccfa01f5 | 11814 | a particular bit. Convert it to the appropriate AND. */ |
971ba038 | 11815 | if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1)) |
1bb04728 | 11816 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
ccfa01f5 | 11817 | { |
1bb04728 | 11818 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
897c6c81 | 11819 | ((unsigned HOST_WIDE_INT) 1 |
1bb04728 | 11820 | << (mode_width - 1 |
11821 | - INTVAL (XEXP (op0, 1))))); | |
ccfa01f5 | 11822 | code = (code == LT ? NE : EQ); |
11823 | continue; | |
11824 | } | |
9efc0f8e | 11825 | |
11826 | /* If this an equality comparison with zero and we are shifting | |
11827 | the low bit to the sign bit, we can convert this to an AND of the | |
11828 | low-order bit. */ | |
11829 | if (const_op == 0 && equality_comparison_p | |
971ba038 | 11830 | && CONST_INT_P (XEXP (op0, 1)) |
897c6c81 | 11831 | && UINTVAL (XEXP (op0, 1)) == mode_width - 1) |
9efc0f8e | 11832 | { |
897c6c81 | 11833 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1); |
9efc0f8e | 11834 | continue; |
11835 | } | |
ccfa01f5 | 11836 | break; |
11837 | ||
11838 | case ASHIFTRT: | |
ec90760f | 11839 | /* If this is an equality comparison with zero, we can do this |
11840 | as a logical shift, which might be much simpler. */ | |
11841 | if (equality_comparison_p && const_op == 0 | |
971ba038 | 11842 | && CONST_INT_P (XEXP (op0, 1))) |
ec90760f | 11843 | { |
11844 | op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, | |
11845 | XEXP (op0, 0), | |
11846 | INTVAL (XEXP (op0, 1))); | |
11847 | continue; | |
11848 | } | |
11849 | ||
ccfa01f5 | 11850 | /* If OP0 is a sign extension and CODE is not an unsigned comparison, |
11851 | do the comparison in a narrower mode. */ | |
11852 | if (! unsigned_comparison_p | |
971ba038 | 11853 | && CONST_INT_P (XEXP (op0, 1)) |
ccfa01f5 | 11854 | && GET_CODE (XEXP (op0, 0)) == ASHIFT |
11855 | && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
11856 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
f1183687 | 11857 | MODE_INT, 1)) != BLKmode |
c0fe441c | 11858 | && (((unsigned HOST_WIDE_INT) const_op |
11859 | + (GET_MODE_MASK (tmode) >> 1) + 1) | |
11860 | <= GET_MODE_MASK (tmode))) | |
ccfa01f5 | 11861 | { |
316f48ea | 11862 | op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0)); |
ccfa01f5 | 11863 | continue; |
11864 | } | |
11865 | ||
155b05dc | 11866 | /* Likewise if OP0 is a PLUS of a sign extension with a |
11867 | constant, which is usually represented with the PLUS | |
11868 | between the shifts. */ | |
11869 | if (! unsigned_comparison_p | |
971ba038 | 11870 | && CONST_INT_P (XEXP (op0, 1)) |
155b05dc | 11871 | && GET_CODE (XEXP (op0, 0)) == PLUS |
971ba038 | 11872 | && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) |
155b05dc | 11873 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT |
11874 | && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) | |
11875 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
11876 | MODE_INT, 1)) != BLKmode | |
c0fe441c | 11877 | && (((unsigned HOST_WIDE_INT) const_op |
11878 | + (GET_MODE_MASK (tmode) >> 1) + 1) | |
11879 | <= GET_MODE_MASK (tmode))) | |
155b05dc | 11880 | { |
11881 | rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); | |
11882 | rtx add_const = XEXP (XEXP (op0, 0), 1); | |
800a7def | 11883 | rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0), |
11884 | add_const, XEXP (op0, 1)); | |
155b05dc | 11885 | |
800a7def | 11886 | op0 = simplify_gen_binary (PLUS, tmode, |
11887 | gen_lowpart (tmode, inner), | |
11888 | new_const); | |
155b05dc | 11889 | continue; |
11890 | } | |
11891 | ||
a92771b8 | 11892 | /* ... fall through ... */ |
ccfa01f5 | 11893 | case LSHIFTRT: |
11894 | /* If we have (compare (xshiftrt FOO N) (const_int C)) and | |
3d882a35 | 11895 | the low order N bits of FOO are known to be zero, we can do this |
ccfa01f5 | 11896 | by comparing FOO with C shifted left N bits so long as no |
12f6bb18 | 11897 | overflow occurs. Even if the low order N bits of FOO aren't known |
11898 | to be zero, if the comparison is >= or < we can use the same | |
11899 | optimization and for > or <= by setting all the low | |
11900 | order N bits in the comparison constant. */ | |
971ba038 | 11901 | if (CONST_INT_P (XEXP (op0, 1)) |
12f6bb18 | 11902 | && INTVAL (XEXP (op0, 1)) > 0 |
1bb04728 | 11903 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT |
11904 | && mode_width <= HOST_BITS_PER_WIDE_INT | |
c0fe441c | 11905 | && (((unsigned HOST_WIDE_INT) const_op |
11906 | + (GET_CODE (op0) != LSHIFTRT | |
11907 | ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) | |
11908 | + 1) | |
11909 | : 0)) | |
11910 | <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) | |
ccfa01f5 | 11911 | { |
12f6bb18 | 11912 | unsigned HOST_WIDE_INT low_bits |
11913 | = (nonzero_bits (XEXP (op0, 0), mode) | |
11914 | & (((unsigned HOST_WIDE_INT) 1 | |
11915 | << INTVAL (XEXP (op0, 1))) - 1)); | |
11916 | if (low_bits == 0 || !equality_comparison_p) | |
11917 | { | |
11918 | /* If the shift was logical, then we must make the condition | |
11919 | unsigned. */ | |
11920 | if (GET_CODE (op0) == LSHIFTRT) | |
11921 | code = unsigned_condition (code); | |
11922 | ||
11923 | const_op <<= INTVAL (XEXP (op0, 1)); | |
11924 | if (low_bits != 0 | |
11925 | && (code == GT || code == GTU | |
11926 | || code == LE || code == LEU)) | |
11927 | const_op | |
11928 | |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1); | |
11929 | op1 = GEN_INT (const_op); | |
11930 | op0 = XEXP (op0, 0); | |
11931 | continue; | |
11932 | } | |
ccfa01f5 | 11933 | } |
11934 | ||
11935 | /* If we are using this shift to extract just the sign bit, we | |
11936 | can replace this with an LT or GE comparison. */ | |
11937 | if (const_op == 0 | |
11938 | && (equality_comparison_p || sign_bit_comparison_p) | |
971ba038 | 11939 | && CONST_INT_P (XEXP (op0, 1)) |
897c6c81 | 11940 | && UINTVAL (XEXP (op0, 1)) == mode_width - 1) |
ccfa01f5 | 11941 | { |
11942 | op0 = XEXP (op0, 0); | |
11943 | code = (code == NE || code == GT ? LT : GE); | |
11944 | continue; | |
11945 | } | |
11946 | break; | |
510f7125 | 11947 | |
0dbd1c74 | 11948 | default: |
11949 | break; | |
ccfa01f5 | 11950 | } |
11951 | ||
11952 | break; | |
11953 | } | |
11954 | ||
11955 | /* Now make any compound operations involved in this comparison. Then, | |
13a0a8d8 | 11956 | check for an outmost SUBREG on OP0 that is not doing anything or is |
295f9df5 | 11957 | paradoxical. The latter transformation must only be performed when |
11958 | it is known that the "extra" bits will be the same in op0 and op1 or | |
11959 | that they don't matter. There are three cases to consider: | |
11960 | ||
11961 | 1. SUBREG_REG (op0) is a register. In this case the bits are don't | |
11962 | care bits and we can assume they have any convenient value. So | |
11963 | making the transformation is safe. | |
11964 | ||
11965 | 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. | |
11966 | In this case the upper bits of op0 are undefined. We should not make | |
11967 | the simplification in that case as we do not know the contents of | |
11968 | those bits. | |
11969 | ||
11970 | 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not | |
21f1e711 | 11971 | UNKNOWN. In that case we know those bits are zeros or ones. We must |
295f9df5 | 11972 | also be sure that they are the same as the upper bits of op1. |
11973 | ||
11974 | We can never remove a SUBREG for a non-equality comparison because | |
11975 | the sign bit is in a different place in the underlying object. */ | |
ccfa01f5 | 11976 | |
11977 | op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); | |
11978 | op1 = make_compound_operation (op1, SET); | |
11979 | ||
11980 | if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) | |
11981 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
8e74bbdf | 11982 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT |
295f9df5 | 11983 | && (code == NE || code == EQ)) |
ccfa01f5 | 11984 | { |
b537bfdb | 11985 | if (paradoxical_subreg_p (op0)) |
295f9df5 | 11986 | { |
aa11e43e | 11987 | /* For paradoxical subregs, allow case 1 as above. Case 3 isn't |
11988 | implemented. */ | |
a0c938f0 | 11989 | if (REG_P (SUBREG_REG (op0))) |
aa11e43e | 11990 | { |
11991 | op0 = SUBREG_REG (op0); | |
316f48ea | 11992 | op1 = gen_lowpart (GET_MODE (op0), op1); |
aa11e43e | 11993 | } |
295f9df5 | 11994 | } |
ded805e6 | 11995 | else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) |
295f9df5 | 11996 | <= HOST_BITS_PER_WIDE_INT) |
11997 | && (nonzero_bits (SUBREG_REG (op0), | |
11998 | GET_MODE (SUBREG_REG (op0))) | |
11999 | & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
12000 | { | |
316f48ea | 12001 | tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1); |
ccfa01f5 | 12002 | |
295f9df5 | 12003 | if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) |
12004 | & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
12005 | op0 = SUBREG_REG (op0), op1 = tem; | |
12006 | } | |
12007 | } | |
ccfa01f5 | 12008 | |
12009 | /* We now do the opposite procedure: Some machines don't have compare | |
12010 | insns in all modes. If OP0's mode is an integer mode smaller than a | |
12011 | word and we can't do a compare in that mode, see if there is a larger | |
4cd6ac21 | 12012 | mode for which we can do the compare. There are a number of cases in |
12013 | which we can use the wider mode. */ | |
ccfa01f5 | 12014 | |
12015 | mode = GET_MODE (op0); | |
12016 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
12017 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
ad99e708 | 12018 | && ! have_insn_for (COMPARE, mode)) |
ccfa01f5 | 12019 | for (tmode = GET_MODE_WIDER_MODE (mode); |
f179ee60 | 12020 | (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode)); |
ccfa01f5 | 12021 | tmode = GET_MODE_WIDER_MODE (tmode)) |
ad99e708 | 12022 | if (have_insn_for (COMPARE, tmode)) |
ccfa01f5 | 12023 | { |
786f554f | 12024 | int zero_extended; |
12025 | ||
538fa3ee | 12026 | /* If this is a test for negative, we can make an explicit |
12027 | test of the sign bit. Test this first so we can use | |
12028 | a paradoxical subreg to extend OP0. */ | |
12029 | ||
12030 | if (op1 == const0_rtx && (code == LT || code == GE) | |
f179ee60 | 12031 | && HWI_COMPUTABLE_MODE_P (mode)) |
538fa3ee | 12032 | { |
5d5ee71f | 12033 | unsigned HOST_WIDE_INT sign |
12034 | = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1); | |
538fa3ee | 12035 | op0 = simplify_gen_binary (AND, tmode, |
12036 | gen_lowpart (tmode, op0), | |
a485453a | 12037 | gen_int_mode (sign, tmode)); |
538fa3ee | 12038 | code = (code == LT) ? NE : EQ; |
12039 | break; | |
12040 | } | |
12041 | ||
3d882a35 | 12042 | /* If the only nonzero bits in OP0 and OP1 are those in the |
4cd6ac21 | 12043 | narrower mode and this is an equality or unsigned comparison, |
12044 | we can use the wider mode. Similarly for sign-extended | |
7995bb82 | 12045 | values, in which case it is true for all comparisons. */ |
786f554f | 12046 | zero_extended = ((code == EQ || code == NE |
12047 | || code == GEU || code == GTU | |
12048 | || code == LEU || code == LTU) | |
12049 | && (nonzero_bits (op0, tmode) | |
12050 | & ~GET_MODE_MASK (mode)) == 0 | |
971ba038 | 12051 | && ((CONST_INT_P (op1) |
786f554f | 12052 | || (nonzero_bits (op1, tmode) |
12053 | & ~GET_MODE_MASK (mode)) == 0))); | |
12054 | ||
12055 | if (zero_extended | |
7995bb82 | 12056 | || ((num_sign_bit_copies (op0, tmode) |
ded805e6 | 12057 | > (unsigned int) (GET_MODE_PRECISION (tmode) |
12058 | - GET_MODE_PRECISION (mode))) | |
4cd6ac21 | 12059 | && (num_sign_bit_copies (op1, tmode) |
ded805e6 | 12060 | > (unsigned int) (GET_MODE_PRECISION (tmode) |
12061 | - GET_MODE_PRECISION (mode))))) | |
4cd6ac21 | 12062 | { |
155b05dc | 12063 | /* If OP0 is an AND and we don't have an AND in MODE either, |
12064 | make a new AND in the proper mode. */ | |
12065 | if (GET_CODE (op0) == AND | |
ad99e708 | 12066 | && !have_insn_for (AND, mode)) |
800a7def | 12067 | op0 = simplify_gen_binary (AND, tmode, |
12068 | gen_lowpart (tmode, | |
12069 | XEXP (op0, 0)), | |
12070 | gen_lowpart (tmode, | |
12071 | XEXP (op0, 1))); | |
538fa3ee | 12072 | else |
12073 | { | |
12074 | if (zero_extended) | |
12075 | { | |
12076 | op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode); | |
12077 | op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode); | |
12078 | } | |
12079 | else | |
12080 | { | |
12081 | op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode); | |
12082 | op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode); | |
12083 | } | |
12084 | break; | |
12085 | } | |
ccfa01f5 | 12086 | } |
ccfa01f5 | 12087 | } |
12088 | ||
90404b57 | 12089 | /* We may have changed the comparison operands. Re-canonicalize. */ |
12090 | if (swap_commutative_operands_p (op0, op1)) | |
12091 | { | |
12092 | tem = op0, op0 = op1, op1 = tem; | |
12093 | code = swap_condition (code); | |
12094 | } | |
12095 | ||
5160f383 | 12096 | /* If this machine only supports a subset of valid comparisons, see if we |
12097 | can convert an unsupported one into a supported one. */ | |
d5065e6e | 12098 | target_canonicalize_comparison (&code, &op0, &op1, 0); |
5160f383 | 12099 | |
ccfa01f5 | 12100 | *pop0 = op0; |
12101 | *pop1 = op1; | |
12102 | ||
12103 | return code; | |
12104 | } | |
12105 | \f | |
9c8b7028 | 12106 | /* Utility function for record_value_for_reg. Count number of |
12107 | rtxs in X. */ | |
12108 | static int | |
12109 | count_rtxs (rtx x) | |
12110 | { | |
12111 | enum rtx_code code = GET_CODE (x); | |
12112 | const char *fmt; | |
d34f4b40 | 12113 | int i, j, ret = 1; |
9c8b7028 | 12114 | |
7ceb0ab3 | 12115 | if (GET_RTX_CLASS (code) == RTX_BIN_ARITH |
12116 | || GET_RTX_CLASS (code) == RTX_COMM_ARITH) | |
9c8b7028 | 12117 | { |
12118 | rtx x0 = XEXP (x, 0); | |
12119 | rtx x1 = XEXP (x, 1); | |
12120 | ||
12121 | if (x0 == x1) | |
12122 | return 1 + 2 * count_rtxs (x0); | |
12123 | ||
7ceb0ab3 | 12124 | if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH |
12125 | || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH) | |
9c8b7028 | 12126 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) |
12127 | return 2 + 2 * count_rtxs (x0) | |
12128 | + count_rtxs (x == XEXP (x1, 0) | |
12129 | ? XEXP (x1, 1) : XEXP (x1, 0)); | |
12130 | ||
7ceb0ab3 | 12131 | if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH |
12132 | || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH) | |
9c8b7028 | 12133 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) |
12134 | return 2 + 2 * count_rtxs (x1) | |
12135 | + count_rtxs (x == XEXP (x0, 0) | |
12136 | ? XEXP (x0, 1) : XEXP (x0, 0)); | |
12137 | } | |
12138 | ||
12139 | fmt = GET_RTX_FORMAT (code); | |
12140 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
12141 | if (fmt[i] == 'e') | |
12142 | ret += count_rtxs (XEXP (x, i)); | |
d34f4b40 | 12143 | else if (fmt[i] == 'E') |
12144 | for (j = 0; j < XVECLEN (x, i); j++) | |
12145 | ret += count_rtxs (XVECEXP (x, i, j)); | |
9c8b7028 | 12146 | |
12147 | return ret; | |
12148 | } | |
12149 | \f | |
ccfa01f5 | 12150 | /* Utility function for following routine. Called when X is part of a value |
acac6d5d | 12151 | being stored into last_set_value. Sets last_set_table_tick |
ccfa01f5 | 12152 | for each register mentioned. Similar to mention_regs in cse.c */ |
12153 | ||
12154 | static void | |
d598ad0d | 12155 | update_table_tick (rtx x) |
ccfa01f5 | 12156 | { |
19cb6b50 | 12157 | enum rtx_code code = GET_CODE (x); |
12158 | const char *fmt = GET_RTX_FORMAT (code); | |
d34f4b40 | 12159 | int i, j; |
ccfa01f5 | 12160 | |
12161 | if (code == REG) | |
12162 | { | |
02e7a332 | 12163 | unsigned int regno = REGNO (x); |
a2c6f0b7 | 12164 | unsigned int endregno = END_REGNO (x); |
02e7a332 | 12165 | unsigned int r; |
ccfa01f5 | 12166 | |
02e7a332 | 12167 | for (r = regno; r < endregno; r++) |
7ed1bb71 | 12168 | { |
f1f41a6c | 12169 | reg_stat_type *rsp = ®_stat[r]; |
7ed1bb71 | 12170 | rsp->last_set_table_tick = label_tick; |
12171 | } | |
ccfa01f5 | 12172 | |
12173 | return; | |
12174 | } | |
510f7125 | 12175 | |
ccfa01f5 | 12176 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
ccfa01f5 | 12177 | if (fmt[i] == 'e') |
0defd243 | 12178 | { |
12179 | /* Check for identical subexpressions. If x contains | |
12180 | identical subexpression we only have to traverse one of | |
12181 | them. */ | |
6720e96c | 12182 | if (i == 0 && ARITHMETIC_P (x)) |
0defd243 | 12183 | { |
12184 | /* Note that at this point x1 has already been | |
12185 | processed. */ | |
12186 | rtx x0 = XEXP (x, 0); | |
12187 | rtx x1 = XEXP (x, 1); | |
12188 | ||
12189 | /* If x0 and x1 are identical then there is no need to | |
12190 | process x0. */ | |
12191 | if (x0 == x1) | |
12192 | break; | |
12193 | ||
12194 | /* If x0 is identical to a subexpression of x1 then while | |
12195 | processing x1, x0 has already been processed. Thus we | |
12196 | are done with x. */ | |
6720e96c | 12197 | if (ARITHMETIC_P (x1) |
0defd243 | 12198 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) |
12199 | break; | |
12200 | ||
12201 | /* If x1 is identical to a subexpression of x0 then we | |
12202 | still have to process the rest of x0. */ | |
6720e96c | 12203 | if (ARITHMETIC_P (x0) |
0defd243 | 12204 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) |
12205 | { | |
12206 | update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0)); | |
12207 | break; | |
12208 | } | |
12209 | } | |
f65c89fb | 12210 | |
0defd243 | 12211 | update_table_tick (XEXP (x, i)); |
12212 | } | |
d34f4b40 | 12213 | else if (fmt[i] == 'E') |
12214 | for (j = 0; j < XVECLEN (x, i); j++) | |
12215 | update_table_tick (XVECEXP (x, i, j)); | |
ccfa01f5 | 12216 | } |
12217 | ||
12218 | /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we | |
12219 | are saying that the register is clobbered and we no longer know its | |
acac6d5d | 12220 | value. If INSN is zero, don't update reg_stat[].last_set; this is |
12221 | only permitted with VALUE also zero and is used to invalidate the | |
12222 | register. */ | |
ccfa01f5 | 12223 | |
12224 | static void | |
35330d19 | 12225 | record_value_for_reg (rtx reg, rtx_insn *insn, rtx value) |
ccfa01f5 | 12226 | { |
02e7a332 | 12227 | unsigned int regno = REGNO (reg); |
a2c6f0b7 | 12228 | unsigned int endregno = END_REGNO (reg); |
02e7a332 | 12229 | unsigned int i; |
7ed1bb71 | 12230 | reg_stat_type *rsp; |
ccfa01f5 | 12231 | |
12232 | /* If VALUE contains REG and we have a previous value for REG, substitute | |
12233 | the previous value. */ | |
12234 | if (value && insn && reg_overlap_mentioned_p (reg, value)) | |
12235 | { | |
12236 | rtx tem; | |
12237 | ||
12238 | /* Set things up so get_last_value is allowed to see anything set up to | |
12239 | our insn. */ | |
3072d30e | 12240 | subst_low_luid = DF_INSN_LUID (insn); |
510f7125 | 12241 | tem = get_last_value (reg); |
ccfa01f5 | 12242 | |
155b05dc | 12243 | /* If TEM is simply a binary operation with two CLOBBERs as operands, |
12244 | it isn't going to be useful and will take a lot of time to process, | |
12245 | so just use the CLOBBER. */ | |
12246 | ||
ccfa01f5 | 12247 | if (tem) |
155b05dc | 12248 | { |
6720e96c | 12249 | if (ARITHMETIC_P (tem) |
155b05dc | 12250 | && GET_CODE (XEXP (tem, 0)) == CLOBBER |
12251 | && GET_CODE (XEXP (tem, 1)) == CLOBBER) | |
12252 | tem = XEXP (tem, 0); | |
9c8b7028 | 12253 | else if (count_occurrences (value, reg, 1) >= 2) |
12254 | { | |
12255 | /* If there are two or more occurrences of REG in VALUE, | |
12256 | prevent the value from growing too much. */ | |
12257 | if (count_rtxs (tem) > MAX_LAST_VALUE_RTL) | |
12258 | tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx); | |
12259 | } | |
155b05dc | 12260 | |
12261 | value = replace_rtx (copy_rtx (value), reg, tem); | |
12262 | } | |
ccfa01f5 | 12263 | } |
12264 | ||
12265 | /* For each register modified, show we don't know its value, that | |
e647dd3a | 12266 | we don't know about its bitwise content, that its value has been |
12267 | updated, and that we don't know the location of the death of the | |
12268 | register. */ | |
02e7a332 | 12269 | for (i = regno; i < endregno; i++) |
ccfa01f5 | 12270 | { |
f1f41a6c | 12271 | rsp = ®_stat[i]; |
7ed1bb71 | 12272 | |
ccfa01f5 | 12273 | if (insn) |
7ed1bb71 | 12274 | rsp->last_set = insn; |
02e7a332 | 12275 | |
7ed1bb71 | 12276 | rsp->last_set_value = 0; |
8458f4ca | 12277 | rsp->last_set_mode = VOIDmode; |
7ed1bb71 | 12278 | rsp->last_set_nonzero_bits = 0; |
12279 | rsp->last_set_sign_bit_copies = 0; | |
12280 | rsp->last_death = 0; | |
8458f4ca | 12281 | rsp->truncated_to_mode = VOIDmode; |
ccfa01f5 | 12282 | } |
12283 | ||
12284 | /* Mark registers that are being referenced in this value. */ | |
12285 | if (value) | |
12286 | update_table_tick (value); | |
12287 | ||
12288 | /* Now update the status of each register being set. | |
12289 | If someone is using this register in this block, set this register | |
12290 | to invalid since we will get confused between the two lives in this | |
12291 | basic block. This makes using this register always invalid. In cse, we | |
12292 | scan the table to invalidate all entries using this register, but this | |
12293 | is too much work for us. */ | |
12294 | ||
12295 | for (i = regno; i < endregno; i++) | |
12296 | { | |
f1f41a6c | 12297 | rsp = ®_stat[i]; |
7ed1bb71 | 12298 | rsp->last_set_label = label_tick; |
3072d30e | 12299 | if (!insn |
7ed1bb71 | 12300 | || (value && rsp->last_set_table_tick >= label_tick_ebb_start)) |
12301 | rsp->last_set_invalid = 1; | |
ccfa01f5 | 12302 | else |
7ed1bb71 | 12303 | rsp->last_set_invalid = 0; |
ccfa01f5 | 12304 | } |
12305 | ||
12306 | /* The value being assigned might refer to X (like in "x++;"). In that | |
12307 | case, we must replace it with (clobber (const_int 0)) to prevent | |
12308 | infinite loops. */ | |
f1f41a6c | 12309 | rsp = ®_stat[regno]; |
a8d7c2f9 | 12310 | if (value && !get_last_value_validate (&value, insn, label_tick, 0)) |
ccfa01f5 | 12311 | { |
12312 | value = copy_rtx (value); | |
a8d7c2f9 | 12313 | if (!get_last_value_validate (&value, insn, label_tick, 1)) |
ccfa01f5 | 12314 | value = 0; |
12315 | } | |
12316 | ||
e7731ac6 | 12317 | /* For the main register being modified, update the value, the mode, the |
12318 | nonzero bits, and the number of sign bit copies. */ | |
12319 | ||
7ed1bb71 | 12320 | rsp->last_set_value = value; |
ccfa01f5 | 12321 | |
e7731ac6 | 12322 | if (value) |
12323 | { | |
faecad48 | 12324 | enum machine_mode mode = GET_MODE (reg); |
3072d30e | 12325 | subst_low_luid = DF_INSN_LUID (insn); |
7ed1bb71 | 12326 | rsp->last_set_mode = mode; |
faecad48 | 12327 | if (GET_MODE_CLASS (mode) == MODE_INT |
f179ee60 | 12328 | && HWI_COMPUTABLE_MODE_P (mode)) |
faecad48 | 12329 | mode = nonzero_bits_mode; |
7ed1bb71 | 12330 | rsp->last_set_nonzero_bits = nonzero_bits (value, mode); |
12331 | rsp->last_set_sign_bit_copies | |
e7731ac6 | 12332 | = num_sign_bit_copies (value, GET_MODE (reg)); |
12333 | } | |
ccfa01f5 | 12334 | } |
12335 | ||
ccfa01f5 | 12336 | /* Called via note_stores from record_dead_and_set_regs to handle one |
ec8895d7 | 12337 | SET or CLOBBER in an insn. DATA is the instruction in which the |
12338 | set is occurring. */ | |
ccfa01f5 | 12339 | |
12340 | static void | |
81a410b1 | 12341 | record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data) |
ccfa01f5 | 12342 | { |
35330d19 | 12343 | rtx_insn *record_dead_insn = (rtx_insn *) data; |
ec8895d7 | 12344 | |
771d2960 | 12345 | if (GET_CODE (dest) == SUBREG) |
12346 | dest = SUBREG_REG (dest); | |
12347 | ||
549e9b78 | 12348 | if (!record_dead_insn) |
12349 | { | |
12350 | if (REG_P (dest)) | |
35330d19 | 12351 | record_value_for_reg (dest, NULL, NULL_RTX); |
549e9b78 | 12352 | return; |
12353 | } | |
12354 | ||
8ad4c111 | 12355 | if (REG_P (dest)) |
ccfa01f5 | 12356 | { |
12357 | /* If we are setting the whole register, we know its value. Otherwise | |
12358 | show that we don't know the value. We can handle SUBREG in | |
12359 | some cases. */ | |
12360 | if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) | |
12361 | record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); | |
12362 | else if (GET_CODE (setter) == SET | |
12363 | && GET_CODE (SET_DEST (setter)) == SUBREG | |
12364 | && SUBREG_REG (SET_DEST (setter)) == dest | |
ded805e6 | 12365 | && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD |
ccfa01f5 | 12366 | && subreg_lowpart_p (SET_DEST (setter))) |
ec90760f | 12367 | record_value_for_reg (dest, record_dead_insn, |
316f48ea | 12368 | gen_lowpart (GET_MODE (dest), |
ec90760f | 12369 | SET_SRC (setter))); |
ccfa01f5 | 12370 | else |
1bb04728 | 12371 | record_value_for_reg (dest, record_dead_insn, NULL_RTX); |
ccfa01f5 | 12372 | } |
e16ceb8e | 12373 | else if (MEM_P (dest) |
ccfa01f5 | 12374 | /* Ignore pushes, they clobber nothing. */ |
12375 | && ! push_operand (dest, GET_MODE (dest))) | |
3072d30e | 12376 | mem_last_set = DF_INSN_LUID (record_dead_insn); |
ccfa01f5 | 12377 | } |
12378 | ||
12379 | /* Update the records of when each REG was most recently set or killed | |
12380 | for the things done by INSN. This is the last thing done in processing | |
12381 | INSN in the combiner loop. | |
12382 | ||
acac6d5d | 12383 | We update reg_stat[], in particular fields last_set, last_set_value, |
12384 | last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, | |
12385 | last_death, and also the similar information mem_last_set (which insn | |
3072d30e | 12386 | most recently modified memory) and last_call_luid (which insn was the |
acac6d5d | 12387 | most recent subroutine call). */ |
ccfa01f5 | 12388 | |
12389 | static void | |
35330d19 | 12390 | record_dead_and_set_regs (rtx_insn *insn) |
ccfa01f5 | 12391 | { |
19cb6b50 | 12392 | rtx link; |
02e7a332 | 12393 | unsigned int i; |
e7731ac6 | 12394 | |
ccfa01f5 | 12395 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
12396 | { | |
0cae3b93 | 12397 | if (REG_NOTE_KIND (link) == REG_DEAD |
8ad4c111 | 12398 | && REG_P (XEXP (link, 0))) |
0cae3b93 | 12399 | { |
02e7a332 | 12400 | unsigned int regno = REGNO (XEXP (link, 0)); |
a2c6f0b7 | 12401 | unsigned int endregno = END_REGNO (XEXP (link, 0)); |
0cae3b93 | 12402 | |
12403 | for (i = regno; i < endregno; i++) | |
7ed1bb71 | 12404 | { |
12405 | reg_stat_type *rsp; | |
12406 | ||
f1f41a6c | 12407 | rsp = ®_stat[i]; |
7ed1bb71 | 12408 | rsp->last_death = insn; |
12409 | } | |
0cae3b93 | 12410 | } |
ccfa01f5 | 12411 | else if (REG_NOTE_KIND (link) == REG_INC) |
1bb04728 | 12412 | record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); |
ccfa01f5 | 12413 | } |
12414 | ||
6d7dc5b9 | 12415 | if (CALL_P (insn)) |
e7731ac6 | 12416 | { |
24ec6636 | 12417 | hard_reg_set_iterator hrsi; |
12418 | EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi) | |
12419 | { | |
12420 | reg_stat_type *rsp; | |
12421 | ||
f1f41a6c | 12422 | rsp = ®_stat[i]; |
24ec6636 | 12423 | rsp->last_set_invalid = 1; |
12424 | rsp->last_set = insn; | |
12425 | rsp->last_set_value = 0; | |
12426 | rsp->last_set_mode = VOIDmode; | |
12427 | rsp->last_set_nonzero_bits = 0; | |
12428 | rsp->last_set_sign_bit_copies = 0; | |
12429 | rsp->last_death = 0; | |
12430 | rsp->truncated_to_mode = VOIDmode; | |
12431 | } | |
e7731ac6 | 12432 | |
3072d30e | 12433 | last_call_luid = mem_last_set = DF_INSN_LUID (insn); |
35505ed4 | 12434 | |
549e9b78 | 12435 | /* We can't combine into a call pattern. Remember, though, that |
3072d30e | 12436 | the return value register is set at this LUID. We could |
549e9b78 | 12437 | still replace a register with the return value from the |
12438 | wrong subroutine call! */ | |
12439 | note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX); | |
e7731ac6 | 12440 | } |
549e9b78 | 12441 | else |
12442 | note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); | |
ccfa01f5 | 12443 | } |
1ea41dd2 | 12444 | |
1ea41dd2 | 12445 | /* If a SUBREG has the promoted bit set, it is in fact a property of the |
12446 | register present in the SUBREG, so for each such SUBREG go back and | |
12447 | adjust nonzero and sign bit information of the registers that are | |
12448 | known to have some zero/sign bits set. | |
12449 | ||
12450 | This is needed because when combine blows the SUBREGs away, the | |
12451 | information on zero/sign bits is lost and further combines can be | |
12452 | missed because of that. */ | |
12453 | ||
12454 | static void | |
35330d19 | 12455 | record_promoted_value (rtx_insn *insn, rtx subreg) |
1ea41dd2 | 12456 | { |
2a0877d8 | 12457 | struct insn_link *links; |
12458 | rtx set; | |
02e7a332 | 12459 | unsigned int regno = REGNO (SUBREG_REG (subreg)); |
1ea41dd2 | 12460 | enum machine_mode mode = GET_MODE (subreg); |
12461 | ||
ded805e6 | 12462 | if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT) |
1ea41dd2 | 12463 | return; |
12464 | ||
510f7125 | 12465 | for (links = LOG_LINKS (insn); links;) |
1ea41dd2 | 12466 | { |
7ed1bb71 | 12467 | reg_stat_type *rsp; |
12468 | ||
2a0877d8 | 12469 | insn = links->insn; |
1ea41dd2 | 12470 | set = single_set (insn); |
12471 | ||
8ad4c111 | 12472 | if (! set || !REG_P (SET_DEST (set)) |
1ea41dd2 | 12473 | || REGNO (SET_DEST (set)) != regno |
12474 | || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) | |
12475 | { | |
2a0877d8 | 12476 | links = links->next; |
1ea41dd2 | 12477 | continue; |
12478 | } | |
12479 | ||
f1f41a6c | 12480 | rsp = ®_stat[regno]; |
7ed1bb71 | 12481 | if (rsp->last_set == insn) |
510f7125 | 12482 | { |
e8629f9e | 12483 | if (SUBREG_PROMOTED_UNSIGNED_P (subreg)) |
7ed1bb71 | 12484 | rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode); |
510f7125 | 12485 | } |
1ea41dd2 | 12486 | |
8ad4c111 | 12487 | if (REG_P (SET_SRC (set))) |
1ea41dd2 | 12488 | { |
12489 | regno = REGNO (SET_SRC (set)); | |
12490 | links = LOG_LINKS (insn); | |
12491 | } | |
12492 | else | |
12493 | break; | |
12494 | } | |
12495 | } | |
12496 | ||
4c199243 | 12497 | /* Check if X, a register, is known to contain a value already |
12498 | truncated to MODE. In this case we can use a subreg to refer to | |
12499 | the truncated value even though in the generic case we would need | |
12500 | an explicit truncation. */ | |
12501 | ||
12502 | static bool | |
b7bf20db | 12503 | reg_truncated_to_mode (enum machine_mode mode, const_rtx x) |
4c199243 | 12504 | { |
f1f41a6c | 12505 | reg_stat_type *rsp = ®_stat[REGNO (x)]; |
7ed1bb71 | 12506 | enum machine_mode truncated = rsp->truncated_to_mode; |
4c199243 | 12507 | |
3072d30e | 12508 | if (truncated == 0 |
7ed1bb71 | 12509 | || rsp->truncation_label < label_tick_ebb_start) |
4c199243 | 12510 | return false; |
12511 | if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode)) | |
12512 | return true; | |
396f2130 | 12513 | if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated)) |
4c199243 | 12514 | return true; |
12515 | return false; | |
12516 | } | |
12517 | ||
7e5943a4 | 12518 | /* If X is a hard reg or a subreg record the mode that the register is |
12519 | accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able | |
12520 | to turn a truncate into a subreg using this information. Return true | |
12521 | if traversing X is complete. */ | |
1ea41dd2 | 12522 | |
7e5943a4 | 12523 | static bool |
12524 | record_truncated_value (rtx x) | |
1ea41dd2 | 12525 | { |
4c199243 | 12526 | enum machine_mode truncated_mode; |
7ed1bb71 | 12527 | reg_stat_type *rsp; |
a0c938f0 | 12528 | |
4c199243 | 12529 | if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))) |
12530 | { | |
12531 | enum machine_mode original_mode = GET_MODE (SUBREG_REG (x)); | |
12532 | truncated_mode = GET_MODE (x); | |
12533 | ||
12534 | if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode)) | |
7e5943a4 | 12535 | return true; |
4c199243 | 12536 | |
396f2130 | 12537 | if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode)) |
7e5943a4 | 12538 | return true; |
4c199243 | 12539 | |
12540 | x = SUBREG_REG (x); | |
12541 | } | |
334ec2d8 | 12542 | /* ??? For hard-regs we now record everything. We might be able to |
4c199243 | 12543 | optimize this using last_set_mode. */ |
12544 | else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
12545 | truncated_mode = GET_MODE (x); | |
12546 | else | |
7e5943a4 | 12547 | return false; |
4c199243 | 12548 | |
f1f41a6c | 12549 | rsp = ®_stat[REGNO (x)]; |
7ed1bb71 | 12550 | if (rsp->truncated_to_mode == 0 |
12551 | || rsp->truncation_label < label_tick_ebb_start | |
4c199243 | 12552 | || (GET_MODE_SIZE (truncated_mode) |
7ed1bb71 | 12553 | < GET_MODE_SIZE (rsp->truncated_to_mode))) |
4c199243 | 12554 | { |
7ed1bb71 | 12555 | rsp->truncated_to_mode = truncated_mode; |
12556 | rsp->truncation_label = label_tick; | |
4c199243 | 12557 | } |
d9a71d72 | 12558 | |
7e5943a4 | 12559 | return true; |
4c199243 | 12560 | } |
12561 | ||
d9a71d72 | 12562 | /* Callback for note_uses. Find hardregs and subregs of pseudos and |
12563 | the modes they are used in. This can help truning TRUNCATEs into | |
12564 | SUBREGs. */ | |
4c199243 | 12565 | |
12566 | static void | |
7e5943a4 | 12567 | record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED) |
4c199243 | 12568 | { |
7e5943a4 | 12569 | subrtx_var_iterator::array_type array; |
12570 | FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST) | |
12571 | if (record_truncated_value (*iter)) | |
12572 | iter.skip_subrtxes (); | |
d9a71d72 | 12573 | } |
4c199243 | 12574 | |
d9a71d72 | 12575 | /* Scan X for promoted SUBREGs. For each one found, |
12576 | note what it implies to the registers used in it. */ | |
12577 | ||
12578 | static void | |
35330d19 | 12579 | check_promoted_subreg (rtx_insn *insn, rtx x) |
d9a71d72 | 12580 | { |
12581 | if (GET_CODE (x) == SUBREG | |
12582 | && SUBREG_PROMOTED_VAR_P (x) | |
12583 | && REG_P (SUBREG_REG (x))) | |
12584 | record_promoted_value (insn, x); | |
1ea41dd2 | 12585 | else |
12586 | { | |
12587 | const char *format = GET_RTX_FORMAT (GET_CODE (x)); | |
12588 | int i, j; | |
12589 | ||
12590 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) | |
510f7125 | 12591 | switch (format[i]) |
1ea41dd2 | 12592 | { |
12593 | case 'e': | |
d9a71d72 | 12594 | check_promoted_subreg (insn, XEXP (x, i)); |
1ea41dd2 | 12595 | break; |
12596 | case 'V': | |
12597 | case 'E': | |
12598 | if (XVEC (x, i) != 0) | |
12599 | for (j = 0; j < XVECLEN (x, i); j++) | |
d9a71d72 | 12600 | check_promoted_subreg (insn, XVECEXP (x, i, j)); |
1ea41dd2 | 12601 | break; |
12602 | } | |
12603 | } | |
12604 | } | |
ccfa01f5 | 12605 | \f |
a8d7c2f9 | 12606 | /* Verify that all the registers and memory references mentioned in *LOC are |
12607 | still valid. *LOC was part of a value set in INSN when label_tick was | |
12608 | equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace | |
12609 | the invalid references with (clobber (const_int 0)) and return 1. This | |
12610 | replacement is useful because we often can get useful information about | |
12611 | the form of a value (e.g., if it was produced by a shift that always | |
12612 | produces -1 or 0) even though we don't know exactly what registers it | |
12613 | was produced from. */ | |
ccfa01f5 | 12614 | |
12615 | static int | |
35330d19 | 12616 | get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace) |
ccfa01f5 | 12617 | { |
12618 | rtx x = *loc; | |
d2ca078f | 12619 | const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); |
ccfa01f5 | 12620 | int len = GET_RTX_LENGTH (GET_CODE (x)); |
d34f4b40 | 12621 | int i, j; |
ccfa01f5 | 12622 | |
8ad4c111 | 12623 | if (REG_P (x)) |
ccfa01f5 | 12624 | { |
02e7a332 | 12625 | unsigned int regno = REGNO (x); |
a2c6f0b7 | 12626 | unsigned int endregno = END_REGNO (x); |
02e7a332 | 12627 | unsigned int j; |
ccfa01f5 | 12628 | |
12629 | for (j = regno; j < endregno; j++) | |
7ed1bb71 | 12630 | { |
f1f41a6c | 12631 | reg_stat_type *rsp = ®_stat[j]; |
7ed1bb71 | 12632 | if (rsp->last_set_invalid |
12633 | /* If this is a pseudo-register that was only set once and not | |
12634 | live at the beginning of the function, it is always valid. */ | |
12635 | || (! (regno >= FIRST_PSEUDO_REGISTER | |
12636 | && REG_N_SETS (regno) == 1 | |
12637 | && (!REGNO_REG_SET_P | |
34154e27 | 12638 | (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), |
12639 | regno))) | |
7ed1bb71 | 12640 | && rsp->last_set_label > tick)) |
ccfa01f5 | 12641 | { |
12642 | if (replace) | |
941522d6 | 12643 | *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
ccfa01f5 | 12644 | return replace; |
12645 | } | |
7ed1bb71 | 12646 | } |
ccfa01f5 | 12647 | |
12648 | return 1; | |
12649 | } | |
a8d7c2f9 | 12650 | /* If this is a memory reference, make sure that there were no stores after |
12651 | it that might have clobbered the value. We don't have alias info, so we | |
12652 | assume any store invalidates it. Moreover, we only have local UIDs, so | |
12653 | we also assume that there were stores in the intervening basic blocks. */ | |
b04fab2a | 12654 | else if (MEM_P (x) && !MEM_READONLY_P (x) |
a8d7c2f9 | 12655 | && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set)) |
5bc78114 | 12656 | { |
12657 | if (replace) | |
941522d6 | 12658 | *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
5bc78114 | 12659 | return replace; |
12660 | } | |
ccfa01f5 | 12661 | |
12662 | for (i = 0; i < len; i++) | |
0defd243 | 12663 | { |
12664 | if (fmt[i] == 'e') | |
12665 | { | |
12666 | /* Check for identical subexpressions. If x contains | |
12667 | identical subexpression we only have to traverse one of | |
12668 | them. */ | |
6720e96c | 12669 | if (i == 1 && ARITHMETIC_P (x)) |
0defd243 | 12670 | { |
12671 | /* Note that at this point x0 has already been checked | |
12672 | and found valid. */ | |
12673 | rtx x0 = XEXP (x, 0); | |
12674 | rtx x1 = XEXP (x, 1); | |
12675 | ||
12676 | /* If x0 and x1 are identical then x is also valid. */ | |
12677 | if (x0 == x1) | |
12678 | return 1; | |
12679 | ||
12680 | /* If x1 is identical to a subexpression of x0 then | |
12681 | while checking x0, x1 has already been checked. Thus | |
12682 | it is valid and so as x. */ | |
6720e96c | 12683 | if (ARITHMETIC_P (x0) |
0defd243 | 12684 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) |
12685 | return 1; | |
12686 | ||
12687 | /* If x0 is identical to a subexpression of x1 then x is | |
12688 | valid iff the rest of x1 is valid. */ | |
6720e96c | 12689 | if (ARITHMETIC_P (x1) |
0defd243 | 12690 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) |
12691 | return | |
12692 | get_last_value_validate (&XEXP (x1, | |
12693 | x0 == XEXP (x1, 0) ? 1 : 0), | |
12694 | insn, tick, replace); | |
12695 | } | |
12696 | ||
12697 | if (get_last_value_validate (&XEXP (x, i), insn, tick, | |
12698 | replace) == 0) | |
12699 | return 0; | |
12700 | } | |
0defd243 | 12701 | else if (fmt[i] == 'E') |
d34f4b40 | 12702 | for (j = 0; j < XVECLEN (x, i); j++) |
12703 | if (get_last_value_validate (&XVECEXP (x, i, j), | |
12704 | insn, tick, replace) == 0) | |
12705 | return 0; | |
0defd243 | 12706 | } |
ccfa01f5 | 12707 | |
12708 | /* If we haven't found a reason for it to be invalid, it is valid. */ | |
12709 | return 1; | |
12710 | } | |
12711 | ||
12712 | /* Get the last value assigned to X, if known. Some registers | |
12713 | in the value may be replaced with (clobber (const_int 0)) if their value | |
12714 | is known longer known reliably. */ | |
12715 | ||
12716 | static rtx | |
b7bf20db | 12717 | get_last_value (const_rtx x) |
ccfa01f5 | 12718 | { |
02e7a332 | 12719 | unsigned int regno; |
ccfa01f5 | 12720 | rtx value; |
7ed1bb71 | 12721 | reg_stat_type *rsp; |
ccfa01f5 | 12722 | |
12723 | /* If this is a non-paradoxical SUBREG, get the value of its operand and | |
12724 | then convert it to the desired mode. If this is a paradoxical SUBREG, | |
a92771b8 | 12725 | we cannot predict what values the "extra" bits might have. */ |
ccfa01f5 | 12726 | if (GET_CODE (x) == SUBREG |
12727 | && subreg_lowpart_p (x) | |
b537bfdb | 12728 | && !paradoxical_subreg_p (x) |
ccfa01f5 | 12729 | && (value = get_last_value (SUBREG_REG (x))) != 0) |
316f48ea | 12730 | return gen_lowpart (GET_MODE (x), value); |
ccfa01f5 | 12731 | |
8ad4c111 | 12732 | if (!REG_P (x)) |
ccfa01f5 | 12733 | return 0; |
12734 | ||
12735 | regno = REGNO (x); | |
f1f41a6c | 12736 | rsp = ®_stat[regno]; |
7ed1bb71 | 12737 | value = rsp->last_set_value; |
ccfa01f5 | 12738 | |
5826468d | 12739 | /* If we don't have a value, or if it isn't for this basic block and |
12740 | it's either a hard register, set more than once, or it's a live | |
510f7125 | 12741 | at the beginning of the function, return 0. |
5826468d | 12742 | |
4a82352a | 12743 | Because if it's not live at the beginning of the function then the reg |
5826468d | 12744 | is always set before being used (is never used without being set). |
12745 | And, if it's set only once, and it's always set before use, then all | |
12746 | uses must have the same last value, even if it's not from this basic | |
12747 | block. */ | |
ccfa01f5 | 12748 | |
12749 | if (value == 0 | |
7ed1bb71 | 12750 | || (rsp->last_set_label < label_tick_ebb_start |
5826468d | 12751 | && (regno < FIRST_PSEUDO_REGISTER |
12752 | || REG_N_SETS (regno) != 1 | |
3072d30e | 12753 | || REGNO_REG_SET_P |
34154e27 | 12754 | (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno)))) |
ccfa01f5 | 12755 | return 0; |
12756 | ||
0ee47665 | 12757 | /* If the value was set in a later insn than the ones we are processing, |
393cac3b | 12758 | we can't use it even if the register was only set once. */ |
7ed1bb71 | 12759 | if (rsp->last_set_label == label_tick |
12760 | && DF_INSN_LUID (rsp->last_set) >= subst_low_luid) | |
393cac3b | 12761 | return 0; |
ec90760f | 12762 | |
12763 | /* If the value has all its registers valid, return it. */ | |
a8d7c2f9 | 12764 | if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0)) |
ccfa01f5 | 12765 | return value; |
12766 | ||
12767 | /* Otherwise, make a copy and replace any invalid register with | |
12768 | (clobber (const_int 0)). If that fails for some reason, return 0. */ | |
12769 | ||
12770 | value = copy_rtx (value); | |
a8d7c2f9 | 12771 | if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1)) |
ccfa01f5 | 12772 | return value; |
12773 | ||
12774 | return 0; | |
12775 | } | |
12776 | \f | |
12777 | /* Return nonzero if expression X refers to a REG or to memory | |
3072d30e | 12778 | that is set in an instruction more recent than FROM_LUID. */ |
ccfa01f5 | 12779 | |
12780 | static int | |
81a410b1 | 12781 | use_crosses_set_p (const_rtx x, int from_luid) |
ccfa01f5 | 12782 | { |
19cb6b50 | 12783 | const char *fmt; |
12784 | int i; | |
12785 | enum rtx_code code = GET_CODE (x); | |
ccfa01f5 | 12786 | |
12787 | if (code == REG) | |
12788 | { | |
02e7a332 | 12789 | unsigned int regno = REGNO (x); |
a2c6f0b7 | 12790 | unsigned endreg = END_REGNO (x); |
510f7125 | 12791 | |
ccfa01f5 | 12792 | #ifdef PUSH_ROUNDING |
12793 | /* Don't allow uses of the stack pointer to be moved, | |
12794 | because we don't know whether the move crosses a push insn. */ | |
4448f543 | 12795 | if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) |
ccfa01f5 | 12796 | return 1; |
12797 | #endif | |
02e7a332 | 12798 | for (; regno < endreg; regno++) |
7ed1bb71 | 12799 | { |
f1f41a6c | 12800 | reg_stat_type *rsp = ®_stat[regno]; |
7ed1bb71 | 12801 | if (rsp->last_set |
12802 | && rsp->last_set_label == label_tick | |
12803 | && DF_INSN_LUID (rsp->last_set) > from_luid) | |
12804 | return 1; | |
12805 | } | |
06a89553 | 12806 | return 0; |
ccfa01f5 | 12807 | } |
12808 | ||
3072d30e | 12809 | if (code == MEM && mem_last_set > from_luid) |
ccfa01f5 | 12810 | return 1; |
12811 | ||
12812 | fmt = GET_RTX_FORMAT (code); | |
12813 | ||
12814 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
12815 | { | |
12816 | if (fmt[i] == 'E') | |
12817 | { | |
19cb6b50 | 12818 | int j; |
ccfa01f5 | 12819 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
3072d30e | 12820 | if (use_crosses_set_p (XVECEXP (x, i, j), from_luid)) |
ccfa01f5 | 12821 | return 1; |
12822 | } | |
12823 | else if (fmt[i] == 'e' | |
3072d30e | 12824 | && use_crosses_set_p (XEXP (x, i), from_luid)) |
ccfa01f5 | 12825 | return 1; |
12826 | } | |
12827 | return 0; | |
12828 | } | |
12829 | \f | |
12830 | /* Define three variables used for communication between the following | |
12831 | routines. */ | |
12832 | ||
02e7a332 | 12833 | static unsigned int reg_dead_regno, reg_dead_endregno; |
ccfa01f5 | 12834 | static int reg_dead_flag; |
12835 | ||
12836 | /* Function called via note_stores from reg_dead_at_p. | |
12837 | ||
510f7125 | 12838 | If DEST is within [reg_dead_regno, reg_dead_endregno), set |
ccfa01f5 | 12839 | reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ |
12840 | ||
12841 | static void | |
81a410b1 | 12842 | reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) |
ccfa01f5 | 12843 | { |
02e7a332 | 12844 | unsigned int regno, endregno; |
ccfa01f5 | 12845 | |
8ad4c111 | 12846 | if (!REG_P (dest)) |
ccfa01f5 | 12847 | return; |
12848 | ||
12849 | regno = REGNO (dest); | |
a2c6f0b7 | 12850 | endregno = END_REGNO (dest); |
ccfa01f5 | 12851 | if (reg_dead_endregno > regno && reg_dead_regno < endregno) |
12852 | reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; | |
12853 | } | |
12854 | ||
d10cfa8d | 12855 | /* Return nonzero if REG is known to be dead at INSN. |
ccfa01f5 | 12856 | |
12857 | We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER | |
12858 | referencing REG, it is dead. If we hit a SET referencing REG, it is | |
12859 | live. Otherwise, see if it is live or dead at the start of the basic | |
cee293e3 | 12860 | block we are in. Hard regs marked as being live in NEWPAT_USED_REGS |
12861 | must be assumed to be always live. */ | |
ccfa01f5 | 12862 | |
12863 | static int | |
35330d19 | 12864 | reg_dead_at_p (rtx reg, rtx_insn *insn) |
ccfa01f5 | 12865 | { |
4c26117a | 12866 | basic_block block; |
02e7a332 | 12867 | unsigned int i; |
ccfa01f5 | 12868 | |
12869 | /* Set variables for reg_dead_at_p_1. */ | |
12870 | reg_dead_regno = REGNO (reg); | |
a2c6f0b7 | 12871 | reg_dead_endregno = END_REGNO (reg); |
ccfa01f5 | 12872 | |
12873 | reg_dead_flag = 0; | |
12874 | ||
b9f1cca5 | 12875 | /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers |
12876 | we allow the machine description to decide whether use-and-clobber | |
12877 | patterns are OK. */ | |
cee293e3 | 12878 | if (reg_dead_regno < FIRST_PSEUDO_REGISTER) |
12879 | { | |
12880 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
b9f1cca5 | 12881 | if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i)) |
cee293e3 | 12882 | return 0; |
12883 | } | |
12884 | ||
ee4d588d | 12885 | /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or |
12886 | beginning of basic block. */ | |
12887 | block = BLOCK_FOR_INSN (insn); | |
12888 | for (;;) | |
ccfa01f5 | 12889 | { |
ee4d588d | 12890 | if (INSN_P (insn)) |
12891 | { | |
12892 | note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); | |
12893 | if (reg_dead_flag) | |
12894 | return reg_dead_flag == 1 ? 1 : 0; | |
ccfa01f5 | 12895 | |
ee4d588d | 12896 | if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) |
12897 | return 1; | |
12898 | } | |
ccfa01f5 | 12899 | |
ee4d588d | 12900 | if (insn == BB_HEAD (block)) |
12901 | break; | |
ccfa01f5 | 12902 | |
ee4d588d | 12903 | insn = PREV_INSN (insn); |
ccfa01f5 | 12904 | } |
12905 | ||
ee4d588d | 12906 | /* Look at live-in sets for the basic block that we were in. */ |
ccfa01f5 | 12907 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) |
deb2741b | 12908 | if (REGNO_REG_SET_P (df_get_live_in (block), i)) |
ccfa01f5 | 12909 | return 0; |
12910 | ||
12911 | return 1; | |
12912 | } | |
cee293e3 | 12913 | \f |
3072d30e | 12914 | /* Note hard registers in X that are used. */ |
cee293e3 | 12915 | |
12916 | static void | |
d598ad0d | 12917 | mark_used_regs_combine (rtx x) |
cee293e3 | 12918 | { |
02e7a332 | 12919 | RTX_CODE code = GET_CODE (x); |
12920 | unsigned int regno; | |
cee293e3 | 12921 | int i; |
12922 | ||
12923 | switch (code) | |
12924 | { | |
12925 | case LABEL_REF: | |
12926 | case SYMBOL_REF: | |
cee293e3 | 12927 | case CONST: |
0349edce | 12928 | CASE_CONST_ANY: |
cee293e3 | 12929 | case PC: |
12930 | case ADDR_VEC: | |
12931 | case ADDR_DIFF_VEC: | |
12932 | case ASM_INPUT: | |
12933 | #ifdef HAVE_cc0 | |
12934 | /* CC0 must die in the insn after it is set, so we don't need to take | |
12935 | special note of it here. */ | |
12936 | case CC0: | |
12937 | #endif | |
12938 | return; | |
12939 | ||
12940 | case CLOBBER: | |
12941 | /* If we are clobbering a MEM, mark any hard registers inside the | |
12942 | address as used. */ | |
e16ceb8e | 12943 | if (MEM_P (XEXP (x, 0))) |
cee293e3 | 12944 | mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); |
12945 | return; | |
12946 | ||
12947 | case REG: | |
12948 | regno = REGNO (x); | |
12949 | /* A hard reg in a wide mode may really be multiple registers. | |
12950 | If so, mark all of them just like the first. */ | |
12951 | if (regno < FIRST_PSEUDO_REGISTER) | |
12952 | { | |
45498ea1 | 12953 | /* None of this applies to the stack, frame or arg pointers. */ |
cee293e3 | 12954 | if (regno == STACK_POINTER_REGNUM |
5ae82d58 | 12955 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
cee293e3 | 12956 | || regno == HARD_FRAME_POINTER_REGNUM |
12957 | #endif | |
12958 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
12959 | || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
12960 | #endif | |
12961 | || regno == FRAME_POINTER_REGNUM) | |
12962 | return; | |
12963 | ||
a2c6f0b7 | 12964 | add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno); |
cee293e3 | 12965 | } |
12966 | return; | |
12967 | ||
12968 | case SET: | |
12969 | { | |
12970 | /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in | |
12971 | the address. */ | |
19cb6b50 | 12972 | rtx testreg = SET_DEST (x); |
cee293e3 | 12973 | |
d8bb25c5 | 12974 | while (GET_CODE (testreg) == SUBREG |
12975 | || GET_CODE (testreg) == ZERO_EXTRACT | |
d8bb25c5 | 12976 | || GET_CODE (testreg) == STRICT_LOW_PART) |
cee293e3 | 12977 | testreg = XEXP (testreg, 0); |
12978 | ||
e16ceb8e | 12979 | if (MEM_P (testreg)) |
cee293e3 | 12980 | mark_used_regs_combine (XEXP (testreg, 0)); |
12981 | ||
12982 | mark_used_regs_combine (SET_SRC (x)); | |
cee293e3 | 12983 | } |
0dbd1c74 | 12984 | return; |
12985 | ||
12986 | default: | |
12987 | break; | |
cee293e3 | 12988 | } |
12989 | ||
12990 | /* Recursively scan the operands of this expression. */ | |
12991 | ||
12992 | { | |
19cb6b50 | 12993 | const char *fmt = GET_RTX_FORMAT (code); |
cee293e3 | 12994 | |
12995 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
12996 | { | |
510f7125 | 12997 | if (fmt[i] == 'e') |
cee293e3 | 12998 | mark_used_regs_combine (XEXP (x, i)); |
510f7125 | 12999 | else if (fmt[i] == 'E') |
13000 | { | |
19cb6b50 | 13001 | int j; |
cee293e3 | 13002 | |
510f7125 | 13003 | for (j = 0; j < XVECLEN (x, i); j++) |
13004 | mark_used_regs_combine (XVECEXP (x, i, j)); | |
13005 | } | |
cee293e3 | 13006 | } |
13007 | } | |
13008 | } | |
ccfa01f5 | 13009 | \f |
13010 | /* Remove register number REGNO from the dead registers list of INSN. | |
13011 | ||
13012 | Return the note used to record the death, if there was one. */ | |
13013 | ||
13014 | rtx | |
e149ca56 | 13015 | remove_death (unsigned int regno, rtx_insn *insn) |
ccfa01f5 | 13016 | { |
19cb6b50 | 13017 | rtx note = find_regno_note (insn, REG_DEAD, regno); |
ccfa01f5 | 13018 | |
13019 | if (note) | |
3072d30e | 13020 | remove_note (insn, note); |
ccfa01f5 | 13021 | |
13022 | return note; | |
13023 | } | |
13024 | ||
13025 | /* For each register (hardware or pseudo) used within expression X, if its | |
3072d30e | 13026 | death is in an instruction with luid between FROM_LUID (inclusive) and |
ccfa01f5 | 13027 | TO_INSN (exclusive), put a REG_DEAD note for that register in the |
510f7125 | 13028 | list headed by PNOTES. |
ccfa01f5 | 13029 | |
11f912ae | 13030 | That said, don't move registers killed by maybe_kill_insn. |
13031 | ||
ccfa01f5 | 13032 | This is done when X is being merged by combination into TO_INSN. These |
13033 | notes will then be distributed as needed. */ | |
13034 | ||
13035 | static void | |
35330d19 | 13036 | move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn, |
d598ad0d | 13037 | rtx *pnotes) |
ccfa01f5 | 13038 | { |
19cb6b50 | 13039 | const char *fmt; |
13040 | int len, i; | |
13041 | enum rtx_code code = GET_CODE (x); | |
ccfa01f5 | 13042 | |
13043 | if (code == REG) | |
13044 | { | |
02e7a332 | 13045 | unsigned int regno = REGNO (x); |
e149ca56 | 13046 | rtx_insn *where_dead = reg_stat[regno].last_death; |
543de094 | 13047 | |
45498ea1 | 13048 | /* Don't move the register if it gets killed in between from and to. */ |
11f912ae | 13049 | if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) |
02e7a332 | 13050 | && ! reg_referenced_p (x, maybe_kill_insn)) |
11f912ae | 13051 | return; |
13052 | ||
3072d30e | 13053 | if (where_dead |
bc20fdd7 | 13054 | && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn) |
3072d30e | 13055 | && DF_INSN_LUID (where_dead) >= from_luid |
13056 | && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn)) | |
ccfa01f5 | 13057 | { |
0cae3b93 | 13058 | rtx note = remove_death (regno, where_dead); |
ccfa01f5 | 13059 | |
13060 | /* It is possible for the call above to return 0. This can occur | |
acac6d5d | 13061 | when last_death points to I2 or I1 that we combined with. |
0cae3b93 | 13062 | In that case make a new note. |
13063 | ||
13064 | We must also check for the case where X is a hard register | |
13065 | and NOTE is a death note for a range of hard registers | |
13066 | including X. In that case, we must put REG_DEAD notes for | |
13067 | the remaining registers in place of NOTE. */ | |
13068 | ||
13069 | if (note != 0 && regno < FIRST_PSEUDO_REGISTER | |
13070 | && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
dcbcfb63 | 13071 | > GET_MODE_SIZE (GET_MODE (x)))) |
0cae3b93 | 13072 | { |
02e7a332 | 13073 | unsigned int deadregno = REGNO (XEXP (note, 0)); |
a2c6f0b7 | 13074 | unsigned int deadend = END_HARD_REGNO (XEXP (note, 0)); |
13075 | unsigned int ourend = END_HARD_REGNO (x); | |
02e7a332 | 13076 | unsigned int i; |
0cae3b93 | 13077 | |
13078 | for (i = deadregno; i < deadend; i++) | |
13079 | if (i < regno || i >= ourend) | |
a1ddb869 | 13080 | add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]); |
0cae3b93 | 13081 | } |
02e7a332 | 13082 | |
dcbcfb63 | 13083 | /* If we didn't find any note, or if we found a REG_DEAD note that |
13084 | covers only part of the given reg, and we have a multi-reg hard | |
15a6c14d | 13085 | register, then to be safe we must check for REG_DEAD notes |
13086 | for each register other than the first. They could have | |
13087 | their own REG_DEAD notes lying around. */ | |
dcbcfb63 | 13088 | else if ((note == 0 |
13089 | || (note != 0 | |
13090 | && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
13091 | < GET_MODE_SIZE (GET_MODE (x))))) | |
13092 | && regno < FIRST_PSEUDO_REGISTER | |
67d6c12b | 13093 | && hard_regno_nregs[regno][GET_MODE (x)] > 1) |
15a6c14d | 13094 | { |
a2c6f0b7 | 13095 | unsigned int ourend = END_HARD_REGNO (x); |
02e7a332 | 13096 | unsigned int i, offset; |
15a6c14d | 13097 | rtx oldnotes = 0; |
13098 | ||
dcbcfb63 | 13099 | if (note) |
67d6c12b | 13100 | offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]; |
dcbcfb63 | 13101 | else |
13102 | offset = 1; | |
13103 | ||
13104 | for (i = regno + offset; i < ourend; i++) | |
936082bb | 13105 | move_deaths (regno_reg_rtx[i], |
3072d30e | 13106 | maybe_kill_insn, from_luid, to_insn, &oldnotes); |
15a6c14d | 13107 | } |
ccfa01f5 | 13108 | |
0cae3b93 | 13109 | if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) |
ccfa01f5 | 13110 | { |
13111 | XEXP (note, 1) = *pnotes; | |
13112 | *pnotes = note; | |
13113 | } | |
13114 | else | |
5859ee98 | 13115 | *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes); |
ccfa01f5 | 13116 | } |
13117 | ||
13118 | return; | |
13119 | } | |
13120 | ||
13121 | else if (GET_CODE (x) == SET) | |
13122 | { | |
13123 | rtx dest = SET_DEST (x); | |
13124 | ||
3072d30e | 13125 | move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes); |
ccfa01f5 | 13126 | |
d976ad75 | 13127 | /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG |
13128 | that accesses one word of a multi-word item, some | |
13129 | piece of everything register in the expression is used by | |
13130 | this insn, so remove any old death. */ | |
701e46d0 | 13131 | /* ??? So why do we test for equality of the sizes? */ |
d976ad75 | 13132 | |
13133 | if (GET_CODE (dest) == ZERO_EXTRACT | |
13134 | || GET_CODE (dest) == STRICT_LOW_PART | |
13135 | || (GET_CODE (dest) == SUBREG | |
13136 | && (((GET_MODE_SIZE (GET_MODE (dest)) | |
13137 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
13138 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) | |
13139 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) | |
ccfa01f5 | 13140 | { |
3072d30e | 13141 | move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes); |
d976ad75 | 13142 | return; |
ccfa01f5 | 13143 | } |
13144 | ||
d976ad75 | 13145 | /* If this is some other SUBREG, we know it replaces the entire |
13146 | value, so use that as the destination. */ | |
13147 | if (GET_CODE (dest) == SUBREG) | |
13148 | dest = SUBREG_REG (dest); | |
13149 | ||
13150 | /* If this is a MEM, adjust deaths of anything used in the address. | |
13151 | For a REG (the only other possibility), the entire value is | |
13152 | being replaced so the old value is not used in this insn. */ | |
ccfa01f5 | 13153 | |
e16ceb8e | 13154 | if (MEM_P (dest)) |
3072d30e | 13155 | move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid, |
11f912ae | 13156 | to_insn, pnotes); |
ccfa01f5 | 13157 | return; |
13158 | } | |
13159 | ||
13160 | else if (GET_CODE (x) == CLOBBER) | |
13161 | return; | |
13162 | ||
13163 | len = GET_RTX_LENGTH (code); | |
13164 | fmt = GET_RTX_FORMAT (code); | |
13165 | ||
13166 | for (i = 0; i < len; i++) | |
13167 | { | |
13168 | if (fmt[i] == 'E') | |
13169 | { | |
19cb6b50 | 13170 | int j; |
ccfa01f5 | 13171 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
3072d30e | 13172 | move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid, |
11f912ae | 13173 | to_insn, pnotes); |
ccfa01f5 | 13174 | } |
13175 | else if (fmt[i] == 'e') | |
3072d30e | 13176 | move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes); |
ccfa01f5 | 13177 | } |
13178 | } | |
13179 | \f | |
d976ad75 | 13180 | /* Return 1 if X is the target of a bit-field assignment in BODY, the |
13181 | pattern of an insn. X must be a REG. */ | |
ccfa01f5 | 13182 | |
13183 | static int | |
d598ad0d | 13184 | reg_bitfield_target_p (rtx x, rtx body) |
ccfa01f5 | 13185 | { |
13186 | int i; | |
13187 | ||
13188 | if (GET_CODE (body) == SET) | |
d976ad75 | 13189 | { |
13190 | rtx dest = SET_DEST (body); | |
13191 | rtx target; | |
02e7a332 | 13192 | unsigned int regno, tregno, endregno, endtregno; |
d976ad75 | 13193 | |
13194 | if (GET_CODE (dest) == ZERO_EXTRACT) | |
13195 | target = XEXP (dest, 0); | |
13196 | else if (GET_CODE (dest) == STRICT_LOW_PART) | |
13197 | target = SUBREG_REG (XEXP (dest, 0)); | |
13198 | else | |
13199 | return 0; | |
13200 | ||
13201 | if (GET_CODE (target) == SUBREG) | |
13202 | target = SUBREG_REG (target); | |
13203 | ||
8ad4c111 | 13204 | if (!REG_P (target)) |
d976ad75 | 13205 | return 0; |
13206 | ||
13207 | tregno = REGNO (target), regno = REGNO (x); | |
13208 | if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) | |
13209 | return target == x; | |
13210 | ||
a2c6f0b7 | 13211 | endtregno = end_hard_regno (GET_MODE (target), tregno); |
13212 | endregno = end_hard_regno (GET_MODE (x), regno); | |
d976ad75 | 13213 | |
13214 | return endregno > tregno && regno < endtregno; | |
13215 | } | |
ccfa01f5 | 13216 | |
13217 | else if (GET_CODE (body) == PARALLEL) | |
13218 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
d976ad75 | 13219 | if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) |
ccfa01f5 | 13220 | return 1; |
13221 | ||
13222 | return 0; | |
510f7125 | 13223 | } |
ccfa01f5 | 13224 | \f |
13225 | /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them | |
13226 | as appropriate. I3 and I2 are the insns resulting from the combination | |
13227 | insns including FROM (I2 may be zero). | |
13228 | ||
40a8fb89 | 13229 | ELIM_I2 and ELIM_I1 are either zero or registers that we know will |
13230 | not need REG_DEAD notes because they are being substituted for. This | |
13231 | saves searching in the most common cases. | |
13232 | ||
ccfa01f5 | 13233 | Each note in the list is either ignored or placed on some insns, depending |
13234 | on the type of note. */ | |
13235 | ||
13236 | static void | |
35330d19 | 13237 | distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2, |
13238 | rtx elim_i2, rtx elim_i1, rtx elim_i0) | |
ccfa01f5 | 13239 | { |
13240 | rtx note, next_note; | |
35330d19 | 13241 | rtx tem_note; |
13242 | rtx_insn *tem_insn; | |
ccfa01f5 | 13243 | |
13244 | for (note = notes; note; note = next_note) | |
13245 | { | |
35330d19 | 13246 | rtx_insn *place = 0, *place2 = 0; |
ccfa01f5 | 13247 | |
ccfa01f5 | 13248 | next_note = XEXP (note, 1); |
13249 | switch (REG_NOTE_KIND (note)) | |
13250 | { | |
30637659 | 13251 | case REG_BR_PROB: |
13488c51 | 13252 | case REG_BR_PRED: |
30637659 | 13253 | /* Doesn't matter much where we put this, as long as it's somewhere. |
13254 | It is preferable to keep these notes on branches, which is most | |
13255 | likely to be i3. */ | |
cef0c6a0 | 13256 | place = i3; |
13257 | break; | |
13258 | ||
1e48a998 | 13259 | case REG_NON_LOCAL_GOTO: |
6d7dc5b9 | 13260 | if (JUMP_P (i3)) |
1e48a998 | 13261 | place = i3; |
1e48a998 | 13262 | else |
cc636d56 | 13263 | { |
13264 | gcc_assert (i2 && JUMP_P (i2)); | |
13265 | place = i2; | |
13266 | } | |
1e48a998 | 13267 | break; |
13268 | ||
1e6cb85a | 13269 | case REG_EH_REGION: |
de1df5b4 | 13270 | /* These notes must remain with the call or trapping instruction. */ |
6d7dc5b9 | 13271 | if (CALL_P (i3)) |
de1df5b4 | 13272 | place = i3; |
6d7dc5b9 | 13273 | else if (i2 && CALL_P (i2)) |
de1df5b4 | 13274 | place = i2; |
cc636d56 | 13275 | else |
de1df5b4 | 13276 | { |
cbeb677e | 13277 | gcc_assert (cfun->can_throw_non_call_exceptions); |
de1df5b4 | 13278 | if (may_trap_p (i3)) |
13279 | place = i3; | |
13280 | else if (i2 && may_trap_p (i2)) | |
13281 | place = i2; | |
13282 | /* ??? Otherwise assume we've combined things such that we | |
13283 | can now prove that the instructions can't trap. Drop the | |
13284 | note in this case. */ | |
13285 | } | |
de1df5b4 | 13286 | break; |
13287 | ||
dfe00a8f | 13288 | case REG_ARGS_SIZE: |
a343634a | 13289 | /* ??? How to distribute between i3-i1. Assume i3 contains the |
13290 | entire adjustment. Assert i3 contains at least some adjust. */ | |
13291 | if (!noop_move_p (i3)) | |
13292 | { | |
13293 | int old_size, args_size = INTVAL (XEXP (note, 0)); | |
45152a7b | 13294 | /* fixup_args_size_notes looks at REG_NORETURN note, |
13295 | so ensure the note is placed there first. */ | |
13296 | if (CALL_P (i3)) | |
13297 | { | |
13298 | rtx *np; | |
13299 | for (np = &next_note; *np; np = &XEXP (*np, 1)) | |
13300 | if (REG_NOTE_KIND (*np) == REG_NORETURN) | |
13301 | { | |
13302 | rtx n = *np; | |
13303 | *np = XEXP (n, 1); | |
13304 | XEXP (n, 1) = REG_NOTES (i3); | |
13305 | REG_NOTES (i3) = n; | |
13306 | break; | |
13307 | } | |
13308 | } | |
a343634a | 13309 | old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size); |
45152a7b | 13310 | /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS |
13311 | REG_ARGS_SIZE note to all noreturn calls, allow that here. */ | |
13312 | gcc_assert (old_size != args_size | |
13313 | || (CALL_P (i3) | |
13314 | && !ACCUMULATE_OUTGOING_ARGS | |
13315 | && find_reg_note (i3, REG_NORETURN, NULL_RTX))); | |
a343634a | 13316 | } |
dfe00a8f | 13317 | break; |
13318 | ||
356b51a0 | 13319 | case REG_NORETURN: |
911d4e2e | 13320 | case REG_SETJMP: |
4c0315d0 | 13321 | case REG_TM: |
2e3b0d0f | 13322 | case REG_CALL_DECL: |
dcaf19ea | 13323 | /* These notes must remain with the call. It should not be |
13324 | possible for both I2 and I3 to be a call. */ | |
6d7dc5b9 | 13325 | if (CALL_P (i3)) |
1e6cb85a | 13326 | place = i3; |
1e6cb85a | 13327 | else |
cc636d56 | 13328 | { |
13329 | gcc_assert (i2 && CALL_P (i2)); | |
13330 | place = i2; | |
13331 | } | |
1e6cb85a | 13332 | break; |
13333 | ||
ccfa01f5 | 13334 | case REG_UNUSED: |
ff1c03cd | 13335 | /* Any clobbers for i3 may still exist, and so we must process |
4ac0b86b | 13336 | REG_UNUSED notes from that insn. |
13337 | ||
13338 | Any clobbers from i2 or i1 can only exist if they were added by | |
13339 | recog_for_combine. In that case, recog_for_combine created the | |
13340 | necessary REG_UNUSED notes. Trying to keep any original | |
13341 | REG_UNUSED notes from these insns can cause incorrect output | |
13342 | if it is for the same register as the original i3 dest. | |
13343 | In that case, we will notice that the register is set in i3, | |
13344 | and then add a REG_UNUSED note for the destination of i3, which | |
ff1c03cd | 13345 | is wrong. However, it is possible to have REG_UNUSED notes from |
13346 | i2 or i1 for register which were both used and clobbered, so | |
13347 | we keep notes from i2 or i1 if they will turn into REG_DEAD | |
13348 | notes. */ | |
4ac0b86b | 13349 | |
ccfa01f5 | 13350 | /* If this register is set or clobbered in I3, put the note there |
13351 | unless there is one already. */ | |
ff1c03cd | 13352 | if (reg_set_p (XEXP (note, 0), PATTERN (i3))) |
ccfa01f5 | 13353 | { |
ff1c03cd | 13354 | if (from_insn != i3) |
13355 | break; | |
13356 | ||
8ad4c111 | 13357 | if (! (REG_P (XEXP (note, 0)) |
ccfa01f5 | 13358 | ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) |
13359 | : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) | |
13360 | place = i3; | |
13361 | } | |
13362 | /* Otherwise, if this register is used by I3, then this register | |
13363 | now dies here, so we must put a REG_DEAD note here unless there | |
13364 | is one already. */ | |
13365 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) | |
8ad4c111 | 13366 | && ! (REG_P (XEXP (note, 0)) |
02e7a332 | 13367 | ? find_regno_note (i3, REG_DEAD, |
13368 | REGNO (XEXP (note, 0))) | |
ccfa01f5 | 13369 | : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) |
13370 | { | |
13371 | PUT_REG_NOTE_KIND (note, REG_DEAD); | |
13372 | place = i3; | |
13373 | } | |
13374 | break; | |
13375 | ||
13376 | case REG_EQUAL: | |
13377 | case REG_EQUIV: | |
ea0cb7ae | 13378 | case REG_NOALIAS: |
ccfa01f5 | 13379 | /* These notes say something about results of an insn. We can |
13380 | only support them if they used to be on I3 in which case they | |
4cd6ac21 | 13381 | remain on I3. Otherwise they are ignored. |
13382 | ||
13383 | If the note refers to an expression that is not a constant, we | |
13384 | must also ignore the note since we cannot tell whether the | |
13385 | equivalence is still true. It might be possible to do | |
13386 | slightly better than this (we only have a problem if I2DEST | |
13387 | or I1DEST is present in the expression), but it doesn't | |
13388 | seem worth the trouble. */ | |
13389 | ||
13390 | if (from_insn == i3 | |
13391 | && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) | |
ccfa01f5 | 13392 | place = i3; |
13393 | break; | |
13394 | ||
13395 | case REG_INC: | |
ccfa01f5 | 13396 | /* These notes say something about how a register is used. They must |
13397 | be present on any use of the register in I2 or I3. */ | |
13398 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) | |
13399 | place = i3; | |
13400 | ||
13401 | if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) | |
13402 | { | |
13403 | if (place) | |
13404 | place2 = i2; | |
13405 | else | |
13406 | place = i2; | |
13407 | } | |
13408 | break; | |
13409 | ||
19d2fe05 | 13410 | case REG_LABEL_TARGET: |
13411 | case REG_LABEL_OPERAND: | |
a69c9ae5 | 13412 | /* This can show up in several ways -- either directly in the |
13413 | pattern, or hidden off in the constant pool with (or without?) | |
13414 | a REG_EQUAL note. */ | |
13415 | /* ??? Ignore the without-reg_equal-note problem for now. */ | |
13416 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) | |
35330d19 | 13417 | || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX)) |
13418 | && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF | |
b49f2e4b | 13419 | && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0))) |
a69c9ae5 | 13420 | place = i3; |
13421 | ||
13422 | if (i2 | |
13423 | && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) | |
35330d19 | 13424 | || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX)) |
13425 | && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF | |
b49f2e4b | 13426 | && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0)))) |
a69c9ae5 | 13427 | { |
13428 | if (place) | |
13429 | place2 = i2; | |
13430 | else | |
13431 | place = i2; | |
13432 | } | |
a31c1c9f | 13433 | |
19d2fe05 | 13434 | /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note |
13435 | as a JUMP_LABEL or decrement LABEL_NUSES if it's already | |
13436 | there. */ | |
13437 | if (place && JUMP_P (place) | |
13438 | && REG_NOTE_KIND (note) == REG_LABEL_TARGET | |
13439 | && (JUMP_LABEL (place) == NULL | |
13440 | || JUMP_LABEL (place) == XEXP (note, 0))) | |
a31c1c9f | 13441 | { |
cc636d56 | 13442 | rtx label = JUMP_LABEL (place); |
a0c938f0 | 13443 | |
cc636d56 | 13444 | if (!label) |
f439075a | 13445 | JUMP_LABEL (place) = XEXP (note, 0); |
19d2fe05 | 13446 | else if (LABEL_P (label)) |
13447 | LABEL_NUSES (label)--; | |
a31c1c9f | 13448 | } |
19d2fe05 | 13449 | |
13450 | if (place2 && JUMP_P (place2) | |
13451 | && REG_NOTE_KIND (note) == REG_LABEL_TARGET | |
13452 | && (JUMP_LABEL (place2) == NULL | |
13453 | || JUMP_LABEL (place2) == XEXP (note, 0))) | |
a31c1c9f | 13454 | { |
cc636d56 | 13455 | rtx label = JUMP_LABEL (place2); |
a0c938f0 | 13456 | |
cc636d56 | 13457 | if (!label) |
f439075a | 13458 | JUMP_LABEL (place2) = XEXP (note, 0); |
19d2fe05 | 13459 | else if (LABEL_P (label)) |
13460 | LABEL_NUSES (label)--; | |
a31c1c9f | 13461 | place2 = 0; |
13462 | } | |
a69c9ae5 | 13463 | break; |
13464 | ||
323f7906 | 13465 | case REG_NONNEG: |
8e999997 | 13466 | /* This note says something about the value of a register prior |
323f7906 | 13467 | to the execution of an insn. It is too much trouble to see |
13468 | if the note is still correct in all situations. It is better | |
13469 | to simply delete it. */ | |
ccfa01f5 | 13470 | break; |
13471 | ||
ccfa01f5 | 13472 | case REG_DEAD: |
810d7bbd | 13473 | /* If we replaced the right hand side of FROM_INSN with a |
13474 | REG_EQUAL note, the original use of the dying register | |
13475 | will not have been combined into I3 and I2. In such cases, | |
13476 | FROM_INSN is guaranteed to be the first of the combined | |
13477 | instructions, so we simply need to search back before | |
13478 | FROM_INSN for the previous use or set of this register, | |
13479 | then alter the notes there appropriately. | |
13480 | ||
13481 | If the register is used as an input in I3, it dies there. | |
d10cfa8d | 13482 | Similarly for I2, if it is nonzero and adjacent to I3. |
ccfa01f5 | 13483 | |
13484 | If the register is not used as an input in either I3 or I2 | |
13485 | and it is not one of the registers we were supposed to eliminate, | |
13486 | there are two possibilities. We might have a non-adjacent I2 | |
13487 | or we might have somehow eliminated an additional register | |
13488 | from a computation. For example, we might have had A & B where | |
13489 | we discover that B will always be zero. In this case we will | |
13490 | eliminate the reference to A. | |
13491 | ||
13492 | In both cases, we must search to see if we can find a previous | |
13493 | use of A and put the death note there. */ | |
13494 | ||
98c26c78 | 13495 | if (from_insn |
cf86e5ce | 13496 | && from_insn == i2mod |
13497 | && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs)) | |
35330d19 | 13498 | tem_insn = from_insn; |
810d7bbd | 13499 | else |
13500 | { | |
13501 | if (from_insn | |
13502 | && CALL_P (from_insn) | |
13503 | && find_reg_fusage (from_insn, USE, XEXP (note, 0))) | |
13504 | place = from_insn; | |
13505 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) | |
13506 | place = i3; | |
9845d120 | 13507 | else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3 |
810d7bbd | 13508 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) |
13509 | place = i2; | |
cf86e5ce | 13510 | else if ((rtx_equal_p (XEXP (note, 0), elim_i2) |
13511 | && !(i2mod | |
13512 | && reg_overlap_mentioned_p (XEXP (note, 0), | |
13513 | i2mod_old_rhs))) | |
6342422c | 13514 | || rtx_equal_p (XEXP (note, 0), elim_i1) |
13515 | || rtx_equal_p (XEXP (note, 0), elim_i0)) | |
810d7bbd | 13516 | break; |
35330d19 | 13517 | tem_insn = i3; |
810d7bbd | 13518 | } |
40a8fb89 | 13519 | |
ccfa01f5 | 13520 | if (place == 0) |
41630864 | 13521 | { |
345ac34a | 13522 | basic_block bb = this_basic_block; |
2d9b9dfe | 13523 | |
35330d19 | 13524 | for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn)) |
41630864 | 13525 | { |
35330d19 | 13526 | if (!NONDEBUG_INSN_P (tem_insn)) |
2d9b9dfe | 13527 | { |
35330d19 | 13528 | if (tem_insn == BB_HEAD (bb)) |
2d9b9dfe | 13529 | break; |
13530 | continue; | |
13531 | } | |
13532 | ||
35330d19 | 13533 | /* If the register is being set at TEM_INSN, see if that is all |
13534 | TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this | |
cf86e5ce | 13535 | into a REG_UNUSED note instead. Don't delete sets to |
13536 | global register vars. */ | |
13537 | if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER | |
13538 | || !global_regs[REGNO (XEXP (note, 0))]) | |
35330d19 | 13539 | && reg_set_p (XEXP (note, 0), PATTERN (tem_insn))) |
41630864 | 13540 | { |
35330d19 | 13541 | rtx set = single_set (tem_insn); |
997d68fe | 13542 | rtx inner_dest = 0; |
274c11d8 | 13543 | #ifdef HAVE_cc0 |
35330d19 | 13544 | rtx_insn *cc0_setter = NULL; |
274c11d8 | 13545 | #endif |
997d68fe | 13546 | |
13547 | if (set != 0) | |
13548 | for (inner_dest = SET_DEST (set); | |
510f7125 | 13549 | (GET_CODE (inner_dest) == STRICT_LOW_PART |
13550 | || GET_CODE (inner_dest) == SUBREG | |
13551 | || GET_CODE (inner_dest) == ZERO_EXTRACT); | |
997d68fe | 13552 | inner_dest = XEXP (inner_dest, 0)) |
13553 | ; | |
41630864 | 13554 | |
13555 | /* Verify that it was the set, and not a clobber that | |
510f7125 | 13556 | modified the register. |
89a9144c | 13557 | |
13558 | CC0 targets must be careful to maintain setter/user | |
13559 | pairs. If we cannot delete the setter due to side | |
13560 | effects, mark the user with an UNUSED note instead | |
13561 | of deleting it. */ | |
41630864 | 13562 | |
13563 | if (set != 0 && ! side_effects_p (SET_SRC (set)) | |
89a9144c | 13564 | && rtx_equal_p (XEXP (note, 0), inner_dest) |
13565 | #ifdef HAVE_cc0 | |
13566 | && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) | |
35330d19 | 13567 | || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL |
89a9144c | 13568 | && sets_cc0_p (PATTERN (cc0_setter)) > 0)) |
13569 | #endif | |
13570 | ) | |
41630864 | 13571 | { |
35330d19 | 13572 | /* Move the notes and links of TEM_INSN elsewhere. |
510f7125 | 13573 | This might delete other dead insns recursively. |
41630864 | 13574 | First set the pattern to something that won't use |
13575 | any register. */ | |
35330d19 | 13576 | rtx old_notes = REG_NOTES (tem_insn); |
41630864 | 13577 | |
35330d19 | 13578 | PATTERN (tem_insn) = pc_rtx; |
13579 | REG_NOTES (tem_insn) = NULL; | |
41630864 | 13580 | |
35330d19 | 13581 | distribute_notes (old_notes, tem_insn, tem_insn, NULL, |
6342422c | 13582 | NULL_RTX, NULL_RTX, NULL_RTX); |
35330d19 | 13583 | distribute_links (LOG_LINKS (tem_insn)); |
41630864 | 13584 | |
35330d19 | 13585 | SET_INSN_DELETED (tem_insn); |
13586 | if (tem_insn == i2) | |
13587 | i2 = NULL; | |
89a9144c | 13588 | |
13589 | #ifdef HAVE_cc0 | |
13590 | /* Delete the setter too. */ | |
13591 | if (cc0_setter) | |
13592 | { | |
13593 | PATTERN (cc0_setter) = pc_rtx; | |
7b842133 | 13594 | old_notes = REG_NOTES (cc0_setter); |
13595 | REG_NOTES (cc0_setter) = NULL; | |
89a9144c | 13596 | |
7b842133 | 13597 | distribute_notes (old_notes, cc0_setter, |
35330d19 | 13598 | cc0_setter, NULL, |
6342422c | 13599 | NULL_RTX, NULL_RTX, NULL_RTX); |
89a9144c | 13600 | distribute_links (LOG_LINKS (cc0_setter)); |
13601 | ||
7bd3dcc4 | 13602 | SET_INSN_DELETED (cc0_setter); |
fc3d1695 | 13603 | if (cc0_setter == i2) |
35330d19 | 13604 | i2 = NULL; |
89a9144c | 13605 | } |
13606 | #endif | |
41630864 | 13607 | } |
13608 | else | |
13609 | { | |
13610 | PUT_REG_NOTE_KIND (note, REG_UNUSED); | |
510f7125 | 13611 | |
41630864 | 13612 | /* If there isn't already a REG_UNUSED note, put one |
bcbf3e49 | 13613 | here. Do not place a REG_DEAD note, even if |
13614 | the register is also used here; that would not | |
13615 | match the algorithm used in lifetime analysis | |
13616 | and can cause the consistency check in the | |
13617 | scheduler to fail. */ | |
35330d19 | 13618 | if (! find_regno_note (tem_insn, REG_UNUSED, |
41630864 | 13619 | REGNO (XEXP (note, 0)))) |
35330d19 | 13620 | place = tem_insn; |
41630864 | 13621 | break; |
2d9b9dfe | 13622 | } |
13623 | } | |
35330d19 | 13624 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn)) |
13625 | || (CALL_P (tem_insn) | |
13626 | && find_reg_fusage (tem_insn, USE, XEXP (note, 0)))) | |
2d9b9dfe | 13627 | { |
35330d19 | 13628 | place = tem_insn; |
2d9b9dfe | 13629 | |
13630 | /* If we are doing a 3->2 combination, and we have a | |
13631 | register which formerly died in i3 and was not used | |
13632 | by i2, which now no longer dies in i3 and is used in | |
13633 | i2 but does not die in i2, and place is between i2 | |
13634 | and i3, then we may need to move a link from place to | |
13635 | i2. */ | |
3072d30e | 13636 | if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2) |
510f7125 | 13637 | && from_insn |
3072d30e | 13638 | && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2) |
2d9b9dfe | 13639 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) |
13640 | { | |
2a0877d8 | 13641 | struct insn_link *links = LOG_LINKS (place); |
13642 | LOG_LINKS (place) = NULL; | |
2d9b9dfe | 13643 | distribute_links (links); |
13644 | } | |
13645 | break; | |
13646 | } | |
13647 | ||
35330d19 | 13648 | if (tem_insn == BB_HEAD (bb)) |
ccfa01f5 | 13649 | break; |
41630864 | 13650 | } |
510f7125 | 13651 | |
41630864 | 13652 | } |
ccfa01f5 | 13653 | |
13654 | /* If the register is set or already dead at PLACE, we needn't do | |
997d68fe | 13655 | anything with this note if it is still a REG_DEAD note. |
1e9a1a86 | 13656 | We check here if it is set at all, not if is it totally replaced, |
997d68fe | 13657 | which is what `dead_or_set_p' checks, so also check for it being |
13658 | set partially. */ | |
13659 | ||
ccfa01f5 | 13660 | if (place && REG_NOTE_KIND (note) == REG_DEAD) |
13661 | { | |
02e7a332 | 13662 | unsigned int regno = REGNO (XEXP (note, 0)); |
f1f41a6c | 13663 | reg_stat_type *rsp = ®_stat[regno]; |
a2ad2f9b | 13664 | |
ccfa01f5 | 13665 | if (dead_or_set_p (place, XEXP (note, 0)) |
13666 | || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) | |
13667 | { | |
13668 | /* Unless the register previously died in PLACE, clear | |
acac6d5d | 13669 | last_death. [I no longer understand why this is |
ccfa01f5 | 13670 | being done.] */ |
7ed1bb71 | 13671 | if (rsp->last_death != place) |
13672 | rsp->last_death = 0; | |
ccfa01f5 | 13673 | place = 0; |
13674 | } | |
13675 | else | |
7ed1bb71 | 13676 | rsp->last_death = place; |
ccfa01f5 | 13677 | |
13678 | /* If this is a death note for a hard reg that is occupying | |
13679 | multiple registers, ensure that we are still using all | |
13680 | parts of the object. If we find a piece of the object | |
813ebca1 | 13681 | that is unused, we must arrange for an appropriate REG_DEAD |
13682 | note to be added for it. However, we can't just emit a USE | |
13683 | and tag the note to it, since the register might actually | |
13684 | be dead; so we recourse, and the recursive call then finds | |
13685 | the previous insn that used this register. */ | |
ccfa01f5 | 13686 | |
13687 | if (place && regno < FIRST_PSEUDO_REGISTER | |
67d6c12b | 13688 | && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1) |
ccfa01f5 | 13689 | { |
a2c6f0b7 | 13690 | unsigned int endregno = END_HARD_REGNO (XEXP (note, 0)); |
ed3a8d75 | 13691 | bool all_used = true; |
02e7a332 | 13692 | unsigned int i; |
ccfa01f5 | 13693 | |
13694 | for (i = regno; i < endregno; i++) | |
813ebca1 | 13695 | if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0) |
13696 | && ! find_regno_fusage (place, USE, i)) | |
13697 | || dead_or_set_regno_p (place, i)) | |
ed3a8d75 | 13698 | { |
13699 | all_used = false; | |
13700 | break; | |
13701 | } | |
132bf6d3 | 13702 | |
ccfa01f5 | 13703 | if (! all_used) |
13704 | { | |
13705 | /* Put only REG_DEAD notes for pieces that are | |
813ebca1 | 13706 | not already dead or set. */ |
ccfa01f5 | 13707 | |
813ebca1 | 13708 | for (i = regno; i < endregno; |
67d6c12b | 13709 | i += hard_regno_nregs[i][reg_raw_mode[i]]) |
ccfa01f5 | 13710 | { |
936082bb | 13711 | rtx piece = regno_reg_rtx[i]; |
345ac34a | 13712 | basic_block bb = this_basic_block; |
ccfa01f5 | 13713 | |
813ebca1 | 13714 | if (! dead_or_set_p (place, piece) |
ccfa01f5 | 13715 | && ! reg_bitfield_target_p (piece, |
13716 | PATTERN (place))) | |
813ebca1 | 13717 | { |
5859ee98 | 13718 | rtx new_note = alloc_reg_note (REG_DEAD, piece, |
13719 | NULL_RTX); | |
813ebca1 | 13720 | |
13721 | distribute_notes (new_note, place, place, | |
35330d19 | 13722 | NULL, NULL_RTX, NULL_RTX, |
6342422c | 13723 | NULL_RTX); |
813ebca1 | 13724 | } |
f9b79678 | 13725 | else if (! refers_to_regno_p (i, i + 1, |
13726 | PATTERN (place), 0) | |
13727 | && ! find_regno_fusage (place, USE, i)) | |
35330d19 | 13728 | for (tem_insn = PREV_INSN (place); ; |
13729 | tem_insn = PREV_INSN (tem_insn)) | |
f9b79678 | 13730 | { |
35330d19 | 13731 | if (!NONDEBUG_INSN_P (tem_insn)) |
f9b79678 | 13732 | { |
35330d19 | 13733 | if (tem_insn == BB_HEAD (bb)) |
3072d30e | 13734 | break; |
f9b79678 | 13735 | continue; |
13736 | } | |
35330d19 | 13737 | if (dead_or_set_p (tem_insn, piece) |
f9b79678 | 13738 | || reg_bitfield_target_p (piece, |
35330d19 | 13739 | PATTERN (tem_insn))) |
f9b79678 | 13740 | { |
35330d19 | 13741 | add_reg_note (tem_insn, REG_UNUSED, piece); |
f9b79678 | 13742 | break; |
13743 | } | |
13744 | } | |
ccfa01f5 | 13745 | } |
13746 | ||
13747 | place = 0; | |
13748 | } | |
13749 | } | |
13750 | } | |
13751 | break; | |
13752 | ||
13753 | default: | |
13754 | /* Any other notes should not be present at this point in the | |
13755 | compilation. */ | |
cc636d56 | 13756 | gcc_unreachable (); |
ccfa01f5 | 13757 | } |
13758 | ||
13759 | if (place) | |
13760 | { | |
13761 | XEXP (note, 1) = REG_NOTES (place); | |
13762 | REG_NOTES (place) = note; | |
13763 | } | |
13764 | ||
13765 | if (place2) | |
9eb946de | 13766 | add_shallow_copy_of_reg_note (place2, note); |
ccfa01f5 | 13767 | } |
13768 | } | |
13769 | \f | |
13770 | /* Similarly to above, distribute the LOG_LINKS that used to be present on | |
2584991b | 13771 | I3, I2, and I1 to new locations. This is also called to add a link |
13772 | pointing at I3 when I3's destination is changed. */ | |
ccfa01f5 | 13773 | |
13774 | static void | |
2a0877d8 | 13775 | distribute_links (struct insn_link *links) |
ccfa01f5 | 13776 | { |
2a0877d8 | 13777 | struct insn_link *link, *next_link; |
ccfa01f5 | 13778 | |
13779 | for (link = links; link; link = next_link) | |
13780 | { | |
35330d19 | 13781 | rtx_insn *place = 0; |
13782 | rtx_insn *insn; | |
ccfa01f5 | 13783 | rtx set, reg; |
13784 | ||
2a0877d8 | 13785 | next_link = link->next; |
ccfa01f5 | 13786 | |
13787 | /* If the insn that this link points to is a NOTE or isn't a single | |
13788 | set, ignore it. In the latter case, it isn't clear what we | |
510f7125 | 13789 | can do other than ignore the link, since we can't tell which |
ccfa01f5 | 13790 | register it was for. Such links wouldn't be used by combine |
13791 | anyway. | |
13792 | ||
13793 | It is not possible for the destination of the target of the link to | |
13794 | have been changed by combine. The only potential of this is if we | |
13795 | replace I3, I2, and I1 by I3 and I2. But in that case the | |
13796 | destination of I2 also remains unchanged. */ | |
13797 | ||
2a0877d8 | 13798 | if (NOTE_P (link->insn) |
13799 | || (set = single_set (link->insn)) == 0) | |
ccfa01f5 | 13800 | continue; |
13801 | ||
13802 | reg = SET_DEST (set); | |
13803 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
ccfa01f5 | 13804 | || GET_CODE (reg) == STRICT_LOW_PART) |
13805 | reg = XEXP (reg, 0); | |
13806 | ||
13807 | /* A LOG_LINK is defined as being placed on the first insn that uses | |
13808 | a register and points to the insn that sets the register. Start | |
13809 | searching at the next insn after the target of the link and stop | |
13810 | when we reach a set of the register or the end of the basic block. | |
13811 | ||
13812 | Note that this correctly handles the link that used to point from | |
88355298 | 13813 | I3 to I2. Also note that not much searching is typically done here |
ccfa01f5 | 13814 | since most links don't point very far away. */ |
13815 | ||
2a0877d8 | 13816 | for (insn = NEXT_INSN (link->insn); |
34154e27 | 13817 | (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) |
5496dbfc | 13818 | || BB_HEAD (this_basic_block->next_bb) != insn)); |
ccfa01f5 | 13819 | insn = NEXT_INSN (insn)) |
9845d120 | 13820 | if (DEBUG_INSN_P (insn)) |
13821 | continue; | |
13822 | else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
ccfa01f5 | 13823 | { |
13824 | if (reg_referenced_p (reg, PATTERN (insn))) | |
13825 | place = insn; | |
13826 | break; | |
13827 | } | |
6d7dc5b9 | 13828 | else if (CALL_P (insn) |
510f7125 | 13829 | && find_reg_fusage (insn, USE, reg)) |
6d1e4f1e | 13830 | { |
13831 | place = insn; | |
13832 | break; | |
13833 | } | |
63173cd9 | 13834 | else if (INSN_P (insn) && reg_set_p (reg, insn)) |
13835 | break; | |
ccfa01f5 | 13836 | |
13837 | /* If we found a place to put the link, place it there unless there | |
13838 | is already a link to the same insn as LINK at that point. */ | |
13839 | ||
13840 | if (place) | |
13841 | { | |
2a0877d8 | 13842 | struct insn_link *link2; |
ccfa01f5 | 13843 | |
2a0877d8 | 13844 | FOR_EACH_LOG_LINK (link2, place) |
13845 | if (link2->insn == link->insn) | |
ccfa01f5 | 13846 | break; |
13847 | ||
2a0877d8 | 13848 | if (link2 == NULL) |
ccfa01f5 | 13849 | { |
2a0877d8 | 13850 | link->next = LOG_LINKS (place); |
ccfa01f5 | 13851 | LOG_LINKS (place) = link; |
862e4898 | 13852 | |
13853 | /* Set added_links_insn to the earliest insn we added a | |
13854 | link to. */ | |
510f7125 | 13855 | if (added_links_insn == 0 |
3072d30e | 13856 | || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place)) |
862e4898 | 13857 | added_links_insn = place; |
ccfa01f5 | 13858 | } |
13859 | } | |
13860 | } | |
13861 | } | |
13862 | \f | |
7d87562d | 13863 | /* Check for any register or memory mentioned in EQUIV that is not |
13864 | mentioned in EXPR. This is used to restrict EQUIV to "specializations" | |
13865 | of EXPR where some registers may have been replaced by constants. */ | |
13866 | ||
13867 | static bool | |
13868 | unmentioned_reg_p (rtx equiv, rtx expr) | |
13869 | { | |
802dfe65 | 13870 | subrtx_iterator::array_type array; |
13871 | FOR_EACH_SUBRTX (iter, array, equiv, NONCONST) | |
13872 | { | |
13873 | const_rtx x = *iter; | |
13874 | if ((REG_P (x) || MEM_P (x)) | |
13875 | && !reg_mentioned_p (x, expr)) | |
13876 | return true; | |
13877 | } | |
13878 | return false; | |
7d87562d | 13879 | } |
13880 | \f | |
d2bb3f9d | 13881 | DEBUG_FUNCTION void |
d598ad0d | 13882 | dump_combine_stats (FILE *file) |
ccfa01f5 | 13883 | { |
0a81f5a0 | 13884 | fprintf |
ccfa01f5 | 13885 | (file, |
13886 | ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", | |
13887 | combine_attempts, combine_merges, combine_extras, combine_successes); | |
13888 | } | |
13889 | ||
13890 | void | |
d598ad0d | 13891 | dump_combine_total_stats (FILE *file) |
ccfa01f5 | 13892 | { |
0a81f5a0 | 13893 | fprintf |
ccfa01f5 | 13894 | (file, |
13895 | "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", | |
13896 | total_attempts, total_merges, total_extras, total_successes); | |
13897 | } | |
77fce4cd | 13898 | \f |
77fce4cd | 13899 | /* Try combining insns through substitution. */ |
2a1990e9 | 13900 | static unsigned int |
77fce4cd | 13901 | rest_of_handle_combine (void) |
13902 | { | |
3072d30e | 13903 | int rebuild_jump_labels_after_combine; |
13904 | ||
13905 | df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN); | |
13906 | df_note_add_problem (); | |
13907 | df_analyze (); | |
13908 | ||
13909 | regstat_init_n_sets_and_refs (); | |
13910 | ||
13911 | rebuild_jump_labels_after_combine | |
77fce4cd | 13912 | = combine_instructions (get_insns (), max_reg_num ()); |
13913 | ||
13914 | /* Combining insns may have turned an indirect jump into a | |
13915 | direct jump. Rebuild the JUMP_LABEL fields of jumping | |
13916 | instructions. */ | |
13917 | if (rebuild_jump_labels_after_combine) | |
13918 | { | |
13919 | timevar_push (TV_JUMP); | |
13920 | rebuild_jump_labels (get_insns ()); | |
3072d30e | 13921 | cleanup_cfg (0); |
77fce4cd | 13922 | timevar_pop (TV_JUMP); |
77fce4cd | 13923 | } |
3072d30e | 13924 | |
13925 | regstat_free_n_sets_and_refs (); | |
2a1990e9 | 13926 | return 0; |
77fce4cd | 13927 | } |
13928 | ||
cbe8bda8 | 13929 | namespace { |
13930 | ||
13931 | const pass_data pass_data_combine = | |
77fce4cd | 13932 | { |
cbe8bda8 | 13933 | RTL_PASS, /* type */ |
13934 | "combine", /* name */ | |
13935 | OPTGROUP_NONE, /* optinfo_flags */ | |
cbe8bda8 | 13936 | TV_COMBINE, /* tv_id */ |
13937 | PROP_cfglayout, /* properties_required */ | |
13938 | 0, /* properties_provided */ | |
13939 | 0, /* properties_destroyed */ | |
13940 | 0, /* todo_flags_start */ | |
8b88439e | 13941 | TODO_df_finish, /* todo_flags_finish */ |
77fce4cd | 13942 | }; |
cbe8bda8 | 13943 | |
13944 | class pass_combine : public rtl_opt_pass | |
13945 | { | |
13946 | public: | |
9af5ce0c | 13947 | pass_combine (gcc::context *ctxt) |
13948 | : rtl_opt_pass (pass_data_combine, ctxt) | |
cbe8bda8 | 13949 | {} |
13950 | ||
13951 | /* opt_pass methods: */ | |
31315c24 | 13952 | virtual bool gate (function *) { return (optimize > 0); } |
65b0537f | 13953 | virtual unsigned int execute (function *) |
13954 | { | |
13955 | return rest_of_handle_combine (); | |
13956 | } | |
cbe8bda8 | 13957 | |
13958 | }; // class pass_combine | |
13959 | ||
13960 | } // anon namespace | |
13961 | ||
13962 | rtl_opt_pass * | |
13963 | make_pass_combine (gcc::context *ctxt) | |
13964 | { | |
13965 | return new pass_combine (ctxt); | |
13966 | } |