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230d793d | 1 | /* Optimize by combining instructions for GNU compiler. |
3c71940f | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
505ddab6 | 3 | 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
230d793d | 4 | |
1322177d | 5 | This file is part of GCC. |
230d793d | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
230d793d | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
230d793d RS |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
230d793d | 21 | |
230d793d RS |
22 | /* This module is essentially the "combiner" phase of the U. of Arizona |
23 | Portable Optimizer, but redone to work on our list-structured | |
24 | representation for RTL instead of their string representation. | |
25 | ||
26 | The LOG_LINKS of each insn identify the most recent assignment | |
27 | to each REG used in the insn. It is a list of previous insns, | |
28 | each of which contains a SET for a REG that is used in this insn | |
29 | and not used or set in between. LOG_LINKs never cross basic blocks. | |
30 | They were set up by the preceding pass (lifetime analysis). | |
31 | ||
32 | We try to combine each pair of insns joined by a logical link. | |
33 | We also try to combine triples of insns A, B and C when | |
34 | C has a link back to B and B has a link back to A. | |
35 | ||
36 | LOG_LINKS does not have links for use of the CC0. They don't | |
37 | need to, because the insn that sets the CC0 is always immediately | |
38 | before the insn that tests it. So we always regard a branch | |
39 | insn as having a logical link to the preceding insn. The same is true | |
40 | for an insn explicitly using CC0. | |
41 | ||
42 | We check (with use_crosses_set_p) to avoid combining in such a way | |
43 | as to move a computation to a place where its value would be different. | |
44 | ||
45 | Combination is done by mathematically substituting the previous | |
46 | insn(s) values for the regs they set into the expressions in | |
47 | the later insns that refer to these regs. If the result is a valid insn | |
48 | for our target machine, according to the machine description, | |
49 | we install it, delete the earlier insns, and update the data flow | |
50 | information (LOG_LINKS and REG_NOTES) for what we did. | |
51 | ||
52 | There are a few exceptions where the dataflow information created by | |
53 | flow.c aren't completely updated: | |
54 | ||
55 | - reg_live_length is not updated | |
56 | - reg_n_refs is not adjusted in the rare case when a register is | |
57 | no longer required in a computation | |
58 | - there are extremely rare cases (see distribute_regnotes) when a | |
59 | REG_DEAD note is lost | |
60 | - a LOG_LINKS entry that refers to an insn with multiple SETs may be | |
663522cb | 61 | removed because there is no way to know which register it was |
230d793d RS |
62 | linking |
63 | ||
64 | To simplify substitution, we combine only when the earlier insn(s) | |
65 | consist of only a single assignment. To simplify updating afterward, | |
66 | we never combine when a subroutine call appears in the middle. | |
67 | ||
68 | Since we do not represent assignments to CC0 explicitly except when that | |
69 | is all an insn does, there is no LOG_LINKS entry in an insn that uses | |
70 | the condition code for the insn that set the condition code. | |
71 | Fortunately, these two insns must be consecutive. | |
72 | Therefore, every JUMP_INSN is taken to have an implicit logical link | |
73 | to the preceding insn. This is not quite right, since non-jumps can | |
74 | also use the condition code; but in practice such insns would not | |
75 | combine anyway. */ | |
76 | ||
230d793d | 77 | #include "config.h" |
670ee920 | 78 | #include "system.h" |
c5c76735 | 79 | #include "rtl.h" |
a091679a | 80 | #include "tm_p.h" |
230d793d RS |
81 | #include "flags.h" |
82 | #include "regs.h" | |
55310dad | 83 | #include "hard-reg-set.h" |
230d793d RS |
84 | #include "basic-block.h" |
85 | #include "insn-config.h" | |
49ad7cfa | 86 | #include "function.h" |
ec5c56db | 87 | /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ |
d6f4ec51 | 88 | #include "expr.h" |
230d793d RS |
89 | #include "insn-attr.h" |
90 | #include "recog.h" | |
91 | #include "real.h" | |
2e107e9e | 92 | #include "toplev.h" |
f73ad30e | 93 | |
230d793d RS |
94 | /* It is not safe to use ordinary gen_lowpart in combine. |
95 | Use gen_lowpart_for_combine instead. See comments there. */ | |
96 | #define gen_lowpart dont_use_gen_lowpart_you_dummy | |
97 | ||
98 | /* Number of attempts to combine instructions in this function. */ | |
99 | ||
100 | static int combine_attempts; | |
101 | ||
102 | /* Number of attempts that got as far as substitution in this function. */ | |
103 | ||
104 | static int combine_merges; | |
105 | ||
106 | /* Number of instructions combined with added SETs in this function. */ | |
107 | ||
108 | static int combine_extras; | |
109 | ||
110 | /* Number of instructions combined in this function. */ | |
111 | ||
112 | static int combine_successes; | |
113 | ||
114 | /* Totals over entire compilation. */ | |
115 | ||
116 | static int total_attempts, total_merges, total_extras, total_successes; | |
9210df58 | 117 | |
230d793d RS |
118 | \f |
119 | /* Vector mapping INSN_UIDs to cuids. | |
5089e22e | 120 | The cuids are like uids but increase monotonically always. |
230d793d RS |
121 | Combine always uses cuids so that it can compare them. |
122 | But actually renumbering the uids, which we used to do, | |
123 | proves to be a bad idea because it makes it hard to compare | |
124 | the dumps produced by earlier passes with those from later passes. */ | |
125 | ||
126 | static int *uid_cuid; | |
4255220d | 127 | static int max_uid_cuid; |
230d793d RS |
128 | |
129 | /* Get the cuid of an insn. */ | |
130 | ||
1427d6d2 RK |
131 | #define INSN_CUID(INSN) \ |
132 | (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)]) | |
230d793d | 133 | |
42a6ff51 AO |
134 | /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by |
135 | BITS_PER_WORD would invoke undefined behavior. Work around it. */ | |
136 | ||
137 | #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \ | |
505ddab6 | 138 | (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1) |
42a6ff51 | 139 | |
230d793d RS |
140 | /* Maximum register number, which is the size of the tables below. */ |
141 | ||
770ae6cc | 142 | static unsigned int combine_max_regno; |
230d793d RS |
143 | |
144 | /* Record last point of death of (hard or pseudo) register n. */ | |
145 | ||
146 | static rtx *reg_last_death; | |
147 | ||
148 | /* Record last point of modification of (hard or pseudo) register n. */ | |
149 | ||
150 | static rtx *reg_last_set; | |
151 | ||
152 | /* Record the cuid of the last insn that invalidated memory | |
153 | (anything that writes memory, and subroutine calls, but not pushes). */ | |
154 | ||
155 | static int mem_last_set; | |
156 | ||
157 | /* Record the cuid of the last CALL_INSN | |
158 | so we can tell whether a potential combination crosses any calls. */ | |
159 | ||
160 | static int last_call_cuid; | |
161 | ||
162 | /* When `subst' is called, this is the insn that is being modified | |
163 | (by combining in a previous insn). The PATTERN of this insn | |
164 | is still the old pattern partially modified and it should not be | |
165 | looked at, but this may be used to examine the successors of the insn | |
166 | to judge whether a simplification is valid. */ | |
167 | ||
168 | static rtx subst_insn; | |
169 | ||
0d9641d1 JW |
170 | /* This is an insn that belongs before subst_insn, but is not currently |
171 | on the insn chain. */ | |
172 | ||
173 | static rtx subst_prev_insn; | |
174 | ||
230d793d RS |
175 | /* This is the lowest CUID that `subst' is currently dealing with. |
176 | get_last_value will not return a value if the register was set at or | |
177 | after this CUID. If not for this mechanism, we could get confused if | |
178 | I2 or I1 in try_combine were an insn that used the old value of a register | |
179 | to obtain a new value. In that case, we might erroneously get the | |
180 | new value of the register when we wanted the old one. */ | |
181 | ||
182 | static int subst_low_cuid; | |
183 | ||
6e25d159 RK |
184 | /* This contains any hard registers that are used in newpat; reg_dead_at_p |
185 | must consider all these registers to be always live. */ | |
186 | ||
187 | static HARD_REG_SET newpat_used_regs; | |
188 | ||
abe6e52f RK |
189 | /* This is an insn to which a LOG_LINKS entry has been added. If this |
190 | insn is the earlier than I2 or I3, combine should rescan starting at | |
191 | that location. */ | |
192 | ||
193 | static rtx added_links_insn; | |
194 | ||
f6366fc7 ZD |
195 | /* Basic block in which we are performing combines. */ |
196 | static basic_block this_basic_block; | |
715e7fbc | 197 | |
663522cb KH |
198 | /* A bitmap indicating which blocks had registers go dead at entry. |
199 | After combine, we'll need to re-do global life analysis with | |
715e7fbc RH |
200 | those blocks as starting points. */ |
201 | static sbitmap refresh_blocks; | |
202 | static int need_refresh; | |
230d793d RS |
203 | \f |
204 | /* The next group of arrays allows the recording of the last value assigned | |
205 | to (hard or pseudo) register n. We use this information to see if a | |
5089e22e | 206 | operation being processed is redundant given a prior operation performed |
230d793d RS |
207 | on the register. For example, an `and' with a constant is redundant if |
208 | all the zero bits are already known to be turned off. | |
209 | ||
210 | We use an approach similar to that used by cse, but change it in the | |
211 | following ways: | |
212 | ||
213 | (1) We do not want to reinitialize at each label. | |
214 | (2) It is useful, but not critical, to know the actual value assigned | |
215 | to a register. Often just its form is helpful. | |
216 | ||
217 | Therefore, we maintain the following arrays: | |
218 | ||
219 | reg_last_set_value the last value assigned | |
220 | reg_last_set_label records the value of label_tick when the | |
221 | register was assigned | |
222 | reg_last_set_table_tick records the value of label_tick when a | |
223 | value using the register is assigned | |
da7d8304 | 224 | reg_last_set_invalid set to nonzero when it is not valid |
230d793d RS |
225 | to use the value of this register in some |
226 | register's value | |
227 | ||
228 | To understand the usage of these tables, it is important to understand | |
229 | the distinction between the value in reg_last_set_value being valid | |
230 | and the register being validly contained in some other expression in the | |
231 | table. | |
232 | ||
da7d8304 | 233 | Entry I in reg_last_set_value is valid if it is nonzero, and either |
230d793d RS |
234 | reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick. |
235 | ||
236 | Register I may validly appear in any expression returned for the value | |
237 | of another register if reg_n_sets[i] is 1. It may also appear in the | |
238 | value for register J if reg_last_set_label[i] < reg_last_set_label[j] or | |
239 | reg_last_set_invalid[j] is zero. | |
240 | ||
241 | If an expression is found in the table containing a register which may | |
242 | not validly appear in an expression, the register is replaced by | |
243 | something that won't match, (clobber (const_int 0)). | |
244 | ||
da7d8304 | 245 | reg_last_set_invalid[i] is set nonzero when register I is being assigned |
230d793d RS |
246 | to and reg_last_set_table_tick[i] == label_tick. */ |
247 | ||
0f41302f | 248 | /* Record last value assigned to (hard or pseudo) register n. */ |
230d793d RS |
249 | |
250 | static rtx *reg_last_set_value; | |
251 | ||
252 | /* Record the value of label_tick when the value for register n is placed in | |
253 | reg_last_set_value[n]. */ | |
254 | ||
568356af | 255 | static int *reg_last_set_label; |
230d793d RS |
256 | |
257 | /* Record the value of label_tick when an expression involving register n | |
0f41302f | 258 | is placed in reg_last_set_value. */ |
230d793d | 259 | |
568356af | 260 | static int *reg_last_set_table_tick; |
230d793d | 261 | |
da7d8304 | 262 | /* Set nonzero if references to register n in expressions should not be |
230d793d RS |
263 | used. */ |
264 | ||
265 | static char *reg_last_set_invalid; | |
266 | ||
0f41302f | 267 | /* Incremented for each label. */ |
230d793d | 268 | |
568356af | 269 | static int label_tick; |
230d793d RS |
270 | |
271 | /* Some registers that are set more than once and used in more than one | |
272 | basic block are nevertheless always set in similar ways. For example, | |
273 | a QImode register may be loaded from memory in two places on a machine | |
274 | where byte loads zero extend. | |
275 | ||
951553af | 276 | We record in the following array what we know about the nonzero |
230d793d RS |
277 | bits of a register, specifically which bits are known to be zero. |
278 | ||
279 | If an entry is zero, it means that we don't know anything special. */ | |
280 | ||
55310dad | 281 | static unsigned HOST_WIDE_INT *reg_nonzero_bits; |
230d793d | 282 | |
951553af | 283 | /* Mode used to compute significance in reg_nonzero_bits. It is the largest |
5f4f0e22 | 284 | integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ |
230d793d | 285 | |
951553af | 286 | static enum machine_mode nonzero_bits_mode; |
230d793d | 287 | |
d0ab8cd3 RK |
288 | /* Nonzero if we know that a register has some leading bits that are always |
289 | equal to the sign bit. */ | |
290 | ||
770ae6cc | 291 | static unsigned char *reg_sign_bit_copies; |
d0ab8cd3 | 292 | |
951553af | 293 | /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used. |
1a26b032 RK |
294 | It is zero while computing them and after combine has completed. This |
295 | former test prevents propagating values based on previously set values, | |
296 | which can be incorrect if a variable is modified in a loop. */ | |
230d793d | 297 | |
951553af | 298 | static int nonzero_sign_valid; |
55310dad RK |
299 | |
300 | /* These arrays are maintained in parallel with reg_last_set_value | |
301 | and are used to store the mode in which the register was last set, | |
302 | the bits that were known to be zero when it was last set, and the | |
303 | number of sign bits copies it was known to have when it was last set. */ | |
304 | ||
305 | static enum machine_mode *reg_last_set_mode; | |
306 | static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits; | |
307 | static char *reg_last_set_sign_bit_copies; | |
230d793d RS |
308 | \f |
309 | /* Record one modification to rtl structure | |
310 | to be undone by storing old_contents into *where. | |
311 | is_int is 1 if the contents are an int. */ | |
312 | ||
313 | struct undo | |
314 | { | |
241cea85 | 315 | struct undo *next; |
230d793d | 316 | int is_int; |
3129af4c RS |
317 | union {rtx r; int i;} old_contents; |
318 | union {rtx *r; int *i;} where; | |
230d793d RS |
319 | }; |
320 | ||
321 | /* Record a bunch of changes to be undone, up to MAX_UNDO of them. | |
322 | num_undo says how many are currently recorded. | |
323 | ||
230d793d | 324 | other_insn is nonzero if we have modified some other insn in the process |
f1c6ba8b | 325 | of working on subst_insn. It must be verified too. */ |
230d793d RS |
326 | |
327 | struct undobuf | |
328 | { | |
241cea85 RK |
329 | struct undo *undos; |
330 | struct undo *frees; | |
230d793d RS |
331 | rtx other_insn; |
332 | }; | |
333 | ||
334 | static struct undobuf undobuf; | |
335 | ||
230d793d RS |
336 | /* Number of times the pseudo being substituted for |
337 | was found and replaced. */ | |
338 | ||
339 | static int n_occurrences; | |
340 | ||
83d2b3b9 | 341 | static void do_SUBST PARAMS ((rtx *, rtx)); |
3129af4c | 342 | static void do_SUBST_INT PARAMS ((int *, int)); |
83d2b3b9 KG |
343 | static void init_reg_last_arrays PARAMS ((void)); |
344 | static void setup_incoming_promotions PARAMS ((void)); | |
345 | static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *)); | |
c3410241 | 346 | static int cant_combine_insn_p PARAMS ((rtx)); |
83d2b3b9 KG |
347 | static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *)); |
348 | static int sets_function_arg_p PARAMS ((rtx)); | |
349 | static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *)); | |
350 | static int contains_muldiv PARAMS ((rtx)); | |
44a76fc8 | 351 | static rtx try_combine PARAMS ((rtx, rtx, rtx, int *)); |
83d2b3b9 KG |
352 | static void undo_all PARAMS ((void)); |
353 | static void undo_commit PARAMS ((void)); | |
354 | static rtx *find_split_point PARAMS ((rtx *, rtx)); | |
355 | static rtx subst PARAMS ((rtx, rtx, rtx, int, int)); | |
356 | static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int)); | |
357 | static rtx simplify_if_then_else PARAMS ((rtx)); | |
358 | static rtx simplify_set PARAMS ((rtx)); | |
359 | static rtx simplify_logical PARAMS ((rtx, int)); | |
360 | static rtx expand_compound_operation PARAMS ((rtx)); | |
361 | static rtx expand_field_assignment PARAMS ((rtx)); | |
770ae6cc RK |
362 | static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT, |
363 | rtx, unsigned HOST_WIDE_INT, int, | |
364 | int, int)); | |
83d2b3b9 KG |
365 | static rtx extract_left_shift PARAMS ((rtx, int)); |
366 | static rtx make_compound_operation PARAMS ((rtx, enum rtx_code)); | |
770ae6cc RK |
367 | static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT, |
368 | unsigned HOST_WIDE_INT *)); | |
83d2b3b9 KG |
369 | static rtx force_to_mode PARAMS ((rtx, enum machine_mode, |
370 | unsigned HOST_WIDE_INT, rtx, int)); | |
371 | static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *)); | |
372 | static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx)); | |
373 | static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx)); | |
374 | static rtx make_field_assignment PARAMS ((rtx)); | |
375 | static rtx apply_distributive_law PARAMS ((rtx)); | |
376 | static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx, | |
377 | unsigned HOST_WIDE_INT)); | |
378 | static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode)); | |
770ae6cc | 379 | static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode)); |
83d2b3b9 KG |
380 | static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *, |
381 | enum rtx_code, HOST_WIDE_INT, | |
382 | enum machine_mode, int *)); | |
383 | static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode, | |
384 | rtx, int)); | |
385 | static int recog_for_combine PARAMS ((rtx *, rtx, rtx *)); | |
386 | static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx)); | |
83d2b3b9 KG |
387 | static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode, |
388 | rtx, rtx)); | |
83d2b3b9 | 389 | static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *)); |
83d2b3b9 KG |
390 | static void update_table_tick PARAMS ((rtx)); |
391 | static void record_value_for_reg PARAMS ((rtx, rtx, rtx)); | |
392 | static void check_promoted_subreg PARAMS ((rtx, rtx)); | |
393 | static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *)); | |
394 | static void record_dead_and_set_regs PARAMS ((rtx)); | |
395 | static int get_last_value_validate PARAMS ((rtx *, rtx, int, int)); | |
396 | static rtx get_last_value PARAMS ((rtx)); | |
397 | static int use_crosses_set_p PARAMS ((rtx, int)); | |
398 | static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *)); | |
399 | static int reg_dead_at_p PARAMS ((rtx, rtx)); | |
400 | static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *)); | |
401 | static int reg_bitfield_target_p PARAMS ((rtx, rtx)); | |
402 | static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx)); | |
403 | static void distribute_links PARAMS ((rtx)); | |
404 | static void mark_used_regs_combine PARAMS ((rtx)); | |
405 | static int insn_cuid PARAMS ((rtx)); | |
c6991660 | 406 | static void record_promoted_value PARAMS ((rtx, rtx)); |
9a915772 JH |
407 | static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx)); |
408 | static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx)); | |
230d793d | 409 | \f |
76095e2f RH |
410 | /* Substitute NEWVAL, an rtx expression, into INTO, a place in some |
411 | insn. The substitution can be undone by undo_all. If INTO is already | |
412 | set to NEWVAL, do not record this change. Because computing NEWVAL might | |
413 | also call SUBST, we have to compute it before we put anything into | |
414 | the undo table. */ | |
415 | ||
416 | static void | |
663522cb | 417 | do_SUBST (into, newval) |
76095e2f RH |
418 | rtx *into, newval; |
419 | { | |
420 | struct undo *buf; | |
421 | rtx oldval = *into; | |
422 | ||
423 | if (oldval == newval) | |
424 | return; | |
425 | ||
4161da12 AO |
426 | /* We'd like to catch as many invalid transformations here as |
427 | possible. Unfortunately, there are way too many mode changes | |
428 | that are perfectly valid, so we'd waste too much effort for | |
429 | little gain doing the checks here. Focus on catching invalid | |
430 | transformations involving integer constants. */ | |
431 | if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT | |
432 | && GET_CODE (newval) == CONST_INT) | |
433 | { | |
434 | /* Sanity check that we're replacing oldval with a CONST_INT | |
435 | that is a valid sign-extension for the original mode. */ | |
436 | if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval), | |
437 | GET_MODE (oldval))) | |
438 | abort (); | |
439 | ||
440 | /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a | |
441 | CONST_INT is not valid, because after the replacement, the | |
442 | original mode would be gone. Unfortunately, we can't tell | |
443 | when do_SUBST is called to replace the operand thereof, so we | |
444 | perform this test on oldval instead, checking whether an | |
445 | invalid replacement took place before we got here. */ | |
446 | if ((GET_CODE (oldval) == SUBREG | |
447 | && GET_CODE (SUBREG_REG (oldval)) == CONST_INT) | |
448 | || (GET_CODE (oldval) == ZERO_EXTEND | |
449 | && GET_CODE (XEXP (oldval, 0)) == CONST_INT)) | |
450 | abort (); | |
451 | } | |
452 | ||
76095e2f RH |
453 | if (undobuf.frees) |
454 | buf = undobuf.frees, undobuf.frees = buf->next; | |
455 | else | |
456 | buf = (struct undo *) xmalloc (sizeof (struct undo)); | |
457 | ||
458 | buf->is_int = 0; | |
459 | buf->where.r = into; | |
460 | buf->old_contents.r = oldval; | |
461 | *into = newval; | |
462 | ||
463 | buf->next = undobuf.undos, undobuf.undos = buf; | |
464 | } | |
465 | ||
466 | #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL)) | |
467 | ||
468 | /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution | |
469 | for the value of a HOST_WIDE_INT value (including CONST_INT) is | |
470 | not safe. */ | |
471 | ||
472 | static void | |
663522cb | 473 | do_SUBST_INT (into, newval) |
3129af4c | 474 | int *into, newval; |
76095e2f RH |
475 | { |
476 | struct undo *buf; | |
3129af4c | 477 | int oldval = *into; |
76095e2f RH |
478 | |
479 | if (oldval == newval) | |
480 | return; | |
481 | ||
482 | if (undobuf.frees) | |
483 | buf = undobuf.frees, undobuf.frees = buf->next; | |
484 | else | |
485 | buf = (struct undo *) xmalloc (sizeof (struct undo)); | |
486 | ||
487 | buf->is_int = 1; | |
488 | buf->where.i = into; | |
489 | buf->old_contents.i = oldval; | |
490 | *into = newval; | |
491 | ||
492 | buf->next = undobuf.undos, undobuf.undos = buf; | |
493 | } | |
494 | ||
495 | #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL)) | |
496 | \f | |
230d793d | 497 | /* Main entry point for combiner. F is the first insn of the function. |
663522cb | 498 | NREGS is the first unused pseudo-reg number. |
230d793d | 499 | |
da7d8304 | 500 | Return nonzero if the combiner has turned an indirect jump |
44a76fc8 AG |
501 | instruction into a direct jump. */ |
502 | int | |
230d793d RS |
503 | combine_instructions (f, nregs) |
504 | rtx f; | |
770ae6cc | 505 | unsigned int nregs; |
230d793d | 506 | { |
b3694847 | 507 | rtx insn, next; |
b729186a | 508 | #ifdef HAVE_cc0 |
b3694847 | 509 | rtx prev; |
b729186a | 510 | #endif |
b3694847 SS |
511 | int i; |
512 | rtx links, nextlinks; | |
230d793d | 513 | |
44a76fc8 AG |
514 | int new_direct_jump_p = 0; |
515 | ||
230d793d RS |
516 | combine_attempts = 0; |
517 | combine_merges = 0; | |
518 | combine_extras = 0; | |
519 | combine_successes = 0; | |
520 | ||
521 | combine_max_regno = nregs; | |
522 | ||
663522cb | 523 | reg_nonzero_bits = ((unsigned HOST_WIDE_INT *) |
c05ddfa7 | 524 | xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT))); |
770ae6cc RK |
525 | reg_sign_bit_copies |
526 | = (unsigned char *) xcalloc (nregs, sizeof (unsigned char)); | |
c05ddfa7 MM |
527 | |
528 | reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx)); | |
529 | reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx)); | |
530 | reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx)); | |
531 | reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int)); | |
532 | reg_last_set_label = (int *) xmalloc (nregs * sizeof (int)); | |
533 | reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char)); | |
55310dad | 534 | reg_last_set_mode |
c05ddfa7 | 535 | = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode)); |
55310dad | 536 | reg_last_set_nonzero_bits |
c05ddfa7 | 537 | = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT)); |
55310dad | 538 | reg_last_set_sign_bit_copies |
c05ddfa7 | 539 | = (char *) xmalloc (nregs * sizeof (char)); |
55310dad | 540 | |
ef026f91 | 541 | init_reg_last_arrays (); |
230d793d RS |
542 | |
543 | init_recog_no_volatile (); | |
544 | ||
545 | /* Compute maximum uid value so uid_cuid can be allocated. */ | |
546 | ||
547 | for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) | |
548 | if (INSN_UID (insn) > i) | |
549 | i = INSN_UID (insn); | |
550 | ||
c05ddfa7 | 551 | uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int)); |
4255220d | 552 | max_uid_cuid = i; |
230d793d | 553 | |
951553af | 554 | nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
230d793d | 555 | |
951553af | 556 | /* Don't use reg_nonzero_bits when computing it. This can cause problems |
230d793d RS |
557 | when, for example, we have j <<= 1 in a loop. */ |
558 | ||
951553af | 559 | nonzero_sign_valid = 0; |
230d793d RS |
560 | |
561 | /* Compute the mapping from uids to cuids. | |
562 | Cuids are numbers assigned to insns, like uids, | |
663522cb | 563 | except that cuids increase monotonically through the code. |
230d793d RS |
564 | |
565 | Scan all SETs and see if we can deduce anything about what | |
951553af | 566 | bits are known to be zero for some registers and how many copies |
d79f08e0 RK |
567 | of the sign bit are known to exist for those registers. |
568 | ||
569 | Also set any known values so that we can use it while searching | |
570 | for what bits are known to be set. */ | |
571 | ||
572 | label_tick = 1; | |
230d793d | 573 | |
bcd49eb7 JW |
574 | /* We need to initialize it here, because record_dead_and_set_regs may call |
575 | get_last_value. */ | |
576 | subst_prev_insn = NULL_RTX; | |
577 | ||
7988fd36 RK |
578 | setup_incoming_promotions (); |
579 | ||
d55bc081 | 580 | refresh_blocks = sbitmap_alloc (last_basic_block); |
715e7fbc RH |
581 | sbitmap_zero (refresh_blocks); |
582 | need_refresh = 0; | |
583 | ||
230d793d RS |
584 | for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) |
585 | { | |
4255220d | 586 | uid_cuid[INSN_UID (insn)] = ++i; |
d79f08e0 RK |
587 | subst_low_cuid = i; |
588 | subst_insn = insn; | |
589 | ||
2c3c49de | 590 | if (INSN_P (insn)) |
d79f08e0 | 591 | { |
663522cb | 592 | note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, |
84832317 | 593 | NULL); |
d79f08e0 | 594 | record_dead_and_set_regs (insn); |
2dab894a RK |
595 | |
596 | #ifdef AUTO_INC_DEC | |
597 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
598 | if (REG_NOTE_KIND (links) == REG_INC) | |
84832317 MM |
599 | set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, |
600 | NULL); | |
2dab894a | 601 | #endif |
d79f08e0 RK |
602 | } |
603 | ||
604 | if (GET_CODE (insn) == CODE_LABEL) | |
605 | label_tick++; | |
230d793d RS |
606 | } |
607 | ||
951553af | 608 | nonzero_sign_valid = 1; |
230d793d RS |
609 | |
610 | /* Now scan all the insns in forward order. */ | |
611 | ||
612 | label_tick = 1; | |
613 | last_call_cuid = 0; | |
614 | mem_last_set = 0; | |
ef026f91 | 615 | init_reg_last_arrays (); |
7988fd36 RK |
616 | setup_incoming_promotions (); |
617 | ||
e0082a72 | 618 | FOR_EACH_BB (this_basic_block) |
230d793d | 619 | { |
e0082a72 ZD |
620 | for (insn = this_basic_block->head; |
621 | insn != NEXT_INSN (this_basic_block->end); | |
622 | insn = next ? next : NEXT_INSN (insn)) | |
230d793d | 623 | { |
e0082a72 | 624 | next = 0; |
aabb6c74 | 625 | |
e0082a72 ZD |
626 | if (GET_CODE (insn) == CODE_LABEL) |
627 | label_tick++; | |
aabb6c74 | 628 | |
e0082a72 | 629 | else if (INSN_P (insn)) |
0b17ab2f | 630 | { |
e0082a72 ZD |
631 | /* See if we know about function return values before this |
632 | insn based upon SUBREG flags. */ | |
633 | check_promoted_subreg (insn, PATTERN (insn)); | |
230d793d | 634 | |
e0082a72 | 635 | /* Try this insn with each insn it links back to. */ |
230d793d | 636 | |
e0082a72 ZD |
637 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) |
638 | if ((next = try_combine (insn, XEXP (links, 0), | |
639 | NULL_RTX, &new_direct_jump_p)) != 0) | |
230d793d | 640 | goto retry; |
0b17ab2f | 641 | |
e0082a72 ZD |
642 | /* Try each sequence of three linked insns ending with this one. */ |
643 | ||
644 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
645 | { | |
646 | rtx link = XEXP (links, 0); | |
647 | ||
648 | /* If the linked insn has been replaced by a note, then there | |
649 | is no point in pursuing this chain any further. */ | |
650 | if (GET_CODE (link) == NOTE) | |
651 | continue; | |
652 | ||
653 | for (nextlinks = LOG_LINKS (link); | |
654 | nextlinks; | |
655 | nextlinks = XEXP (nextlinks, 1)) | |
656 | if ((next = try_combine (insn, link, | |
657 | XEXP (nextlinks, 0), | |
658 | &new_direct_jump_p)) != 0) | |
659 | goto retry; | |
660 | } | |
230d793d | 661 | |
9b89393b | 662 | #ifdef HAVE_cc0 |
e0082a72 ZD |
663 | /* Try to combine a jump insn that uses CC0 |
664 | with a preceding insn that sets CC0, and maybe with its | |
665 | logical predecessor as well. | |
666 | This is how we make decrement-and-branch insns. | |
667 | We need this special code because data flow connections | |
668 | via CC0 do not get entered in LOG_LINKS. */ | |
669 | ||
670 | if (GET_CODE (insn) == JUMP_INSN | |
671 | && (prev = prev_nonnote_insn (insn)) != 0 | |
672 | && GET_CODE (prev) == INSN | |
673 | && sets_cc0_p (PATTERN (prev))) | |
674 | { | |
675 | if ((next = try_combine (insn, prev, | |
676 | NULL_RTX, &new_direct_jump_p)) != 0) | |
677 | goto retry; | |
678 | ||
679 | for (nextlinks = LOG_LINKS (prev); nextlinks; | |
680 | nextlinks = XEXP (nextlinks, 1)) | |
681 | if ((next = try_combine (insn, prev, | |
682 | XEXP (nextlinks, 0), | |
683 | &new_direct_jump_p)) != 0) | |
684 | goto retry; | |
685 | } | |
230d793d | 686 | |
e0082a72 ZD |
687 | /* Do the same for an insn that explicitly references CC0. */ |
688 | if (GET_CODE (insn) == INSN | |
689 | && (prev = prev_nonnote_insn (insn)) != 0 | |
690 | && GET_CODE (prev) == INSN | |
691 | && sets_cc0_p (PATTERN (prev)) | |
692 | && GET_CODE (PATTERN (insn)) == SET | |
693 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) | |
694 | { | |
695 | if ((next = try_combine (insn, prev, | |
696 | NULL_RTX, &new_direct_jump_p)) != 0) | |
697 | goto retry; | |
698 | ||
699 | for (nextlinks = LOG_LINKS (prev); nextlinks; | |
700 | nextlinks = XEXP (nextlinks, 1)) | |
701 | if ((next = try_combine (insn, prev, | |
702 | XEXP (nextlinks, 0), | |
703 | &new_direct_jump_p)) != 0) | |
704 | goto retry; | |
705 | } | |
230d793d | 706 | |
e0082a72 ZD |
707 | /* Finally, see if any of the insns that this insn links to |
708 | explicitly references CC0. If so, try this insn, that insn, | |
709 | and its predecessor if it sets CC0. */ | |
710 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
711 | if (GET_CODE (XEXP (links, 0)) == INSN | |
712 | && GET_CODE (PATTERN (XEXP (links, 0))) == SET | |
713 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) | |
714 | && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 | |
715 | && GET_CODE (prev) == INSN | |
716 | && sets_cc0_p (PATTERN (prev)) | |
717 | && (next = try_combine (insn, XEXP (links, 0), | |
718 | prev, &new_direct_jump_p)) != 0) | |
719 | goto retry; | |
9b89393b | 720 | #endif |
e0082a72 ZD |
721 | |
722 | /* Try combining an insn with two different insns whose results it | |
723 | uses. */ | |
724 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
725 | for (nextlinks = XEXP (links, 1); nextlinks; | |
726 | nextlinks = XEXP (nextlinks, 1)) | |
727 | if ((next = try_combine (insn, XEXP (links, 0), | |
728 | XEXP (nextlinks, 0), | |
729 | &new_direct_jump_p)) != 0) | |
730 | goto retry; | |
731 | ||
732 | if (GET_CODE (insn) != NOTE) | |
733 | record_dead_and_set_regs (insn); | |
734 | ||
735 | retry: | |
736 | ; | |
737 | } | |
230d793d RS |
738 | } |
739 | } | |
c51d95ec | 740 | clear_bb_flags (); |
230d793d | 741 | |
f6366fc7 ZD |
742 | EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i, |
743 | BASIC_BLOCK (i)->flags |= BB_DIRTY); | |
c51d95ec | 744 | new_direct_jump_p |= purge_all_dead_edges (0); |
0005550b JH |
745 | delete_noop_moves (f); |
746 | ||
c51d95ec JH |
747 | update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES, |
748 | PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE | |
749 | | PROP_KILL_DEAD_CODE); | |
c05ddfa7 MM |
750 | |
751 | /* Clean up. */ | |
715e7fbc | 752 | sbitmap_free (refresh_blocks); |
c05ddfa7 MM |
753 | free (reg_nonzero_bits); |
754 | free (reg_sign_bit_copies); | |
755 | free (reg_last_death); | |
756 | free (reg_last_set); | |
757 | free (reg_last_set_value); | |
758 | free (reg_last_set_table_tick); | |
759 | free (reg_last_set_label); | |
760 | free (reg_last_set_invalid); | |
761 | free (reg_last_set_mode); | |
762 | free (reg_last_set_nonzero_bits); | |
763 | free (reg_last_set_sign_bit_copies); | |
764 | free (uid_cuid); | |
715e7fbc | 765 | |
e7749837 RH |
766 | { |
767 | struct undo *undo, *next; | |
768 | for (undo = undobuf.frees; undo; undo = next) | |
769 | { | |
770 | next = undo->next; | |
771 | free (undo); | |
772 | } | |
773 | undobuf.frees = 0; | |
774 | } | |
775 | ||
230d793d RS |
776 | total_attempts += combine_attempts; |
777 | total_merges += combine_merges; | |
778 | total_extras += combine_extras; | |
779 | total_successes += combine_successes; | |
1a26b032 | 780 | |
951553af | 781 | nonzero_sign_valid = 0; |
972b320c R |
782 | |
783 | /* Make recognizer allow volatile MEMs again. */ | |
784 | init_recog (); | |
44a76fc8 AG |
785 | |
786 | return new_direct_jump_p; | |
230d793d | 787 | } |
ef026f91 RS |
788 | |
789 | /* Wipe the reg_last_xxx arrays in preparation for another pass. */ | |
790 | ||
791 | static void | |
792 | init_reg_last_arrays () | |
793 | { | |
770ae6cc | 794 | unsigned int nregs = combine_max_regno; |
ef026f91 | 795 | |
961192e1 JM |
796 | memset ((char *) reg_last_death, 0, nregs * sizeof (rtx)); |
797 | memset ((char *) reg_last_set, 0, nregs * sizeof (rtx)); | |
798 | memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx)); | |
799 | memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int)); | |
800 | memset ((char *) reg_last_set_label, 0, nregs * sizeof (int)); | |
801 | memset (reg_last_set_invalid, 0, nregs * sizeof (char)); | |
802 | memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode)); | |
803 | memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT)); | |
804 | memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char)); | |
ef026f91 | 805 | } |
230d793d | 806 | \f |
7988fd36 RK |
807 | /* Set up any promoted values for incoming argument registers. */ |
808 | ||
ee791cc3 | 809 | static void |
7988fd36 RK |
810 | setup_incoming_promotions () |
811 | { | |
812 | #ifdef PROMOTE_FUNCTION_ARGS | |
770ae6cc | 813 | unsigned int regno; |
7988fd36 RK |
814 | rtx reg; |
815 | enum machine_mode mode; | |
816 | int unsignedp; | |
817 | rtx first = get_insns (); | |
818 | ||
c285f57a JJ |
819 | #ifndef OUTGOING_REGNO |
820 | #define OUTGOING_REGNO(N) N | |
821 | #endif | |
7988fd36 | 822 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
c285f57a JJ |
823 | /* Check whether this register can hold an incoming pointer |
824 | argument. FUNCTION_ARG_REGNO_P tests outgoing register | |
825 | numbers, so translate if necessary due to register windows. */ | |
826 | if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno)) | |
7988fd36 | 827 | && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) |
38a448ca RH |
828 | { |
829 | record_value_for_reg | |
830 | (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND | |
831 | : SIGN_EXTEND), | |
832 | GET_MODE (reg), | |
833 | gen_rtx_CLOBBER (mode, const0_rtx))); | |
834 | } | |
7988fd36 RK |
835 | #endif |
836 | } | |
837 | \f | |
91102d5a RK |
838 | /* Called via note_stores. If X is a pseudo that is narrower than |
839 | HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. | |
230d793d RS |
840 | |
841 | If we are setting only a portion of X and we can't figure out what | |
842 | portion, assume all bits will be used since we don't know what will | |
d0ab8cd3 RK |
843 | be happening. |
844 | ||
845 | Similarly, set how many bits of X are known to be copies of the sign bit | |
663522cb | 846 | at all locations in the function. This is the smallest number implied |
d0ab8cd3 | 847 | by any set of X. */ |
230d793d RS |
848 | |
849 | static void | |
84832317 | 850 | set_nonzero_bits_and_sign_copies (x, set, data) |
230d793d RS |
851 | rtx x; |
852 | rtx set; | |
84832317 | 853 | void *data ATTRIBUTE_UNUSED; |
230d793d | 854 | { |
770ae6cc | 855 | unsigned int num; |
d0ab8cd3 | 856 | |
230d793d RS |
857 | if (GET_CODE (x) == REG |
858 | && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
e8095e80 RK |
859 | /* If this register is undefined at the start of the file, we can't |
860 | say what its contents were. */ | |
f6366fc7 | 861 | && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x)) |
5f4f0e22 | 862 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) |
230d793d | 863 | { |
2dab894a | 864 | if (set == 0 || GET_CODE (set) == CLOBBER) |
e8095e80 RK |
865 | { |
866 | reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); | |
88306d12 | 867 | reg_sign_bit_copies[REGNO (x)] = 1; |
e8095e80 RK |
868 | return; |
869 | } | |
230d793d RS |
870 | |
871 | /* If this is a complex assignment, see if we can convert it into a | |
5089e22e | 872 | simple assignment. */ |
230d793d | 873 | set = expand_field_assignment (set); |
d79f08e0 RK |
874 | |
875 | /* If this is a simple assignment, or we have a paradoxical SUBREG, | |
876 | set what we know about X. */ | |
877 | ||
878 | if (SET_DEST (set) == x | |
879 | || (GET_CODE (SET_DEST (set)) == SUBREG | |
705c7b3b JW |
880 | && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) |
881 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) | |
d79f08e0 | 882 | && SUBREG_REG (SET_DEST (set)) == x)) |
d0ab8cd3 | 883 | { |
9afa3d54 RK |
884 | rtx src = SET_SRC (set); |
885 | ||
886 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND | |
887 | /* If X is narrower than a word and SRC is a non-negative | |
888 | constant that would appear negative in the mode of X, | |
889 | sign-extend it for use in reg_nonzero_bits because some | |
890 | machines (maybe most) will actually do the sign-extension | |
663522cb | 891 | and this is the conservative approach. |
9afa3d54 RK |
892 | |
893 | ??? For 2.5, try to tighten up the MD files in this regard | |
894 | instead of this kludge. */ | |
895 | ||
896 | if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD | |
897 | && GET_CODE (src) == CONST_INT | |
898 | && INTVAL (src) > 0 | |
899 | && 0 != (INTVAL (src) | |
900 | & ((HOST_WIDE_INT) 1 | |
9e69be8c | 901 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) |
9afa3d54 RK |
902 | src = GEN_INT (INTVAL (src) |
903 | | ((HOST_WIDE_INT) (-1) | |
904 | << GET_MODE_BITSIZE (GET_MODE (x)))); | |
905 | #endif | |
906 | ||
0a0440c9 JJ |
907 | /* Don't call nonzero_bits if it cannot change anything. */ |
908 | if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0) | |
909 | reg_nonzero_bits[REGNO (x)] | |
910 | |= nonzero_bits (src, nonzero_bits_mode); | |
d0ab8cd3 RK |
911 | num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); |
912 | if (reg_sign_bit_copies[REGNO (x)] == 0 | |
913 | || reg_sign_bit_copies[REGNO (x)] > num) | |
914 | reg_sign_bit_copies[REGNO (x)] = num; | |
915 | } | |
230d793d | 916 | else |
d0ab8cd3 | 917 | { |
951553af | 918 | reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); |
88306d12 | 919 | reg_sign_bit_copies[REGNO (x)] = 1; |
d0ab8cd3 | 920 | } |
230d793d RS |
921 | } |
922 | } | |
923 | \f | |
924 | /* See if INSN can be combined into I3. PRED and SUCC are optionally | |
925 | insns that were previously combined into I3 or that will be combined | |
926 | into the merger of INSN and I3. | |
927 | ||
928 | Return 0 if the combination is not allowed for any reason. | |
929 | ||
663522cb | 930 | If the combination is allowed, *PDEST will be set to the single |
230d793d RS |
931 | destination of INSN and *PSRC to the single source, and this function |
932 | will return 1. */ | |
933 | ||
934 | static int | |
935 | can_combine_p (insn, i3, pred, succ, pdest, psrc) | |
936 | rtx insn; | |
937 | rtx i3; | |
e51712db KG |
938 | rtx pred ATTRIBUTE_UNUSED; |
939 | rtx succ; | |
230d793d RS |
940 | rtx *pdest, *psrc; |
941 | { | |
942 | int i; | |
943 | rtx set = 0, src, dest; | |
b729186a JL |
944 | rtx p; |
945 | #ifdef AUTO_INC_DEC | |
76d31c63 | 946 | rtx link; |
b729186a | 947 | #endif |
230d793d RS |
948 | int all_adjacent = (succ ? (next_active_insn (insn) == succ |
949 | && next_active_insn (succ) == i3) | |
950 | : next_active_insn (insn) == i3); | |
951 | ||
952 | /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. | |
663522cb | 953 | or a PARALLEL consisting of such a SET and CLOBBERs. |
230d793d RS |
954 | |
955 | If INSN has CLOBBER parallel parts, ignore them for our processing. | |
956 | By definition, these happen during the execution of the insn. When it | |
957 | is merged with another insn, all bets are off. If they are, in fact, | |
958 | needed and aren't also supplied in I3, they may be added by | |
663522cb | 959 | recog_for_combine. Otherwise, it won't match. |
230d793d RS |
960 | |
961 | We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED | |
962 | note. | |
963 | ||
663522cb | 964 | Get the source and destination of INSN. If more than one, can't |
230d793d | 965 | combine. */ |
663522cb | 966 | |
230d793d RS |
967 | if (GET_CODE (PATTERN (insn)) == SET) |
968 | set = PATTERN (insn); | |
969 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
970 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
971 | { | |
972 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
973 | { | |
974 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
975 | ||
976 | switch (GET_CODE (elt)) | |
977 | { | |
e3258cef R |
978 | /* This is important to combine floating point insns |
979 | for the SH4 port. */ | |
980 | case USE: | |
981 | /* Combining an isolated USE doesn't make sense. | |
d2604ae9 | 982 | We depend here on combinable_i3pat to reject them. */ |
e3258cef R |
983 | /* The code below this loop only verifies that the inputs of |
984 | the SET in INSN do not change. We call reg_set_between_p | |
eaec9b3d | 985 | to verify that the REG in the USE does not change between |
e3258cef R |
986 | I3 and INSN. |
987 | If the USE in INSN was for a pseudo register, the matching | |
988 | insn pattern will likely match any register; combining this | |
989 | with any other USE would only be safe if we knew that the | |
990 | used registers have identical values, or if there was | |
991 | something to tell them apart, e.g. different modes. For | |
eaec9b3d | 992 | now, we forgo such complicated tests and simply disallow |
e3258cef R |
993 | combining of USES of pseudo registers with any other USE. */ |
994 | if (GET_CODE (XEXP (elt, 0)) == REG | |
995 | && GET_CODE (PATTERN (i3)) == PARALLEL) | |
996 | { | |
997 | rtx i3pat = PATTERN (i3); | |
998 | int i = XVECLEN (i3pat, 0) - 1; | |
770ae6cc RK |
999 | unsigned int regno = REGNO (XEXP (elt, 0)); |
1000 | ||
e3258cef R |
1001 | do |
1002 | { | |
1003 | rtx i3elt = XVECEXP (i3pat, 0, i); | |
770ae6cc | 1004 | |
e3258cef R |
1005 | if (GET_CODE (i3elt) == USE |
1006 | && GET_CODE (XEXP (i3elt, 0)) == REG | |
1007 | && (REGNO (XEXP (i3elt, 0)) == regno | |
1008 | ? reg_set_between_p (XEXP (elt, 0), | |
1009 | PREV_INSN (insn), i3) | |
1010 | : regno >= FIRST_PSEUDO_REGISTER)) | |
1011 | return 0; | |
1012 | } | |
1013 | while (--i >= 0); | |
1014 | } | |
1015 | break; | |
1016 | ||
230d793d RS |
1017 | /* We can ignore CLOBBERs. */ |
1018 | case CLOBBER: | |
1019 | break; | |
1020 | ||
1021 | case SET: | |
1022 | /* Ignore SETs whose result isn't used but not those that | |
1023 | have side-effects. */ | |
1024 | if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) | |
1025 | && ! side_effects_p (elt)) | |
1026 | break; | |
1027 | ||
1028 | /* If we have already found a SET, this is a second one and | |
1029 | so we cannot combine with this insn. */ | |
1030 | if (set) | |
1031 | return 0; | |
1032 | ||
1033 | set = elt; | |
1034 | break; | |
1035 | ||
1036 | default: | |
1037 | /* Anything else means we can't combine. */ | |
1038 | return 0; | |
1039 | } | |
1040 | } | |
1041 | ||
1042 | if (set == 0 | |
1043 | /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, | |
1044 | so don't do anything with it. */ | |
1045 | || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) | |
1046 | return 0; | |
1047 | } | |
1048 | else | |
1049 | return 0; | |
1050 | ||
1051 | if (set == 0) | |
1052 | return 0; | |
1053 | ||
1054 | set = expand_field_assignment (set); | |
1055 | src = SET_SRC (set), dest = SET_DEST (set); | |
1056 | ||
1057 | /* Don't eliminate a store in the stack pointer. */ | |
1058 | if (dest == stack_pointer_rtx | |
230d793d RS |
1059 | /* If we couldn't eliminate a field assignment, we can't combine. */ |
1060 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART | |
1061 | /* Don't combine with an insn that sets a register to itself if it has | |
1062 | a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ | |
5f4f0e22 | 1063 | || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) |
62f7f1f5 GK |
1064 | /* Can't merge an ASM_OPERANDS. */ |
1065 | || GET_CODE (src) == ASM_OPERANDS | |
230d793d RS |
1066 | /* Can't merge a function call. */ |
1067 | || GET_CODE (src) == CALL | |
cd5e8f1f | 1068 | /* Don't eliminate a function call argument. */ |
4dca5ec5 RK |
1069 | || (GET_CODE (i3) == CALL_INSN |
1070 | && (find_reg_fusage (i3, USE, dest) | |
1071 | || (GET_CODE (dest) == REG | |
1072 | && REGNO (dest) < FIRST_PSEUDO_REGISTER | |
1073 | && global_regs[REGNO (dest)]))) | |
230d793d RS |
1074 | /* Don't substitute into an incremented register. */ |
1075 | || FIND_REG_INC_NOTE (i3, dest) | |
1076 | || (succ && FIND_REG_INC_NOTE (succ, dest)) | |
ec35104c | 1077 | #if 0 |
230d793d | 1078 | /* Don't combine the end of a libcall into anything. */ |
ec35104c JL |
1079 | /* ??? This gives worse code, and appears to be unnecessary, since no |
1080 | pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does | |
1081 | use REG_RETVAL notes for noconflict blocks, but other code here | |
1082 | makes sure that those insns don't disappear. */ | |
5f4f0e22 | 1083 | || find_reg_note (insn, REG_RETVAL, NULL_RTX) |
ec35104c | 1084 | #endif |
230d793d RS |
1085 | /* Make sure that DEST is not used after SUCC but before I3. */ |
1086 | || (succ && ! all_adjacent | |
1087 | && reg_used_between_p (dest, succ, i3)) | |
1088 | /* Make sure that the value that is to be substituted for the register | |
1089 | does not use any registers whose values alter in between. However, | |
1090 | If the insns are adjacent, a use can't cross a set even though we | |
1091 | think it might (this can happen for a sequence of insns each setting | |
1092 | the same destination; reg_last_set of that register might point to | |
d81481d3 RK |
1093 | a NOTE). If INSN has a REG_EQUIV note, the register is always |
1094 | equivalent to the memory so the substitution is valid even if there | |
1095 | are intervening stores. Also, don't move a volatile asm or | |
1096 | UNSPEC_VOLATILE across any other insns. */ | |
230d793d | 1097 | || (! all_adjacent |
d81481d3 RK |
1098 | && (((GET_CODE (src) != MEM |
1099 | || ! find_reg_note (insn, REG_EQUIV, src)) | |
1100 | && use_crosses_set_p (src, INSN_CUID (insn))) | |
a66a10c7 RS |
1101 | || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) |
1102 | || GET_CODE (src) == UNSPEC_VOLATILE)) | |
230d793d RS |
1103 | /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get |
1104 | better register allocation by not doing the combine. */ | |
1105 | || find_reg_note (i3, REG_NO_CONFLICT, dest) | |
1106 | || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) | |
1107 | /* Don't combine across a CALL_INSN, because that would possibly | |
1108 | change whether the life span of some REGs crosses calls or not, | |
1109 | and it is a pain to update that information. | |
1110 | Exception: if source is a constant, moving it later can't hurt. | |
1111 | Accept that special case, because it helps -fforce-addr a lot. */ | |
1112 | || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) | |
1113 | return 0; | |
1114 | ||
1115 | /* DEST must either be a REG or CC0. */ | |
1116 | if (GET_CODE (dest) == REG) | |
1117 | { | |
1118 | /* If register alignment is being enforced for multi-word items in all | |
1119 | cases except for parameters, it is possible to have a register copy | |
1120 | insn referencing a hard register that is not allowed to contain the | |
1121 | mode being copied and which would not be valid as an operand of most | |
1122 | insns. Eliminate this problem by not combining with such an insn. | |
1123 | ||
1124 | Also, on some machines we don't want to extend the life of a hard | |
53895717 | 1125 | register. */ |
230d793d RS |
1126 | |
1127 | if (GET_CODE (src) == REG | |
1128 | && ((REGNO (dest) < FIRST_PSEUDO_REGISTER | |
1129 | && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) | |
c448a43e RK |
1130 | /* Don't extend the life of a hard register unless it is |
1131 | user variable (if we have few registers) or it can't | |
1132 | fit into the desired register (meaning something special | |
ecd40809 RK |
1133 | is going on). |
1134 | Also avoid substituting a return register into I3, because | |
1135 | reload can't handle a conflict with constraints of other | |
1136 | inputs. */ | |
230d793d | 1137 | || (REGNO (src) < FIRST_PSEUDO_REGISTER |
53895717 | 1138 | && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) |
230d793d RS |
1139 | return 0; |
1140 | } | |
1141 | else if (GET_CODE (dest) != CC0) | |
1142 | return 0; | |
1143 | ||
5f96750d RS |
1144 | /* Don't substitute for a register intended as a clobberable operand. |
1145 | Similarly, don't substitute an expression containing a register that | |
1146 | will be clobbered in I3. */ | |
230d793d RS |
1147 | if (GET_CODE (PATTERN (i3)) == PARALLEL) |
1148 | for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) | |
1149 | if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER | |
5f96750d RS |
1150 | && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), |
1151 | src) | |
1152 | || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))) | |
230d793d RS |
1153 | return 0; |
1154 | ||
1155 | /* If INSN contains anything volatile, or is an `asm' (whether volatile | |
d276f2bb | 1156 | or not), reject, unless nothing volatile comes between it and I3 */ |
230d793d RS |
1157 | |
1158 | if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) | |
d276f2bb CM |
1159 | { |
1160 | /* Make sure succ doesn't contain a volatile reference. */ | |
1161 | if (succ != 0 && volatile_refs_p (PATTERN (succ))) | |
1162 | return 0; | |
663522cb | 1163 | |
d276f2bb | 1164 | for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) |
2c3c49de | 1165 | if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p))) |
cf0d9408 | 1166 | return 0; |
d276f2bb | 1167 | } |
230d793d | 1168 | |
b79ee7eb RH |
1169 | /* If INSN is an asm, and DEST is a hard register, reject, since it has |
1170 | to be an explicit register variable, and was chosen for a reason. */ | |
1171 | ||
1172 | if (GET_CODE (src) == ASM_OPERANDS | |
1173 | && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
1174 | return 0; | |
1175 | ||
4b2cb4a2 RS |
1176 | /* If there are any volatile insns between INSN and I3, reject, because |
1177 | they might affect machine state. */ | |
1178 | ||
1179 | for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) | |
2c3c49de | 1180 | if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p))) |
4b2cb4a2 RS |
1181 | return 0; |
1182 | ||
230d793d RS |
1183 | /* If INSN or I2 contains an autoincrement or autodecrement, |
1184 | make sure that register is not used between there and I3, | |
1185 | and not already used in I3 either. | |
1186 | Also insist that I3 not be a jump; if it were one | |
1187 | and the incremented register were spilled, we would lose. */ | |
1188 | ||
1189 | #ifdef AUTO_INC_DEC | |
1190 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1191 | if (REG_NOTE_KIND (link) == REG_INC | |
1192 | && (GET_CODE (i3) == JUMP_INSN | |
1193 | || reg_used_between_p (XEXP (link, 0), insn, i3) | |
1194 | || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) | |
1195 | return 0; | |
1196 | #endif | |
1197 | ||
1198 | #ifdef HAVE_cc0 | |
1199 | /* Don't combine an insn that follows a CC0-setting insn. | |
1200 | An insn that uses CC0 must not be separated from the one that sets it. | |
1201 | We do, however, allow I2 to follow a CC0-setting insn if that insn | |
1202 | is passed as I1; in that case it will be deleted also. | |
1203 | We also allow combining in this case if all the insns are adjacent | |
1204 | because that would leave the two CC0 insns adjacent as well. | |
1205 | It would be more logical to test whether CC0 occurs inside I1 or I2, | |
1206 | but that would be much slower, and this ought to be equivalent. */ | |
1207 | ||
1208 | p = prev_nonnote_insn (insn); | |
1209 | if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p)) | |
1210 | && ! all_adjacent) | |
1211 | return 0; | |
1212 | #endif | |
1213 | ||
1214 | /* If we get here, we have passed all the tests and the combination is | |
1215 | to be allowed. */ | |
1216 | ||
1217 | *pdest = dest; | |
1218 | *psrc = src; | |
1219 | ||
1220 | return 1; | |
1221 | } | |
1222 | \f | |
956d6950 JL |
1223 | /* Check if PAT is an insn - or a part of it - used to set up an |
1224 | argument for a function in a hard register. */ | |
1225 | ||
1226 | static int | |
1227 | sets_function_arg_p (pat) | |
1228 | rtx pat; | |
1229 | { | |
1230 | int i; | |
1231 | rtx inner_dest; | |
1232 | ||
1233 | switch (GET_CODE (pat)) | |
1234 | { | |
1235 | case INSN: | |
1236 | return sets_function_arg_p (PATTERN (pat)); | |
1237 | ||
1238 | case PARALLEL: | |
1239 | for (i = XVECLEN (pat, 0); --i >= 0;) | |
1240 | if (sets_function_arg_p (XVECEXP (pat, 0, i))) | |
1241 | return 1; | |
1242 | ||
1243 | break; | |
1244 | ||
1245 | case SET: | |
1246 | inner_dest = SET_DEST (pat); | |
1247 | while (GET_CODE (inner_dest) == STRICT_LOW_PART | |
1248 | || GET_CODE (inner_dest) == SUBREG | |
1249 | || GET_CODE (inner_dest) == ZERO_EXTRACT) | |
1250 | inner_dest = XEXP (inner_dest, 0); | |
1251 | ||
1252 | return (GET_CODE (inner_dest) == REG | |
1253 | && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER | |
1254 | && FUNCTION_ARG_REGNO_P (REGNO (inner_dest))); | |
1d300e19 KG |
1255 | |
1256 | default: | |
1257 | break; | |
956d6950 JL |
1258 | } |
1259 | ||
1260 | return 0; | |
1261 | } | |
1262 | ||
230d793d RS |
1263 | /* LOC is the location within I3 that contains its pattern or the component |
1264 | of a PARALLEL of the pattern. We validate that it is valid for combining. | |
1265 | ||
1266 | One problem is if I3 modifies its output, as opposed to replacing it | |
1267 | entirely, we can't allow the output to contain I2DEST or I1DEST as doing | |
1268 | so would produce an insn that is not equivalent to the original insns. | |
1269 | ||
1270 | Consider: | |
1271 | ||
1272 | (set (reg:DI 101) (reg:DI 100)) | |
1273 | (set (subreg:SI (reg:DI 101) 0) <foo>) | |
1274 | ||
1275 | This is NOT equivalent to: | |
1276 | ||
1277 | (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) | |
23190837 | 1278 | (set (reg:DI 101) (reg:DI 100))]) |
230d793d RS |
1279 | |
1280 | Not only does this modify 100 (in which case it might still be valid | |
663522cb | 1281 | if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. |
230d793d RS |
1282 | |
1283 | We can also run into a problem if I2 sets a register that I1 | |
1284 | uses and I1 gets directly substituted into I3 (not via I2). In that | |
1285 | case, we would be getting the wrong value of I2DEST into I3, so we | |
1286 | must reject the combination. This case occurs when I2 and I1 both | |
1287 | feed into I3, rather than when I1 feeds into I2, which feeds into I3. | |
da7d8304 | 1288 | If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source |
230d793d RS |
1289 | of a SET must prevent combination from occurring. |
1290 | ||
230d793d RS |
1291 | Before doing the above check, we first try to expand a field assignment |
1292 | into a set of logical operations. | |
1293 | ||
da7d8304 | 1294 | If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which |
230d793d RS |
1295 | we place a register that is both set and used within I3. If more than one |
1296 | such register is detected, we fail. | |
1297 | ||
1298 | Return 1 if the combination is valid, zero otherwise. */ | |
1299 | ||
1300 | static int | |
1301 | combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed) | |
1302 | rtx i3; | |
1303 | rtx *loc; | |
1304 | rtx i2dest; | |
1305 | rtx i1dest; | |
1306 | int i1_not_in_src; | |
1307 | rtx *pi3dest_killed; | |
1308 | { | |
1309 | rtx x = *loc; | |
1310 | ||
1311 | if (GET_CODE (x) == SET) | |
1312 | { | |
1313 | rtx set = expand_field_assignment (x); | |
1314 | rtx dest = SET_DEST (set); | |
1315 | rtx src = SET_SRC (set); | |
29a82058 | 1316 | rtx inner_dest = dest; |
663522cb | 1317 | |
29a82058 JL |
1318 | #if 0 |
1319 | rtx inner_src = src; | |
1320 | #endif | |
230d793d RS |
1321 | |
1322 | SUBST (*loc, set); | |
1323 | ||
1324 | while (GET_CODE (inner_dest) == STRICT_LOW_PART | |
1325 | || GET_CODE (inner_dest) == SUBREG | |
1326 | || GET_CODE (inner_dest) == ZERO_EXTRACT) | |
1327 | inner_dest = XEXP (inner_dest, 0); | |
1328 | ||
1329 | /* We probably don't need this any more now that LIMIT_RELOAD_CLASS | |
1330 | was added. */ | |
1331 | #if 0 | |
1332 | while (GET_CODE (inner_src) == STRICT_LOW_PART | |
1333 | || GET_CODE (inner_src) == SUBREG | |
1334 | || GET_CODE (inner_src) == ZERO_EXTRACT) | |
1335 | inner_src = XEXP (inner_src, 0); | |
1336 | ||
1337 | /* If it is better that two different modes keep two different pseudos, | |
1338 | avoid combining them. This avoids producing the following pattern | |
1339 | on a 386: | |
1340 | (set (subreg:SI (reg/v:QI 21) 0) | |
1341 | (lshiftrt:SI (reg/v:SI 20) | |
1342 | (const_int 24))) | |
1343 | If that were made, reload could not handle the pair of | |
1344 | reg 20/21, since it would try to get any GENERAL_REGS | |
1345 | but some of them don't handle QImode. */ | |
1346 | ||
1347 | if (rtx_equal_p (inner_src, i2dest) | |
1348 | && GET_CODE (inner_dest) == REG | |
1349 | && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest))) | |
1350 | return 0; | |
1351 | #endif | |
1352 | ||
1353 | /* Check for the case where I3 modifies its output, as | |
1354 | discussed above. */ | |
1355 | if ((inner_dest != dest | |
1356 | && (reg_overlap_mentioned_p (i2dest, inner_dest) | |
1357 | || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) | |
956d6950 | 1358 | |
53895717 BS |
1359 | /* This is the same test done in can_combine_p except we can't test |
1360 | all_adjacent; we don't have to, since this instruction will stay | |
1361 | in place, thus we are not considering increasing the lifetime of | |
1362 | INNER_DEST. | |
956d6950 JL |
1363 | |
1364 | Also, if this insn sets a function argument, combining it with | |
1365 | something that might need a spill could clobber a previous | |
1366 | function argument; the all_adjacent test in can_combine_p also | |
1367 | checks this; here, we do a more specific test for this case. */ | |
663522cb | 1368 | |
230d793d | 1369 | || (GET_CODE (inner_dest) == REG |
dfbe1b2f | 1370 | && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER |
c448a43e | 1371 | && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), |
53895717 | 1372 | GET_MODE (inner_dest)))) |
230d793d RS |
1373 | || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) |
1374 | return 0; | |
1375 | ||
1376 | /* If DEST is used in I3, it is being killed in this insn, | |
663522cb | 1377 | so record that for later. |
36a9c2e9 JL |
1378 | Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the |
1379 | STACK_POINTER_REGNUM, since these are always considered to be | |
1380 | live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ | |
230d793d | 1381 | if (pi3dest_killed && GET_CODE (dest) == REG |
36a9c2e9 JL |
1382 | && reg_referenced_p (dest, PATTERN (i3)) |
1383 | && REGNO (dest) != FRAME_POINTER_REGNUM | |
6d7096b0 DE |
1384 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
1385 | && REGNO (dest) != HARD_FRAME_POINTER_REGNUM | |
1386 | #endif | |
36a9c2e9 JL |
1387 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM |
1388 | && (REGNO (dest) != ARG_POINTER_REGNUM | |
1389 | || ! fixed_regs [REGNO (dest)]) | |
1390 | #endif | |
1391 | && REGNO (dest) != STACK_POINTER_REGNUM) | |
230d793d RS |
1392 | { |
1393 | if (*pi3dest_killed) | |
1394 | return 0; | |
1395 | ||
1396 | *pi3dest_killed = dest; | |
1397 | } | |
1398 | } | |
1399 | ||
1400 | else if (GET_CODE (x) == PARALLEL) | |
1401 | { | |
1402 | int i; | |
1403 | ||
1404 | for (i = 0; i < XVECLEN (x, 0); i++) | |
1405 | if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, | |
1406 | i1_not_in_src, pi3dest_killed)) | |
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | return 1; | |
1411 | } | |
1412 | \f | |
14a774a9 RK |
1413 | /* Return 1 if X is an arithmetic expression that contains a multiplication |
1414 | and division. We don't count multiplications by powers of two here. */ | |
1415 | ||
1416 | static int | |
1417 | contains_muldiv (x) | |
1418 | rtx x; | |
1419 | { | |
1420 | switch (GET_CODE (x)) | |
1421 | { | |
1422 | case MOD: case DIV: case UMOD: case UDIV: | |
1423 | return 1; | |
1424 | ||
1425 | case MULT: | |
1426 | return ! (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1427 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0); | |
1428 | default: | |
1429 | switch (GET_RTX_CLASS (GET_CODE (x))) | |
1430 | { | |
1431 | case 'c': case '<': case '2': | |
1432 | return contains_muldiv (XEXP (x, 0)) | |
1433 | || contains_muldiv (XEXP (x, 1)); | |
1434 | ||
1435 | case '1': | |
1436 | return contains_muldiv (XEXP (x, 0)); | |
1437 | ||
1438 | default: | |
1439 | return 0; | |
1440 | } | |
1441 | } | |
1442 | } | |
1443 | \f | |
c3410241 BS |
1444 | /* Determine whether INSN can be used in a combination. Return nonzero if |
1445 | not. This is used in try_combine to detect early some cases where we | |
1446 | can't perform combinations. */ | |
1447 | ||
1448 | static int | |
1449 | cant_combine_insn_p (insn) | |
1450 | rtx insn; | |
1451 | { | |
1452 | rtx set; | |
1453 | rtx src, dest; | |
23190837 | 1454 | |
c3410241 BS |
1455 | /* If this isn't really an insn, we can't do anything. |
1456 | This can occur when flow deletes an insn that it has merged into an | |
1457 | auto-increment address. */ | |
1458 | if (! INSN_P (insn)) | |
1459 | return 1; | |
1460 | ||
4c11675d DJ |
1461 | /* Never combine loads and stores involving hard regs. The register |
1462 | allocator can usually handle such reg-reg moves by tying. If we allow | |
1463 | the combiner to make substitutions of hard regs, we risk aborting in | |
1464 | reload on machines that have SMALL_REGISTER_CLASSES. | |
c3410241 BS |
1465 | As an exception, we allow combinations involving fixed regs; these are |
1466 | not available to the register allocator so there's no risk involved. */ | |
1467 | ||
1468 | set = single_set (insn); | |
1469 | if (! set) | |
1470 | return 0; | |
1471 | src = SET_SRC (set); | |
1472 | dest = SET_DEST (set); | |
ad334b51 JH |
1473 | if (GET_CODE (src) == SUBREG) |
1474 | src = SUBREG_REG (src); | |
1475 | if (GET_CODE (dest) == SUBREG) | |
1476 | dest = SUBREG_REG (dest); | |
53895717 BS |
1477 | if (REG_P (src) && REG_P (dest) |
1478 | && ((REGNO (src) < FIRST_PSEUDO_REGISTER | |
4c11675d | 1479 | && ! fixed_regs[REGNO (src)]) |
53895717 | 1480 | || (REGNO (dest) < FIRST_PSEUDO_REGISTER |
4c11675d | 1481 | && ! fixed_regs[REGNO (dest)]))) |
c3410241 | 1482 | return 1; |
53895717 | 1483 | |
c3410241 BS |
1484 | return 0; |
1485 | } | |
1486 | ||
230d793d RS |
1487 | /* Try to combine the insns I1 and I2 into I3. |
1488 | Here I1 and I2 appear earlier than I3. | |
1489 | I1 can be zero; then we combine just I2 into I3. | |
663522cb | 1490 | |
04956a1a | 1491 | If we are combining three insns and the resulting insn is not recognized, |
230d793d RS |
1492 | try splitting it into two insns. If that happens, I2 and I3 are retained |
1493 | and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 | |
1494 | are pseudo-deleted. | |
1495 | ||
663522cb | 1496 | Return 0 if the combination does not work. Then nothing is changed. |
abe6e52f | 1497 | If we did the combination, return the insn at which combine should |
663522cb KH |
1498 | resume scanning. |
1499 | ||
da7d8304 | 1500 | Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a |
44a76fc8 | 1501 | new direct jump instruction. */ |
230d793d RS |
1502 | |
1503 | static rtx | |
44a76fc8 | 1504 | try_combine (i3, i2, i1, new_direct_jump_p) |
b3694847 SS |
1505 | rtx i3, i2, i1; |
1506 | int *new_direct_jump_p; | |
230d793d | 1507 | { |
02359929 | 1508 | /* New patterns for I3 and I2, respectively. */ |
230d793d | 1509 | rtx newpat, newi2pat = 0; |
cddd8b72 | 1510 | int substed_i2 = 0, substed_i1 = 0; |
230d793d RS |
1511 | /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ |
1512 | int added_sets_1, added_sets_2; | |
1513 | /* Total number of SETs to put into I3. */ | |
1514 | int total_sets; | |
1515 | /* Nonzero is I2's body now appears in I3. */ | |
1516 | int i2_is_used; | |
1517 | /* INSN_CODEs for new I3, new I2, and user of condition code. */ | |
6a651371 | 1518 | int insn_code_number, i2_code_number = 0, other_code_number = 0; |
230d793d RS |
1519 | /* Contains I3 if the destination of I3 is used in its source, which means |
1520 | that the old life of I3 is being killed. If that usage is placed into | |
1521 | I2 and not in I3, a REG_DEAD note must be made. */ | |
1522 | rtx i3dest_killed = 0; | |
1523 | /* SET_DEST and SET_SRC of I2 and I1. */ | |
1524 | rtx i2dest, i2src, i1dest = 0, i1src = 0; | |
1525 | /* PATTERN (I2), or a copy of it in certain cases. */ | |
1526 | rtx i2pat; | |
1527 | /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ | |
c4e861e8 | 1528 | int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; |
230d793d RS |
1529 | int i1_feeds_i3 = 0; |
1530 | /* Notes that must be added to REG_NOTES in I3 and I2. */ | |
1531 | rtx new_i3_notes, new_i2_notes; | |
176c9e6b JW |
1532 | /* Notes that we substituted I3 into I2 instead of the normal case. */ |
1533 | int i3_subst_into_i2 = 0; | |
df7d75de RK |
1534 | /* Notes that I1, I2 or I3 is a MULT operation. */ |
1535 | int have_mult = 0; | |
230d793d RS |
1536 | |
1537 | int maxreg; | |
1538 | rtx temp; | |
b3694847 | 1539 | rtx link; |
230d793d RS |
1540 | int i; |
1541 | ||
c3410241 BS |
1542 | /* Exit early if one of the insns involved can't be used for |
1543 | combinations. */ | |
1544 | if (cant_combine_insn_p (i3) | |
1545 | || cant_combine_insn_p (i2) | |
1546 | || (i1 && cant_combine_insn_p (i1)) | |
1547 | /* We also can't do anything if I3 has a | |
1548 | REG_LIBCALL note since we don't want to disrupt the contiguity of a | |
1549 | libcall. */ | |
ec35104c JL |
1550 | #if 0 |
1551 | /* ??? This gives worse code, and appears to be unnecessary, since no | |
1552 | pass after flow uses REG_LIBCALL/REG_RETVAL notes. */ | |
1553 | || find_reg_note (i3, REG_LIBCALL, NULL_RTX) | |
1554 | #endif | |
663522cb | 1555 | ) |
230d793d RS |
1556 | return 0; |
1557 | ||
1558 | combine_attempts++; | |
230d793d RS |
1559 | undobuf.other_insn = 0; |
1560 | ||
6e25d159 RK |
1561 | /* Reset the hard register usage information. */ |
1562 | CLEAR_HARD_REG_SET (newpat_used_regs); | |
1563 | ||
230d793d RS |
1564 | /* If I1 and I2 both feed I3, they can be in any order. To simplify the |
1565 | code below, set I1 to be the earlier of the two insns. */ | |
1566 | if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) | |
1567 | temp = i1, i1 = i2, i2 = temp; | |
1568 | ||
abe6e52f | 1569 | added_links_insn = 0; |
137e889e | 1570 | |
230d793d | 1571 | /* First check for one important special-case that the code below will |
c7be4f66 | 1572 | not handle. Namely, the case where I1 is zero, I2 is a PARALLEL |
230d793d RS |
1573 | and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, |
1574 | we may be able to replace that destination with the destination of I3. | |
1575 | This occurs in the common code where we compute both a quotient and | |
1576 | remainder into a structure, in which case we want to do the computation | |
1577 | directly into the structure to avoid register-register copies. | |
1578 | ||
c7be4f66 RK |
1579 | Note that this case handles both multiple sets in I2 and also |
1580 | cases where I2 has a number of CLOBBER or PARALLELs. | |
1581 | ||
230d793d RS |
1582 | We make very conservative checks below and only try to handle the |
1583 | most common cases of this. For example, we only handle the case | |
1584 | where I2 and I3 are adjacent to avoid making difficult register | |
1585 | usage tests. */ | |
1586 | ||
1587 | if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET | |
1588 | && GET_CODE (SET_SRC (PATTERN (i3))) == REG | |
1589 | && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER | |
230d793d RS |
1590 | && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) |
1591 | && GET_CODE (PATTERN (i2)) == PARALLEL | |
1592 | && ! side_effects_p (SET_DEST (PATTERN (i3))) | |
5089e22e RS |
1593 | /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code |
1594 | below would need to check what is inside (and reg_overlap_mentioned_p | |
1595 | doesn't support those codes anyway). Don't allow those destinations; | |
1596 | the resulting insn isn't likely to be recognized anyway. */ | |
1597 | && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT | |
1598 | && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART | |
230d793d RS |
1599 | && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), |
1600 | SET_DEST (PATTERN (i3))) | |
1601 | && next_real_insn (i2) == i3) | |
5089e22e RS |
1602 | { |
1603 | rtx p2 = PATTERN (i2); | |
1604 | ||
1605 | /* Make sure that the destination of I3, | |
1606 | which we are going to substitute into one output of I2, | |
1607 | is not used within another output of I2. We must avoid making this: | |
1608 | (parallel [(set (mem (reg 69)) ...) | |
1609 | (set (reg 69) ...)]) | |
1610 | which is not well-defined as to order of actions. | |
1611 | (Besides, reload can't handle output reloads for this.) | |
1612 | ||
1613 | The problem can also happen if the dest of I3 is a memory ref, | |
1614 | if another dest in I2 is an indirect memory ref. */ | |
1615 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
7ca919b7 RK |
1616 | if ((GET_CODE (XVECEXP (p2, 0, i)) == SET |
1617 | || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
5089e22e RS |
1618 | && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), |
1619 | SET_DEST (XVECEXP (p2, 0, i)))) | |
1620 | break; | |
230d793d | 1621 | |
5089e22e RS |
1622 | if (i == XVECLEN (p2, 0)) |
1623 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
481c7efa FS |
1624 | if ((GET_CODE (XVECEXP (p2, 0, i)) == SET |
1625 | || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
1626 | && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) | |
5089e22e RS |
1627 | { |
1628 | combine_merges++; | |
230d793d | 1629 | |
5089e22e RS |
1630 | subst_insn = i3; |
1631 | subst_low_cuid = INSN_CUID (i2); | |
230d793d | 1632 | |
c4e861e8 | 1633 | added_sets_2 = added_sets_1 = 0; |
5089e22e | 1634 | i2dest = SET_SRC (PATTERN (i3)); |
230d793d | 1635 | |
5089e22e RS |
1636 | /* Replace the dest in I2 with our dest and make the resulting |
1637 | insn the new pattern for I3. Then skip to where we | |
1638 | validate the pattern. Everything was set up above. */ | |
663522cb | 1639 | SUBST (SET_DEST (XVECEXP (p2, 0, i)), |
5089e22e RS |
1640 | SET_DEST (PATTERN (i3))); |
1641 | ||
1642 | newpat = p2; | |
176c9e6b | 1643 | i3_subst_into_i2 = 1; |
5089e22e RS |
1644 | goto validate_replacement; |
1645 | } | |
1646 | } | |
230d793d | 1647 | |
667c1c2c RK |
1648 | /* If I2 is setting a double-word pseudo to a constant and I3 is setting |
1649 | one of those words to another constant, merge them by making a new | |
1650 | constant. */ | |
1651 | if (i1 == 0 | |
1652 | && (temp = single_set (i2)) != 0 | |
1653 | && (GET_CODE (SET_SRC (temp)) == CONST_INT | |
1654 | || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE) | |
1655 | && GET_CODE (SET_DEST (temp)) == REG | |
1656 | && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT | |
1657 | && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD | |
1658 | && GET_CODE (PATTERN (i3)) == SET | |
1659 | && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG | |
1660 | && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp) | |
1661 | && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT | |
1662 | && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD | |
1663 | && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT) | |
1664 | { | |
1665 | HOST_WIDE_INT lo, hi; | |
1666 | ||
1667 | if (GET_CODE (SET_SRC (temp)) == CONST_INT) | |
1668 | lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0; | |
1669 | else | |
1670 | { | |
1671 | lo = CONST_DOUBLE_LOW (SET_SRC (temp)); | |
1672 | hi = CONST_DOUBLE_HIGH (SET_SRC (temp)); | |
1673 | } | |
1674 | ||
1675 | if (subreg_lowpart_p (SET_DEST (PATTERN (i3)))) | |
48b4d901 AO |
1676 | { |
1677 | /* We don't handle the case of the target word being wider | |
1678 | than a host wide int. */ | |
1679 | if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD) | |
1680 | abort (); | |
1681 | ||
42a6ff51 | 1682 | lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1); |
2ef1a7f9 GK |
1683 | lo |= (INTVAL (SET_SRC (PATTERN (i3))) |
1684 | & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); | |
48b4d901 AO |
1685 | } |
1686 | else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
667c1c2c | 1687 | hi = INTVAL (SET_SRC (PATTERN (i3))); |
48b4d901 AO |
1688 | else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD) |
1689 | { | |
1690 | int sign = -(int) ((unsigned HOST_WIDE_INT) lo | |
1691 | >> (HOST_BITS_PER_WIDE_INT - 1)); | |
1692 | ||
42a6ff51 AO |
1693 | lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD |
1694 | (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); | |
1695 | lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD | |
1696 | (INTVAL (SET_SRC (PATTERN (i3))))); | |
48b4d901 AO |
1697 | if (hi == sign) |
1698 | hi = lo < 0 ? -1 : 0; | |
1699 | } | |
1700 | else | |
1701 | /* We don't handle the case of the higher word not fitting | |
1702 | entirely in either hi or lo. */ | |
1703 | abort (); | |
667c1c2c RK |
1704 | |
1705 | combine_merges++; | |
1706 | subst_insn = i3; | |
1707 | subst_low_cuid = INSN_CUID (i2); | |
1708 | added_sets_2 = added_sets_1 = 0; | |
1709 | i2dest = SET_DEST (temp); | |
1710 | ||
1711 | SUBST (SET_SRC (temp), | |
1712 | immed_double_const (lo, hi, GET_MODE (SET_DEST (temp)))); | |
1713 | ||
1714 | newpat = PATTERN (i2); | |
667c1c2c RK |
1715 | goto validate_replacement; |
1716 | } | |
1717 | ||
230d793d RS |
1718 | #ifndef HAVE_cc0 |
1719 | /* If we have no I1 and I2 looks like: | |
1720 | (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) | |
1721 | (set Y OP)]) | |
1722 | make up a dummy I1 that is | |
1723 | (set Y OP) | |
1724 | and change I2 to be | |
1725 | (set (reg:CC X) (compare:CC Y (const_int 0))) | |
1726 | ||
1727 | (We can ignore any trailing CLOBBERs.) | |
1728 | ||
1729 | This undoes a previous combination and allows us to match a branch-and- | |
1730 | decrement insn. */ | |
1731 | ||
1732 | if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL | |
1733 | && XVECLEN (PATTERN (i2), 0) >= 2 | |
1734 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET | |
1735 | && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) | |
1736 | == MODE_CC) | |
1737 | && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE | |
1738 | && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx | |
1739 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET | |
1740 | && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG | |
1741 | && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), | |
1742 | SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) | |
1743 | { | |
663522cb | 1744 | for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) |
230d793d RS |
1745 | if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) |
1746 | break; | |
1747 | ||
1748 | if (i == 1) | |
1749 | { | |
1750 | /* We make I1 with the same INSN_UID as I2. This gives it | |
1751 | the same INSN_CUID for value tracking. Our fake I1 will | |
1752 | never appear in the insn stream so giving it the same INSN_UID | |
1753 | as I2 will not cause a problem. */ | |
1754 | ||
0d9641d1 | 1755 | subst_prev_insn = i1 |
38a448ca | 1756 | = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, |
ba4f7968 | 1757 | BLOCK_FOR_INSN (i2), INSN_SCOPE (i2), |
38a448ca RH |
1758 | XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, |
1759 | NULL_RTX); | |
230d793d RS |
1760 | |
1761 | SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); | |
1762 | SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), | |
1763 | SET_DEST (PATTERN (i1))); | |
1764 | } | |
1765 | } | |
1766 | #endif | |
1767 | ||
1768 | /* Verify that I2 and I1 are valid for combining. */ | |
5f4f0e22 CH |
1769 | if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) |
1770 | || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) | |
230d793d RS |
1771 | { |
1772 | undo_all (); | |
1773 | return 0; | |
1774 | } | |
1775 | ||
1776 | /* Record whether I2DEST is used in I2SRC and similarly for the other | |
1777 | cases. Knowing this will help in register status updating below. */ | |
1778 | i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); | |
1779 | i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); | |
1780 | i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); | |
1781 | ||
916f14f1 | 1782 | /* See if I1 directly feeds into I3. It does if I1DEST is not used |
230d793d RS |
1783 | in I2SRC. */ |
1784 | i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); | |
1785 | ||
1786 | /* Ensure that I3's pattern can be the destination of combines. */ | |
1787 | if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, | |
1788 | i1 && i2dest_in_i1src && i1_feeds_i3, | |
1789 | &i3dest_killed)) | |
1790 | { | |
1791 | undo_all (); | |
1792 | return 0; | |
1793 | } | |
1794 | ||
df7d75de RK |
1795 | /* See if any of the insns is a MULT operation. Unless one is, we will |
1796 | reject a combination that is, since it must be slower. Be conservative | |
1797 | here. */ | |
1798 | if (GET_CODE (i2src) == MULT | |
1799 | || (i1 != 0 && GET_CODE (i1src) == MULT) | |
1800 | || (GET_CODE (PATTERN (i3)) == SET | |
1801 | && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) | |
1802 | have_mult = 1; | |
1803 | ||
230d793d RS |
1804 | /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. |
1805 | We used to do this EXCEPT in one case: I3 has a post-inc in an | |
1806 | output operand. However, that exception can give rise to insns like | |
23190837 | 1807 | mov r3,(r3)+ |
230d793d | 1808 | which is a famous insn on the PDP-11 where the value of r3 used as the |
5089e22e | 1809 | source was model-dependent. Avoid this sort of thing. */ |
230d793d RS |
1810 | |
1811 | #if 0 | |
1812 | if (!(GET_CODE (PATTERN (i3)) == SET | |
1813 | && GET_CODE (SET_SRC (PATTERN (i3))) == REG | |
1814 | && GET_CODE (SET_DEST (PATTERN (i3))) == MEM | |
1815 | && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC | |
1816 | || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) | |
1817 | /* It's not the exception. */ | |
1818 | #endif | |
1819 | #ifdef AUTO_INC_DEC | |
1820 | for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) | |
1821 | if (REG_NOTE_KIND (link) == REG_INC | |
1822 | && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) | |
1823 | || (i1 != 0 | |
1824 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) | |
1825 | { | |
1826 | undo_all (); | |
1827 | return 0; | |
1828 | } | |
1829 | #endif | |
1830 | ||
1831 | /* See if the SETs in I1 or I2 need to be kept around in the merged | |
1832 | instruction: whenever the value set there is still needed past I3. | |
1833 | For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. | |
1834 | ||
1835 | For the SET in I1, we have two cases: If I1 and I2 independently | |
1836 | feed into I3, the set in I1 needs to be kept around if I1DEST dies | |
1837 | or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set | |
1838 | in I1 needs to be kept around unless I1DEST dies or is set in either | |
1839 | I2 or I3. We can distinguish these cases by seeing if I2SRC mentions | |
1840 | I1DEST. If so, we know I1 feeds into I2. */ | |
1841 | ||
1842 | added_sets_2 = ! dead_or_set_p (i3, i2dest); | |
1843 | ||
1844 | added_sets_1 | |
1845 | = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) | |
1846 | : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); | |
1847 | ||
1848 | /* If the set in I2 needs to be kept around, we must make a copy of | |
1849 | PATTERN (I2), so that when we substitute I1SRC for I1DEST in | |
5089e22e | 1850 | PATTERN (I2), we are only substituting for the original I1DEST, not into |
230d793d RS |
1851 | an already-substituted copy. This also prevents making self-referential |
1852 | rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to | |
1853 | I2DEST. */ | |
1854 | ||
1855 | i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL | |
38a448ca | 1856 | ? gen_rtx_SET (VOIDmode, i2dest, i2src) |
230d793d RS |
1857 | : PATTERN (i2)); |
1858 | ||
1859 | if (added_sets_2) | |
1860 | i2pat = copy_rtx (i2pat); | |
1861 | ||
1862 | combine_merges++; | |
1863 | ||
1864 | /* Substitute in the latest insn for the regs set by the earlier ones. */ | |
1865 | ||
1866 | maxreg = max_reg_num (); | |
1867 | ||
1868 | subst_insn = i3; | |
230d793d RS |
1869 | |
1870 | /* It is possible that the source of I2 or I1 may be performing an | |
1871 | unneeded operation, such as a ZERO_EXTEND of something that is known | |
1872 | to have the high part zero. Handle that case by letting subst look at | |
1873 | the innermost one of them. | |
1874 | ||
1875 | Another way to do this would be to have a function that tries to | |
1876 | simplify a single insn instead of merging two or more insns. We don't | |
1877 | do this because of the potential of infinite loops and because | |
1878 | of the potential extra memory required. However, doing it the way | |
1879 | we are is a bit of a kludge and doesn't catch all cases. | |
1880 | ||
1881 | But only do this if -fexpensive-optimizations since it slows things down | |
1882 | and doesn't usually win. */ | |
1883 | ||
1884 | if (flag_expensive_optimizations) | |
1885 | { | |
1886 | /* Pass pc_rtx so no substitutions are done, just simplifications. | |
1887 | The cases that we are interested in here do not involve the few | |
1888 | cases were is_replaced is checked. */ | |
1889 | if (i1) | |
d0ab8cd3 RK |
1890 | { |
1891 | subst_low_cuid = INSN_CUID (i1); | |
1892 | i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); | |
1893 | } | |
230d793d | 1894 | else |
d0ab8cd3 RK |
1895 | { |
1896 | subst_low_cuid = INSN_CUID (i2); | |
1897 | i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); | |
1898 | } | |
230d793d RS |
1899 | } |
1900 | ||
1901 | #ifndef HAVE_cc0 | |
1902 | /* Many machines that don't use CC0 have insns that can both perform an | |
1903 | arithmetic operation and set the condition code. These operations will | |
1904 | be represented as a PARALLEL with the first element of the vector | |
1905 | being a COMPARE of an arithmetic operation with the constant zero. | |
1906 | The second element of the vector will set some pseudo to the result | |
1907 | of the same arithmetic operation. If we simplify the COMPARE, we won't | |
1908 | match such a pattern and so will generate an extra insn. Here we test | |
1909 | for this case, where both the comparison and the operation result are | |
1910 | needed, and make the PARALLEL by just replacing I2DEST in I3SRC with | |
1911 | I2SRC. Later we will make the PARALLEL that contains I2. */ | |
1912 | ||
1913 | if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET | |
1914 | && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE | |
1915 | && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx | |
1916 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) | |
1917 | { | |
081f5e7e | 1918 | #ifdef EXTRA_CC_MODES |
230d793d RS |
1919 | rtx *cc_use; |
1920 | enum machine_mode compare_mode; | |
081f5e7e | 1921 | #endif |
230d793d RS |
1922 | |
1923 | newpat = PATTERN (i3); | |
1924 | SUBST (XEXP (SET_SRC (newpat), 0), i2src); | |
1925 | ||
1926 | i2_is_used = 1; | |
1927 | ||
1928 | #ifdef EXTRA_CC_MODES | |
1929 | /* See if a COMPARE with the operand we substituted in should be done | |
1930 | with the mode that is currently being used. If not, do the same | |
1931 | processing we do in `subst' for a SET; namely, if the destination | |
1932 | is used only once, try to replace it with a register of the proper | |
1933 | mode and also replace the COMPARE. */ | |
1934 | if (undobuf.other_insn == 0 | |
1935 | && (cc_use = find_single_use (SET_DEST (newpat), i3, | |
1936 | &undobuf.other_insn)) | |
77fa0940 RK |
1937 | && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), |
1938 | i2src, const0_rtx)) | |
230d793d RS |
1939 | != GET_MODE (SET_DEST (newpat)))) |
1940 | { | |
770ae6cc | 1941 | unsigned int regno = REGNO (SET_DEST (newpat)); |
38a448ca | 1942 | rtx new_dest = gen_rtx_REG (compare_mode, regno); |
230d793d RS |
1943 | |
1944 | if (regno < FIRST_PSEUDO_REGISTER | |
b1f21e0a | 1945 | || (REG_N_SETS (regno) == 1 && ! added_sets_2 |
230d793d RS |
1946 | && ! REG_USERVAR_P (SET_DEST (newpat)))) |
1947 | { | |
1948 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1949 | SUBST (regno_reg_rtx[regno], new_dest); | |
1950 | ||
1951 | SUBST (SET_DEST (newpat), new_dest); | |
1952 | SUBST (XEXP (*cc_use, 0), new_dest); | |
1953 | SUBST (SET_SRC (newpat), | |
f1c6ba8b | 1954 | gen_rtx_COMPARE (compare_mode, i2src, const0_rtx)); |
230d793d RS |
1955 | } |
1956 | else | |
1957 | undobuf.other_insn = 0; | |
1958 | } | |
663522cb | 1959 | #endif |
230d793d RS |
1960 | } |
1961 | else | |
1962 | #endif | |
1963 | { | |
1964 | n_occurrences = 0; /* `subst' counts here */ | |
1965 | ||
1966 | /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we | |
1967 | need to make a unique copy of I2SRC each time we substitute it | |
1968 | to avoid self-referential rtl. */ | |
1969 | ||
d0ab8cd3 | 1970 | subst_low_cuid = INSN_CUID (i2); |
230d793d RS |
1971 | newpat = subst (PATTERN (i3), i2dest, i2src, 0, |
1972 | ! i1_feeds_i3 && i1dest_in_i1src); | |
cddd8b72 | 1973 | substed_i2 = 1; |
230d793d RS |
1974 | |
1975 | /* Record whether i2's body now appears within i3's body. */ | |
1976 | i2_is_used = n_occurrences; | |
1977 | } | |
1978 | ||
1979 | /* If we already got a failure, don't try to do more. Otherwise, | |
1980 | try to substitute in I1 if we have it. */ | |
1981 | ||
1982 | if (i1 && GET_CODE (newpat) != CLOBBER) | |
1983 | { | |
1984 | /* Before we can do this substitution, we must redo the test done | |
1985 | above (see detailed comments there) that ensures that I1DEST | |
0f41302f | 1986 | isn't mentioned in any SETs in NEWPAT that are field assignments. */ |
230d793d | 1987 | |
5f4f0e22 | 1988 | if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, |
cf0d9408 | 1989 | 0, (rtx*) 0)) |
230d793d RS |
1990 | { |
1991 | undo_all (); | |
1992 | return 0; | |
1993 | } | |
1994 | ||
1995 | n_occurrences = 0; | |
d0ab8cd3 | 1996 | subst_low_cuid = INSN_CUID (i1); |
230d793d | 1997 | newpat = subst (newpat, i1dest, i1src, 0, 0); |
cddd8b72 | 1998 | substed_i1 = 1; |
230d793d RS |
1999 | } |
2000 | ||
916f14f1 RK |
2001 | /* Fail if an autoincrement side-effect has been duplicated. Be careful |
2002 | to count all the ways that I2SRC and I1SRC can be used. */ | |
5f4f0e22 | 2003 | if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 |
916f14f1 | 2004 | && i2_is_used + added_sets_2 > 1) |
5f4f0e22 | 2005 | || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 |
916f14f1 RK |
2006 | && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) |
2007 | > 1)) | |
230d793d RS |
2008 | /* Fail if we tried to make a new register (we used to abort, but there's |
2009 | really no reason to). */ | |
2010 | || max_reg_num () != maxreg | |
2011 | /* Fail if we couldn't do something and have a CLOBBER. */ | |
df7d75de RK |
2012 | || GET_CODE (newpat) == CLOBBER |
2013 | /* Fail if this new pattern is a MULT and we didn't have one before | |
2014 | at the outer level. */ | |
2015 | || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT | |
2016 | && ! have_mult)) | |
230d793d RS |
2017 | { |
2018 | undo_all (); | |
2019 | return 0; | |
2020 | } | |
2021 | ||
2022 | /* If the actions of the earlier insns must be kept | |
2023 | in addition to substituting them into the latest one, | |
2024 | we must make a new PARALLEL for the latest insn | |
2025 | to hold additional the SETs. */ | |
2026 | ||
2027 | if (added_sets_1 || added_sets_2) | |
2028 | { | |
2029 | combine_extras++; | |
2030 | ||
2031 | if (GET_CODE (newpat) == PARALLEL) | |
2032 | { | |
2033 | rtvec old = XVEC (newpat, 0); | |
2034 | total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; | |
38a448ca | 2035 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); |
d38a30c9 KG |
2036 | memcpy (XVEC (newpat, 0)->elem, &old->elem[0], |
2037 | sizeof (old->elem[0]) * old->num_elem); | |
230d793d RS |
2038 | } |
2039 | else | |
2040 | { | |
2041 | rtx old = newpat; | |
2042 | total_sets = 1 + added_sets_1 + added_sets_2; | |
38a448ca | 2043 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); |
230d793d RS |
2044 | XVECEXP (newpat, 0, 0) = old; |
2045 | } | |
2046 | ||
cf0d9408 KH |
2047 | if (added_sets_1) |
2048 | XVECEXP (newpat, 0, --total_sets) | |
2049 | = (GET_CODE (PATTERN (i1)) == PARALLEL | |
2050 | ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1)); | |
2051 | ||
2052 | if (added_sets_2) | |
2053 | { | |
2054 | /* If there is no I1, use I2's body as is. We used to also not do | |
2055 | the subst call below if I2 was substituted into I3, | |
2056 | but that could lose a simplification. */ | |
2057 | if (i1 == 0) | |
2058 | XVECEXP (newpat, 0, --total_sets) = i2pat; | |
2059 | else | |
2060 | /* See comment where i2pat is assigned. */ | |
2061 | XVECEXP (newpat, 0, --total_sets) | |
2062 | = subst (i2pat, i1dest, i1src, 0, 0); | |
2063 | } | |
230d793d RS |
2064 | } |
2065 | ||
2066 | /* We come here when we are replacing a destination in I2 with the | |
2067 | destination of I3. */ | |
2068 | validate_replacement: | |
2069 | ||
6e25d159 RK |
2070 | /* Note which hard regs this insn has as inputs. */ |
2071 | mark_used_regs_combine (newpat); | |
2072 | ||
230d793d | 2073 | /* Is the result of combination a valid instruction? */ |
8e2f6e35 | 2074 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2075 | |
2076 | /* If the result isn't valid, see if it is a PARALLEL of two SETs where | |
2077 | the second SET's destination is a register that is unused. In that case, | |
2078 | we just need the first SET. This can occur when simplifying a divmod | |
2079 | insn. We *must* test for this case here because the code below that | |
2080 | splits two independent SETs doesn't handle this case correctly when it | |
2081 | updates the register status. Also check the case where the first | |
2082 | SET's destination is unused. That would not cause incorrect code, but | |
2083 | does cause an unneeded insn to remain. */ | |
2084 | ||
2085 | if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL | |
2086 | && XVECLEN (newpat, 0) == 2 | |
2087 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2088 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
2089 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG | |
2090 | && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1))) | |
2091 | && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1))) | |
2092 | && asm_noperands (newpat) < 0) | |
2093 | { | |
2094 | newpat = XVECEXP (newpat, 0, 0); | |
8e2f6e35 | 2095 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2096 | } |
2097 | ||
2098 | else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL | |
2099 | && XVECLEN (newpat, 0) == 2 | |
2100 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2101 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
2102 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG | |
2103 | && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0))) | |
2104 | && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0))) | |
2105 | && asm_noperands (newpat) < 0) | |
2106 | { | |
2107 | newpat = XVECEXP (newpat, 0, 1); | |
8e2f6e35 | 2108 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2109 | } |
2110 | ||
2111 | /* If we were combining three insns and the result is a simple SET | |
2112 | with no ASM_OPERANDS that wasn't recognized, try to split it into two | |
663522cb | 2113 | insns. There are two ways to do this. It can be split using a |
916f14f1 RK |
2114 | machine-specific method (like when you have an addition of a large |
2115 | constant) or by combine in the function find_split_point. */ | |
2116 | ||
230d793d RS |
2117 | if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET |
2118 | && asm_noperands (newpat) < 0) | |
2119 | { | |
916f14f1 | 2120 | rtx m_split, *split; |
42495ca0 | 2121 | rtx ni2dest = i2dest; |
916f14f1 RK |
2122 | |
2123 | /* See if the MD file can split NEWPAT. If it can't, see if letting it | |
42495ca0 RK |
2124 | use I2DEST as a scratch register will help. In the latter case, |
2125 | convert I2DEST to the mode of the source of NEWPAT if we can. */ | |
916f14f1 RK |
2126 | |
2127 | m_split = split_insns (newpat, i3); | |
a70c61d9 JW |
2128 | |
2129 | /* We can only use I2DEST as a scratch reg if it doesn't overlap any | |
2130 | inputs of NEWPAT. */ | |
2131 | ||
2132 | /* ??? If I2DEST is not safe, and I1DEST exists, then it would be | |
2133 | possible to try that as a scratch reg. This would require adding | |
2134 | more code to make it work though. */ | |
2135 | ||
2136 | if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) | |
42495ca0 RK |
2137 | { |
2138 | /* If I2DEST is a hard register or the only use of a pseudo, | |
2139 | we can change its mode. */ | |
2140 | if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest) | |
02f4ada4 | 2141 | && GET_MODE (SET_DEST (newpat)) != VOIDmode |
60654f77 | 2142 | && GET_CODE (i2dest) == REG |
42495ca0 | 2143 | && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER |
b1f21e0a | 2144 | || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 |
42495ca0 | 2145 | && ! REG_USERVAR_P (i2dest)))) |
38a448ca | 2146 | ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)), |
c5c76735 JL |
2147 | REGNO (i2dest)); |
2148 | ||
2149 | m_split = split_insns (gen_rtx_PARALLEL | |
2150 | (VOIDmode, | |
2151 | gen_rtvec (2, newpat, | |
2152 | gen_rtx_CLOBBER (VOIDmode, | |
2153 | ni2dest))), | |
2154 | i3); | |
5dd3e650 R |
2155 | /* If the split with the mode-changed register didn't work, try |
2156 | the original register. */ | |
2157 | if (! m_split && ni2dest != i2dest) | |
c7ca5912 RK |
2158 | { |
2159 | ni2dest = i2dest; | |
2160 | m_split = split_insns (gen_rtx_PARALLEL | |
2161 | (VOIDmode, | |
2162 | gen_rtvec (2, newpat, | |
2163 | gen_rtx_CLOBBER (VOIDmode, | |
2164 | i2dest))), | |
2165 | i3); | |
2166 | } | |
42495ca0 | 2167 | } |
916f14f1 | 2168 | |
2f937369 | 2169 | if (m_split && NEXT_INSN (m_split) == NULL_RTX) |
d340408c | 2170 | { |
2f937369 | 2171 | m_split = PATTERN (m_split); |
d340408c RH |
2172 | insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes); |
2173 | if (insn_code_number >= 0) | |
2174 | newpat = m_split; | |
23190837 | 2175 | } |
2f937369 | 2176 | else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX |
d340408c | 2177 | && (next_real_insn (i2) == i3 |
2f937369 | 2178 | || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2)))) |
916f14f1 | 2179 | { |
1a26b032 | 2180 | rtx i2set, i3set; |
2f937369 DM |
2181 | rtx newi3pat = PATTERN (NEXT_INSN (m_split)); |
2182 | newi2pat = PATTERN (m_split); | |
916f14f1 | 2183 | |
2f937369 DM |
2184 | i3set = single_set (NEXT_INSN (m_split)); |
2185 | i2set = single_set (m_split); | |
1a26b032 | 2186 | |
42495ca0 RK |
2187 | /* In case we changed the mode of I2DEST, replace it in the |
2188 | pseudo-register table here. We can't do it above in case this | |
2189 | code doesn't get executed and we do a split the other way. */ | |
2190 | ||
2191 | if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) | |
2192 | SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); | |
2193 | ||
8e2f6e35 | 2194 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
1a26b032 RK |
2195 | |
2196 | /* If I2 or I3 has multiple SETs, we won't know how to track | |
9cc96794 RK |
2197 | register status, so don't use these insns. If I2's destination |
2198 | is used between I2 and I3, we also can't use these insns. */ | |
1a26b032 | 2199 | |
9cc96794 RK |
2200 | if (i2_code_number >= 0 && i2set && i3set |
2201 | && (next_real_insn (i2) == i3 | |
2202 | || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) | |
8e2f6e35 BS |
2203 | insn_code_number = recog_for_combine (&newi3pat, i3, |
2204 | &new_i3_notes); | |
d0ab8cd3 RK |
2205 | if (insn_code_number >= 0) |
2206 | newpat = newi3pat; | |
2207 | ||
c767f54b | 2208 | /* It is possible that both insns now set the destination of I3. |
22609cbf | 2209 | If so, we must show an extra use of it. */ |
c767f54b | 2210 | |
393de53f RK |
2211 | if (insn_code_number >= 0) |
2212 | { | |
2213 | rtx new_i3_dest = SET_DEST (i3set); | |
2214 | rtx new_i2_dest = SET_DEST (i2set); | |
2215 | ||
2216 | while (GET_CODE (new_i3_dest) == ZERO_EXTRACT | |
2217 | || GET_CODE (new_i3_dest) == STRICT_LOW_PART | |
2218 | || GET_CODE (new_i3_dest) == SUBREG) | |
2219 | new_i3_dest = XEXP (new_i3_dest, 0); | |
2220 | ||
d4096689 RK |
2221 | while (GET_CODE (new_i2_dest) == ZERO_EXTRACT |
2222 | || GET_CODE (new_i2_dest) == STRICT_LOW_PART | |
2223 | || GET_CODE (new_i2_dest) == SUBREG) | |
2224 | new_i2_dest = XEXP (new_i2_dest, 0); | |
2225 | ||
393de53f RK |
2226 | if (GET_CODE (new_i3_dest) == REG |
2227 | && GET_CODE (new_i2_dest) == REG | |
2228 | && REGNO (new_i3_dest) == REGNO (new_i2_dest)) | |
b1f21e0a | 2229 | REG_N_SETS (REGNO (new_i2_dest))++; |
393de53f | 2230 | } |
916f14f1 | 2231 | } |
230d793d RS |
2232 | |
2233 | /* If we can split it and use I2DEST, go ahead and see if that | |
2234 | helps things be recognized. Verify that none of the registers | |
2235 | are set between I2 and I3. */ | |
d0ab8cd3 | 2236 | if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 |
230d793d RS |
2237 | #ifdef HAVE_cc0 |
2238 | && GET_CODE (i2dest) == REG | |
2239 | #endif | |
2240 | /* We need I2DEST in the proper mode. If it is a hard register | |
2241 | or the only use of a pseudo, we can change its mode. */ | |
2242 | && (GET_MODE (*split) == GET_MODE (i2dest) | |
2243 | || GET_MODE (*split) == VOIDmode | |
2244 | || REGNO (i2dest) < FIRST_PSEUDO_REGISTER | |
b1f21e0a | 2245 | || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 |
230d793d RS |
2246 | && ! REG_USERVAR_P (i2dest))) |
2247 | && (next_real_insn (i2) == i3 | |
2248 | || ! use_crosses_set_p (*split, INSN_CUID (i2))) | |
2249 | /* We can't overwrite I2DEST if its value is still used by | |
2250 | NEWPAT. */ | |
2251 | && ! reg_referenced_p (i2dest, newpat)) | |
2252 | { | |
2253 | rtx newdest = i2dest; | |
df7d75de RK |
2254 | enum rtx_code split_code = GET_CODE (*split); |
2255 | enum machine_mode split_mode = GET_MODE (*split); | |
230d793d RS |
2256 | |
2257 | /* Get NEWDEST as a register in the proper mode. We have already | |
2258 | validated that we can do this. */ | |
df7d75de | 2259 | if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) |
230d793d | 2260 | { |
38a448ca | 2261 | newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); |
230d793d RS |
2262 | |
2263 | if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) | |
2264 | SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); | |
2265 | } | |
2266 | ||
2267 | /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to | |
2268 | an ASHIFT. This can occur if it was inside a PLUS and hence | |
2269 | appeared to be a memory address. This is a kludge. */ | |
df7d75de | 2270 | if (split_code == MULT |
230d793d | 2271 | && GET_CODE (XEXP (*split, 1)) == CONST_INT |
1568d79b | 2272 | && INTVAL (XEXP (*split, 1)) > 0 |
230d793d | 2273 | && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) |
1dc8a823 | 2274 | { |
f1c6ba8b RK |
2275 | SUBST (*split, gen_rtx_ASHIFT (split_mode, |
2276 | XEXP (*split, 0), GEN_INT (i))); | |
1dc8a823 JW |
2277 | /* Update split_code because we may not have a multiply |
2278 | anymore. */ | |
2279 | split_code = GET_CODE (*split); | |
2280 | } | |
230d793d RS |
2281 | |
2282 | #ifdef INSN_SCHEDULING | |
2283 | /* If *SPLIT is a paradoxical SUBREG, when we split it, it should | |
2284 | be written as a ZERO_EXTEND. */ | |
df7d75de | 2285 | if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM) |
25c25947 R |
2286 | { |
2287 | #ifdef LOAD_EXTEND_OP | |
2288 | /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's | |
2289 | what it really is. */ | |
2290 | if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split))) | |
2291 | == SIGN_EXTEND) | |
2292 | SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, | |
2293 | SUBREG_REG (*split))); | |
2294 | else | |
2295 | #endif | |
2296 | SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, | |
2297 | SUBREG_REG (*split))); | |
2298 | } | |
230d793d RS |
2299 | #endif |
2300 | ||
f1c6ba8b | 2301 | newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); |
230d793d | 2302 | SUBST (*split, newdest); |
8e2f6e35 | 2303 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
df7d75de RK |
2304 | |
2305 | /* If the split point was a MULT and we didn't have one before, | |
2306 | don't use one now. */ | |
2307 | if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) | |
8e2f6e35 | 2308 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2309 | } |
2310 | } | |
2311 | ||
2312 | /* Check for a case where we loaded from memory in a narrow mode and | |
2313 | then sign extended it, but we need both registers. In that case, | |
2314 | we have a PARALLEL with both loads from the same memory location. | |
2315 | We can split this into a load from memory followed by a register-register | |
2316 | copy. This saves at least one insn, more if register allocation can | |
f0343c74 RK |
2317 | eliminate the copy. |
2318 | ||
a9b2f059 JW |
2319 | We cannot do this if the destination of the first assignment is a |
2320 | condition code register or cc0. We eliminate this case by making sure | |
2321 | the SET_DEST and SET_SRC have the same mode. | |
2322 | ||
f0343c74 RK |
2323 | We cannot do this if the destination of the second assignment is |
2324 | a register that we have already assumed is zero-extended. Similarly | |
2325 | for a SUBREG of such a register. */ | |
230d793d RS |
2326 | |
2327 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
2328 | && GET_CODE (newpat) == PARALLEL | |
2329 | && XVECLEN (newpat, 0) == 2 | |
2330 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2331 | && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND | |
a9b2f059 JW |
2332 | && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) |
2333 | == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) | |
230d793d RS |
2334 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET |
2335 | && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2336 | XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) | |
2337 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2338 | INSN_CUID (i2)) | |
2339 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
2340 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
f0343c74 RK |
2341 | && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), |
2342 | (GET_CODE (temp) == REG | |
2343 | && reg_nonzero_bits[REGNO (temp)] != 0 | |
2344 | && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD | |
2345 | && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT | |
2346 | && (reg_nonzero_bits[REGNO (temp)] | |
2347 | != GET_MODE_MASK (word_mode)))) | |
2348 | && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG | |
2349 | && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), | |
2350 | (GET_CODE (temp) == REG | |
2351 | && reg_nonzero_bits[REGNO (temp)] != 0 | |
2352 | && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD | |
2353 | && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT | |
2354 | && (reg_nonzero_bits[REGNO (temp)] | |
2355 | != GET_MODE_MASK (word_mode))))) | |
230d793d RS |
2356 | && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), |
2357 | SET_SRC (XVECEXP (newpat, 0, 1))) | |
2358 | && ! find_reg_note (i3, REG_UNUSED, | |
2359 | SET_DEST (XVECEXP (newpat, 0, 0)))) | |
2360 | { | |
472fbdd1 RK |
2361 | rtx ni2dest; |
2362 | ||
230d793d | 2363 | newi2pat = XVECEXP (newpat, 0, 0); |
472fbdd1 | 2364 | ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); |
230d793d RS |
2365 | newpat = XVECEXP (newpat, 0, 1); |
2366 | SUBST (SET_SRC (newpat), | |
472fbdd1 | 2367 | gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest)); |
8e2f6e35 | 2368 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
a29ca9db | 2369 | |
230d793d | 2370 | if (i2_code_number >= 0) |
8e2f6e35 | 2371 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
5089e22e RS |
2372 | |
2373 | if (insn_code_number >= 0) | |
2374 | { | |
2375 | rtx insn; | |
2376 | rtx link; | |
2377 | ||
2378 | /* If we will be able to accept this, we have made a change to the | |
2379 | destination of I3. This can invalidate a LOG_LINKS pointing | |
2380 | to I3. No other part of combine.c makes such a transformation. | |
2381 | ||
2382 | The new I3 will have a destination that was previously the | |
2383 | destination of I1 or I2 and which was used in i2 or I3. Call | |
2384 | distribute_links to make a LOG_LINK from the next use of | |
2385 | that destination. */ | |
2386 | ||
2387 | PATTERN (i3) = newpat; | |
38a448ca | 2388 | distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX)); |
5089e22e RS |
2389 | |
2390 | /* I3 now uses what used to be its destination and which is | |
2391 | now I2's destination. That means we need a LOG_LINK from | |
2392 | I3 to I2. But we used to have one, so we still will. | |
2393 | ||
2394 | However, some later insn might be using I2's dest and have | |
2395 | a LOG_LINK pointing at I3. We must remove this link. | |
2396 | The simplest way to remove the link is to point it at I1, | |
2397 | which we know will be a NOTE. */ | |
2398 | ||
2399 | for (insn = NEXT_INSN (i3); | |
f6366fc7 ZD |
2400 | insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR |
2401 | || insn != this_basic_block->next_bb->head); | |
5089e22e RS |
2402 | insn = NEXT_INSN (insn)) |
2403 | { | |
2c3c49de | 2404 | if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) |
5089e22e RS |
2405 | { |
2406 | for (link = LOG_LINKS (insn); link; | |
2407 | link = XEXP (link, 1)) | |
2408 | if (XEXP (link, 0) == i3) | |
2409 | XEXP (link, 0) = i1; | |
2410 | ||
2411 | break; | |
2412 | } | |
2413 | } | |
2414 | } | |
230d793d | 2415 | } |
663522cb | 2416 | |
230d793d RS |
2417 | /* Similarly, check for a case where we have a PARALLEL of two independent |
2418 | SETs but we started with three insns. In this case, we can do the sets | |
2419 | as two separate insns. This case occurs when some SET allows two | |
2420 | other insns to combine, but the destination of that SET is still live. */ | |
2421 | ||
2422 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
2423 | && GET_CODE (newpat) == PARALLEL | |
2424 | && XVECLEN (newpat, 0) == 2 | |
2425 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2426 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT | |
2427 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART | |
2428 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
2429 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
2430 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
2431 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2432 | INSN_CUID (i2)) | |
2433 | /* Don't pass sets with (USE (MEM ...)) dests to the following. */ | |
2434 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE | |
2435 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE | |
2436 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), | |
2437 | XVECEXP (newpat, 0, 0)) | |
2438 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), | |
14a774a9 RK |
2439 | XVECEXP (newpat, 0, 1)) |
2440 | && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) | |
2441 | && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) | |
230d793d | 2442 | { |
e9a25f70 JL |
2443 | /* Normally, it doesn't matter which of the two is done first, |
2444 | but it does if one references cc0. In that case, it has to | |
2445 | be first. */ | |
2446 | #ifdef HAVE_cc0 | |
2447 | if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) | |
2448 | { | |
2449 | newi2pat = XVECEXP (newpat, 0, 0); | |
2450 | newpat = XVECEXP (newpat, 0, 1); | |
2451 | } | |
2452 | else | |
2453 | #endif | |
2454 | { | |
2455 | newi2pat = XVECEXP (newpat, 0, 1); | |
2456 | newpat = XVECEXP (newpat, 0, 0); | |
2457 | } | |
230d793d | 2458 | |
8e2f6e35 | 2459 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
a29ca9db | 2460 | |
230d793d | 2461 | if (i2_code_number >= 0) |
8e2f6e35 | 2462 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2463 | } |
2464 | ||
2465 | /* If it still isn't recognized, fail and change things back the way they | |
2466 | were. */ | |
2467 | if ((insn_code_number < 0 | |
2468 | /* Is the result a reasonable ASM_OPERANDS? */ | |
2469 | && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) | |
2470 | { | |
2471 | undo_all (); | |
2472 | return 0; | |
2473 | } | |
2474 | ||
2475 | /* If we had to change another insn, make sure it is valid also. */ | |
2476 | if (undobuf.other_insn) | |
2477 | { | |
230d793d RS |
2478 | rtx other_pat = PATTERN (undobuf.other_insn); |
2479 | rtx new_other_notes; | |
2480 | rtx note, next; | |
2481 | ||
6e25d159 RK |
2482 | CLEAR_HARD_REG_SET (newpat_used_regs); |
2483 | ||
8e2f6e35 BS |
2484 | other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, |
2485 | &new_other_notes); | |
230d793d RS |
2486 | |
2487 | if (other_code_number < 0 && ! check_asm_operands (other_pat)) | |
2488 | { | |
2489 | undo_all (); | |
2490 | return 0; | |
2491 | } | |
2492 | ||
2493 | PATTERN (undobuf.other_insn) = other_pat; | |
2494 | ||
2495 | /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they | |
2496 | are still valid. Then add any non-duplicate notes added by | |
2497 | recog_for_combine. */ | |
2498 | for (note = REG_NOTES (undobuf.other_insn); note; note = next) | |
2499 | { | |
2500 | next = XEXP (note, 1); | |
2501 | ||
2502 | if (REG_NOTE_KIND (note) == REG_UNUSED | |
2503 | && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) | |
1a26b032 RK |
2504 | { |
2505 | if (GET_CODE (XEXP (note, 0)) == REG) | |
b1f21e0a | 2506 | REG_N_DEATHS (REGNO (XEXP (note, 0)))--; |
1a26b032 RK |
2507 | |
2508 | remove_note (undobuf.other_insn, note); | |
2509 | } | |
230d793d RS |
2510 | } |
2511 | ||
1a26b032 RK |
2512 | for (note = new_other_notes; note; note = XEXP (note, 1)) |
2513 | if (GET_CODE (XEXP (note, 0)) == REG) | |
b1f21e0a | 2514 | REG_N_DEATHS (REGNO (XEXP (note, 0)))++; |
1a26b032 | 2515 | |
230d793d | 2516 | distribute_notes (new_other_notes, undobuf.other_insn, |
5f4f0e22 | 2517 | undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); |
230d793d | 2518 | } |
5ef17dd2 | 2519 | #ifdef HAVE_cc0 |
663522cb | 2520 | /* If I2 is the setter CC0 and I3 is the user CC0 then check whether |
ec5c56db | 2521 | they are adjacent to each other or not. */ |
5ef17dd2 CC |
2522 | { |
2523 | rtx p = prev_nonnote_insn (i3); | |
663522cb KH |
2524 | if (p && p != i2 && GET_CODE (p) == INSN && newi2pat |
2525 | && sets_cc0_p (newi2pat)) | |
5ef17dd2 | 2526 | { |
663522cb KH |
2527 | undo_all (); |
2528 | return 0; | |
5ef17dd2 | 2529 | } |
663522cb KH |
2530 | } |
2531 | #endif | |
230d793d | 2532 | |
663522cb | 2533 | /* We now know that we can do this combination. Merge the insns and |
230d793d RS |
2534 | update the status of registers and LOG_LINKS. */ |
2535 | ||
2536 | { | |
2537 | rtx i3notes, i2notes, i1notes = 0; | |
2538 | rtx i3links, i2links, i1links = 0; | |
2539 | rtx midnotes = 0; | |
770ae6cc | 2540 | unsigned int regno; |
ff3467a9 JW |
2541 | /* Compute which registers we expect to eliminate. newi2pat may be setting |
2542 | either i3dest or i2dest, so we must check it. Also, i1dest may be the | |
2543 | same as i3dest, in which case newi2pat may be setting i1dest. */ | |
2544 | rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) | |
2545 | || i2dest_in_i2src || i2dest_in_i1src | |
230d793d | 2546 | ? 0 : i2dest); |
ff3467a9 JW |
2547 | rtx elim_i1 = (i1 == 0 || i1dest_in_i1src |
2548 | || (newi2pat && reg_set_p (i1dest, newi2pat)) | |
2549 | ? 0 : i1dest); | |
230d793d RS |
2550 | |
2551 | /* Get the old REG_NOTES and LOG_LINKS from all our insns and | |
2552 | clear them. */ | |
2553 | i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); | |
2554 | i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); | |
2555 | if (i1) | |
2556 | i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); | |
2557 | ||
2558 | /* Ensure that we do not have something that should not be shared but | |
2559 | occurs multiple times in the new insns. Check this by first | |
5089e22e | 2560 | resetting all the `used' flags and then copying anything is shared. */ |
230d793d RS |
2561 | |
2562 | reset_used_flags (i3notes); | |
2563 | reset_used_flags (i2notes); | |
2564 | reset_used_flags (i1notes); | |
2565 | reset_used_flags (newpat); | |
2566 | reset_used_flags (newi2pat); | |
2567 | if (undobuf.other_insn) | |
2568 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
2569 | ||
2570 | i3notes = copy_rtx_if_shared (i3notes); | |
2571 | i2notes = copy_rtx_if_shared (i2notes); | |
2572 | i1notes = copy_rtx_if_shared (i1notes); | |
2573 | newpat = copy_rtx_if_shared (newpat); | |
2574 | newi2pat = copy_rtx_if_shared (newi2pat); | |
2575 | if (undobuf.other_insn) | |
2576 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
2577 | ||
2578 | INSN_CODE (i3) = insn_code_number; | |
2579 | PATTERN (i3) = newpat; | |
cddd8b72 AO |
2580 | |
2581 | if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3)) | |
2582 | { | |
2583 | rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3); | |
2584 | ||
2585 | reset_used_flags (call_usage); | |
2586 | call_usage = copy_rtx (call_usage); | |
2587 | ||
2588 | if (substed_i2) | |
2589 | replace_rtx (call_usage, i2dest, i2src); | |
2590 | ||
2591 | if (substed_i1) | |
2592 | replace_rtx (call_usage, i1dest, i1src); | |
2593 | ||
2594 | CALL_INSN_FUNCTION_USAGE (i3) = call_usage; | |
2595 | } | |
2596 | ||
230d793d RS |
2597 | if (undobuf.other_insn) |
2598 | INSN_CODE (undobuf.other_insn) = other_code_number; | |
2599 | ||
2600 | /* We had one special case above where I2 had more than one set and | |
2601 | we replaced a destination of one of those sets with the destination | |
2602 | of I3. In that case, we have to update LOG_LINKS of insns later | |
176c9e6b JW |
2603 | in this basic block. Note that this (expensive) case is rare. |
2604 | ||
2605 | Also, in this case, we must pretend that all REG_NOTEs for I2 | |
2606 | actually came from I3, so that REG_UNUSED notes from I2 will be | |
2607 | properly handled. */ | |
2608 | ||
c7be4f66 | 2609 | if (i3_subst_into_i2) |
176c9e6b | 2610 | { |
1786009e | 2611 | for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) |
95ac07b0 AO |
2612 | if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE |
2613 | && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG | |
1786009e ZW |
2614 | && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest |
2615 | && ! find_reg_note (i2, REG_UNUSED, | |
2616 | SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) | |
2617 | for (temp = NEXT_INSN (i2); | |
f6366fc7 ZD |
2618 | temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR |
2619 | || this_basic_block->head != temp); | |
1786009e ZW |
2620 | temp = NEXT_INSN (temp)) |
2621 | if (temp != i3 && INSN_P (temp)) | |
2622 | for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) | |
2623 | if (XEXP (link, 0) == i2) | |
2624 | XEXP (link, 0) = i3; | |
176c9e6b JW |
2625 | |
2626 | if (i3notes) | |
2627 | { | |
2628 | rtx link = i3notes; | |
2629 | while (XEXP (link, 1)) | |
2630 | link = XEXP (link, 1); | |
2631 | XEXP (link, 1) = i2notes; | |
2632 | } | |
2633 | else | |
2634 | i3notes = i2notes; | |
2635 | i2notes = 0; | |
2636 | } | |
230d793d RS |
2637 | |
2638 | LOG_LINKS (i3) = 0; | |
2639 | REG_NOTES (i3) = 0; | |
2640 | LOG_LINKS (i2) = 0; | |
2641 | REG_NOTES (i2) = 0; | |
2642 | ||
2643 | if (newi2pat) | |
2644 | { | |
2645 | INSN_CODE (i2) = i2_code_number; | |
2646 | PATTERN (i2) = newi2pat; | |
2647 | } | |
2648 | else | |
2649 | { | |
2650 | PUT_CODE (i2, NOTE); | |
2651 | NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; | |
2652 | NOTE_SOURCE_FILE (i2) = 0; | |
2653 | } | |
2654 | ||
2655 | if (i1) | |
2656 | { | |
2657 | LOG_LINKS (i1) = 0; | |
2658 | REG_NOTES (i1) = 0; | |
2659 | PUT_CODE (i1, NOTE); | |
2660 | NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED; | |
2661 | NOTE_SOURCE_FILE (i1) = 0; | |
2662 | } | |
2663 | ||
2664 | /* Get death notes for everything that is now used in either I3 or | |
663522cb | 2665 | I2 and used to die in a previous insn. If we built two new |
6eb12cef RK |
2666 | patterns, move from I1 to I2 then I2 to I3 so that we get the |
2667 | proper movement on registers that I2 modifies. */ | |
230d793d | 2668 | |
230d793d | 2669 | if (newi2pat) |
6eb12cef RK |
2670 | { |
2671 | move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes); | |
2672 | move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes); | |
2673 | } | |
2674 | else | |
2675 | move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2), | |
2676 | i3, &midnotes); | |
230d793d RS |
2677 | |
2678 | /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ | |
2679 | if (i3notes) | |
5f4f0e22 CH |
2680 | distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, |
2681 | elim_i2, elim_i1); | |
230d793d | 2682 | if (i2notes) |
5f4f0e22 CH |
2683 | distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, |
2684 | elim_i2, elim_i1); | |
230d793d | 2685 | if (i1notes) |
5f4f0e22 CH |
2686 | distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, |
2687 | elim_i2, elim_i1); | |
230d793d | 2688 | if (midnotes) |
5f4f0e22 CH |
2689 | distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, |
2690 | elim_i2, elim_i1); | |
230d793d RS |
2691 | |
2692 | /* Distribute any notes added to I2 or I3 by recog_for_combine. We | |
2693 | know these are REG_UNUSED and want them to go to the desired insn, | |
663522cb | 2694 | so we always pass it as i3. We have not counted the notes in |
1a26b032 RK |
2695 | reg_n_deaths yet, so we need to do so now. */ |
2696 | ||
230d793d | 2697 | if (newi2pat && new_i2_notes) |
1a26b032 RK |
2698 | { |
2699 | for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) | |
2700 | if (GET_CODE (XEXP (temp, 0)) == REG) | |
b1f21e0a | 2701 | REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; |
663522cb | 2702 | |
1a26b032 RK |
2703 | distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); |
2704 | } | |
2705 | ||
230d793d | 2706 | if (new_i3_notes) |
1a26b032 RK |
2707 | { |
2708 | for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) | |
2709 | if (GET_CODE (XEXP (temp, 0)) == REG) | |
b1f21e0a | 2710 | REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; |
663522cb | 2711 | |
1a26b032 RK |
2712 | distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); |
2713 | } | |
230d793d RS |
2714 | |
2715 | /* If I3DEST was used in I3SRC, it really died in I3. We may need to | |
e9a25f70 JL |
2716 | put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets |
2717 | I3DEST, the death must be somewhere before I2, not I3. If we passed I3 | |
2718 | in that case, it might delete I2. Similarly for I2 and I1. | |
1a26b032 RK |
2719 | Show an additional death due to the REG_DEAD note we make here. If |
2720 | we discard it in distribute_notes, we will decrement it again. */ | |
d0ab8cd3 | 2721 | |
230d793d | 2722 | if (i3dest_killed) |
1a26b032 RK |
2723 | { |
2724 | if (GET_CODE (i3dest_killed) == REG) | |
b1f21e0a | 2725 | REG_N_DEATHS (REGNO (i3dest_killed))++; |
1a26b032 | 2726 | |
e9a25f70 | 2727 | if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) |
38a448ca RH |
2728 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, |
2729 | NULL_RTX), | |
ff3467a9 | 2730 | NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1); |
e9a25f70 | 2731 | else |
38a448ca RH |
2732 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, |
2733 | NULL_RTX), | |
e9a25f70 | 2734 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, |
ff3467a9 | 2735 | elim_i2, elim_i1); |
1a26b032 | 2736 | } |
58c8c593 | 2737 | |
230d793d | 2738 | if (i2dest_in_i2src) |
58c8c593 | 2739 | { |
1a26b032 | 2740 | if (GET_CODE (i2dest) == REG) |
b1f21e0a | 2741 | REG_N_DEATHS (REGNO (i2dest))++; |
1a26b032 | 2742 | |
58c8c593 | 2743 | if (newi2pat && reg_set_p (i2dest, newi2pat)) |
38a448ca | 2744 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), |
58c8c593 RK |
2745 | NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); |
2746 | else | |
38a448ca | 2747 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), |
58c8c593 RK |
2748 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, |
2749 | NULL_RTX, NULL_RTX); | |
2750 | } | |
2751 | ||
230d793d | 2752 | if (i1dest_in_i1src) |
58c8c593 | 2753 | { |
1a26b032 | 2754 | if (GET_CODE (i1dest) == REG) |
b1f21e0a | 2755 | REG_N_DEATHS (REGNO (i1dest))++; |
1a26b032 | 2756 | |
58c8c593 | 2757 | if (newi2pat && reg_set_p (i1dest, newi2pat)) |
38a448ca | 2758 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), |
58c8c593 RK |
2759 | NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); |
2760 | else | |
38a448ca | 2761 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), |
58c8c593 RK |
2762 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, |
2763 | NULL_RTX, NULL_RTX); | |
2764 | } | |
230d793d RS |
2765 | |
2766 | distribute_links (i3links); | |
2767 | distribute_links (i2links); | |
2768 | distribute_links (i1links); | |
2769 | ||
2770 | if (GET_CODE (i2dest) == REG) | |
2771 | { | |
d0ab8cd3 RK |
2772 | rtx link; |
2773 | rtx i2_insn = 0, i2_val = 0, set; | |
2774 | ||
2775 | /* The insn that used to set this register doesn't exist, and | |
2776 | this life of the register may not exist either. See if one of | |
663522cb | 2777 | I3's links points to an insn that sets I2DEST. If it does, |
d0ab8cd3 RK |
2778 | that is now the last known value for I2DEST. If we don't update |
2779 | this and I2 set the register to a value that depended on its old | |
230d793d RS |
2780 | contents, we will get confused. If this insn is used, thing |
2781 | will be set correctly in combine_instructions. */ | |
d0ab8cd3 RK |
2782 | |
2783 | for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) | |
2784 | if ((set = single_set (XEXP (link, 0))) != 0 | |
2785 | && rtx_equal_p (i2dest, SET_DEST (set))) | |
2786 | i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); | |
2787 | ||
2788 | record_value_for_reg (i2dest, i2_insn, i2_val); | |
230d793d RS |
2789 | |
2790 | /* If the reg formerly set in I2 died only once and that was in I3, | |
2791 | zero its use count so it won't make `reload' do any work. */ | |
538fe8cd ILT |
2792 | if (! added_sets_2 |
2793 | && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) | |
2794 | && ! i2dest_in_i2src) | |
230d793d RS |
2795 | { |
2796 | regno = REGNO (i2dest); | |
b1f21e0a | 2797 | REG_N_SETS (regno)--; |
230d793d RS |
2798 | } |
2799 | } | |
2800 | ||
2801 | if (i1 && GET_CODE (i1dest) == REG) | |
2802 | { | |
d0ab8cd3 RK |
2803 | rtx link; |
2804 | rtx i1_insn = 0, i1_val = 0, set; | |
2805 | ||
2806 | for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) | |
2807 | if ((set = single_set (XEXP (link, 0))) != 0 | |
2808 | && rtx_equal_p (i1dest, SET_DEST (set))) | |
2809 | i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); | |
2810 | ||
2811 | record_value_for_reg (i1dest, i1_insn, i1_val); | |
2812 | ||
230d793d | 2813 | regno = REGNO (i1dest); |
5af91171 | 2814 | if (! added_sets_1 && ! i1dest_in_i1src) |
770ae6cc | 2815 | REG_N_SETS (regno)--; |
230d793d RS |
2816 | } |
2817 | ||
951553af | 2818 | /* Update reg_nonzero_bits et al for any changes that may have been made |
663522cb | 2819 | to this insn. The order of set_nonzero_bits_and_sign_copies() is |
5fb7c247 | 2820 | important. Because newi2pat can affect nonzero_bits of newpat */ |
22609cbf | 2821 | if (newi2pat) |
84832317 | 2822 | note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); |
5fb7c247 | 2823 | note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); |
22609cbf | 2824 | |
44a76fc8 AG |
2825 | /* Set new_direct_jump_p if a new return or simple jump instruction |
2826 | has been created. | |
2827 | ||
663522cb | 2828 | If I3 is now an unconditional jump, ensure that it has a |
230d793d | 2829 | BARRIER following it since it may have initially been a |
381ee8af | 2830 | conditional jump. It may also be the last nonnote insn. */ |
663522cb | 2831 | |
f40f4c8e | 2832 | if (returnjump_p (i3) || any_uncondjump_p (i3)) |
44a76fc8 AG |
2833 | { |
2834 | *new_direct_jump_p = 1; | |
230d793d | 2835 | |
44a76fc8 AG |
2836 | if ((temp = next_nonnote_insn (i3)) == NULL_RTX |
2837 | || GET_CODE (temp) != BARRIER) | |
2838 | emit_barrier_after (i3); | |
2839 | } | |
f40f4c8e RS |
2840 | |
2841 | if (undobuf.other_insn != NULL_RTX | |
2842 | && (returnjump_p (undobuf.other_insn) | |
2843 | || any_uncondjump_p (undobuf.other_insn))) | |
2844 | { | |
2845 | *new_direct_jump_p = 1; | |
2846 | ||
2847 | if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX | |
2848 | || GET_CODE (temp) != BARRIER) | |
2849 | emit_barrier_after (undobuf.other_insn); | |
2850 | } | |
2851 | ||
592a6d1d JH |
2852 | /* An NOOP jump does not need barrier, but it does need cleaning up |
2853 | of CFG. */ | |
2854 | if (GET_CODE (newpat) == SET | |
2855 | && SET_SRC (newpat) == pc_rtx | |
2856 | && SET_DEST (newpat) == pc_rtx) | |
2857 | *new_direct_jump_p = 1; | |
230d793d RS |
2858 | } |
2859 | ||
2860 | combine_successes++; | |
e7749837 | 2861 | undo_commit (); |
230d793d | 2862 | |
bcd49eb7 JW |
2863 | /* Clear this here, so that subsequent get_last_value calls are not |
2864 | affected. */ | |
2865 | subst_prev_insn = NULL_RTX; | |
2866 | ||
abe6e52f RK |
2867 | if (added_links_insn |
2868 | && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) | |
2869 | && INSN_CUID (added_links_insn) < INSN_CUID (i3)) | |
2870 | return added_links_insn; | |
2871 | else | |
2872 | return newi2pat ? i2 : i3; | |
230d793d RS |
2873 | } |
2874 | \f | |
2875 | /* Undo all the modifications recorded in undobuf. */ | |
2876 | ||
2877 | static void | |
2878 | undo_all () | |
2879 | { | |
241cea85 RK |
2880 | struct undo *undo, *next; |
2881 | ||
2882 | for (undo = undobuf.undos; undo; undo = next) | |
7c046e4e | 2883 | { |
241cea85 RK |
2884 | next = undo->next; |
2885 | if (undo->is_int) | |
2886 | *undo->where.i = undo->old_contents.i; | |
7c046e4e | 2887 | else |
241cea85 RK |
2888 | *undo->where.r = undo->old_contents.r; |
2889 | ||
2890 | undo->next = undobuf.frees; | |
2891 | undobuf.frees = undo; | |
7c046e4e | 2892 | } |
230d793d | 2893 | |
f1c6ba8b | 2894 | undobuf.undos = 0; |
bcd49eb7 JW |
2895 | |
2896 | /* Clear this here, so that subsequent get_last_value calls are not | |
2897 | affected. */ | |
2898 | subst_prev_insn = NULL_RTX; | |
230d793d | 2899 | } |
e7749837 RH |
2900 | |
2901 | /* We've committed to accepting the changes we made. Move all | |
2902 | of the undos to the free list. */ | |
2903 | ||
2904 | static void | |
2905 | undo_commit () | |
2906 | { | |
2907 | struct undo *undo, *next; | |
2908 | ||
2909 | for (undo = undobuf.undos; undo; undo = next) | |
2910 | { | |
2911 | next = undo->next; | |
2912 | undo->next = undobuf.frees; | |
2913 | undobuf.frees = undo; | |
2914 | } | |
f1c6ba8b | 2915 | undobuf.undos = 0; |
e7749837 RH |
2916 | } |
2917 | ||
230d793d RS |
2918 | \f |
2919 | /* Find the innermost point within the rtx at LOC, possibly LOC itself, | |
d0ab8cd3 RK |
2920 | where we have an arithmetic expression and return that point. LOC will |
2921 | be inside INSN. | |
230d793d RS |
2922 | |
2923 | try_combine will call this function to see if an insn can be split into | |
2924 | two insns. */ | |
2925 | ||
2926 | static rtx * | |
d0ab8cd3 | 2927 | find_split_point (loc, insn) |
230d793d | 2928 | rtx *loc; |
d0ab8cd3 | 2929 | rtx insn; |
230d793d RS |
2930 | { |
2931 | rtx x = *loc; | |
2932 | enum rtx_code code = GET_CODE (x); | |
2933 | rtx *split; | |
770ae6cc RK |
2934 | unsigned HOST_WIDE_INT len = 0; |
2935 | HOST_WIDE_INT pos = 0; | |
2936 | int unsignedp = 0; | |
6a651371 | 2937 | rtx inner = NULL_RTX; |
230d793d RS |
2938 | |
2939 | /* First special-case some codes. */ | |
2940 | switch (code) | |
2941 | { | |
2942 | case SUBREG: | |
2943 | #ifdef INSN_SCHEDULING | |
2944 | /* If we are making a paradoxical SUBREG invalid, it becomes a split | |
2945 | point. */ | |
2946 | if (GET_CODE (SUBREG_REG (x)) == MEM) | |
2947 | return loc; | |
2948 | #endif | |
d0ab8cd3 | 2949 | return find_split_point (&SUBREG_REG (x), insn); |
230d793d | 2950 | |
230d793d | 2951 | case MEM: |
916f14f1 | 2952 | #ifdef HAVE_lo_sum |
230d793d RS |
2953 | /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it |
2954 | using LO_SUM and HIGH. */ | |
2955 | if (GET_CODE (XEXP (x, 0)) == CONST | |
2956 | || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
2957 | { | |
2958 | SUBST (XEXP (x, 0), | |
f1c6ba8b RK |
2959 | gen_rtx_LO_SUM (Pmode, |
2960 | gen_rtx_HIGH (Pmode, XEXP (x, 0)), | |
2961 | XEXP (x, 0))); | |
230d793d RS |
2962 | return &XEXP (XEXP (x, 0), 0); |
2963 | } | |
230d793d RS |
2964 | #endif |
2965 | ||
916f14f1 RK |
2966 | /* If we have a PLUS whose second operand is a constant and the |
2967 | address is not valid, perhaps will can split it up using | |
2968 | the machine-specific way to split large constants. We use | |
ddd5a7c1 | 2969 | the first pseudo-reg (one of the virtual regs) as a placeholder; |
916f14f1 RK |
2970 | it will not remain in the result. */ |
2971 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
2972 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2973 | && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) | |
2974 | { | |
2975 | rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
38a448ca | 2976 | rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)), |
916f14f1 RK |
2977 | subst_insn); |
2978 | ||
2979 | /* This should have produced two insns, each of which sets our | |
2980 | placeholder. If the source of the second is a valid address, | |
2981 | we can make put both sources together and make a split point | |
2982 | in the middle. */ | |
2983 | ||
2f937369 DM |
2984 | if (seq |
2985 | && NEXT_INSN (seq) != NULL_RTX | |
2986 | && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX | |
2987 | && GET_CODE (seq) == INSN | |
2988 | && GET_CODE (PATTERN (seq)) == SET | |
2989 | && SET_DEST (PATTERN (seq)) == reg | |
916f14f1 | 2990 | && ! reg_mentioned_p (reg, |
2f937369 DM |
2991 | SET_SRC (PATTERN (seq))) |
2992 | && GET_CODE (NEXT_INSN (seq)) == INSN | |
2993 | && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET | |
2994 | && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg | |
916f14f1 | 2995 | && memory_address_p (GET_MODE (x), |
2f937369 | 2996 | SET_SRC (PATTERN (NEXT_INSN (seq))))) |
916f14f1 | 2997 | { |
2f937369 DM |
2998 | rtx src1 = SET_SRC (PATTERN (seq)); |
2999 | rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); | |
916f14f1 RK |
3000 | |
3001 | /* Replace the placeholder in SRC2 with SRC1. If we can | |
3002 | find where in SRC2 it was placed, that can become our | |
3003 | split point and we can replace this address with SRC2. | |
3004 | Just try two obvious places. */ | |
3005 | ||
3006 | src2 = replace_rtx (src2, reg, src1); | |
3007 | split = 0; | |
3008 | if (XEXP (src2, 0) == src1) | |
3009 | split = &XEXP (src2, 0); | |
3010 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' | |
3011 | && XEXP (XEXP (src2, 0), 0) == src1) | |
3012 | split = &XEXP (XEXP (src2, 0), 0); | |
3013 | ||
3014 | if (split) | |
3015 | { | |
3016 | SUBST (XEXP (x, 0), src2); | |
3017 | return split; | |
3018 | } | |
3019 | } | |
663522cb | 3020 | |
1a26b032 RK |
3021 | /* If that didn't work, perhaps the first operand is complex and |
3022 | needs to be computed separately, so make a split point there. | |
3023 | This will occur on machines that just support REG + CONST | |
3024 | and have a constant moved through some previous computation. */ | |
3025 | ||
3026 | else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o' | |
3027 | && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG | |
3028 | && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0)))) | |
3029 | == 'o'))) | |
3030 | return &XEXP (XEXP (x, 0), 0); | |
916f14f1 RK |
3031 | } |
3032 | break; | |
3033 | ||
230d793d RS |
3034 | case SET: |
3035 | #ifdef HAVE_cc0 | |
3036 | /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a | |
3037 | ZERO_EXTRACT, the most likely reason why this doesn't match is that | |
3038 | we need to put the operand into a register. So split at that | |
3039 | point. */ | |
3040 | ||
3041 | if (SET_DEST (x) == cc0_rtx | |
3042 | && GET_CODE (SET_SRC (x)) != COMPARE | |
3043 | && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT | |
3044 | && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o' | |
3045 | && ! (GET_CODE (SET_SRC (x)) == SUBREG | |
3046 | && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o')) | |
3047 | return &SET_SRC (x); | |
3048 | #endif | |
3049 | ||
3050 | /* See if we can split SET_SRC as it stands. */ | |
d0ab8cd3 | 3051 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3052 | if (split && split != &SET_SRC (x)) |
3053 | return split; | |
3054 | ||
041d7180 JL |
3055 | /* See if we can split SET_DEST as it stands. */ |
3056 | split = find_split_point (&SET_DEST (x), insn); | |
3057 | if (split && split != &SET_DEST (x)) | |
3058 | return split; | |
3059 | ||
230d793d RS |
3060 | /* See if this is a bitfield assignment with everything constant. If |
3061 | so, this is an IOR of an AND, so split it into that. */ | |
3062 | if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
3063 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) | |
5f4f0e22 | 3064 | <= HOST_BITS_PER_WIDE_INT) |
230d793d RS |
3065 | && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT |
3066 | && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT | |
3067 | && GET_CODE (SET_SRC (x)) == CONST_INT | |
3068 | && ((INTVAL (XEXP (SET_DEST (x), 1)) | |
cf0d9408 | 3069 | + INTVAL (XEXP (SET_DEST (x), 2))) |
230d793d RS |
3070 | <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) |
3071 | && ! side_effects_p (XEXP (SET_DEST (x), 0))) | |
3072 | { | |
770ae6cc RK |
3073 | HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); |
3074 | unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); | |
3075 | unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); | |
230d793d RS |
3076 | rtx dest = XEXP (SET_DEST (x), 0); |
3077 | enum machine_mode mode = GET_MODE (dest); | |
5f4f0e22 | 3078 | unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; |
230d793d | 3079 | |
f76b9db2 ILT |
3080 | if (BITS_BIG_ENDIAN) |
3081 | pos = GET_MODE_BITSIZE (mode) - len - pos; | |
230d793d | 3082 | |
770ae6cc | 3083 | if (src == mask) |
230d793d | 3084 | SUBST (SET_SRC (x), |
5f4f0e22 | 3085 | gen_binary (IOR, mode, dest, GEN_INT (src << pos))); |
230d793d RS |
3086 | else |
3087 | SUBST (SET_SRC (x), | |
3088 | gen_binary (IOR, mode, | |
663522cb | 3089 | gen_binary (AND, mode, dest, |
da6886f6 FS |
3090 | gen_int_mode (~(mask << pos), |
3091 | mode)), | |
5f4f0e22 | 3092 | GEN_INT (src << pos))); |
230d793d RS |
3093 | |
3094 | SUBST (SET_DEST (x), dest); | |
3095 | ||
d0ab8cd3 | 3096 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3097 | if (split && split != &SET_SRC (x)) |
3098 | return split; | |
3099 | } | |
3100 | ||
3101 | /* Otherwise, see if this is an operation that we can split into two. | |
3102 | If so, try to split that. */ | |
3103 | code = GET_CODE (SET_SRC (x)); | |
3104 | ||
3105 | switch (code) | |
3106 | { | |
d0ab8cd3 RK |
3107 | case AND: |
3108 | /* If we are AND'ing with a large constant that is only a single | |
3109 | bit and the result is only being used in a context where we | |
da7d8304 | 3110 | need to know if it is zero or nonzero, replace it with a bit |
d0ab8cd3 RK |
3111 | extraction. This will avoid the large constant, which might |
3112 | have taken more than one insn to make. If the constant were | |
3113 | not a valid argument to the AND but took only one insn to make, | |
3114 | this is no worse, but if it took more than one insn, it will | |
3115 | be better. */ | |
3116 | ||
3117 | if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
3118 | && GET_CODE (XEXP (SET_SRC (x), 0)) == REG | |
3119 | && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 | |
3120 | && GET_CODE (SET_DEST (x)) == REG | |
cf0d9408 | 3121 | && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0 |
d0ab8cd3 RK |
3122 | && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) |
3123 | && XEXP (*split, 0) == SET_DEST (x) | |
3124 | && XEXP (*split, 1) == const0_rtx) | |
3125 | { | |
76184def DE |
3126 | rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), |
3127 | XEXP (SET_SRC (x), 0), | |
3128 | pos, NULL_RTX, 1, 1, 0, 0); | |
3129 | if (extraction != 0) | |
3130 | { | |
3131 | SUBST (SET_SRC (x), extraction); | |
3132 | return find_split_point (loc, insn); | |
3133 | } | |
d0ab8cd3 RK |
3134 | } |
3135 | break; | |
3136 | ||
1a6ec070 RK |
3137 | case NE: |
3138 | /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X | |
ec5c56db | 3139 | is known to be on, this can be converted into a NEG of a shift. */ |
1a6ec070 RK |
3140 | if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx |
3141 | && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) | |
4eb2cb10 | 3142 | && 1 <= (pos = exact_log2 |
1a6ec070 RK |
3143 | (nonzero_bits (XEXP (SET_SRC (x), 0), |
3144 | GET_MODE (XEXP (SET_SRC (x), 0)))))) | |
3145 | { | |
3146 | enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); | |
3147 | ||
3148 | SUBST (SET_SRC (x), | |
f1c6ba8b RK |
3149 | gen_rtx_NEG (mode, |
3150 | gen_rtx_LSHIFTRT (mode, | |
3151 | XEXP (SET_SRC (x), 0), | |
3152 | GEN_INT (pos)))); | |
1a6ec070 RK |
3153 | |
3154 | split = find_split_point (&SET_SRC (x), insn); | |
3155 | if (split && split != &SET_SRC (x)) | |
3156 | return split; | |
3157 | } | |
3158 | break; | |
3159 | ||
230d793d RS |
3160 | case SIGN_EXTEND: |
3161 | inner = XEXP (SET_SRC (x), 0); | |
101c1a3d JL |
3162 | |
3163 | /* We can't optimize if either mode is a partial integer | |
3164 | mode as we don't know how many bits are significant | |
3165 | in those modes. */ | |
3166 | if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT | |
3167 | || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) | |
3168 | break; | |
3169 | ||
230d793d RS |
3170 | pos = 0; |
3171 | len = GET_MODE_BITSIZE (GET_MODE (inner)); | |
3172 | unsignedp = 0; | |
3173 | break; | |
3174 | ||
3175 | case SIGN_EXTRACT: | |
3176 | case ZERO_EXTRACT: | |
3177 | if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
3178 | && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) | |
3179 | { | |
3180 | inner = XEXP (SET_SRC (x), 0); | |
3181 | len = INTVAL (XEXP (SET_SRC (x), 1)); | |
3182 | pos = INTVAL (XEXP (SET_SRC (x), 2)); | |
3183 | ||
f76b9db2 ILT |
3184 | if (BITS_BIG_ENDIAN) |
3185 | pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; | |
230d793d RS |
3186 | unsignedp = (code == ZERO_EXTRACT); |
3187 | } | |
3188 | break; | |
e9a25f70 JL |
3189 | |
3190 | default: | |
3191 | break; | |
230d793d RS |
3192 | } |
3193 | ||
3194 | if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) | |
3195 | { | |
3196 | enum machine_mode mode = GET_MODE (SET_SRC (x)); | |
3197 | ||
d0ab8cd3 RK |
3198 | /* For unsigned, we have a choice of a shift followed by an |
3199 | AND or two shifts. Use two shifts for field sizes where the | |
3200 | constant might be too large. We assume here that we can | |
3201 | always at least get 8-bit constants in an AND insn, which is | |
3202 | true for every current RISC. */ | |
3203 | ||
3204 | if (unsignedp && len <= 8) | |
230d793d RS |
3205 | { |
3206 | SUBST (SET_SRC (x), | |
f1c6ba8b RK |
3207 | gen_rtx_AND (mode, |
3208 | gen_rtx_LSHIFTRT | |
3209 | (mode, gen_lowpart_for_combine (mode, inner), | |
3210 | GEN_INT (pos)), | |
3211 | GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); | |
230d793d | 3212 | |
d0ab8cd3 | 3213 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3214 | if (split && split != &SET_SRC (x)) |
3215 | return split; | |
3216 | } | |
3217 | else | |
3218 | { | |
3219 | SUBST (SET_SRC (x), | |
f1c6ba8b | 3220 | gen_rtx_fmt_ee |
d0ab8cd3 | 3221 | (unsignedp ? LSHIFTRT : ASHIFTRT, mode, |
f1c6ba8b RK |
3222 | gen_rtx_ASHIFT (mode, |
3223 | gen_lowpart_for_combine (mode, inner), | |
3224 | GEN_INT (GET_MODE_BITSIZE (mode) | |
3225 | - len - pos)), | |
5f4f0e22 | 3226 | GEN_INT (GET_MODE_BITSIZE (mode) - len))); |
230d793d | 3227 | |
d0ab8cd3 | 3228 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3229 | if (split && split != &SET_SRC (x)) |
3230 | return split; | |
3231 | } | |
3232 | } | |
3233 | ||
3234 | /* See if this is a simple operation with a constant as the second | |
3235 | operand. It might be that this constant is out of range and hence | |
3236 | could be used as a split point. */ | |
3237 | if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' | |
3238 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' | |
3239 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<') | |
3240 | && CONSTANT_P (XEXP (SET_SRC (x), 1)) | |
3241 | && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o' | |
3242 | || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG | |
3243 | && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0)))) | |
3244 | == 'o')))) | |
3245 | return &XEXP (SET_SRC (x), 1); | |
3246 | ||
3247 | /* Finally, see if this is a simple operation with its first operand | |
3248 | not in a register. The operation might require this operand in a | |
3249 | register, so return it as a split point. We can always do this | |
3250 | because if the first operand were another operation, we would have | |
3251 | already found it as a split point. */ | |
3252 | if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' | |
3253 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' | |
3254 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<' | |
3255 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1') | |
3256 | && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) | |
3257 | return &XEXP (SET_SRC (x), 0); | |
3258 | ||
3259 | return 0; | |
3260 | ||
3261 | case AND: | |
3262 | case IOR: | |
3263 | /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, | |
3264 | it is better to write this as (not (ior A B)) so we can split it. | |
3265 | Similarly for IOR. */ | |
3266 | if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) | |
3267 | { | |
3268 | SUBST (*loc, | |
f1c6ba8b RK |
3269 | gen_rtx_NOT (GET_MODE (x), |
3270 | gen_rtx_fmt_ee (code == IOR ? AND : IOR, | |
3271 | GET_MODE (x), | |
3272 | XEXP (XEXP (x, 0), 0), | |
3273 | XEXP (XEXP (x, 1), 0)))); | |
d0ab8cd3 | 3274 | return find_split_point (loc, insn); |
230d793d RS |
3275 | } |
3276 | ||
3277 | /* Many RISC machines have a large set of logical insns. If the | |
3278 | second operand is a NOT, put it first so we will try to split the | |
3279 | other operand first. */ | |
3280 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
3281 | { | |
3282 | rtx tem = XEXP (x, 0); | |
3283 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
3284 | SUBST (XEXP (x, 1), tem); | |
3285 | } | |
3286 | break; | |
e9a25f70 JL |
3287 | |
3288 | default: | |
3289 | break; | |
230d793d RS |
3290 | } |
3291 | ||
3292 | /* Otherwise, select our actions depending on our rtx class. */ | |
3293 | switch (GET_RTX_CLASS (code)) | |
3294 | { | |
3295 | case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ | |
3296 | case '3': | |
d0ab8cd3 | 3297 | split = find_split_point (&XEXP (x, 2), insn); |
230d793d RS |
3298 | if (split) |
3299 | return split; | |
0f41302f | 3300 | /* ... fall through ... */ |
230d793d RS |
3301 | case '2': |
3302 | case 'c': | |
3303 | case '<': | |
d0ab8cd3 | 3304 | split = find_split_point (&XEXP (x, 1), insn); |
230d793d RS |
3305 | if (split) |
3306 | return split; | |
0f41302f | 3307 | /* ... fall through ... */ |
230d793d RS |
3308 | case '1': |
3309 | /* Some machines have (and (shift ...) ...) insns. If X is not | |
3310 | an AND, but XEXP (X, 0) is, use it as our split point. */ | |
3311 | if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) | |
3312 | return &XEXP (x, 0); | |
3313 | ||
d0ab8cd3 | 3314 | split = find_split_point (&XEXP (x, 0), insn); |
230d793d RS |
3315 | if (split) |
3316 | return split; | |
3317 | return loc; | |
3318 | } | |
3319 | ||
3320 | /* Otherwise, we don't have a split point. */ | |
3321 | return 0; | |
3322 | } | |
3323 | \f | |
3324 | /* Throughout X, replace FROM with TO, and return the result. | |
3325 | The result is TO if X is FROM; | |
3326 | otherwise the result is X, but its contents may have been modified. | |
3327 | If they were modified, a record was made in undobuf so that | |
3328 | undo_all will (among other things) return X to its original state. | |
3329 | ||
3330 | If the number of changes necessary is too much to record to undo, | |
3331 | the excess changes are not made, so the result is invalid. | |
3332 | The changes already made can still be undone. | |
3333 | undobuf.num_undo is incremented for such changes, so by testing that | |
3334 | the caller can tell whether the result is valid. | |
3335 | ||
3336 | `n_occurrences' is incremented each time FROM is replaced. | |
663522cb | 3337 | |
da7d8304 | 3338 | IN_DEST is nonzero if we are processing the SET_DEST of a SET. |
230d793d | 3339 | |
da7d8304 KH |
3340 | UNIQUE_COPY is nonzero if each substitution must be unique. We do this |
3341 | by copying if `n_occurrences' is nonzero. */ | |
230d793d RS |
3342 | |
3343 | static rtx | |
3344 | subst (x, from, to, in_dest, unique_copy) | |
b3694847 | 3345 | rtx x, from, to; |
230d793d RS |
3346 | int in_dest; |
3347 | int unique_copy; | |
3348 | { | |
b3694847 | 3349 | enum rtx_code code = GET_CODE (x); |
230d793d | 3350 | enum machine_mode op0_mode = VOIDmode; |
b3694847 SS |
3351 | const char *fmt; |
3352 | int len, i; | |
8079805d | 3353 | rtx new; |
230d793d RS |
3354 | |
3355 | /* Two expressions are equal if they are identical copies of a shared | |
3356 | RTX or if they are both registers with the same register number | |
3357 | and mode. */ | |
3358 | ||
3359 | #define COMBINE_RTX_EQUAL_P(X,Y) \ | |
3360 | ((X) == (Y) \ | |
3361 | || (GET_CODE (X) == REG && GET_CODE (Y) == REG \ | |
3362 | && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) | |
3363 | ||
3364 | if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) | |
3365 | { | |
3366 | n_occurrences++; | |
3367 | return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); | |
3368 | } | |
3369 | ||
3370 | /* If X and FROM are the same register but different modes, they will | |
663522cb | 3371 | not have been seen as equal above. However, flow.c will make a |
230d793d RS |
3372 | LOG_LINKS entry for that case. If we do nothing, we will try to |
3373 | rerecognize our original insn and, when it succeeds, we will | |
3374 | delete the feeding insn, which is incorrect. | |
3375 | ||
3376 | So force this insn not to match in this (rare) case. */ | |
3377 | if (! in_dest && code == REG && GET_CODE (from) == REG | |
3378 | && REGNO (x) == REGNO (from)) | |
38a448ca | 3379 | return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
230d793d RS |
3380 | |
3381 | /* If this is an object, we are done unless it is a MEM or LO_SUM, both | |
3382 | of which may contain things that can be combined. */ | |
3383 | if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o') | |
3384 | return x; | |
3385 | ||
3386 | /* It is possible to have a subexpression appear twice in the insn. | |
3387 | Suppose that FROM is a register that appears within TO. | |
3388 | Then, after that subexpression has been scanned once by `subst', | |
3389 | the second time it is scanned, TO may be found. If we were | |
3390 | to scan TO here, we would find FROM within it and create a | |
3391 | self-referent rtl structure which is completely wrong. */ | |
3392 | if (COMBINE_RTX_EQUAL_P (x, to)) | |
3393 | return to; | |
3394 | ||
4f4b3679 RH |
3395 | /* Parallel asm_operands need special attention because all of the |
3396 | inputs are shared across the arms. Furthermore, unsharing the | |
3397 | rtl results in recognition failures. Failure to handle this case | |
3398 | specially can result in circular rtl. | |
3399 | ||
3400 | Solve this by doing a normal pass across the first entry of the | |
3401 | parallel, and only processing the SET_DESTs of the subsequent | |
3402 | entries. Ug. */ | |
3403 | ||
3404 | if (code == PARALLEL | |
3405 | && GET_CODE (XVECEXP (x, 0, 0)) == SET | |
3406 | && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) | |
230d793d | 3407 | { |
4f4b3679 RH |
3408 | new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); |
3409 | ||
3410 | /* If this substitution failed, this whole thing fails. */ | |
3411 | if (GET_CODE (new) == CLOBBER | |
3412 | && XEXP (new, 0) == const0_rtx) | |
3413 | return new; | |
3414 | ||
3415 | SUBST (XVECEXP (x, 0, 0), new); | |
3416 | ||
3417 | for (i = XVECLEN (x, 0) - 1; i >= 1; i--) | |
230d793d | 3418 | { |
4f4b3679 | 3419 | rtx dest = SET_DEST (XVECEXP (x, 0, i)); |
663522cb | 3420 | |
4f4b3679 RH |
3421 | if (GET_CODE (dest) != REG |
3422 | && GET_CODE (dest) != CC0 | |
3423 | && GET_CODE (dest) != PC) | |
230d793d | 3424 | { |
4f4b3679 | 3425 | new = subst (dest, from, to, 0, unique_copy); |
230d793d | 3426 | |
4f4b3679 RH |
3427 | /* If this substitution failed, this whole thing fails. */ |
3428 | if (GET_CODE (new) == CLOBBER | |
3429 | && XEXP (new, 0) == const0_rtx) | |
3430 | return new; | |
230d793d | 3431 | |
4f4b3679 | 3432 | SUBST (SET_DEST (XVECEXP (x, 0, i)), new); |
230d793d RS |
3433 | } |
3434 | } | |
4f4b3679 RH |
3435 | } |
3436 | else | |
3437 | { | |
3438 | len = GET_RTX_LENGTH (code); | |
3439 | fmt = GET_RTX_FORMAT (code); | |
3440 | ||
3441 | /* We don't need to process a SET_DEST that is a register, CC0, | |
3442 | or PC, so set up to skip this common case. All other cases | |
3443 | where we want to suppress replacing something inside a | |
3444 | SET_SRC are handled via the IN_DEST operand. */ | |
3445 | if (code == SET | |
3446 | && (GET_CODE (SET_DEST (x)) == REG | |
3447 | || GET_CODE (SET_DEST (x)) == CC0 | |
3448 | || GET_CODE (SET_DEST (x)) == PC)) | |
3449 | fmt = "ie"; | |
3450 | ||
3451 | /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a | |
3452 | constant. */ | |
3453 | if (fmt[0] == 'e') | |
3454 | op0_mode = GET_MODE (XEXP (x, 0)); | |
3455 | ||
3456 | for (i = 0; i < len; i++) | |
230d793d | 3457 | { |
4f4b3679 | 3458 | if (fmt[i] == 'E') |
230d793d | 3459 | { |
b3694847 | 3460 | int j; |
4f4b3679 RH |
3461 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
3462 | { | |
3463 | if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) | |
3464 | { | |
3465 | new = (unique_copy && n_occurrences | |
3466 | ? copy_rtx (to) : to); | |
3467 | n_occurrences++; | |
3468 | } | |
3469 | else | |
3470 | { | |
3471 | new = subst (XVECEXP (x, i, j), from, to, 0, | |
3472 | unique_copy); | |
3473 | ||
3474 | /* If this substitution failed, this whole thing | |
3475 | fails. */ | |
3476 | if (GET_CODE (new) == CLOBBER | |
3477 | && XEXP (new, 0) == const0_rtx) | |
3478 | return new; | |
3479 | } | |
3480 | ||
3481 | SUBST (XVECEXP (x, i, j), new); | |
3482 | } | |
3483 | } | |
3484 | else if (fmt[i] == 'e') | |
3485 | { | |
0a33d11e RH |
3486 | /* If this is a register being set, ignore it. */ |
3487 | new = XEXP (x, i); | |
3488 | if (in_dest | |
3489 | && (code == SUBREG || code == STRICT_LOW_PART | |
3490 | || code == ZERO_EXTRACT) | |
3491 | && i == 0 | |
3492 | && GET_CODE (new) == REG) | |
3493 | ; | |
3494 | ||
3495 | else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) | |
4f4b3679 RH |
3496 | { |
3497 | /* In general, don't install a subreg involving two | |
3498 | modes not tieable. It can worsen register | |
3499 | allocation, and can even make invalid reload | |
3500 | insns, since the reg inside may need to be copied | |
3501 | from in the outside mode, and that may be invalid | |
3502 | if it is an fp reg copied in integer mode. | |
3503 | ||
3504 | We allow two exceptions to this: It is valid if | |
3505 | it is inside another SUBREG and the mode of that | |
3506 | SUBREG and the mode of the inside of TO is | |
3507 | tieable and it is valid if X is a SET that copies | |
3508 | FROM to CC0. */ | |
3509 | ||
3510 | if (GET_CODE (to) == SUBREG | |
3511 | && ! MODES_TIEABLE_P (GET_MODE (to), | |
3512 | GET_MODE (SUBREG_REG (to))) | |
3513 | && ! (code == SUBREG | |
3514 | && MODES_TIEABLE_P (GET_MODE (x), | |
3515 | GET_MODE (SUBREG_REG (to)))) | |
42301240 | 3516 | #ifdef HAVE_cc0 |
4f4b3679 | 3517 | && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) |
42301240 | 3518 | #endif |
4f4b3679 RH |
3519 | ) |
3520 | return gen_rtx_CLOBBER (VOIDmode, const0_rtx); | |
42301240 | 3521 | |
02188693 | 3522 | #ifdef CLASS_CANNOT_CHANGE_MODE |
ed8afe3a GK |
3523 | if (code == SUBREG |
3524 | && GET_CODE (to) == REG | |
3525 | && REGNO (to) < FIRST_PSEUDO_REGISTER | |
3526 | && (TEST_HARD_REG_BIT | |
02188693 | 3527 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], |
ed8afe3a | 3528 | REGNO (to))) |
02188693 RH |
3529 | && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to), |
3530 | GET_MODE (x))) | |
ed8afe3a GK |
3531 | return gen_rtx_CLOBBER (VOIDmode, const0_rtx); |
3532 | #endif | |
3533 | ||
4f4b3679 RH |
3534 | new = (unique_copy && n_occurrences ? copy_rtx (to) : to); |
3535 | n_occurrences++; | |
3536 | } | |
3537 | else | |
3538 | /* If we are in a SET_DEST, suppress most cases unless we | |
3539 | have gone inside a MEM, in which case we want to | |
3540 | simplify the address. We assume here that things that | |
3541 | are actually part of the destination have their inner | |
663522cb | 3542 | parts in the first expression. This is true for SUBREG, |
4f4b3679 RH |
3543 | STRICT_LOW_PART, and ZERO_EXTRACT, which are the only |
3544 | things aside from REG and MEM that should appear in a | |
3545 | SET_DEST. */ | |
3546 | new = subst (XEXP (x, i), from, to, | |
3547 | (((in_dest | |
3548 | && (code == SUBREG || code == STRICT_LOW_PART | |
3549 | || code == ZERO_EXTRACT)) | |
3550 | || code == SET) | |
3551 | && i == 0), unique_copy); | |
3552 | ||
3553 | /* If we found that we will have to reject this combination, | |
3554 | indicate that by returning the CLOBBER ourselves, rather than | |
3555 | an expression containing it. This will speed things up as | |
3556 | well as prevent accidents where two CLOBBERs are considered | |
3557 | to be equal, thus producing an incorrect simplification. */ | |
3558 | ||
3559 | if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) | |
3560 | return new; | |
3561 | ||
4161da12 AO |
3562 | if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG) |
3563 | { | |
b0dd4808 | 3564 | enum machine_mode mode = GET_MODE (x); |
2e676d78 | 3565 | |
4161da12 AO |
3566 | x = simplify_subreg (GET_MODE (x), new, |
3567 | GET_MODE (SUBREG_REG (x)), | |
3568 | SUBREG_BYTE (x)); | |
3569 | if (! x) | |
b0dd4808 | 3570 | x = gen_rtx_CLOBBER (mode, const0_rtx); |
4161da12 AO |
3571 | } |
3572 | else if (GET_CODE (new) == CONST_INT | |
3573 | && GET_CODE (x) == ZERO_EXTEND) | |
3574 | { | |
3575 | x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
3576 | new, GET_MODE (XEXP (x, 0))); | |
3577 | if (! x) | |
3578 | abort (); | |
3579 | } | |
3580 | else | |
3581 | SUBST (XEXP (x, i), new); | |
230d793d | 3582 | } |
230d793d RS |
3583 | } |
3584 | } | |
3585 | ||
8079805d RK |
3586 | /* Try to simplify X. If the simplification changed the code, it is likely |
3587 | that further simplification will help, so loop, but limit the number | |
3588 | of repetitions that will be performed. */ | |
3589 | ||
3590 | for (i = 0; i < 4; i++) | |
3591 | { | |
3592 | /* If X is sufficiently simple, don't bother trying to do anything | |
3593 | with it. */ | |
3594 | if (code != CONST_INT && code != REG && code != CLOBBER) | |
31ec4e5e | 3595 | x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest); |
d0ab8cd3 | 3596 | |
8079805d RK |
3597 | if (GET_CODE (x) == code) |
3598 | break; | |
d0ab8cd3 | 3599 | |
8079805d | 3600 | code = GET_CODE (x); |
eeb43d32 | 3601 | |
8079805d RK |
3602 | /* We no longer know the original mode of operand 0 since we |
3603 | have changed the form of X) */ | |
3604 | op0_mode = VOIDmode; | |
3605 | } | |
eeb43d32 | 3606 | |
8079805d RK |
3607 | return x; |
3608 | } | |
3609 | \f | |
3610 | /* Simplify X, a piece of RTL. We just operate on the expression at the | |
3611 | outer level; call `subst' to simplify recursively. Return the new | |
3612 | expression. | |
3613 | ||
3614 | OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this | |
3615 | will be the iteration even if an expression with a code different from | |
3616 | X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */ | |
eeb43d32 | 3617 | |
8079805d | 3618 | static rtx |
31ec4e5e | 3619 | combine_simplify_rtx (x, op0_mode, last, in_dest) |
8079805d RK |
3620 | rtx x; |
3621 | enum machine_mode op0_mode; | |
3622 | int last; | |
3623 | int in_dest; | |
3624 | { | |
3625 | enum rtx_code code = GET_CODE (x); | |
3626 | enum machine_mode mode = GET_MODE (x); | |
3627 | rtx temp; | |
9a915772 | 3628 | rtx reversed; |
8079805d | 3629 | int i; |
d0ab8cd3 | 3630 | |
230d793d RS |
3631 | /* If this is a commutative operation, put a constant last and a complex |
3632 | expression first. We don't need to do this for comparisons here. */ | |
3633 | if (GET_RTX_CLASS (code) == 'c' | |
e5c56fd9 | 3634 | && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) |
230d793d RS |
3635 | { |
3636 | temp = XEXP (x, 0); | |
3637 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
3638 | SUBST (XEXP (x, 1), temp); | |
3639 | } | |
3640 | ||
22609cbf RK |
3641 | /* If this is a PLUS, MINUS, or MULT, and the first operand is the |
3642 | sign extension of a PLUS with a constant, reverse the order of the sign | |
3643 | extension and the addition. Note that this not the same as the original | |
3644 | code, but overflow is undefined for signed values. Also note that the | |
3645 | PLUS will have been partially moved "inside" the sign-extension, so that | |
3646 | the first operand of X will really look like: | |
3647 | (ashiftrt (plus (ashift A C4) C5) C4). | |
3648 | We convert this to | |
3649 | (plus (ashiftrt (ashift A C4) C2) C4) | |
3650 | and replace the first operand of X with that expression. Later parts | |
3651 | of this function may simplify the expression further. | |
3652 | ||
3653 | For example, if we start with (mult (sign_extend (plus A C1)) C2), | |
3654 | we swap the SIGN_EXTEND and PLUS. Later code will apply the | |
3655 | distributive law to produce (plus (mult (sign_extend X) C1) C3). | |
3656 | ||
3657 | We do this to simplify address expressions. */ | |
3658 | ||
3659 | if ((code == PLUS || code == MINUS || code == MULT) | |
3660 | && GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
3661 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS | |
3662 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT | |
3663 | && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT | |
3664 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3665 | && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1) | |
3666 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
3667 | && (temp = simplify_binary_operation (ASHIFTRT, mode, | |
3668 | XEXP (XEXP (XEXP (x, 0), 0), 1), | |
3669 | XEXP (XEXP (x, 0), 1))) != 0) | |
3670 | { | |
3671 | rtx new | |
3672 | = simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
3673 | XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0), | |
3674 | INTVAL (XEXP (XEXP (x, 0), 1))); | |
3675 | ||
3676 | new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new, | |
3677 | INTVAL (XEXP (XEXP (x, 0), 1))); | |
3678 | ||
3679 | SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp)); | |
3680 | } | |
3681 | ||
663522cb | 3682 | /* If this is a simple operation applied to an IF_THEN_ELSE, try |
d0ab8cd3 | 3683 | applying it to the arms of the IF_THEN_ELSE. This often simplifies |
abe6e52f RK |
3684 | things. Check for cases where both arms are testing the same |
3685 | condition. | |
3686 | ||
3687 | Don't do anything if all operands are very simple. */ | |
3688 | ||
3689 | if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c' | |
3690 | || GET_RTX_CLASS (code) == '<') | |
3691 | && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' | |
3692 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG | |
3693 | && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) | |
3694 | == 'o'))) | |
3695 | || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o' | |
3696 | && ! (GET_CODE (XEXP (x, 1)) == SUBREG | |
3697 | && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1)))) | |
3698 | == 'o'))))) | |
3699 | || (GET_RTX_CLASS (code) == '1' | |
3700 | && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' | |
3701 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG | |
3702 | && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) | |
3703 | == 'o')))))) | |
d0ab8cd3 | 3704 | { |
d6edb99e | 3705 | rtx cond, true_rtx, false_rtx; |
abe6e52f | 3706 | |
d6edb99e | 3707 | cond = if_then_else_cond (x, &true_rtx, &false_rtx); |
0802d516 RK |
3708 | if (cond != 0 |
3709 | /* If everything is a comparison, what we have is highly unlikely | |
3710 | to be simpler, so don't use it. */ | |
3711 | && ! (GET_RTX_CLASS (code) == '<' | |
d6edb99e ZW |
3712 | && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<' |
3713 | || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<'))) | |
abe6e52f RK |
3714 | { |
3715 | rtx cop1 = const0_rtx; | |
3716 | enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); | |
3717 | ||
15448afc RK |
3718 | if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<') |
3719 | return x; | |
3720 | ||
663522cb | 3721 | /* Simplify the alternative arms; this may collapse the true and |
9210df58 | 3722 | false arms to store-flag values. */ |
d6edb99e ZW |
3723 | true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0); |
3724 | false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0); | |
9210df58 | 3725 | |
d6edb99e | 3726 | /* If true_rtx and false_rtx are not general_operands, an if_then_else |
085f1714 | 3727 | is unlikely to be simpler. */ |
d6edb99e ZW |
3728 | if (general_operand (true_rtx, VOIDmode) |
3729 | && general_operand (false_rtx, VOIDmode)) | |
085f1714 RH |
3730 | { |
3731 | /* Restarting if we generate a store-flag expression will cause | |
3732 | us to loop. Just drop through in this case. */ | |
3733 | ||
3734 | /* If the result values are STORE_FLAG_VALUE and zero, we can | |
3735 | just make the comparison operation. */ | |
d6edb99e | 3736 | if (true_rtx == const_true_rtx && false_rtx == const0_rtx) |
085f1714 | 3737 | x = gen_binary (cond_code, mode, cond, cop1); |
fa4e13e0 RH |
3738 | else if (true_rtx == const0_rtx && false_rtx == const_true_rtx |
3739 | && reverse_condition (cond_code) != UNKNOWN) | |
085f1714 RH |
3740 | x = gen_binary (reverse_condition (cond_code), |
3741 | mode, cond, cop1); | |
3742 | ||
3743 | /* Likewise, we can make the negate of a comparison operation | |
3744 | if the result values are - STORE_FLAG_VALUE and zero. */ | |
d6edb99e ZW |
3745 | else if (GET_CODE (true_rtx) == CONST_INT |
3746 | && INTVAL (true_rtx) == - STORE_FLAG_VALUE | |
3747 | && false_rtx == const0_rtx) | |
f1c6ba8b RK |
3748 | x = simplify_gen_unary (NEG, mode, |
3749 | gen_binary (cond_code, mode, cond, | |
3750 | cop1), | |
3751 | mode); | |
d6edb99e ZW |
3752 | else if (GET_CODE (false_rtx) == CONST_INT |
3753 | && INTVAL (false_rtx) == - STORE_FLAG_VALUE | |
3754 | && true_rtx == const0_rtx) | |
f1c6ba8b RK |
3755 | x = simplify_gen_unary (NEG, mode, |
3756 | gen_binary (reverse_condition | |
3757 | (cond_code), | |
3758 | mode, cond, cop1), | |
3759 | mode); | |
085f1714 RH |
3760 | else |
3761 | return gen_rtx_IF_THEN_ELSE (mode, | |
3762 | gen_binary (cond_code, VOIDmode, | |
3763 | cond, cop1), | |
d6edb99e | 3764 | true_rtx, false_rtx); |
5109d49f | 3765 | |
085f1714 RH |
3766 | code = GET_CODE (x); |
3767 | op0_mode = VOIDmode; | |
3768 | } | |
abe6e52f | 3769 | } |
d0ab8cd3 RK |
3770 | } |
3771 | ||
230d793d RS |
3772 | /* Try to fold this expression in case we have constants that weren't |
3773 | present before. */ | |
3774 | temp = 0; | |
3775 | switch (GET_RTX_CLASS (code)) | |
3776 | { | |
3777 | case '1': | |
3778 | temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); | |
3779 | break; | |
3780 | case '<': | |
47b1e19b JH |
3781 | { |
3782 | enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); | |
3783 | if (cmp_mode == VOIDmode) | |
1cac8785 DD |
3784 | { |
3785 | cmp_mode = GET_MODE (XEXP (x, 1)); | |
3786 | if (cmp_mode == VOIDmode) | |
3787 | cmp_mode = op0_mode; | |
3788 | } | |
47b1e19b JH |
3789 | temp = simplify_relational_operation (code, cmp_mode, |
3790 | XEXP (x, 0), XEXP (x, 1)); | |
3791 | } | |
77fa0940 | 3792 | #ifdef FLOAT_STORE_FLAG_VALUE |
12530dbe RH |
3793 | if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT) |
3794 | { | |
3795 | if (temp == const0_rtx) | |
3796 | temp = CONST0_RTX (mode); | |
3797 | else | |
5692c7bc ZW |
3798 | temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode), |
3799 | mode); | |
12530dbe | 3800 | } |
77fa0940 | 3801 | #endif |
230d793d RS |
3802 | break; |
3803 | case 'c': | |
3804 | case '2': | |
3805 | temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); | |
3806 | break; | |
3807 | case 'b': | |
3808 | case '3': | |
3809 | temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), | |
3810 | XEXP (x, 1), XEXP (x, 2)); | |
3811 | break; | |
3812 | } | |
3813 | ||
3814 | if (temp) | |
4531c1c7 DN |
3815 | { |
3816 | x = temp; | |
3817 | code = GET_CODE (temp); | |
3818 | op0_mode = VOIDmode; | |
3819 | mode = GET_MODE (temp); | |
3820 | } | |
230d793d | 3821 | |
230d793d | 3822 | /* First see if we can apply the inverse distributive law. */ |
224eeff2 RK |
3823 | if (code == PLUS || code == MINUS |
3824 | || code == AND || code == IOR || code == XOR) | |
230d793d RS |
3825 | { |
3826 | x = apply_distributive_law (x); | |
3827 | code = GET_CODE (x); | |
6e20204f | 3828 | op0_mode = VOIDmode; |
230d793d RS |
3829 | } |
3830 | ||
3831 | /* If CODE is an associative operation not otherwise handled, see if we | |
3832 | can associate some operands. This can win if they are constants or | |
e0e08ac2 | 3833 | if they are logically related (i.e. (a & b) & a). */ |
493efd37 TM |
3834 | if ((code == PLUS || code == MINUS || code == MULT || code == DIV |
3835 | || code == AND || code == IOR || code == XOR | |
230d793d | 3836 | || code == SMAX || code == SMIN || code == UMAX || code == UMIN) |
493efd37 | 3837 | && ((INTEGRAL_MODE_P (mode) && code != DIV) |
4ba5f925 | 3838 | || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode)))) |
230d793d RS |
3839 | { |
3840 | if (GET_CODE (XEXP (x, 0)) == code) | |
3841 | { | |
3842 | rtx other = XEXP (XEXP (x, 0), 0); | |
3843 | rtx inner_op0 = XEXP (XEXP (x, 0), 1); | |
3844 | rtx inner_op1 = XEXP (x, 1); | |
3845 | rtx inner; | |
663522cb | 3846 | |
230d793d RS |
3847 | /* Make sure we pass the constant operand if any as the second |
3848 | one if this is a commutative operation. */ | |
3849 | if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c') | |
3850 | { | |
3851 | rtx tem = inner_op0; | |
3852 | inner_op0 = inner_op1; | |
3853 | inner_op1 = tem; | |
3854 | } | |
3855 | inner = simplify_binary_operation (code == MINUS ? PLUS | |
3856 | : code == DIV ? MULT | |
230d793d RS |
3857 | : code, |
3858 | mode, inner_op0, inner_op1); | |
3859 | ||
3860 | /* For commutative operations, try the other pair if that one | |
3861 | didn't simplify. */ | |
3862 | if (inner == 0 && GET_RTX_CLASS (code) == 'c') | |
3863 | { | |
3864 | other = XEXP (XEXP (x, 0), 1); | |
3865 | inner = simplify_binary_operation (code, mode, | |
3866 | XEXP (XEXP (x, 0), 0), | |
3867 | XEXP (x, 1)); | |
3868 | } | |
3869 | ||
3870 | if (inner) | |
8079805d | 3871 | return gen_binary (code, mode, other, inner); |
230d793d RS |
3872 | } |
3873 | } | |
3874 | ||
3875 | /* A little bit of algebraic simplification here. */ | |
3876 | switch (code) | |
3877 | { | |
3878 | case MEM: | |
3879 | /* Ensure that our address has any ASHIFTs converted to MULT in case | |
3880 | address-recognizing predicates are called later. */ | |
3881 | temp = make_compound_operation (XEXP (x, 0), MEM); | |
3882 | SUBST (XEXP (x, 0), temp); | |
3883 | break; | |
3884 | ||
3885 | case SUBREG: | |
eea50aa0 JH |
3886 | if (op0_mode == VOIDmode) |
3887 | op0_mode = GET_MODE (SUBREG_REG (x)); | |
230d793d | 3888 | |
eea50aa0 | 3889 | /* simplify_subreg can't use gen_lowpart_for_combine. */ |
3c99d5ff | 3890 | if (CONSTANT_P (SUBREG_REG (x)) |
156755ac JJ |
3891 | && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) |
3892 | /* Don't call gen_lowpart_for_combine if the inner mode | |
3893 | is VOIDmode and we cannot simplify it, as SUBREG without | |
3894 | inner mode is invalid. */ | |
3895 | && (GET_MODE (SUBREG_REG (x)) != VOIDmode | |
3896 | || gen_lowpart_common (mode, SUBREG_REG (x)))) | |
230d793d RS |
3897 | return gen_lowpart_for_combine (mode, SUBREG_REG (x)); |
3898 | ||
a13287e1 AM |
3899 | if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) |
3900 | break; | |
eea50aa0 JH |
3901 | { |
3902 | rtx temp; | |
3903 | temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, | |
23190837 | 3904 | SUBREG_BYTE (x)); |
eea50aa0 JH |
3905 | if (temp) |
3906 | return temp; | |
3907 | } | |
b65c1b5b | 3908 | |
30984c57 JJ |
3909 | /* Don't change the mode of the MEM if that would change the meaning |
3910 | of the address. */ | |
3911 | if (GET_CODE (SUBREG_REG (x)) == MEM | |
3912 | && (MEM_VOLATILE_P (SUBREG_REG (x)) | |
3913 | || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0)))) | |
3914 | return gen_rtx_CLOBBER (mode, const0_rtx); | |
3915 | ||
87e3e0c1 RK |
3916 | /* Note that we cannot do any narrowing for non-constants since |
3917 | we might have been counting on using the fact that some bits were | |
3918 | zero. We now do this in the SET. */ | |
3919 | ||
230d793d RS |
3920 | break; |
3921 | ||
3922 | case NOT: | |
3923 | /* (not (plus X -1)) can become (neg X). */ | |
3924 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
3925 | && XEXP (XEXP (x, 0), 1) == constm1_rtx) | |
f1c6ba8b | 3926 | return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0)); |
230d793d RS |
3927 | |
3928 | /* Similarly, (not (neg X)) is (plus X -1). */ | |
3929 | if (GET_CODE (XEXP (x, 0)) == NEG) | |
f1c6ba8b | 3930 | return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx); |
230d793d | 3931 | |
663522cb | 3932 | /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */ |
d0ab8cd3 RK |
3933 | if (GET_CODE (XEXP (x, 0)) == XOR |
3934 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3935 | && (temp = simplify_unary_operation (NOT, mode, | |
3936 | XEXP (XEXP (x, 0), 1), | |
3937 | mode)) != 0) | |
787745f5 | 3938 | return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp); |
663522cb | 3939 | |
230d793d RS |
3940 | /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands |
3941 | other than 1, but that is not valid. We could do a similar | |
3942 | simplification for (not (lshiftrt C X)) where C is just the sign bit, | |
3943 | but this doesn't seem common enough to bother with. */ | |
3944 | if (GET_CODE (XEXP (x, 0)) == ASHIFT | |
3945 | && XEXP (XEXP (x, 0), 0) == const1_rtx) | |
f1c6ba8b RK |
3946 | return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode, |
3947 | const1_rtx, mode), | |
38a448ca | 3948 | XEXP (XEXP (x, 0), 1)); |
663522cb | 3949 | |
230d793d RS |
3950 | if (GET_CODE (XEXP (x, 0)) == SUBREG |
3951 | && subreg_lowpart_p (XEXP (x, 0)) | |
3952 | && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) | |
3953 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) | |
3954 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT | |
3955 | && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) | |
3956 | { | |
3957 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); | |
3958 | ||
38a448ca | 3959 | x = gen_rtx_ROTATE (inner_mode, |
f1c6ba8b RK |
3960 | simplify_gen_unary (NOT, inner_mode, const1_rtx, |
3961 | inner_mode), | |
38a448ca | 3962 | XEXP (SUBREG_REG (XEXP (x, 0)), 1)); |
8079805d | 3963 | return gen_lowpart_for_combine (mode, x); |
230d793d | 3964 | } |
663522cb | 3965 | |
0802d516 RK |
3966 | /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by |
3967 | reversing the comparison code if valid. */ | |
3968 | if (STORE_FLAG_VALUE == -1 | |
3969 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
9a915772 JH |
3970 | && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0), |
3971 | XEXP (XEXP (x, 0), 1)))) | |
3972 | return reversed; | |
500c518b | 3973 | |
e61465ed GS |
3974 | /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1 |
3975 | is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can | |
0802d516 | 3976 | perform the above simplification. */ |
500c518b | 3977 | |
0802d516 | 3978 | if (STORE_FLAG_VALUE == -1 |
500c518b RK |
3979 | && GET_CODE (XEXP (x, 0)) == ASHIFTRT |
3980 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3981 | && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) | |
f1c6ba8b | 3982 | return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx); |
230d793d RS |
3983 | |
3984 | /* Apply De Morgan's laws to reduce number of patterns for machines | |
23190837 AJ |
3985 | with negating logical insns (and-not, nand, etc.). If result has |
3986 | only one NOT, put it first, since that is how the patterns are | |
3987 | coded. */ | |
230d793d RS |
3988 | |
3989 | if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) | |
23190837 | 3990 | { |
663522cb | 3991 | rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); |
5bd60ce6 | 3992 | enum machine_mode op_mode; |
230d793d | 3993 | |
5bd60ce6 | 3994 | op_mode = GET_MODE (in1); |
f1c6ba8b | 3995 | in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode); |
230d793d | 3996 | |
5bd60ce6 RH |
3997 | op_mode = GET_MODE (in2); |
3998 | if (op_mode == VOIDmode) | |
3999 | op_mode = mode; | |
f1c6ba8b | 4000 | in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode); |
663522cb | 4001 | |
5bd60ce6 | 4002 | if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT) |
663522cb KH |
4003 | { |
4004 | rtx tem = in2; | |
4005 | in2 = in1; in1 = tem; | |
4006 | } | |
4007 | ||
f1c6ba8b RK |
4008 | return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, |
4009 | mode, in1, in2); | |
663522cb | 4010 | } |
230d793d RS |
4011 | break; |
4012 | ||
4013 | case NEG: | |
4014 | /* (neg (plus X 1)) can become (not X). */ | |
4015 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
4016 | && XEXP (XEXP (x, 0), 1) == const1_rtx) | |
f1c6ba8b | 4017 | return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0)); |
230d793d RS |
4018 | |
4019 | /* Similarly, (neg (not X)) is (plus X 1). */ | |
4020 | if (GET_CODE (XEXP (x, 0)) == NOT) | |
8079805d | 4021 | return plus_constant (XEXP (XEXP (x, 0), 0), 1); |
230d793d | 4022 | |
71925bc0 RS |
4023 | /* (neg (minus X Y)) can become (minus Y X). This transformation |
4024 | isn't safe for modes with signed zeros, since if X and Y are | |
4025 | both +0, (minus Y X) is the same as (minus X Y). If the rounding | |
4026 | mode is towards +infinity (or -infinity) then the two expressions | |
4027 | will be rounded differently. */ | |
230d793d | 4028 | if (GET_CODE (XEXP (x, 0)) == MINUS |
71925bc0 RS |
4029 | && !HONOR_SIGNED_ZEROS (mode) |
4030 | && !HONOR_SIGN_DEPENDENT_ROUNDING (mode)) | |
8079805d RK |
4031 | return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1), |
4032 | XEXP (XEXP (x, 0), 0)); | |
230d793d | 4033 | |
0f41302f | 4034 | /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ |
d0ab8cd3 | 4035 | if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx |
951553af | 4036 | && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) |
8079805d | 4037 | return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); |
d0ab8cd3 | 4038 | |
230d793d RS |
4039 | /* NEG commutes with ASHIFT since it is multiplication. Only do this |
4040 | if we can then eliminate the NEG (e.g., | |
4041 | if the operand is a constant). */ | |
4042 | ||
4043 | if (GET_CODE (XEXP (x, 0)) == ASHIFT) | |
4044 | { | |
4045 | temp = simplify_unary_operation (NEG, mode, | |
4046 | XEXP (XEXP (x, 0), 0), mode); | |
4047 | if (temp) | |
9def18da | 4048 | return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1)); |
230d793d RS |
4049 | } |
4050 | ||
4051 | temp = expand_compound_operation (XEXP (x, 0)); | |
4052 | ||
4053 | /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be | |
23190837 | 4054 | replaced by (lshiftrt X C). This will convert |
230d793d RS |
4055 | (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ |
4056 | ||
4057 | if (GET_CODE (temp) == ASHIFTRT | |
4058 | && GET_CODE (XEXP (temp, 1)) == CONST_INT | |
4059 | && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) | |
8079805d RK |
4060 | return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), |
4061 | INTVAL (XEXP (temp, 1))); | |
230d793d | 4062 | |
951553af | 4063 | /* If X has only a single bit that might be nonzero, say, bit I, convert |
230d793d RS |
4064 | (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of |
4065 | MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to | |
4066 | (sign_extract X 1 Y). But only do this if TEMP isn't a register | |
4067 | or a SUBREG of one since we'd be making the expression more | |
4068 | complex if it was just a register. */ | |
4069 | ||
4070 | if (GET_CODE (temp) != REG | |
4071 | && ! (GET_CODE (temp) == SUBREG | |
4072 | && GET_CODE (SUBREG_REG (temp)) == REG) | |
951553af | 4073 | && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) |
230d793d RS |
4074 | { |
4075 | rtx temp1 = simplify_shift_const | |
5f4f0e22 CH |
4076 | (NULL_RTX, ASHIFTRT, mode, |
4077 | simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, | |
230d793d RS |
4078 | GET_MODE_BITSIZE (mode) - 1 - i), |
4079 | GET_MODE_BITSIZE (mode) - 1 - i); | |
4080 | ||
4081 | /* If all we did was surround TEMP with the two shifts, we | |
4082 | haven't improved anything, so don't use it. Otherwise, | |
4083 | we are better off with TEMP1. */ | |
4084 | if (GET_CODE (temp1) != ASHIFTRT | |
4085 | || GET_CODE (XEXP (temp1, 0)) != ASHIFT | |
4086 | || XEXP (XEXP (temp1, 0), 0) != temp) | |
8079805d | 4087 | return temp1; |
230d793d RS |
4088 | } |
4089 | break; | |
4090 | ||
2ca9ae17 | 4091 | case TRUNCATE: |
e30fb98f JL |
4092 | /* We can't handle truncation to a partial integer mode here |
4093 | because we don't know the real bitsize of the partial | |
4094 | integer mode. */ | |
4095 | if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
4096 | break; | |
4097 | ||
80608e27 JL |
4098 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
4099 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
4100 | GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) | |
2ca9ae17 JW |
4101 | SUBST (XEXP (x, 0), |
4102 | force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), | |
4103 | GET_MODE_MASK (mode), NULL_RTX, 0)); | |
0f13a422 ILT |
4104 | |
4105 | /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */ | |
4106 | if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
4107 | || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
4108 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) | |
4109 | return XEXP (XEXP (x, 0), 0); | |
4110 | ||
4111 | /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is | |
4112 | (OP:SI foo:SI) if OP is NEG or ABS. */ | |
4113 | if ((GET_CODE (XEXP (x, 0)) == ABS | |
4114 | || GET_CODE (XEXP (x, 0)) == NEG) | |
4115 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND | |
4116 | || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND) | |
4117 | && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) | |
f1c6ba8b RK |
4118 | return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, |
4119 | XEXP (XEXP (XEXP (x, 0), 0), 0), mode); | |
0f13a422 ILT |
4120 | |
4121 | /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is | |
4122 | (truncate:SI x). */ | |
4123 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
4124 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE | |
4125 | && subreg_lowpart_p (XEXP (x, 0))) | |
4126 | return SUBREG_REG (XEXP (x, 0)); | |
4127 | ||
4128 | /* If we know that the value is already truncated, we can | |
14a774a9 RK |
4129 | replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION |
4130 | is nonzero for the corresponding modes. But don't do this | |
4131 | for an (LSHIFTRT (MULT ...)) since this will cause problems | |
4132 | with the umulXi3_highpart patterns. */ | |
6a992214 JL |
4133 | if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
4134 | GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) | |
4135 | && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
26c34780 | 4136 | >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1) |
14a774a9 | 4137 | && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT |
23190837 | 4138 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)) |
0f13a422 ILT |
4139 | return gen_lowpart_for_combine (mode, XEXP (x, 0)); |
4140 | ||
4141 | /* A truncate of a comparison can be replaced with a subreg if | |
4142 | STORE_FLAG_VALUE permits. This is like the previous test, | |
4143 | but it works even if the comparison is done in a mode larger | |
4144 | than HOST_BITS_PER_WIDE_INT. */ | |
4145 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
4146 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
663522cb | 4147 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0) |
0f13a422 ILT |
4148 | return gen_lowpart_for_combine (mode, XEXP (x, 0)); |
4149 | ||
4150 | /* Similarly, a truncate of a register whose value is a | |
4151 | comparison can be replaced with a subreg if STORE_FLAG_VALUE | |
4152 | permits. */ | |
4153 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
663522cb | 4154 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 |
0f13a422 ILT |
4155 | && (temp = get_last_value (XEXP (x, 0))) |
4156 | && GET_RTX_CLASS (GET_CODE (temp)) == '<') | |
4157 | return gen_lowpart_for_combine (mode, XEXP (x, 0)); | |
4158 | ||
2ca9ae17 JW |
4159 | break; |
4160 | ||
230d793d RS |
4161 | case FLOAT_TRUNCATE: |
4162 | /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ | |
4163 | if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND | |
4164 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) | |
663522cb | 4165 | return XEXP (XEXP (x, 0), 0); |
4635f748 RK |
4166 | |
4167 | /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is | |
4168 | (OP:SF foo:SF) if OP is NEG or ABS. */ | |
4169 | if ((GET_CODE (XEXP (x, 0)) == ABS | |
4170 | || GET_CODE (XEXP (x, 0)) == NEG) | |
4171 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND | |
4172 | && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) | |
f1c6ba8b RK |
4173 | return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, |
4174 | XEXP (XEXP (XEXP (x, 0), 0), 0), mode); | |
1d12df72 RK |
4175 | |
4176 | /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0)) | |
4177 | is (float_truncate:SF x). */ | |
4178 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
4179 | && subreg_lowpart_p (XEXP (x, 0)) | |
4180 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE) | |
4181 | return SUBREG_REG (XEXP (x, 0)); | |
663522cb | 4182 | break; |
230d793d RS |
4183 | |
4184 | #ifdef HAVE_cc0 | |
4185 | case COMPARE: | |
4186 | /* Convert (compare FOO (const_int 0)) to FOO unless we aren't | |
4187 | using cc0, in which case we want to leave it as a COMPARE | |
4188 | so we can distinguish it from a register-register-copy. */ | |
4189 | if (XEXP (x, 1) == const0_rtx) | |
4190 | return XEXP (x, 0); | |
4191 | ||
71925bc0 RS |
4192 | /* x - 0 is the same as x unless x's mode has signed zeros and |
4193 | allows rounding towards -infinity. Under those conditions, | |
4194 | 0 - 0 is -0. */ | |
4195 | if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0))) | |
4196 | && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0)))) | |
230d793d RS |
4197 | && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) |
4198 | return XEXP (x, 0); | |
4199 | break; | |
4200 | #endif | |
4201 | ||
4202 | case CONST: | |
4203 | /* (const (const X)) can become (const X). Do it this way rather than | |
4204 | returning the inner CONST since CONST can be shared with a | |
4205 | REG_EQUAL note. */ | |
4206 | if (GET_CODE (XEXP (x, 0)) == CONST) | |
4207 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4208 | break; | |
4209 | ||
4210 | #ifdef HAVE_lo_sum | |
4211 | case LO_SUM: | |
4212 | /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we | |
4213 | can add in an offset. find_split_point will split this address up | |
4214 | again if it doesn't match. */ | |
4215 | if (GET_CODE (XEXP (x, 0)) == HIGH | |
4216 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) | |
4217 | return XEXP (x, 1); | |
4218 | break; | |
4219 | #endif | |
4220 | ||
4221 | case PLUS: | |
4222 | /* If we have (plus (plus (A const) B)), associate it so that CONST is | |
4223 | outermost. That's because that's the way indexed addresses are | |
4224 | supposed to appear. This code used to check many more cases, but | |
4225 | they are now checked elsewhere. */ | |
4226 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
4227 | && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) | |
4228 | return gen_binary (PLUS, mode, | |
4229 | gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), | |
4230 | XEXP (x, 1)), | |
4231 | XEXP (XEXP (x, 0), 1)); | |
4232 | ||
4233 | /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) | |
4234 | when c is (const_int (pow2 + 1) / 2) is a sign extension of a | |
4235 | bit-field and can be replaced by either a sign_extend or a | |
e6380233 JL |
4236 | sign_extract. The `and' may be a zero_extend and the two |
4237 | <c>, -<c> constants may be reversed. */ | |
230d793d RS |
4238 | if (GET_CODE (XEXP (x, 0)) == XOR |
4239 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4240 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
663522cb | 4241 | && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) |
e6380233 JL |
4242 | && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 |
4243 | || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
5f4f0e22 | 4244 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
230d793d RS |
4245 | && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND |
4246 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
4247 | && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) | |
5f4f0e22 | 4248 | == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) |
230d793d RS |
4249 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND |
4250 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) | |
770ae6cc | 4251 | == (unsigned int) i + 1)))) |
8079805d RK |
4252 | return simplify_shift_const |
4253 | (NULL_RTX, ASHIFTRT, mode, | |
4254 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
4255 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
4256 | GET_MODE_BITSIZE (mode) - (i + 1)), | |
4257 | GET_MODE_BITSIZE (mode) - (i + 1)); | |
230d793d | 4258 | |
bc0776c6 RK |
4259 | /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if |
4260 | C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE | |
4261 | is 1. This produces better code than the alternative immediately | |
4262 | below. */ | |
4263 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
bc0776c6 | 4264 | && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx) |
9a915772 JH |
4265 | || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)) |
4266 | && (reversed = reversed_comparison (XEXP (x, 0), mode, | |
4267 | XEXP (XEXP (x, 0), 0), | |
4268 | XEXP (XEXP (x, 0), 1)))) | |
8079805d | 4269 | return |
f1c6ba8b | 4270 | simplify_gen_unary (NEG, mode, reversed, mode); |
bc0776c6 RK |
4271 | |
4272 | /* If only the low-order bit of X is possibly nonzero, (plus x -1) | |
230d793d RS |
4273 | can become (ashiftrt (ashift (xor x 1) C) C) where C is |
4274 | the bitsize of the mode - 1. This allows simplification of | |
4275 | "a = (b & 8) == 0;" */ | |
4276 | if (XEXP (x, 1) == constm1_rtx | |
4277 | && GET_CODE (XEXP (x, 0)) != REG | |
4278 | && ! (GET_CODE (XEXP (x,0)) == SUBREG | |
4279 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG) | |
951553af | 4280 | && nonzero_bits (XEXP (x, 0), mode) == 1) |
8079805d RK |
4281 | return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, |
4282 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
f1c6ba8b | 4283 | gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), |
8079805d RK |
4284 | GET_MODE_BITSIZE (mode) - 1), |
4285 | GET_MODE_BITSIZE (mode) - 1); | |
02f4ada4 RK |
4286 | |
4287 | /* If we are adding two things that have no bits in common, convert | |
4288 | the addition into an IOR. This will often be further simplified, | |
4289 | for example in cases like ((a & 1) + (a & 2)), which can | |
4290 | become a & 3. */ | |
4291 | ||
ac49a949 | 4292 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
951553af RK |
4293 | && (nonzero_bits (XEXP (x, 0), mode) |
4294 | & nonzero_bits (XEXP (x, 1), mode)) == 0) | |
085f1714 RH |
4295 | { |
4296 | /* Try to simplify the expression further. */ | |
4297 | rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); | |
4298 | temp = combine_simplify_rtx (tor, mode, last, in_dest); | |
4299 | ||
4300 | /* If we could, great. If not, do not go ahead with the IOR | |
4301 | replacement, since PLUS appears in many special purpose | |
4302 | address arithmetic instructions. */ | |
4303 | if (GET_CODE (temp) != CLOBBER && temp != tor) | |
4304 | return temp; | |
4305 | } | |
230d793d RS |
4306 | break; |
4307 | ||
4308 | case MINUS: | |
0802d516 RK |
4309 | /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done |
4310 | by reversing the comparison code if valid. */ | |
4311 | if (STORE_FLAG_VALUE == 1 | |
4312 | && XEXP (x, 0) == const1_rtx | |
5109d49f | 4313 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<' |
9a915772 JH |
4314 | && (reversed = reversed_comparison (XEXP (x, 1), mode, |
4315 | XEXP (XEXP (x, 1), 0), | |
4316 | XEXP (XEXP (x, 1), 1)))) | |
4317 | return reversed; | |
5109d49f | 4318 | |
230d793d RS |
4319 | /* (minus <foo> (and <foo> (const_int -pow2))) becomes |
4320 | (and <foo> (const_int pow2-1)) */ | |
4321 | if (GET_CODE (XEXP (x, 1)) == AND | |
4322 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
663522cb | 4323 | && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 |
230d793d | 4324 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
8079805d | 4325 | return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), |
663522cb | 4326 | -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); |
7bef8680 RK |
4327 | |
4328 | /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for | |
4329 | integers. */ | |
4330 | if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode)) | |
8079805d RK |
4331 | return gen_binary (MINUS, mode, |
4332 | gen_binary (MINUS, mode, XEXP (x, 0), | |
4333 | XEXP (XEXP (x, 1), 0)), | |
4334 | XEXP (XEXP (x, 1), 1)); | |
230d793d RS |
4335 | break; |
4336 | ||
4337 | case MULT: | |
4338 | /* If we have (mult (plus A B) C), apply the distributive law and then | |
4339 | the inverse distributive law to see if things simplify. This | |
4340 | occurs mostly in addresses, often when unrolling loops. */ | |
4341 | ||
4342 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
4343 | { | |
4344 | x = apply_distributive_law | |
4345 | (gen_binary (PLUS, mode, | |
4346 | gen_binary (MULT, mode, | |
4347 | XEXP (XEXP (x, 0), 0), XEXP (x, 1)), | |
4348 | gen_binary (MULT, mode, | |
3749f4ca BS |
4349 | XEXP (XEXP (x, 0), 1), |
4350 | copy_rtx (XEXP (x, 1))))); | |
230d793d RS |
4351 | |
4352 | if (GET_CODE (x) != MULT) | |
8079805d | 4353 | return x; |
230d793d | 4354 | } |
4ba5f925 JH |
4355 | /* Try simplify a*(b/c) as (a*b)/c. */ |
4356 | if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations | |
4357 | && GET_CODE (XEXP (x, 0)) == DIV) | |
4358 | { | |
4359 | rtx tem = simplify_binary_operation (MULT, mode, | |
4360 | XEXP (XEXP (x, 0), 0), | |
4361 | XEXP (x, 1)); | |
4362 | if (tem) | |
4363 | return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); | |
4364 | } | |
230d793d RS |
4365 | break; |
4366 | ||
4367 | case UDIV: | |
4368 | /* If this is a divide by a power of two, treat it as a shift if | |
4369 | its first operand is a shift. */ | |
4370 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
4371 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 | |
4372 | && (GET_CODE (XEXP (x, 0)) == ASHIFT | |
4373 | || GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
4374 | || GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
4375 | || GET_CODE (XEXP (x, 0)) == ROTATE | |
4376 | || GET_CODE (XEXP (x, 0)) == ROTATERT)) | |
8079805d | 4377 | return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); |
230d793d RS |
4378 | break; |
4379 | ||
4380 | case EQ: case NE: | |
4381 | case GT: case GTU: case GE: case GEU: | |
4382 | case LT: case LTU: case LE: case LEU: | |
69bc0a1f | 4383 | case UNEQ: case LTGT: |
23190837 AJ |
4384 | case UNGT: case UNGE: |
4385 | case UNLT: case UNLE: | |
69bc0a1f | 4386 | case UNORDERED: case ORDERED: |
230d793d RS |
4387 | /* If the first operand is a condition code, we can't do anything |
4388 | with it. */ | |
4389 | if (GET_CODE (XEXP (x, 0)) == COMPARE | |
4390 | || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC | |
4391 | #ifdef HAVE_cc0 | |
4392 | && XEXP (x, 0) != cc0_rtx | |
4393 | #endif | |
663522cb | 4394 | )) |
230d793d RS |
4395 | { |
4396 | rtx op0 = XEXP (x, 0); | |
4397 | rtx op1 = XEXP (x, 1); | |
4398 | enum rtx_code new_code; | |
4399 | ||
4400 | if (GET_CODE (op0) == COMPARE) | |
4401 | op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
4402 | ||
4403 | /* Simplify our comparison, if possible. */ | |
4404 | new_code = simplify_comparison (code, &op0, &op1); | |
4405 | ||
230d793d | 4406 | /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X |
951553af | 4407 | if only the low-order bit is possibly nonzero in X (such as when |
5109d49f RK |
4408 | X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to |
4409 | (xor X 1) or (minus 1 X); we use the former. Finally, if X is | |
4410 | known to be either 0 or -1, NE becomes a NEG and EQ becomes | |
4411 | (plus X 1). | |
4412 | ||
4413 | Remove any ZERO_EXTRACT we made when thinking this was a | |
4414 | comparison. It may now be simpler to use, e.g., an AND. If a | |
4415 | ZERO_EXTRACT is indeed appropriate, it will be placed back by | |
4416 | the call to make_compound_operation in the SET case. */ | |
4417 | ||
0802d516 RK |
4418 | if (STORE_FLAG_VALUE == 1 |
4419 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
a191f0ee RH |
4420 | && op1 == const0_rtx |
4421 | && mode == GET_MODE (op0) | |
4422 | && nonzero_bits (op0, mode) == 1) | |
818b11b9 RK |
4423 | return gen_lowpart_for_combine (mode, |
4424 | expand_compound_operation (op0)); | |
5109d49f | 4425 | |
0802d516 RK |
4426 | else if (STORE_FLAG_VALUE == 1 |
4427 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4428 | && op1 == const0_rtx |
a191f0ee | 4429 | && mode == GET_MODE (op0) |
5109d49f RK |
4430 | && (num_sign_bit_copies (op0, mode) |
4431 | == GET_MODE_BITSIZE (mode))) | |
4432 | { | |
4433 | op0 = expand_compound_operation (op0); | |
f1c6ba8b RK |
4434 | return simplify_gen_unary (NEG, mode, |
4435 | gen_lowpart_for_combine (mode, op0), | |
4436 | mode); | |
5109d49f RK |
4437 | } |
4438 | ||
0802d516 RK |
4439 | else if (STORE_FLAG_VALUE == 1 |
4440 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
230d793d | 4441 | && op1 == const0_rtx |
a191f0ee | 4442 | && mode == GET_MODE (op0) |
5109d49f | 4443 | && nonzero_bits (op0, mode) == 1) |
818b11b9 RK |
4444 | { |
4445 | op0 = expand_compound_operation (op0); | |
8079805d RK |
4446 | return gen_binary (XOR, mode, |
4447 | gen_lowpart_for_combine (mode, op0), | |
4448 | const1_rtx); | |
5109d49f | 4449 | } |
818b11b9 | 4450 | |
0802d516 RK |
4451 | else if (STORE_FLAG_VALUE == 1 |
4452 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4453 | && op1 == const0_rtx |
a191f0ee | 4454 | && mode == GET_MODE (op0) |
5109d49f RK |
4455 | && (num_sign_bit_copies (op0, mode) |
4456 | == GET_MODE_BITSIZE (mode))) | |
4457 | { | |
4458 | op0 = expand_compound_operation (op0); | |
8079805d | 4459 | return plus_constant (gen_lowpart_for_combine (mode, op0), 1); |
818b11b9 | 4460 | } |
230d793d | 4461 | |
5109d49f RK |
4462 | /* If STORE_FLAG_VALUE is -1, we have cases similar to |
4463 | those above. */ | |
0802d516 RK |
4464 | if (STORE_FLAG_VALUE == -1 |
4465 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
230d793d | 4466 | && op1 == const0_rtx |
5109d49f RK |
4467 | && (num_sign_bit_copies (op0, mode) |
4468 | == GET_MODE_BITSIZE (mode))) | |
4469 | return gen_lowpart_for_combine (mode, | |
4470 | expand_compound_operation (op0)); | |
4471 | ||
0802d516 RK |
4472 | else if (STORE_FLAG_VALUE == -1 |
4473 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4474 | && op1 == const0_rtx |
a191f0ee | 4475 | && mode == GET_MODE (op0) |
5109d49f RK |
4476 | && nonzero_bits (op0, mode) == 1) |
4477 | { | |
4478 | op0 = expand_compound_operation (op0); | |
f1c6ba8b RK |
4479 | return simplify_gen_unary (NEG, mode, |
4480 | gen_lowpart_for_combine (mode, op0), | |
4481 | mode); | |
5109d49f RK |
4482 | } |
4483 | ||
0802d516 RK |
4484 | else if (STORE_FLAG_VALUE == -1 |
4485 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4486 | && op1 == const0_rtx |
a191f0ee | 4487 | && mode == GET_MODE (op0) |
5109d49f RK |
4488 | && (num_sign_bit_copies (op0, mode) |
4489 | == GET_MODE_BITSIZE (mode))) | |
230d793d | 4490 | { |
818b11b9 | 4491 | op0 = expand_compound_operation (op0); |
f1c6ba8b RK |
4492 | return simplify_gen_unary (NOT, mode, |
4493 | gen_lowpart_for_combine (mode, op0), | |
4494 | mode); | |
5109d49f RK |
4495 | } |
4496 | ||
4497 | /* If X is 0/1, (eq X 0) is X-1. */ | |
0802d516 RK |
4498 | else if (STORE_FLAG_VALUE == -1 |
4499 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4500 | && op1 == const0_rtx |
a191f0ee | 4501 | && mode == GET_MODE (op0) |
5109d49f RK |
4502 | && nonzero_bits (op0, mode) == 1) |
4503 | { | |
4504 | op0 = expand_compound_operation (op0); | |
8079805d | 4505 | return plus_constant (gen_lowpart_for_combine (mode, op0), -1); |
230d793d | 4506 | } |
230d793d RS |
4507 | |
4508 | /* If STORE_FLAG_VALUE says to just test the sign bit and X has just | |
951553af RK |
4509 | one bit that might be nonzero, we can convert (ne x 0) to |
4510 | (ashift x c) where C puts the bit in the sign bit. Remove any | |
4511 | AND with STORE_FLAG_VALUE when we are done, since we are only | |
4512 | going to test the sign bit. */ | |
3f508eca | 4513 | if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
5f4f0e22 | 4514 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
0802d516 | 4515 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
e51712db | 4516 | == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1)) |
230d793d RS |
4517 | && op1 == const0_rtx |
4518 | && mode == GET_MODE (op0) | |
5109d49f | 4519 | && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) |
230d793d | 4520 | { |
818b11b9 RK |
4521 | x = simplify_shift_const (NULL_RTX, ASHIFT, mode, |
4522 | expand_compound_operation (op0), | |
230d793d RS |
4523 | GET_MODE_BITSIZE (mode) - 1 - i); |
4524 | if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) | |
4525 | return XEXP (x, 0); | |
4526 | else | |
4527 | return x; | |
4528 | } | |
4529 | ||
4530 | /* If the code changed, return a whole new comparison. */ | |
4531 | if (new_code != code) | |
f1c6ba8b | 4532 | return gen_rtx_fmt_ee (new_code, mode, op0, op1); |
230d793d | 4533 | |
663522cb | 4534 | /* Otherwise, keep this operation, but maybe change its operands. |
230d793d RS |
4535 | This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ |
4536 | SUBST (XEXP (x, 0), op0); | |
4537 | SUBST (XEXP (x, 1), op1); | |
4538 | } | |
4539 | break; | |
663522cb | 4540 | |
230d793d | 4541 | case IF_THEN_ELSE: |
8079805d | 4542 | return simplify_if_then_else (x); |
9210df58 | 4543 | |
8079805d RK |
4544 | case ZERO_EXTRACT: |
4545 | case SIGN_EXTRACT: | |
4546 | case ZERO_EXTEND: | |
4547 | case SIGN_EXTEND: | |
0f41302f | 4548 | /* If we are processing SET_DEST, we are done. */ |
8079805d RK |
4549 | if (in_dest) |
4550 | return x; | |
d0ab8cd3 | 4551 | |
8079805d | 4552 | return expand_compound_operation (x); |
d0ab8cd3 | 4553 | |
8079805d RK |
4554 | case SET: |
4555 | return simplify_set (x); | |
1a26b032 | 4556 | |
8079805d RK |
4557 | case AND: |
4558 | case IOR: | |
4559 | case XOR: | |
4560 | return simplify_logical (x, last); | |
d0ab8cd3 | 4561 | |
663522cb | 4562 | case ABS: |
8079805d RK |
4563 | /* (abs (neg <foo>)) -> (abs <foo>) */ |
4564 | if (GET_CODE (XEXP (x, 0)) == NEG) | |
4565 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
1a26b032 | 4566 | |
b472527b JL |
4567 | /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS), |
4568 | do nothing. */ | |
4569 | if (GET_MODE (XEXP (x, 0)) == VOIDmode) | |
4570 | break; | |
f40421ce | 4571 | |
8079805d RK |
4572 | /* If operand is something known to be positive, ignore the ABS. */ |
4573 | if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS | |
4574 | || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) | |
4575 | <= HOST_BITS_PER_WIDE_INT) | |
4576 | && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
4577 | & ((HOST_WIDE_INT) 1 | |
4578 | << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) | |
4579 | == 0))) | |
4580 | return XEXP (x, 0); | |
1a26b032 | 4581 | |
8079805d RK |
4582 | /* If operand is known to be only -1 or 0, convert ABS to NEG. */ |
4583 | if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) | |
f1c6ba8b | 4584 | return gen_rtx_NEG (mode, XEXP (x, 0)); |
1a26b032 | 4585 | |
8079805d | 4586 | break; |
1a26b032 | 4587 | |
8079805d RK |
4588 | case FFS: |
4589 | /* (ffs (*_extend <X>)) = (ffs <X>) */ | |
4590 | if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
4591 | || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
4592 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4593 | break; | |
1a26b032 | 4594 | |
8079805d RK |
4595 | case FLOAT: |
4596 | /* (float (sign_extend <X>)) = (float <X>). */ | |
4597 | if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
4598 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4599 | break; | |
1a26b032 | 4600 | |
8079805d RK |
4601 | case ASHIFT: |
4602 | case LSHIFTRT: | |
4603 | case ASHIFTRT: | |
4604 | case ROTATE: | |
4605 | case ROTATERT: | |
4606 | /* If this is a shift by a constant amount, simplify it. */ | |
4607 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
663522cb | 4608 | return simplify_shift_const (x, code, mode, XEXP (x, 0), |
8079805d RK |
4609 | INTVAL (XEXP (x, 1))); |
4610 | ||
4611 | #ifdef SHIFT_COUNT_TRUNCATED | |
4612 | else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG) | |
4613 | SUBST (XEXP (x, 1), | |
f1b1186f | 4614 | force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), |
663522cb | 4615 | ((HOST_WIDE_INT) 1 |
8079805d RK |
4616 | << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) |
4617 | - 1, | |
4618 | NULL_RTX, 0)); | |
4619 | #endif | |
4620 | ||
4621 | break; | |
e9a25f70 | 4622 | |
82be40f7 BS |
4623 | case VEC_SELECT: |
4624 | { | |
4625 | rtx op0 = XEXP (x, 0); | |
4626 | rtx op1 = XEXP (x, 1); | |
4627 | int len; | |
4628 | ||
4629 | if (GET_CODE (op1) != PARALLEL) | |
4630 | abort (); | |
4631 | len = XVECLEN (op1, 0); | |
4632 | if (len == 1 | |
4633 | && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT | |
4634 | && GET_CODE (op0) == VEC_CONCAT) | |
4635 | { | |
4636 | int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x)); | |
4637 | ||
4638 | /* Try to find the element in the VEC_CONCAT. */ | |
4639 | for (;;) | |
4640 | { | |
4641 | if (GET_MODE (op0) == GET_MODE (x)) | |
4642 | return op0; | |
4643 | if (GET_CODE (op0) == VEC_CONCAT) | |
4644 | { | |
4645 | HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))); | |
4646 | if (op0_size < offset) | |
4647 | op0 = XEXP (op0, 0); | |
4648 | else | |
4649 | { | |
4650 | offset -= op0_size; | |
4651 | op0 = XEXP (op0, 1); | |
4652 | } | |
4653 | } | |
4654 | else | |
4655 | break; | |
4656 | } | |
4657 | } | |
4658 | } | |
4659 | ||
4660 | break; | |
23190837 | 4661 | |
e9a25f70 JL |
4662 | default: |
4663 | break; | |
8079805d RK |
4664 | } |
4665 | ||
4666 | return x; | |
4667 | } | |
4668 | \f | |
4669 | /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ | |
5109d49f | 4670 | |
8079805d RK |
4671 | static rtx |
4672 | simplify_if_then_else (x) | |
4673 | rtx x; | |
4674 | { | |
4675 | enum machine_mode mode = GET_MODE (x); | |
4676 | rtx cond = XEXP (x, 0); | |
d6edb99e ZW |
4677 | rtx true_rtx = XEXP (x, 1); |
4678 | rtx false_rtx = XEXP (x, 2); | |
8079805d RK |
4679 | enum rtx_code true_code = GET_CODE (cond); |
4680 | int comparison_p = GET_RTX_CLASS (true_code) == '<'; | |
4681 | rtx temp; | |
4682 | int i; | |
9a915772 JH |
4683 | enum rtx_code false_code; |
4684 | rtx reversed; | |
8079805d | 4685 | |
0f41302f | 4686 | /* Simplify storing of the truth value. */ |
d6edb99e | 4687 | if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) |
8079805d | 4688 | return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1)); |
663522cb | 4689 | |
0f41302f | 4690 | /* Also when the truth value has to be reversed. */ |
9a915772 | 4691 | if (comparison_p |
d6edb99e | 4692 | && true_rtx == const0_rtx && false_rtx == const_true_rtx |
9a915772 JH |
4693 | && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0), |
4694 | XEXP (cond, 1)))) | |
4695 | return reversed; | |
8079805d RK |
4696 | |
4697 | /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used | |
4698 | in it is being compared against certain values. Get the true and false | |
4699 | comparisons and see if that says anything about the value of each arm. */ | |
4700 | ||
9a915772 JH |
4701 | if (comparison_p |
4702 | && ((false_code = combine_reversed_comparison_code (cond)) | |
4703 | != UNKNOWN) | |
8079805d RK |
4704 | && GET_CODE (XEXP (cond, 0)) == REG) |
4705 | { | |
4706 | HOST_WIDE_INT nzb; | |
4707 | rtx from = XEXP (cond, 0); | |
8079805d RK |
4708 | rtx true_val = XEXP (cond, 1); |
4709 | rtx false_val = true_val; | |
4710 | int swapped = 0; | |
9210df58 | 4711 | |
8079805d | 4712 | /* If FALSE_CODE is EQ, swap the codes and arms. */ |
5109d49f | 4713 | |
8079805d | 4714 | if (false_code == EQ) |
1a26b032 | 4715 | { |
8079805d | 4716 | swapped = 1, true_code = EQ, false_code = NE; |
d6edb99e | 4717 | temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; |
8079805d | 4718 | } |
5109d49f | 4719 | |
8079805d RK |
4720 | /* If we are comparing against zero and the expression being tested has |
4721 | only a single bit that might be nonzero, that is its value when it is | |
4722 | not equal to zero. Similarly if it is known to be -1 or 0. */ | |
4723 | ||
4724 | if (true_code == EQ && true_val == const0_rtx | |
4725 | && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) | |
4726 | false_code = EQ, false_val = GEN_INT (nzb); | |
4727 | else if (true_code == EQ && true_val == const0_rtx | |
4728 | && (num_sign_bit_copies (from, GET_MODE (from)) | |
4729 | == GET_MODE_BITSIZE (GET_MODE (from)))) | |
4730 | false_code = EQ, false_val = constm1_rtx; | |
4731 | ||
4732 | /* Now simplify an arm if we know the value of the register in the | |
4733 | branch and it is used in the arm. Be careful due to the potential | |
4734 | of locally-shared RTL. */ | |
4735 | ||
d6edb99e ZW |
4736 | if (reg_mentioned_p (from, true_rtx)) |
4737 | true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, | |
4738 | from, true_val), | |
8079805d | 4739 | pc_rtx, pc_rtx, 0, 0); |
d6edb99e ZW |
4740 | if (reg_mentioned_p (from, false_rtx)) |
4741 | false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, | |
8079805d RK |
4742 | from, false_val), |
4743 | pc_rtx, pc_rtx, 0, 0); | |
4744 | ||
d6edb99e ZW |
4745 | SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); |
4746 | SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); | |
8079805d | 4747 | |
d6edb99e ZW |
4748 | true_rtx = XEXP (x, 1); |
4749 | false_rtx = XEXP (x, 2); | |
4750 | true_code = GET_CODE (cond); | |
8079805d | 4751 | } |
5109d49f | 4752 | |
8079805d RK |
4753 | /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be |
4754 | reversed, do so to avoid needing two sets of patterns for | |
4755 | subtract-and-branch insns. Similarly if we have a constant in the true | |
4756 | arm, the false arm is the same as the first operand of the comparison, or | |
4757 | the false arm is more complicated than the true arm. */ | |
4758 | ||
9a915772 JH |
4759 | if (comparison_p |
4760 | && combine_reversed_comparison_code (cond) != UNKNOWN | |
d6edb99e ZW |
4761 | && (true_rtx == pc_rtx |
4762 | || (CONSTANT_P (true_rtx) | |
4763 | && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx) | |
4764 | || true_rtx == const0_rtx | |
4765 | || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o' | |
4766 | && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o') | |
4767 | || (GET_CODE (true_rtx) == SUBREG | |
4768 | && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o' | |
4769 | && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o') | |
4770 | || reg_mentioned_p (true_rtx, false_rtx) | |
4771 | || rtx_equal_p (false_rtx, XEXP (cond, 0)))) | |
8079805d | 4772 | { |
9a915772 | 4773 | true_code = reversed_comparison_code (cond, NULL); |
8079805d | 4774 | SUBST (XEXP (x, 0), |
9a915772 JH |
4775 | reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0), |
4776 | XEXP (cond, 1))); | |
5109d49f | 4777 | |
d6edb99e ZW |
4778 | SUBST (XEXP (x, 1), false_rtx); |
4779 | SUBST (XEXP (x, 2), true_rtx); | |
1a26b032 | 4780 | |
d6edb99e ZW |
4781 | temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; |
4782 | cond = XEXP (x, 0); | |
bb821298 | 4783 | |
0f41302f | 4784 | /* It is possible that the conditional has been simplified out. */ |
bb821298 RK |
4785 | true_code = GET_CODE (cond); |
4786 | comparison_p = GET_RTX_CLASS (true_code) == '<'; | |
8079805d | 4787 | } |
abe6e52f | 4788 | |
8079805d | 4789 | /* If the two arms are identical, we don't need the comparison. */ |
1a26b032 | 4790 | |
d6edb99e ZW |
4791 | if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) |
4792 | return true_rtx; | |
1a26b032 | 4793 | |
5be669c7 RK |
4794 | /* Convert a == b ? b : a to "a". */ |
4795 | if (true_code == EQ && ! side_effects_p (cond) | |
73e42cf3 | 4796 | && !HONOR_NANS (mode) |
d6edb99e ZW |
4797 | && rtx_equal_p (XEXP (cond, 0), false_rtx) |
4798 | && rtx_equal_p (XEXP (cond, 1), true_rtx)) | |
4799 | return false_rtx; | |
5be669c7 | 4800 | else if (true_code == NE && ! side_effects_p (cond) |
73e42cf3 | 4801 | && !HONOR_NANS (mode) |
d6edb99e ZW |
4802 | && rtx_equal_p (XEXP (cond, 0), true_rtx) |
4803 | && rtx_equal_p (XEXP (cond, 1), false_rtx)) | |
4804 | return true_rtx; | |
5be669c7 | 4805 | |
8079805d RK |
4806 | /* Look for cases where we have (abs x) or (neg (abs X)). */ |
4807 | ||
4808 | if (GET_MODE_CLASS (mode) == MODE_INT | |
d6edb99e ZW |
4809 | && GET_CODE (false_rtx) == NEG |
4810 | && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) | |
8079805d | 4811 | && comparison_p |
d6edb99e ZW |
4812 | && rtx_equal_p (true_rtx, XEXP (cond, 0)) |
4813 | && ! side_effects_p (true_rtx)) | |
8079805d RK |
4814 | switch (true_code) |
4815 | { | |
4816 | case GT: | |
4817 | case GE: | |
f1c6ba8b | 4818 | return simplify_gen_unary (ABS, mode, true_rtx, mode); |
8079805d RK |
4819 | case LT: |
4820 | case LE: | |
f1c6ba8b RK |
4821 | return |
4822 | simplify_gen_unary (NEG, mode, | |
4823 | simplify_gen_unary (ABS, mode, true_rtx, mode), | |
4824 | mode); | |
cf0d9408 KH |
4825 | default: |
4826 | break; | |
8079805d RK |
4827 | } |
4828 | ||
4829 | /* Look for MIN or MAX. */ | |
4830 | ||
de6c5979 | 4831 | if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) |
8079805d | 4832 | && comparison_p |
d6edb99e ZW |
4833 | && rtx_equal_p (XEXP (cond, 0), true_rtx) |
4834 | && rtx_equal_p (XEXP (cond, 1), false_rtx) | |
8079805d RK |
4835 | && ! side_effects_p (cond)) |
4836 | switch (true_code) | |
4837 | { | |
4838 | case GE: | |
4839 | case GT: | |
d6edb99e | 4840 | return gen_binary (SMAX, mode, true_rtx, false_rtx); |
8079805d RK |
4841 | case LE: |
4842 | case LT: | |
d6edb99e | 4843 | return gen_binary (SMIN, mode, true_rtx, false_rtx); |
8079805d RK |
4844 | case GEU: |
4845 | case GTU: | |
d6edb99e | 4846 | return gen_binary (UMAX, mode, true_rtx, false_rtx); |
8079805d RK |
4847 | case LEU: |
4848 | case LTU: | |
d6edb99e | 4849 | return gen_binary (UMIN, mode, true_rtx, false_rtx); |
e9a25f70 JL |
4850 | default: |
4851 | break; | |
8079805d | 4852 | } |
663522cb | 4853 | |
8079805d RK |
4854 | /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its |
4855 | second operand is zero, this can be done as (OP Z (mult COND C2)) where | |
4856 | C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or | |
4857 | SIGN_EXTEND as long as Z is already extended (so we don't destroy it). | |
4858 | We can do this kind of thing in some cases when STORE_FLAG_VALUE is | |
0802d516 | 4859 | neither 1 or -1, but it isn't worth checking for. */ |
8079805d | 4860 | |
0802d516 RK |
4861 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
4862 | && comparison_p && mode != VOIDmode && ! side_effects_p (x)) | |
8079805d | 4863 | { |
d6edb99e ZW |
4864 | rtx t = make_compound_operation (true_rtx, SET); |
4865 | rtx f = make_compound_operation (false_rtx, SET); | |
8079805d RK |
4866 | rtx cond_op0 = XEXP (cond, 0); |
4867 | rtx cond_op1 = XEXP (cond, 1); | |
6a651371 | 4868 | enum rtx_code op = NIL, extend_op = NIL; |
8079805d | 4869 | enum machine_mode m = mode; |
6a651371 | 4870 | rtx z = 0, c1 = NULL_RTX; |
8079805d | 4871 | |
8079805d RK |
4872 | if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS |
4873 | || GET_CODE (t) == IOR || GET_CODE (t) == XOR | |
4874 | || GET_CODE (t) == ASHIFT | |
4875 | || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) | |
4876 | && rtx_equal_p (XEXP (t, 0), f)) | |
4877 | c1 = XEXP (t, 1), op = GET_CODE (t), z = f; | |
4878 | ||
4879 | /* If an identity-zero op is commutative, check whether there | |
0f41302f | 4880 | would be a match if we swapped the operands. */ |
8079805d RK |
4881 | else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR |
4882 | || GET_CODE (t) == XOR) | |
4883 | && rtx_equal_p (XEXP (t, 1), f)) | |
4884 | c1 = XEXP (t, 0), op = GET_CODE (t), z = f; | |
4885 | else if (GET_CODE (t) == SIGN_EXTEND | |
4886 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
4887 | || GET_CODE (XEXP (t, 0)) == MINUS | |
4888 | || GET_CODE (XEXP (t, 0)) == IOR | |
4889 | || GET_CODE (XEXP (t, 0)) == XOR | |
4890 | || GET_CODE (XEXP (t, 0)) == ASHIFT | |
4891 | || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
4892 | || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
4893 | && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
4894 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
4895 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
4896 | && (num_sign_bit_copies (f, GET_MODE (f)) | |
26c34780 RS |
4897 | > (unsigned int) |
4898 | (GET_MODE_BITSIZE (mode) | |
8079805d RK |
4899 | - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) |
4900 | { | |
4901 | c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
4902 | extend_op = SIGN_EXTEND; | |
4903 | m = GET_MODE (XEXP (t, 0)); | |
1a26b032 | 4904 | } |
8079805d RK |
4905 | else if (GET_CODE (t) == SIGN_EXTEND |
4906 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
4907 | || GET_CODE (XEXP (t, 0)) == IOR | |
4908 | || GET_CODE (XEXP (t, 0)) == XOR) | |
4909 | && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
4910 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
4911 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
4912 | && (num_sign_bit_copies (f, GET_MODE (f)) | |
26c34780 RS |
4913 | > (unsigned int) |
4914 | (GET_MODE_BITSIZE (mode) | |
8079805d RK |
4915 | - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) |
4916 | { | |
4917 | c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
4918 | extend_op = SIGN_EXTEND; | |
4919 | m = GET_MODE (XEXP (t, 0)); | |
4920 | } | |
4921 | else if (GET_CODE (t) == ZERO_EXTEND | |
4922 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
4923 | || GET_CODE (XEXP (t, 0)) == MINUS | |
4924 | || GET_CODE (XEXP (t, 0)) == IOR | |
4925 | || GET_CODE (XEXP (t, 0)) == XOR | |
4926 | || GET_CODE (XEXP (t, 0)) == ASHIFT | |
4927 | || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
4928 | || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
4929 | && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
4930 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
4931 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
4932 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
4933 | && ((nonzero_bits (f, GET_MODE (f)) | |
663522cb | 4934 | & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) |
8079805d RK |
4935 | == 0)) |
4936 | { | |
4937 | c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
4938 | extend_op = ZERO_EXTEND; | |
4939 | m = GET_MODE (XEXP (t, 0)); | |
4940 | } | |
4941 | else if (GET_CODE (t) == ZERO_EXTEND | |
4942 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
4943 | || GET_CODE (XEXP (t, 0)) == IOR | |
4944 | || GET_CODE (XEXP (t, 0)) == XOR) | |
4945 | && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
4946 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
4947 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
4948 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
4949 | && ((nonzero_bits (f, GET_MODE (f)) | |
663522cb | 4950 | & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) |
8079805d RK |
4951 | == 0)) |
4952 | { | |
4953 | c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
4954 | extend_op = ZERO_EXTEND; | |
4955 | m = GET_MODE (XEXP (t, 0)); | |
4956 | } | |
663522cb | 4957 | |
8079805d RK |
4958 | if (z) |
4959 | { | |
4960 | temp = subst (gen_binary (true_code, m, cond_op0, cond_op1), | |
4961 | pc_rtx, pc_rtx, 0, 0); | |
4962 | temp = gen_binary (MULT, m, temp, | |
4963 | gen_binary (MULT, m, c1, const_true_rtx)); | |
4964 | temp = subst (temp, pc_rtx, pc_rtx, 0, 0); | |
4965 | temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp); | |
4966 | ||
4967 | if (extend_op != NIL) | |
f1c6ba8b | 4968 | temp = simplify_gen_unary (extend_op, mode, temp, m); |
8079805d RK |
4969 | |
4970 | return temp; | |
4971 | } | |
4972 | } | |
224eeff2 | 4973 | |
8079805d RK |
4974 | /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or |
4975 | 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the | |
4976 | negation of a single bit, we can convert this operation to a shift. We | |
4977 | can actually do this more generally, but it doesn't seem worth it. */ | |
4978 | ||
4979 | if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
d6edb99e | 4980 | && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT |
8079805d | 4981 | && ((1 == nonzero_bits (XEXP (cond, 0), mode) |
d6edb99e | 4982 | && (i = exact_log2 (INTVAL (true_rtx))) >= 0) |
8079805d RK |
4983 | || ((num_sign_bit_copies (XEXP (cond, 0), mode) |
4984 | == GET_MODE_BITSIZE (mode)) | |
d6edb99e | 4985 | && (i = exact_log2 (-INTVAL (true_rtx))) >= 0))) |
8079805d RK |
4986 | return |
4987 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
4988 | gen_lowpart_for_combine (mode, XEXP (cond, 0)), i); | |
230d793d | 4989 | |
8079805d RK |
4990 | return x; |
4991 | } | |
4992 | \f | |
4993 | /* Simplify X, a SET expression. Return the new expression. */ | |
230d793d | 4994 | |
8079805d RK |
4995 | static rtx |
4996 | simplify_set (x) | |
4997 | rtx x; | |
4998 | { | |
4999 | rtx src = SET_SRC (x); | |
5000 | rtx dest = SET_DEST (x); | |
5001 | enum machine_mode mode | |
5002 | = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); | |
5003 | rtx other_insn; | |
5004 | rtx *cc_use; | |
5005 | ||
5006 | /* (set (pc) (return)) gets written as (return). */ | |
5007 | if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) | |
5008 | return src; | |
230d793d | 5009 | |
87e3e0c1 RK |
5010 | /* Now that we know for sure which bits of SRC we are using, see if we can |
5011 | simplify the expression for the object knowing that we only need the | |
5012 | low-order bits. */ | |
5013 | ||
855c3a2e IS |
5014 | if (GET_MODE_CLASS (mode) == MODE_INT |
5015 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
c5c76735 | 5016 | { |
e8dc6d50 | 5017 | src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0); |
c5c76735 JL |
5018 | SUBST (SET_SRC (x), src); |
5019 | } | |
87e3e0c1 | 5020 | |
8079805d RK |
5021 | /* If we are setting CC0 or if the source is a COMPARE, look for the use of |
5022 | the comparison result and try to simplify it unless we already have used | |
5023 | undobuf.other_insn. */ | |
5024 | if ((GET_CODE (src) == COMPARE | |
230d793d | 5025 | #ifdef HAVE_cc0 |
8079805d | 5026 | || dest == cc0_rtx |
230d793d | 5027 | #endif |
8079805d RK |
5028 | ) |
5029 | && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 | |
5030 | && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) | |
5031 | && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<' | |
c0d3ac4d | 5032 | && rtx_equal_p (XEXP (*cc_use, 0), dest)) |
8079805d RK |
5033 | { |
5034 | enum rtx_code old_code = GET_CODE (*cc_use); | |
5035 | enum rtx_code new_code; | |
f40f4c8e | 5036 | rtx op0, op1, tmp; |
8079805d RK |
5037 | int other_changed = 0; |
5038 | enum machine_mode compare_mode = GET_MODE (dest); | |
f40f4c8e | 5039 | enum machine_mode tmp_mode; |
8079805d RK |
5040 | |
5041 | if (GET_CODE (src) == COMPARE) | |
5042 | op0 = XEXP (src, 0), op1 = XEXP (src, 1); | |
5043 | else | |
5044 | op0 = src, op1 = const0_rtx; | |
230d793d | 5045 | |
f40f4c8e RS |
5046 | /* Check whether the comparison is known at compile time. */ |
5047 | if (GET_MODE (op0) != VOIDmode) | |
5048 | tmp_mode = GET_MODE (op0); | |
5049 | else if (GET_MODE (op1) != VOIDmode) | |
5050 | tmp_mode = GET_MODE (op1); | |
5051 | else | |
5052 | tmp_mode = compare_mode; | |
5053 | tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1); | |
5054 | if (tmp != NULL_RTX) | |
5055 | { | |
5056 | rtx pat = PATTERN (other_insn); | |
5057 | undobuf.other_insn = other_insn; | |
5058 | SUBST (*cc_use, tmp); | |
5059 | ||
5060 | /* Attempt to simplify CC user. */ | |
5061 | if (GET_CODE (pat) == SET) | |
5062 | { | |
5063 | rtx new = simplify_rtx (SET_SRC (pat)); | |
5064 | if (new != NULL_RTX) | |
5065 | SUBST (SET_SRC (pat), new); | |
5066 | } | |
5067 | ||
5068 | /* Convert X into a no-op move. */ | |
5069 | SUBST (SET_DEST (x), pc_rtx); | |
5070 | SUBST (SET_SRC (x), pc_rtx); | |
5071 | return x; | |
5072 | } | |
5073 | ||
8079805d RK |
5074 | /* Simplify our comparison, if possible. */ |
5075 | new_code = simplify_comparison (old_code, &op0, &op1); | |
230d793d | 5076 | |
c141a106 | 5077 | #ifdef EXTRA_CC_MODES |
8079805d RK |
5078 | /* If this machine has CC modes other than CCmode, check to see if we |
5079 | need to use a different CC mode here. */ | |
5080 | compare_mode = SELECT_CC_MODE (new_code, op0, op1); | |
c141a106 | 5081 | #endif /* EXTRA_CC_MODES */ |
230d793d | 5082 | |
c141a106 | 5083 | #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES) |
8079805d RK |
5084 | /* If the mode changed, we have to change SET_DEST, the mode in the |
5085 | compare, and the mode in the place SET_DEST is used. If SET_DEST is | |
5086 | a hard register, just build new versions with the proper mode. If it | |
5087 | is a pseudo, we lose unless it is only time we set the pseudo, in | |
5088 | which case we can safely change its mode. */ | |
5089 | if (compare_mode != GET_MODE (dest)) | |
5090 | { | |
770ae6cc | 5091 | unsigned int regno = REGNO (dest); |
38a448ca | 5092 | rtx new_dest = gen_rtx_REG (compare_mode, regno); |
8079805d RK |
5093 | |
5094 | if (regno < FIRST_PSEUDO_REGISTER | |
b1f21e0a | 5095 | || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest))) |
230d793d | 5096 | { |
8079805d RK |
5097 | if (regno >= FIRST_PSEUDO_REGISTER) |
5098 | SUBST (regno_reg_rtx[regno], new_dest); | |
230d793d | 5099 | |
8079805d RK |
5100 | SUBST (SET_DEST (x), new_dest); |
5101 | SUBST (XEXP (*cc_use, 0), new_dest); | |
5102 | other_changed = 1; | |
230d793d | 5103 | |
8079805d | 5104 | dest = new_dest; |
230d793d | 5105 | } |
8079805d | 5106 | } |
230d793d RS |
5107 | #endif |
5108 | ||
8079805d RK |
5109 | /* If the code changed, we have to build a new comparison in |
5110 | undobuf.other_insn. */ | |
5111 | if (new_code != old_code) | |
5112 | { | |
5113 | unsigned HOST_WIDE_INT mask; | |
5114 | ||
f1c6ba8b RK |
5115 | SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), |
5116 | dest, const0_rtx)); | |
8079805d RK |
5117 | |
5118 | /* If the only change we made was to change an EQ into an NE or | |
5119 | vice versa, OP0 has only one bit that might be nonzero, and OP1 | |
5120 | is zero, check if changing the user of the condition code will | |
5121 | produce a valid insn. If it won't, we can keep the original code | |
5122 | in that insn by surrounding our operation with an XOR. */ | |
5123 | ||
5124 | if (((old_code == NE && new_code == EQ) | |
5125 | || (old_code == EQ && new_code == NE)) | |
5126 | && ! other_changed && op1 == const0_rtx | |
5127 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT | |
5128 | && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) | |
230d793d | 5129 | { |
8079805d | 5130 | rtx pat = PATTERN (other_insn), note = 0; |
230d793d | 5131 | |
8e2f6e35 | 5132 | if ((recog_for_combine (&pat, other_insn, ¬e) < 0 |
8079805d RK |
5133 | && ! check_asm_operands (pat))) |
5134 | { | |
5135 | PUT_CODE (*cc_use, old_code); | |
5136 | other_insn = 0; | |
230d793d | 5137 | |
8079805d | 5138 | op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask)); |
230d793d | 5139 | } |
230d793d RS |
5140 | } |
5141 | ||
8079805d RK |
5142 | other_changed = 1; |
5143 | } | |
5144 | ||
5145 | if (other_changed) | |
5146 | undobuf.other_insn = other_insn; | |
230d793d RS |
5147 | |
5148 | #ifdef HAVE_cc0 | |
8079805d RK |
5149 | /* If we are now comparing against zero, change our source if |
5150 | needed. If we do not use cc0, we always have a COMPARE. */ | |
5151 | if (op1 == const0_rtx && dest == cc0_rtx) | |
5152 | { | |
5153 | SUBST (SET_SRC (x), op0); | |
5154 | src = op0; | |
5155 | } | |
5156 | else | |
230d793d RS |
5157 | #endif |
5158 | ||
8079805d RK |
5159 | /* Otherwise, if we didn't previously have a COMPARE in the |
5160 | correct mode, we need one. */ | |
5161 | if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) | |
5162 | { | |
f1c6ba8b | 5163 | SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); |
8079805d | 5164 | src = SET_SRC (x); |
230d793d RS |
5165 | } |
5166 | else | |
5167 | { | |
8079805d RK |
5168 | /* Otherwise, update the COMPARE if needed. */ |
5169 | SUBST (XEXP (src, 0), op0); | |
5170 | SUBST (XEXP (src, 1), op1); | |
230d793d | 5171 | } |
8079805d RK |
5172 | } |
5173 | else | |
5174 | { | |
5175 | /* Get SET_SRC in a form where we have placed back any | |
5176 | compound expressions. Then do the checks below. */ | |
5177 | src = make_compound_operation (src, SET); | |
5178 | SUBST (SET_SRC (x), src); | |
5179 | } | |
230d793d | 5180 | |
8079805d RK |
5181 | /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, |
5182 | and X being a REG or (subreg (reg)), we may be able to convert this to | |
663522cb | 5183 | (set (subreg:m2 x) (op)). |
df62f951 | 5184 | |
8079805d RK |
5185 | We can always do this if M1 is narrower than M2 because that means that |
5186 | we only care about the low bits of the result. | |
df62f951 | 5187 | |
8079805d | 5188 | However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot |
9ec36da5 | 5189 | perform a narrower operation than requested since the high-order bits will |
8079805d RK |
5190 | be undefined. On machine where it is defined, this transformation is safe |
5191 | as long as M1 and M2 have the same number of words. */ | |
663522cb | 5192 | |
8079805d RK |
5193 | if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) |
5194 | && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o' | |
5195 | && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) | |
5196 | / UNITS_PER_WORD) | |
5197 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) | |
5198 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
8baf60bb | 5199 | #ifndef WORD_REGISTER_OPERATIONS |
8079805d RK |
5200 | && (GET_MODE_SIZE (GET_MODE (src)) |
5201 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) | |
df62f951 | 5202 | #endif |
02188693 | 5203 | #ifdef CLASS_CANNOT_CHANGE_MODE |
f507a070 RK |
5204 | && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER |
5205 | && (TEST_HARD_REG_BIT | |
02188693 | 5206 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], |
f507a070 | 5207 | REGNO (dest))) |
02188693 RH |
5208 | && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src), |
5209 | GET_MODE (SUBREG_REG (src)))) | |
663522cb | 5210 | #endif |
8079805d RK |
5211 | && (GET_CODE (dest) == REG |
5212 | || (GET_CODE (dest) == SUBREG | |
5213 | && GET_CODE (SUBREG_REG (dest)) == REG))) | |
5214 | { | |
5215 | SUBST (SET_DEST (x), | |
5216 | gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)), | |
5217 | dest)); | |
5218 | SUBST (SET_SRC (x), SUBREG_REG (src)); | |
5219 | ||
5220 | src = SET_SRC (x), dest = SET_DEST (x); | |
5221 | } | |
df62f951 | 5222 | |
8c1d52a3 KH |
5223 | #ifdef HAVE_cc0 |
5224 | /* If we have (set (cc0) (subreg ...)), we try to remove the subreg | |
5225 | in SRC. */ | |
5226 | if (dest == cc0_rtx | |
5227 | && GET_CODE (src) == SUBREG | |
5228 | && subreg_lowpart_p (src) | |
5229 | && (GET_MODE_BITSIZE (GET_MODE (src)) | |
5230 | < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src))))) | |
5231 | { | |
5232 | rtx inner = SUBREG_REG (src); | |
5233 | enum machine_mode inner_mode = GET_MODE (inner); | |
5234 | ||
5235 | /* Here we make sure that we don't have a sign bit on. */ | |
5236 | if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT | |
5237 | && (nonzero_bits (inner, inner_mode) | |
5238 | < ((unsigned HOST_WIDE_INT) 1 | |
ff076520 | 5239 | << (GET_MODE_BITSIZE (GET_MODE (src)) - 1)))) |
8c1d52a3 KH |
5240 | { |
5241 | SUBST (SET_SRC (x), inner); | |
5242 | src = SET_SRC (x); | |
5243 | } | |
5244 | } | |
5245 | #endif | |
5246 | ||
8baf60bb | 5247 | #ifdef LOAD_EXTEND_OP |
8079805d RK |
5248 | /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this |
5249 | would require a paradoxical subreg. Replace the subreg with a | |
0f41302f | 5250 | zero_extend to avoid the reload that would otherwise be required. */ |
8079805d RK |
5251 | |
5252 | if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) | |
5253 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL | |
ddef6bc7 | 5254 | && SUBREG_BYTE (src) == 0 |
8079805d RK |
5255 | && (GET_MODE_SIZE (GET_MODE (src)) |
5256 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) | |
5257 | && GET_CODE (SUBREG_REG (src)) == MEM) | |
5258 | { | |
5259 | SUBST (SET_SRC (x), | |
f1c6ba8b | 5260 | gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), |
ddef6bc7 | 5261 | GET_MODE (src), SUBREG_REG (src))); |
8079805d RK |
5262 | |
5263 | src = SET_SRC (x); | |
5264 | } | |
230d793d RS |
5265 | #endif |
5266 | ||
8079805d RK |
5267 | /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we |
5268 | are comparing an item known to be 0 or -1 against 0, use a logical | |
5269 | operation instead. Check for one of the arms being an IOR of the other | |
5270 | arm with some value. We compute three terms to be IOR'ed together. In | |
5271 | practice, at most two will be nonzero. Then we do the IOR's. */ | |
5272 | ||
5273 | if (GET_CODE (dest) != PC | |
5274 | && GET_CODE (src) == IF_THEN_ELSE | |
36b8d792 | 5275 | && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT |
8079805d RK |
5276 | && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) |
5277 | && XEXP (XEXP (src, 0), 1) == const0_rtx | |
6dd49058 | 5278 | && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) |
ea414472 DE |
5279 | #ifdef HAVE_conditional_move |
5280 | && ! can_conditionally_move_p (GET_MODE (src)) | |
5281 | #endif | |
8079805d RK |
5282 | && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), |
5283 | GET_MODE (XEXP (XEXP (src, 0), 0))) | |
5284 | == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) | |
5285 | && ! side_effects_p (src)) | |
5286 | { | |
d6edb99e | 5287 | rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE |
8079805d | 5288 | ? XEXP (src, 1) : XEXP (src, 2)); |
d6edb99e | 5289 | rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE |
8079805d RK |
5290 | ? XEXP (src, 2) : XEXP (src, 1)); |
5291 | rtx term1 = const0_rtx, term2, term3; | |
5292 | ||
d6edb99e ZW |
5293 | if (GET_CODE (true_rtx) == IOR |
5294 | && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) | |
5295 | term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx; | |
5296 | else if (GET_CODE (true_rtx) == IOR | |
5297 | && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) | |
5298 | term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx; | |
5299 | else if (GET_CODE (false_rtx) == IOR | |
5300 | && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) | |
5301 | term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx; | |
5302 | else if (GET_CODE (false_rtx) == IOR | |
5303 | && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) | |
5304 | term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx; | |
5305 | ||
5306 | term2 = gen_binary (AND, GET_MODE (src), | |
5307 | XEXP (XEXP (src, 0), 0), true_rtx); | |
8079805d | 5308 | term3 = gen_binary (AND, GET_MODE (src), |
f1c6ba8b RK |
5309 | simplify_gen_unary (NOT, GET_MODE (src), |
5310 | XEXP (XEXP (src, 0), 0), | |
5311 | GET_MODE (src)), | |
d6edb99e | 5312 | false_rtx); |
8079805d RK |
5313 | |
5314 | SUBST (SET_SRC (x), | |
5315 | gen_binary (IOR, GET_MODE (src), | |
5316 | gen_binary (IOR, GET_MODE (src), term1, term2), | |
5317 | term3)); | |
5318 | ||
5319 | src = SET_SRC (x); | |
5320 | } | |
230d793d | 5321 | |
246e00f2 RK |
5322 | /* If either SRC or DEST is a CLOBBER of (const_int 0), make this |
5323 | whole thing fail. */ | |
5324 | if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) | |
5325 | return src; | |
5326 | else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) | |
5327 | return dest; | |
5328 | else | |
5329 | /* Convert this into a field assignment operation, if possible. */ | |
5330 | return make_field_assignment (x); | |
8079805d RK |
5331 | } |
5332 | \f | |
5333 | /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified | |
5334 | result. LAST is nonzero if this is the last retry. */ | |
5335 | ||
5336 | static rtx | |
5337 | simplify_logical (x, last) | |
5338 | rtx x; | |
5339 | int last; | |
5340 | { | |
5341 | enum machine_mode mode = GET_MODE (x); | |
5342 | rtx op0 = XEXP (x, 0); | |
5343 | rtx op1 = XEXP (x, 1); | |
9a915772 | 5344 | rtx reversed; |
8079805d RK |
5345 | |
5346 | switch (GET_CODE (x)) | |
5347 | { | |
230d793d | 5348 | case AND: |
663522cb | 5349 | /* Convert (A ^ B) & A to A & (~B) since the latter is often a single |
8079805d RK |
5350 | insn (and may simplify more). */ |
5351 | if (GET_CODE (op0) == XOR | |
5352 | && rtx_equal_p (XEXP (op0, 0), op1) | |
5353 | && ! side_effects_p (op1)) | |
0c1c8ea6 | 5354 | x = gen_binary (AND, mode, |
f1c6ba8b RK |
5355 | simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode), |
5356 | op1); | |
8079805d RK |
5357 | |
5358 | if (GET_CODE (op0) == XOR | |
5359 | && rtx_equal_p (XEXP (op0, 1), op1) | |
5360 | && ! side_effects_p (op1)) | |
0c1c8ea6 | 5361 | x = gen_binary (AND, mode, |
f1c6ba8b RK |
5362 | simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode), |
5363 | op1); | |
8079805d | 5364 | |
663522cb | 5365 | /* Similarly for (~(A ^ B)) & A. */ |
8079805d RK |
5366 | if (GET_CODE (op0) == NOT |
5367 | && GET_CODE (XEXP (op0, 0)) == XOR | |
5368 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1) | |
5369 | && ! side_effects_p (op1)) | |
5370 | x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1); | |
5371 | ||
5372 | if (GET_CODE (op0) == NOT | |
5373 | && GET_CODE (XEXP (op0, 0)) == XOR | |
5374 | && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1) | |
5375 | && ! side_effects_p (op1)) | |
5376 | x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1); | |
5377 | ||
2e8f9abf DM |
5378 | /* We can call simplify_and_const_int only if we don't lose |
5379 | any (sign) bits when converting INTVAL (op1) to | |
5380 | "unsigned HOST_WIDE_INT". */ | |
5381 | if (GET_CODE (op1) == CONST_INT | |
5382 | && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5383 | || INTVAL (op1) > 0)) | |
230d793d | 5384 | { |
8079805d | 5385 | x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); |
230d793d RS |
5386 | |
5387 | /* If we have (ior (and (X C1) C2)) and the next restart would be | |
5388 | the last, simplify this by making C1 as small as possible | |
0f41302f | 5389 | and then exit. */ |
8079805d RK |
5390 | if (last |
5391 | && GET_CODE (x) == IOR && GET_CODE (op0) == AND | |
5392 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5393 | && GET_CODE (op1) == CONST_INT) | |
5394 | return gen_binary (IOR, mode, | |
5395 | gen_binary (AND, mode, XEXP (op0, 0), | |
5396 | GEN_INT (INTVAL (XEXP (op0, 1)) | |
663522cb | 5397 | & ~INTVAL (op1))), op1); |
230d793d RS |
5398 | |
5399 | if (GET_CODE (x) != AND) | |
8079805d | 5400 | return x; |
0e32506c | 5401 | |
663522cb | 5402 | if (GET_RTX_CLASS (GET_CODE (x)) == 'c' |
0e32506c RK |
5403 | || GET_RTX_CLASS (GET_CODE (x)) == '2') |
5404 | op0 = XEXP (x, 0), op1 = XEXP (x, 1); | |
230d793d RS |
5405 | } |
5406 | ||
5407 | /* Convert (A | B) & A to A. */ | |
8079805d RK |
5408 | if (GET_CODE (op0) == IOR |
5409 | && (rtx_equal_p (XEXP (op0, 0), op1) | |
5410 | || rtx_equal_p (XEXP (op0, 1), op1)) | |
5411 | && ! side_effects_p (XEXP (op0, 0)) | |
5412 | && ! side_effects_p (XEXP (op0, 1))) | |
5413 | return op1; | |
230d793d | 5414 | |
d0ab8cd3 | 5415 | /* In the following group of tests (and those in case IOR below), |
230d793d RS |
5416 | we start with some combination of logical operations and apply |
5417 | the distributive law followed by the inverse distributive law. | |
5418 | Most of the time, this results in no change. However, if some of | |
5419 | the operands are the same or inverses of each other, simplifications | |
5420 | will result. | |
5421 | ||
5422 | For example, (and (ior A B) (not B)) can occur as the result of | |
5423 | expanding a bit field assignment. When we apply the distributive | |
5424 | law to this, we get (ior (and (A (not B))) (and (B (not B)))), | |
663522cb | 5425 | which then simplifies to (and (A (not B))). |
230d793d | 5426 | |
8079805d | 5427 | If we have (and (ior A B) C), apply the distributive law and then |
230d793d RS |
5428 | the inverse distributive law to see if things simplify. */ |
5429 | ||
8079805d | 5430 | if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) |
230d793d RS |
5431 | { |
5432 | x = apply_distributive_law | |
8079805d RK |
5433 | (gen_binary (GET_CODE (op0), mode, |
5434 | gen_binary (AND, mode, XEXP (op0, 0), op1), | |
3749f4ca BS |
5435 | gen_binary (AND, mode, XEXP (op0, 1), |
5436 | copy_rtx (op1)))); | |
230d793d | 5437 | if (GET_CODE (x) != AND) |
8079805d | 5438 | return x; |
230d793d RS |
5439 | } |
5440 | ||
8079805d RK |
5441 | if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) |
5442 | return apply_distributive_law | |
5443 | (gen_binary (GET_CODE (op1), mode, | |
5444 | gen_binary (AND, mode, XEXP (op1, 0), op0), | |
3749f4ca BS |
5445 | gen_binary (AND, mode, XEXP (op1, 1), |
5446 | copy_rtx (op0)))); | |
230d793d RS |
5447 | |
5448 | /* Similarly, taking advantage of the fact that | |
5449 | (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */ | |
5450 | ||
8079805d RK |
5451 | if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR) |
5452 | return apply_distributive_law | |
5453 | (gen_binary (XOR, mode, | |
5454 | gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)), | |
3749f4ca BS |
5455 | gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)), |
5456 | XEXP (op1, 1)))); | |
663522cb | 5457 | |
8079805d RK |
5458 | else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR) |
5459 | return apply_distributive_law | |
5460 | (gen_binary (XOR, mode, | |
5461 | gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)), | |
3749f4ca | 5462 | gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1)))); |
230d793d RS |
5463 | break; |
5464 | ||
5465 | case IOR: | |
951553af | 5466 | /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ |
8079805d | 5467 | if (GET_CODE (op1) == CONST_INT |
ac49a949 | 5468 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
663522cb | 5469 | && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) |
8079805d | 5470 | return op1; |
d0ab8cd3 | 5471 | |
230d793d | 5472 | /* Convert (A & B) | A to A. */ |
8079805d RK |
5473 | if (GET_CODE (op0) == AND |
5474 | && (rtx_equal_p (XEXP (op0, 0), op1) | |
5475 | || rtx_equal_p (XEXP (op0, 1), op1)) | |
5476 | && ! side_effects_p (XEXP (op0, 0)) | |
5477 | && ! side_effects_p (XEXP (op0, 1))) | |
5478 | return op1; | |
230d793d RS |
5479 | |
5480 | /* If we have (ior (and A B) C), apply the distributive law and then | |
5481 | the inverse distributive law to see if things simplify. */ | |
5482 | ||
8079805d | 5483 | if (GET_CODE (op0) == AND) |
230d793d RS |
5484 | { |
5485 | x = apply_distributive_law | |
5486 | (gen_binary (AND, mode, | |
8079805d | 5487 | gen_binary (IOR, mode, XEXP (op0, 0), op1), |
3749f4ca BS |
5488 | gen_binary (IOR, mode, XEXP (op0, 1), |
5489 | copy_rtx (op1)))); | |
230d793d RS |
5490 | |
5491 | if (GET_CODE (x) != IOR) | |
8079805d | 5492 | return x; |
230d793d RS |
5493 | } |
5494 | ||
8079805d | 5495 | if (GET_CODE (op1) == AND) |
230d793d RS |
5496 | { |
5497 | x = apply_distributive_law | |
5498 | (gen_binary (AND, mode, | |
8079805d | 5499 | gen_binary (IOR, mode, XEXP (op1, 0), op0), |
3749f4ca BS |
5500 | gen_binary (IOR, mode, XEXP (op1, 1), |
5501 | copy_rtx (op0)))); | |
230d793d RS |
5502 | |
5503 | if (GET_CODE (x) != IOR) | |
8079805d | 5504 | return x; |
230d793d RS |
5505 | } |
5506 | ||
5507 | /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the | |
5508 | mode size to (rotate A CX). */ | |
5509 | ||
8079805d RK |
5510 | if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) |
5511 | || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT)) | |
5512 | && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)) | |
5513 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5514 | && GET_CODE (XEXP (op1, 1)) == CONST_INT | |
5515 | && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1)) | |
230d793d | 5516 | == GET_MODE_BITSIZE (mode))) |
38a448ca RH |
5517 | return gen_rtx_ROTATE (mode, XEXP (op0, 0), |
5518 | (GET_CODE (op0) == ASHIFT | |
5519 | ? XEXP (op0, 1) : XEXP (op1, 1))); | |
230d793d | 5520 | |
71923da7 RK |
5521 | /* If OP0 is (ashiftrt (plus ...) C), it might actually be |
5522 | a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS | |
5523 | does not affect any of the bits in OP1, it can really be done | |
5524 | as a PLUS and we can associate. We do this by seeing if OP1 | |
5525 | can be safely shifted left C bits. */ | |
5526 | if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT | |
5527 | && GET_CODE (XEXP (op0, 0)) == PLUS | |
5528 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
5529 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5530 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT) | |
5531 | { | |
5532 | int count = INTVAL (XEXP (op0, 1)); | |
5533 | HOST_WIDE_INT mask = INTVAL (op1) << count; | |
5534 | ||
5535 | if (mask >> count == INTVAL (op1) | |
5536 | && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) | |
5537 | { | |
5538 | SUBST (XEXP (XEXP (op0, 0), 1), | |
5539 | GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask)); | |
5540 | return op0; | |
5541 | } | |
5542 | } | |
230d793d RS |
5543 | break; |
5544 | ||
5545 | case XOR: | |
79e8185c JH |
5546 | /* If we are XORing two things that have no bits in common, |
5547 | convert them into an IOR. This helps to detect rotation encoded | |
5548 | using those methods and possibly other simplifications. */ | |
5549 | ||
5550 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5551 | && (nonzero_bits (op0, mode) | |
5552 | & nonzero_bits (op1, mode)) == 0) | |
5553 | return (gen_binary (IOR, mode, op0, op1)); | |
5554 | ||
230d793d RS |
5555 | /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). |
5556 | Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for | |
5557 | (NOT y). */ | |
5558 | { | |
5559 | int num_negated = 0; | |
230d793d | 5560 | |
8079805d RK |
5561 | if (GET_CODE (op0) == NOT) |
5562 | num_negated++, op0 = XEXP (op0, 0); | |
5563 | if (GET_CODE (op1) == NOT) | |
5564 | num_negated++, op1 = XEXP (op1, 0); | |
230d793d RS |
5565 | |
5566 | if (num_negated == 2) | |
5567 | { | |
8079805d RK |
5568 | SUBST (XEXP (x, 0), op0); |
5569 | SUBST (XEXP (x, 1), op1); | |
230d793d RS |
5570 | } |
5571 | else if (num_negated == 1) | |
f1c6ba8b RK |
5572 | return |
5573 | simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1), | |
5574 | mode); | |
230d793d RS |
5575 | } |
5576 | ||
5577 | /* Convert (xor (and A B) B) to (and (not A) B). The latter may | |
5578 | correspond to a machine insn or result in further simplifications | |
5579 | if B is a constant. */ | |
5580 | ||
8079805d RK |
5581 | if (GET_CODE (op0) == AND |
5582 | && rtx_equal_p (XEXP (op0, 1), op1) | |
5583 | && ! side_effects_p (op1)) | |
0c1c8ea6 | 5584 | return gen_binary (AND, mode, |
f1c6ba8b | 5585 | simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode), |
8079805d | 5586 | op1); |
230d793d | 5587 | |
8079805d RK |
5588 | else if (GET_CODE (op0) == AND |
5589 | && rtx_equal_p (XEXP (op0, 0), op1) | |
5590 | && ! side_effects_p (op1)) | |
0c1c8ea6 | 5591 | return gen_binary (AND, mode, |
f1c6ba8b | 5592 | simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode), |
8079805d | 5593 | op1); |
230d793d | 5594 | |
230d793d | 5595 | /* (xor (comparison foo bar) (const_int 1)) can become the reversed |
0802d516 RK |
5596 | comparison if STORE_FLAG_VALUE is 1. */ |
5597 | if (STORE_FLAG_VALUE == 1 | |
5598 | && op1 == const1_rtx | |
8079805d | 5599 | && GET_RTX_CLASS (GET_CODE (op0)) == '<' |
9a915772 JH |
5600 | && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0), |
5601 | XEXP (op0, 1)))) | |
5602 | return reversed; | |
500c518b RK |
5603 | |
5604 | /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 | |
5605 | is (lt foo (const_int 0)), so we can perform the above | |
0802d516 | 5606 | simplification if STORE_FLAG_VALUE is 1. */ |
500c518b | 5607 | |
0802d516 RK |
5608 | if (STORE_FLAG_VALUE == 1 |
5609 | && op1 == const1_rtx | |
8079805d RK |
5610 | && GET_CODE (op0) == LSHIFTRT |
5611 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5612 | && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1) | |
f1c6ba8b | 5613 | return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx); |
230d793d RS |
5614 | |
5615 | /* (xor (comparison foo bar) (const_int sign-bit)) | |
5616 | when STORE_FLAG_VALUE is the sign bit. */ | |
5f4f0e22 | 5617 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
0802d516 | 5618 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
e51712db | 5619 | == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) |
8079805d RK |
5620 | && op1 == const_true_rtx |
5621 | && GET_RTX_CLASS (GET_CODE (op0)) == '<' | |
9a915772 JH |
5622 | && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0), |
5623 | XEXP (op0, 1)))) | |
5624 | return reversed; | |
0918eca0 | 5625 | |
230d793d | 5626 | break; |
e9a25f70 JL |
5627 | |
5628 | default: | |
5629 | abort (); | |
230d793d RS |
5630 | } |
5631 | ||
5632 | return x; | |
5633 | } | |
5634 | \f | |
5635 | /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound | |
5636 | operations" because they can be replaced with two more basic operations. | |
5637 | ZERO_EXTEND is also considered "compound" because it can be replaced with | |
5638 | an AND operation, which is simpler, though only one operation. | |
5639 | ||
5640 | The function expand_compound_operation is called with an rtx expression | |
663522cb | 5641 | and will convert it to the appropriate shifts and AND operations, |
230d793d RS |
5642 | simplifying at each stage. |
5643 | ||
5644 | The function make_compound_operation is called to convert an expression | |
5645 | consisting of shifts and ANDs into the equivalent compound expression. | |
5646 | It is the inverse of this function, loosely speaking. */ | |
5647 | ||
5648 | static rtx | |
5649 | expand_compound_operation (x) | |
5650 | rtx x; | |
5651 | { | |
770ae6cc | 5652 | unsigned HOST_WIDE_INT pos = 0, len; |
230d793d | 5653 | int unsignedp = 0; |
770ae6cc | 5654 | unsigned int modewidth; |
230d793d RS |
5655 | rtx tem; |
5656 | ||
5657 | switch (GET_CODE (x)) | |
5658 | { | |
5659 | case ZERO_EXTEND: | |
5660 | unsignedp = 1; | |
5661 | case SIGN_EXTEND: | |
75473182 RS |
5662 | /* We can't necessarily use a const_int for a multiword mode; |
5663 | it depends on implicitly extending the value. | |
5664 | Since we don't know the right way to extend it, | |
5665 | we can't tell whether the implicit way is right. | |
5666 | ||
5667 | Even for a mode that is no wider than a const_int, | |
5668 | we can't win, because we need to sign extend one of its bits through | |
5669 | the rest of it, and we don't know which bit. */ | |
230d793d | 5670 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
75473182 | 5671 | return x; |
230d793d | 5672 | |
8079805d RK |
5673 | /* Return if (subreg:MODE FROM 0) is not a safe replacement for |
5674 | (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM | |
5675 | because (SUBREG (MEM...)) is guaranteed to cause the MEM to be | |
5676 | reloaded. If not for that, MEM's would very rarely be safe. | |
5677 | ||
5678 | Reject MODEs bigger than a word, because we might not be able | |
5679 | to reference a two-register group starting with an arbitrary register | |
5680 | (and currently gen_lowpart might crash for a SUBREG). */ | |
663522cb | 5681 | |
8079805d | 5682 | if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) |
230d793d RS |
5683 | return x; |
5684 | ||
71012d97 GK |
5685 | /* Reject MODEs that aren't scalar integers because turning vector |
5686 | or complex modes into shifts causes problems. */ | |
5687 | ||
5688 | if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
5689 | return x; | |
5690 | ||
230d793d RS |
5691 | len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); |
5692 | /* If the inner object has VOIDmode (the only way this can happen | |
e0a2f705 | 5693 | is if it is an ASM_OPERANDS), we can't do anything since we don't |
230d793d RS |
5694 | know how much masking to do. */ |
5695 | if (len == 0) | |
5696 | return x; | |
5697 | ||
5698 | break; | |
5699 | ||
5700 | case ZERO_EXTRACT: | |
5701 | unsignedp = 1; | |
5702 | case SIGN_EXTRACT: | |
5703 | /* If the operand is a CLOBBER, just return it. */ | |
5704 | if (GET_CODE (XEXP (x, 0)) == CLOBBER) | |
5705 | return XEXP (x, 0); | |
5706 | ||
5707 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
5708 | || GET_CODE (XEXP (x, 2)) != CONST_INT | |
5709 | || GET_MODE (XEXP (x, 0)) == VOIDmode) | |
5710 | return x; | |
5711 | ||
71012d97 GK |
5712 | /* Reject MODEs that aren't scalar integers because turning vector |
5713 | or complex modes into shifts causes problems. */ | |
5714 | ||
5715 | if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
5716 | return x; | |
5717 | ||
230d793d RS |
5718 | len = INTVAL (XEXP (x, 1)); |
5719 | pos = INTVAL (XEXP (x, 2)); | |
5720 | ||
5721 | /* If this goes outside the object being extracted, replace the object | |
5722 | with a (use (mem ...)) construct that only combine understands | |
5723 | and is used only for this purpose. */ | |
5724 | if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) | |
38a448ca | 5725 | SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0))); |
230d793d | 5726 | |
f76b9db2 ILT |
5727 | if (BITS_BIG_ENDIAN) |
5728 | pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; | |
5729 | ||
230d793d RS |
5730 | break; |
5731 | ||
5732 | default: | |
5733 | return x; | |
5734 | } | |
0f808b6f JH |
5735 | /* Convert sign extension to zero extension, if we know that the high |
5736 | bit is not set, as this is easier to optimize. It will be converted | |
5737 | back to cheaper alternative in make_extraction. */ | |
5738 | if (GET_CODE (x) == SIGN_EXTEND | |
5739 | && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5740 | && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
663522cb | 5741 | & ~(((unsigned HOST_WIDE_INT) |
0f808b6f JH |
5742 | GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) |
5743 | >> 1)) | |
5744 | == 0))) | |
5745 | { | |
5746 | rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); | |
5747 | return expand_compound_operation (temp); | |
5748 | } | |
230d793d | 5749 | |
0f13a422 ILT |
5750 | /* We can optimize some special cases of ZERO_EXTEND. */ |
5751 | if (GET_CODE (x) == ZERO_EXTEND) | |
5752 | { | |
5753 | /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we | |
5754 | know that the last value didn't have any inappropriate bits | |
5755 | set. */ | |
5756 | if (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
5757 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
5758 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5759 | && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) | |
663522cb | 5760 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5761 | return XEXP (XEXP (x, 0), 0); |
5762 | ||
5763 | /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
5764 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
5765 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
5766 | && subreg_lowpart_p (XEXP (x, 0)) | |
5767 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5768 | && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) | |
663522cb | 5769 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5770 | return SUBREG_REG (XEXP (x, 0)); |
5771 | ||
5772 | /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo | |
5773 | is a comparison and STORE_FLAG_VALUE permits. This is like | |
5774 | the first case, but it works even when GET_MODE (x) is larger | |
5775 | than HOST_WIDE_INT. */ | |
5776 | if (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
5777 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
5778 | && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<' | |
5779 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) | |
5780 | <= HOST_BITS_PER_WIDE_INT) | |
23190837 | 5781 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE |
663522cb | 5782 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5783 | return XEXP (XEXP (x, 0), 0); |
5784 | ||
5785 | /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
5786 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
5787 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
5788 | && subreg_lowpart_p (XEXP (x, 0)) | |
5789 | && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<' | |
5790 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) | |
5791 | <= HOST_BITS_PER_WIDE_INT) | |
5792 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE | |
663522cb | 5793 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5794 | return SUBREG_REG (XEXP (x, 0)); |
5795 | ||
0f13a422 ILT |
5796 | } |
5797 | ||
230d793d RS |
5798 | /* If we reach here, we want to return a pair of shifts. The inner |
5799 | shift is a left shift of BITSIZE - POS - LEN bits. The outer | |
5800 | shift is a right shift of BITSIZE - LEN bits. It is arithmetic or | |
5801 | logical depending on the value of UNSIGNEDP. | |
5802 | ||
5803 | If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be | |
5804 | converted into an AND of a shift. | |
5805 | ||
5806 | We must check for the case where the left shift would have a negative | |
5807 | count. This can happen in a case like (x >> 31) & 255 on machines | |
5808 | that can't shift by a constant. On those machines, we would first | |
663522cb | 5809 | combine the shift with the AND to produce a variable-position |
230d793d RS |
5810 | extraction. Then the constant of 31 would be substituted in to produce |
5811 | a such a position. */ | |
5812 | ||
5813 | modewidth = GET_MODE_BITSIZE (GET_MODE (x)); | |
770ae6cc | 5814 | if (modewidth + len >= pos) |
5f4f0e22 | 5815 | tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, |
230d793d | 5816 | GET_MODE (x), |
5f4f0e22 CH |
5817 | simplify_shift_const (NULL_RTX, ASHIFT, |
5818 | GET_MODE (x), | |
230d793d RS |
5819 | XEXP (x, 0), |
5820 | modewidth - pos - len), | |
5821 | modewidth - len); | |
5822 | ||
5f4f0e22 CH |
5823 | else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) |
5824 | tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), | |
5825 | simplify_shift_const (NULL_RTX, LSHIFTRT, | |
230d793d RS |
5826 | GET_MODE (x), |
5827 | XEXP (x, 0), pos), | |
5f4f0e22 | 5828 | ((HOST_WIDE_INT) 1 << len) - 1); |
230d793d RS |
5829 | else |
5830 | /* Any other cases we can't handle. */ | |
5831 | return x; | |
230d793d RS |
5832 | |
5833 | /* If we couldn't do this for some reason, return the original | |
5834 | expression. */ | |
5835 | if (GET_CODE (tem) == CLOBBER) | |
5836 | return x; | |
5837 | ||
5838 | return tem; | |
5839 | } | |
5840 | \f | |
5841 | /* X is a SET which contains an assignment of one object into | |
5842 | a part of another (such as a bit-field assignment, STRICT_LOW_PART, | |
5843 | or certain SUBREGS). If possible, convert it into a series of | |
5844 | logical operations. | |
5845 | ||
5846 | We half-heartedly support variable positions, but do not at all | |
5847 | support variable lengths. */ | |
5848 | ||
5849 | static rtx | |
5850 | expand_field_assignment (x) | |
5851 | rtx x; | |
5852 | { | |
5853 | rtx inner; | |
0f41302f | 5854 | rtx pos; /* Always counts from low bit. */ |
230d793d RS |
5855 | int len; |
5856 | rtx mask; | |
5857 | enum machine_mode compute_mode; | |
5858 | ||
5859 | /* Loop until we find something we can't simplify. */ | |
5860 | while (1) | |
5861 | { | |
5862 | if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART | |
5863 | && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) | |
5864 | { | |
5865 | inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); | |
5866 | len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); | |
47073a38 | 5867 | pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); |
230d793d RS |
5868 | } |
5869 | else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
5870 | && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) | |
5871 | { | |
5872 | inner = XEXP (SET_DEST (x), 0); | |
5873 | len = INTVAL (XEXP (SET_DEST (x), 1)); | |
5874 | pos = XEXP (SET_DEST (x), 2); | |
5875 | ||
5876 | /* If the position is constant and spans the width of INNER, | |
5877 | surround INNER with a USE to indicate this. */ | |
5878 | if (GET_CODE (pos) == CONST_INT | |
5879 | && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) | |
38a448ca | 5880 | inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner); |
230d793d | 5881 | |
f76b9db2 ILT |
5882 | if (BITS_BIG_ENDIAN) |
5883 | { | |
5884 | if (GET_CODE (pos) == CONST_INT) | |
5885 | pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len | |
5886 | - INTVAL (pos)); | |
5887 | else if (GET_CODE (pos) == MINUS | |
5888 | && GET_CODE (XEXP (pos, 1)) == CONST_INT | |
5889 | && (INTVAL (XEXP (pos, 1)) | |
5890 | == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) | |
5891 | /* If position is ADJUST - X, new position is X. */ | |
5892 | pos = XEXP (pos, 0); | |
5893 | else | |
5894 | pos = gen_binary (MINUS, GET_MODE (pos), | |
5895 | GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) | |
5896 | - len), | |
5897 | pos); | |
5898 | } | |
230d793d RS |
5899 | } |
5900 | ||
5901 | /* A SUBREG between two modes that occupy the same numbers of words | |
5902 | can be done by moving the SUBREG to the source. */ | |
5903 | else if (GET_CODE (SET_DEST (x)) == SUBREG | |
b1e9c8a9 AO |
5904 | /* We need SUBREGs to compute nonzero_bits properly. */ |
5905 | && nonzero_sign_valid | |
230d793d RS |
5906 | && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) |
5907 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
5908 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
5909 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
5910 | { | |
38a448ca | 5911 | x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), |
c5c76735 JL |
5912 | gen_lowpart_for_combine |
5913 | (GET_MODE (SUBREG_REG (SET_DEST (x))), | |
5914 | SET_SRC (x))); | |
230d793d RS |
5915 | continue; |
5916 | } | |
5917 | else | |
5918 | break; | |
5919 | ||
5920 | while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
5921 | inner = SUBREG_REG (inner); | |
5922 | ||
5923 | compute_mode = GET_MODE (inner); | |
5924 | ||
71012d97 GK |
5925 | /* Don't attempt bitwise arithmetic on non scalar integer modes. */ |
5926 | if (! SCALAR_INT_MODE_P (compute_mode)) | |
861556b4 RH |
5927 | { |
5928 | enum machine_mode imode; | |
5929 | ||
71012d97 | 5930 | /* Don't do anything for vector or complex integral types. */ |
861556b4 RH |
5931 | if (! FLOAT_MODE_P (compute_mode)) |
5932 | break; | |
5933 | ||
5934 | /* Try to find an integral mode to pun with. */ | |
5935 | imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); | |
5936 | if (imode == BLKmode) | |
5937 | break; | |
5938 | ||
5939 | compute_mode = imode; | |
5940 | inner = gen_lowpart_for_combine (imode, inner); | |
5941 | } | |
5942 | ||
230d793d | 5943 | /* Compute a mask of LEN bits, if we can do this on the host machine. */ |
5f4f0e22 CH |
5944 | if (len < HOST_BITS_PER_WIDE_INT) |
5945 | mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); | |
230d793d RS |
5946 | else |
5947 | break; | |
5948 | ||
5949 | /* Now compute the equivalent expression. Make a copy of INNER | |
5950 | for the SET_DEST in case it is a MEM into which we will substitute; | |
5951 | we don't want shared RTL in that case. */ | |
c5c76735 JL |
5952 | x = gen_rtx_SET |
5953 | (VOIDmode, copy_rtx (inner), | |
5954 | gen_binary (IOR, compute_mode, | |
5955 | gen_binary (AND, compute_mode, | |
f1c6ba8b RK |
5956 | simplify_gen_unary (NOT, compute_mode, |
5957 | gen_binary (ASHIFT, | |
5958 | compute_mode, | |
5959 | mask, pos), | |
5960 | compute_mode), | |
c5c76735 JL |
5961 | inner), |
5962 | gen_binary (ASHIFT, compute_mode, | |
5963 | gen_binary (AND, compute_mode, | |
5964 | gen_lowpart_for_combine | |
5965 | (compute_mode, SET_SRC (x)), | |
5966 | mask), | |
5967 | pos))); | |
230d793d RS |
5968 | } |
5969 | ||
5970 | return x; | |
5971 | } | |
5972 | \f | |
8999a12e RK |
5973 | /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, |
5974 | it is an RTX that represents a variable starting position; otherwise, | |
5975 | POS is the (constant) starting bit position (counted from the LSB). | |
230d793d RS |
5976 | |
5977 | INNER may be a USE. This will occur when we started with a bitfield | |
5978 | that went outside the boundary of the object in memory, which is | |
5979 | allowed on most machines. To isolate this case, we produce a USE | |
5980 | whose mode is wide enough and surround the MEM with it. The only | |
5981 | code that understands the USE is this routine. If it is not removed, | |
5982 | it will cause the resulting insn not to match. | |
5983 | ||
da7d8304 | 5984 | UNSIGNEDP is nonzero for an unsigned reference and zero for a |
230d793d RS |
5985 | signed reference. |
5986 | ||
da7d8304 KH |
5987 | IN_DEST is nonzero if this is a reference in the destination of a |
5988 | SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, | |
230d793d RS |
5989 | a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will |
5990 | be used. | |
5991 | ||
da7d8304 | 5992 | IN_COMPARE is nonzero if we are in a COMPARE. This means that a |
230d793d RS |
5993 | ZERO_EXTRACT should be built even for bits starting at bit 0. |
5994 | ||
76184def DE |
5995 | MODE is the desired mode of the result (if IN_DEST == 0). |
5996 | ||
5997 | The result is an RTX for the extraction or NULL_RTX if the target | |
5998 | can't handle it. */ | |
230d793d RS |
5999 | |
6000 | static rtx | |
6001 | make_extraction (mode, inner, pos, pos_rtx, len, | |
6002 | unsignedp, in_dest, in_compare) | |
6003 | enum machine_mode mode; | |
6004 | rtx inner; | |
770ae6cc | 6005 | HOST_WIDE_INT pos; |
230d793d | 6006 | rtx pos_rtx; |
770ae6cc | 6007 | unsigned HOST_WIDE_INT len; |
230d793d RS |
6008 | int unsignedp; |
6009 | int in_dest, in_compare; | |
6010 | { | |
94b4b17a RS |
6011 | /* This mode describes the size of the storage area |
6012 | to fetch the overall value from. Within that, we | |
6013 | ignore the POS lowest bits, etc. */ | |
230d793d RS |
6014 | enum machine_mode is_mode = GET_MODE (inner); |
6015 | enum machine_mode inner_mode; | |
d7cd794f RK |
6016 | enum machine_mode wanted_inner_mode = byte_mode; |
6017 | enum machine_mode wanted_inner_reg_mode = word_mode; | |
230d793d RS |
6018 | enum machine_mode pos_mode = word_mode; |
6019 | enum machine_mode extraction_mode = word_mode; | |
6020 | enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); | |
6021 | int spans_byte = 0; | |
6022 | rtx new = 0; | |
8999a12e | 6023 | rtx orig_pos_rtx = pos_rtx; |
770ae6cc | 6024 | HOST_WIDE_INT orig_pos; |
230d793d RS |
6025 | |
6026 | /* Get some information about INNER and get the innermost object. */ | |
6027 | if (GET_CODE (inner) == USE) | |
94b4b17a | 6028 | /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ |
230d793d RS |
6029 | /* We don't need to adjust the position because we set up the USE |
6030 | to pretend that it was a full-word object. */ | |
6031 | spans_byte = 1, inner = XEXP (inner, 0); | |
6032 | else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
94b4b17a RS |
6033 | { |
6034 | /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), | |
6035 | consider just the QI as the memory to extract from. | |
6036 | The subreg adds or removes high bits; its mode is | |
6037 | irrelevant to the meaning of this extraction, | |
6038 | since POS and LEN count from the lsb. */ | |
6039 | if (GET_CODE (SUBREG_REG (inner)) == MEM) | |
6040 | is_mode = GET_MODE (SUBREG_REG (inner)); | |
6041 | inner = SUBREG_REG (inner); | |
6042 | } | |
988ef418 RS |
6043 | else if (GET_CODE (inner) == ASHIFT |
6044 | && GET_CODE (XEXP (inner, 1)) == CONST_INT | |
6045 | && pos_rtx == 0 && pos == 0 | |
3129af4c | 6046 | && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1))) |
988ef418 RS |
6047 | { |
6048 | /* We're extracting the least significant bits of an rtx | |
6049 | (ashift X (const_int C)), where LEN > C. Extract the | |
6050 | least significant (LEN - C) bits of X, giving an rtx | |
6051 | whose mode is MODE, then shift it left C times. */ | |
6052 | new = make_extraction (mode, XEXP (inner, 0), | |
6053 | 0, 0, len - INTVAL (XEXP (inner, 1)), | |
6054 | unsignedp, in_dest, in_compare); | |
6055 | if (new != 0) | |
6056 | return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1)); | |
6057 | } | |
230d793d RS |
6058 | |
6059 | inner_mode = GET_MODE (inner); | |
6060 | ||
6061 | if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) | |
8999a12e | 6062 | pos = INTVAL (pos_rtx), pos_rtx = 0; |
230d793d RS |
6063 | |
6064 | /* See if this can be done without an extraction. We never can if the | |
6065 | width of the field is not the same as that of some integer mode. For | |
6066 | registers, we can only avoid the extraction if the position is at the | |
6067 | low-order bit and this is either not in the destination or we have the | |
6068 | appropriate STRICT_LOW_PART operation available. | |
6069 | ||
6070 | For MEM, we can avoid an extract if the field starts on an appropriate | |
6071 | boundary and we can change the mode of the memory reference. However, | |
6072 | we cannot directly access the MEM if we have a USE and the underlying | |
6073 | MEM is not TMODE. This combination means that MEM was being used in a | |
6074 | context where bits outside its mode were being referenced; that is only | |
6075 | valid in bit-field insns. */ | |
6076 | ||
6077 | if (tmode != BLKmode | |
6078 | && ! (spans_byte && inner_mode != tmode) | |
4d9cfc7b RK |
6079 | && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 |
6080 | && GET_CODE (inner) != MEM | |
230d793d | 6081 | && (! in_dest |
df62f951 | 6082 | || (GET_CODE (inner) == REG |
ef89d648 | 6083 | && have_insn_for (STRICT_LOW_PART, tmode)))) |
8999a12e | 6084 | || (GET_CODE (inner) == MEM && pos_rtx == 0 |
dfbe1b2f RK |
6085 | && (pos |
6086 | % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) | |
6087 | : BITS_PER_UNIT)) == 0 | |
230d793d RS |
6088 | /* We can't do this if we are widening INNER_MODE (it |
6089 | may not be aligned, for one thing). */ | |
6090 | && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) | |
6091 | && (inner_mode == tmode | |
6092 | || (! mode_dependent_address_p (XEXP (inner, 0)) | |
6093 | && ! MEM_VOLATILE_P (inner)))))) | |
6094 | { | |
230d793d RS |
6095 | /* If INNER is a MEM, make a new MEM that encompasses just the desired |
6096 | field. If the original and current mode are the same, we need not | |
663522cb | 6097 | adjust the offset. Otherwise, we do if bytes big endian. |
230d793d | 6098 | |
4d9cfc7b RK |
6099 | If INNER is not a MEM, get a piece consisting of just the field |
6100 | of interest (in this case POS % BITS_PER_WORD must be 0). */ | |
230d793d RS |
6101 | |
6102 | if (GET_CODE (inner) == MEM) | |
6103 | { | |
f1ec5147 RK |
6104 | HOST_WIDE_INT offset; |
6105 | ||
94b4b17a RS |
6106 | /* POS counts from lsb, but make OFFSET count in memory order. */ |
6107 | if (BYTES_BIG_ENDIAN) | |
6108 | offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; | |
6109 | else | |
6110 | offset = pos / BITS_PER_UNIT; | |
230d793d | 6111 | |
f1ec5147 | 6112 | new = adjust_address_nv (inner, tmode, offset); |
230d793d | 6113 | } |
df62f951 | 6114 | else if (GET_CODE (inner) == REG) |
c0d3ac4d RK |
6115 | { |
6116 | /* We can't call gen_lowpart_for_combine here since we always want | |
6117 | a SUBREG and it would sometimes return a new hard register. */ | |
6118 | if (tmode != inner_mode) | |
ddef6bc7 | 6119 | { |
f1ec5147 | 6120 | HOST_WIDE_INT final_word = pos / BITS_PER_WORD; |
ddef6bc7 JJ |
6121 | |
6122 | if (WORDS_BIG_ENDIAN | |
6123 | && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) | |
6124 | final_word = ((GET_MODE_SIZE (inner_mode) | |
6125 | - GET_MODE_SIZE (tmode)) | |
6126 | / UNITS_PER_WORD) - final_word; | |
6127 | ||
6128 | final_word *= UNITS_PER_WORD; | |
6129 | if (BYTES_BIG_ENDIAN && | |
6130 | GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) | |
6131 | final_word += (GET_MODE_SIZE (inner_mode) | |
6132 | - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; | |
6133 | ||
307f767b | 6134 | /* Avoid creating invalid subregs, for example when |
991b6592 | 6135 | simplifying (x>>32)&255. */ |
307f767b DJ |
6136 | if (final_word >= GET_MODE_SIZE (inner_mode)) |
6137 | return NULL_RTX; | |
6138 | ||
ddef6bc7 JJ |
6139 | new = gen_rtx_SUBREG (tmode, inner, final_word); |
6140 | } | |
23190837 AJ |
6141 | else |
6142 | new = inner; | |
6143 | } | |
230d793d | 6144 | else |
6139ff20 RK |
6145 | new = force_to_mode (inner, tmode, |
6146 | len >= HOST_BITS_PER_WIDE_INT | |
0345195a | 6147 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 | 6148 | : ((unsigned HOST_WIDE_INT) 1 << len) - 1, |
e3d616e3 | 6149 | NULL_RTX, 0); |
230d793d | 6150 | |
663522cb | 6151 | /* If this extraction is going into the destination of a SET, |
230d793d RS |
6152 | make a STRICT_LOW_PART unless we made a MEM. */ |
6153 | ||
6154 | if (in_dest) | |
6155 | return (GET_CODE (new) == MEM ? new | |
77fa0940 | 6156 | : (GET_CODE (new) != SUBREG |
38a448ca | 6157 | ? gen_rtx_CLOBBER (tmode, const0_rtx) |
f1c6ba8b | 6158 | : gen_rtx_STRICT_LOW_PART (VOIDmode, new))); |
230d793d | 6159 | |
0f808b6f JH |
6160 | if (mode == tmode) |
6161 | return new; | |
6162 | ||
0a7ec763 | 6163 | if (GET_CODE (new) == CONST_INT) |
2496c7bd | 6164 | return gen_int_mode (INTVAL (new), mode); |
0a7ec763 | 6165 | |
0f808b6f JH |
6166 | /* If we know that no extraneous bits are set, and that the high |
6167 | bit is not set, convert the extraction to the cheaper of | |
6168 | sign and zero extension, that are equivalent in these cases. */ | |
6169 | if (flag_expensive_optimizations | |
6170 | && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT | |
6171 | && ((nonzero_bits (new, tmode) | |
663522cb KH |
6172 | & ~(((unsigned HOST_WIDE_INT) |
6173 | GET_MODE_MASK (tmode)) | |
6174 | >> 1)) | |
0f808b6f JH |
6175 | == 0))) |
6176 | { | |
6177 | rtx temp = gen_rtx_ZERO_EXTEND (mode, new); | |
6178 | rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new); | |
6179 | ||
6180 | /* Prefer ZERO_EXTENSION, since it gives more information to | |
6181 | backends. */ | |
25ffb1f6 | 6182 | if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET)) |
0f808b6f JH |
6183 | return temp; |
6184 | return temp1; | |
6185 | } | |
6186 | ||
230d793d RS |
6187 | /* Otherwise, sign- or zero-extend unless we already are in the |
6188 | proper mode. */ | |
6189 | ||
f1c6ba8b RK |
6190 | return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, |
6191 | mode, new)); | |
230d793d RS |
6192 | } |
6193 | ||
cc471082 RS |
6194 | /* Unless this is a COMPARE or we have a funny memory reference, |
6195 | don't do anything with zero-extending field extracts starting at | |
6196 | the low-order bit since they are simple AND operations. */ | |
8999a12e RK |
6197 | if (pos_rtx == 0 && pos == 0 && ! in_dest |
6198 | && ! in_compare && ! spans_byte && unsignedp) | |
230d793d RS |
6199 | return 0; |
6200 | ||
c5c76735 JL |
6201 | /* Unless we are allowed to span bytes or INNER is not MEM, reject this if |
6202 | we would be spanning bytes or if the position is not a constant and the | |
6203 | length is not 1. In all other cases, we would only be going outside | |
6204 | our object in cases when an original shift would have been | |
e7373556 | 6205 | undefined. */ |
c5c76735 | 6206 | if (! spans_byte && GET_CODE (inner) == MEM |
e7373556 RK |
6207 | && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) |
6208 | || (pos_rtx != 0 && len != 1))) | |
6209 | return 0; | |
6210 | ||
d7cd794f | 6211 | /* Get the mode to use should INNER not be a MEM, the mode for the position, |
230d793d | 6212 | and the mode for the result. */ |
505ddab6 | 6213 | if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE) |
230d793d | 6214 | { |
da920570 ZW |
6215 | wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0); |
6216 | pos_mode = mode_for_extraction (EP_insv, 2); | |
6217 | extraction_mode = mode_for_extraction (EP_insv, 3); | |
230d793d | 6218 | } |
230d793d | 6219 | |
da920570 ZW |
6220 | if (! in_dest && unsignedp |
6221 | && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE) | |
230d793d | 6222 | { |
da920570 ZW |
6223 | wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1); |
6224 | pos_mode = mode_for_extraction (EP_extzv, 3); | |
6225 | extraction_mode = mode_for_extraction (EP_extzv, 0); | |
230d793d | 6226 | } |
230d793d | 6227 | |
da920570 ZW |
6228 | if (! in_dest && ! unsignedp |
6229 | && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE) | |
230d793d | 6230 | { |
da920570 ZW |
6231 | wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1); |
6232 | pos_mode = mode_for_extraction (EP_extv, 3); | |
6233 | extraction_mode = mode_for_extraction (EP_extv, 0); | |
230d793d | 6234 | } |
230d793d RS |
6235 | |
6236 | /* Never narrow an object, since that might not be safe. */ | |
6237 | ||
6238 | if (mode != VOIDmode | |
6239 | && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) | |
6240 | extraction_mode = mode; | |
6241 | ||
6242 | if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode | |
6243 | && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
6244 | pos_mode = GET_MODE (pos_rtx); | |
6245 | ||
d7cd794f RK |
6246 | /* If this is not from memory, the desired mode is wanted_inner_reg_mode; |
6247 | if we have to change the mode of memory and cannot, the desired mode is | |
6248 | EXTRACTION_MODE. */ | |
6249 | if (GET_CODE (inner) != MEM) | |
6250 | wanted_inner_mode = wanted_inner_reg_mode; | |
6251 | else if (inner_mode != wanted_inner_mode | |
6252 | && (mode_dependent_address_p (XEXP (inner, 0)) | |
6253 | || MEM_VOLATILE_P (inner))) | |
6254 | wanted_inner_mode = extraction_mode; | |
230d793d | 6255 | |
6139ff20 RK |
6256 | orig_pos = pos; |
6257 | ||
f76b9db2 ILT |
6258 | if (BITS_BIG_ENDIAN) |
6259 | { | |
cf54c2cd DE |
6260 | /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to |
6261 | BITS_BIG_ENDIAN style. If position is constant, compute new | |
6262 | position. Otherwise, build subtraction. | |
6263 | Note that POS is relative to the mode of the original argument. | |
6264 | If it's a MEM we need to recompute POS relative to that. | |
6265 | However, if we're extracting from (or inserting into) a register, | |
6266 | we want to recompute POS relative to wanted_inner_mode. */ | |
6267 | int width = (GET_CODE (inner) == MEM | |
6268 | ? GET_MODE_BITSIZE (is_mode) | |
6269 | : GET_MODE_BITSIZE (wanted_inner_mode)); | |
6270 | ||
f76b9db2 | 6271 | if (pos_rtx == 0) |
cf54c2cd | 6272 | pos = width - len - pos; |
f76b9db2 ILT |
6273 | else |
6274 | pos_rtx | |
f1c6ba8b | 6275 | = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx); |
cf54c2cd DE |
6276 | /* POS may be less than 0 now, but we check for that below. |
6277 | Note that it can only be less than 0 if GET_CODE (inner) != MEM. */ | |
f76b9db2 | 6278 | } |
230d793d RS |
6279 | |
6280 | /* If INNER has a wider mode, make it smaller. If this is a constant | |
6281 | extract, try to adjust the byte to point to the byte containing | |
6282 | the value. */ | |
d7cd794f RK |
6283 | if (wanted_inner_mode != VOIDmode |
6284 | && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) | |
230d793d | 6285 | && ((GET_CODE (inner) == MEM |
d7cd794f | 6286 | && (inner_mode == wanted_inner_mode |
230d793d RS |
6287 | || (! mode_dependent_address_p (XEXP (inner, 0)) |
6288 | && ! MEM_VOLATILE_P (inner)))))) | |
6289 | { | |
6290 | int offset = 0; | |
6291 | ||
6292 | /* The computations below will be correct if the machine is big | |
6293 | endian in both bits and bytes or little endian in bits and bytes. | |
6294 | If it is mixed, we must adjust. */ | |
663522cb | 6295 | |
230d793d | 6296 | /* If bytes are big endian and we had a paradoxical SUBREG, we must |
0f41302f | 6297 | adjust OFFSET to compensate. */ |
f76b9db2 ILT |
6298 | if (BYTES_BIG_ENDIAN |
6299 | && ! spans_byte | |
230d793d RS |
6300 | && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) |
6301 | offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); | |
230d793d RS |
6302 | |
6303 | /* If this is a constant position, we can move to the desired byte. */ | |
8999a12e | 6304 | if (pos_rtx == 0) |
230d793d RS |
6305 | { |
6306 | offset += pos / BITS_PER_UNIT; | |
d7cd794f | 6307 | pos %= GET_MODE_BITSIZE (wanted_inner_mode); |
230d793d RS |
6308 | } |
6309 | ||
f76b9db2 ILT |
6310 | if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN |
6311 | && ! spans_byte | |
d7cd794f | 6312 | && is_mode != wanted_inner_mode) |
c6b3f1f2 | 6313 | offset = (GET_MODE_SIZE (is_mode) |
d7cd794f | 6314 | - GET_MODE_SIZE (wanted_inner_mode) - offset); |
c6b3f1f2 | 6315 | |
d7cd794f | 6316 | if (offset != 0 || inner_mode != wanted_inner_mode) |
f1ec5147 | 6317 | inner = adjust_address_nv (inner, wanted_inner_mode, offset); |
230d793d RS |
6318 | } |
6319 | ||
9e74dc41 RK |
6320 | /* If INNER is not memory, we can always get it into the proper mode. If we |
6321 | are changing its mode, POS must be a constant and smaller than the size | |
6322 | of the new mode. */ | |
230d793d | 6323 | else if (GET_CODE (inner) != MEM) |
9e74dc41 RK |
6324 | { |
6325 | if (GET_MODE (inner) != wanted_inner_mode | |
6326 | && (pos_rtx != 0 | |
6327 | || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) | |
6328 | return 0; | |
6329 | ||
6330 | inner = force_to_mode (inner, wanted_inner_mode, | |
6331 | pos_rtx | |
6332 | || len + orig_pos >= HOST_BITS_PER_WIDE_INT | |
0345195a | 6333 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 RK |
6334 | : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) |
6335 | << orig_pos), | |
9e74dc41 RK |
6336 | NULL_RTX, 0); |
6337 | } | |
230d793d RS |
6338 | |
6339 | /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we | |
6340 | have to zero extend. Otherwise, we can just use a SUBREG. */ | |
8999a12e | 6341 | if (pos_rtx != 0 |
230d793d | 6342 | && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) |
0f808b6f | 6343 | { |
f1c6ba8b | 6344 | rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx); |
0f808b6f JH |
6345 | |
6346 | /* If we know that no extraneous bits are set, and that the high | |
eaec9b3d | 6347 | bit is not set, convert extraction to cheaper one - either |
0f808b6f JH |
6348 | SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these |
6349 | cases. */ | |
6350 | if (flag_expensive_optimizations | |
6351 | && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT | |
6352 | && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) | |
663522cb KH |
6353 | & ~(((unsigned HOST_WIDE_INT) |
6354 | GET_MODE_MASK (GET_MODE (pos_rtx))) | |
6355 | >> 1)) | |
0f808b6f JH |
6356 | == 0))) |
6357 | { | |
6358 | rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx); | |
6359 | ||
25ffb1f6 | 6360 | /* Prefer ZERO_EXTENSION, since it gives more information to |
0f808b6f JH |
6361 | backends. */ |
6362 | if (rtx_cost (temp1, SET) < rtx_cost (temp, SET)) | |
6363 | temp = temp1; | |
6364 | } | |
6365 | pos_rtx = temp; | |
6366 | } | |
8999a12e | 6367 | else if (pos_rtx != 0 |
230d793d RS |
6368 | && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) |
6369 | pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx); | |
6370 | ||
8999a12e RK |
6371 | /* Make POS_RTX unless we already have it and it is correct. If we don't |
6372 | have a POS_RTX but we do have an ORIG_POS_RTX, the latter must | |
0f41302f | 6373 | be a CONST_INT. */ |
8999a12e RK |
6374 | if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) |
6375 | pos_rtx = orig_pos_rtx; | |
6376 | ||
6377 | else if (pos_rtx == 0) | |
5f4f0e22 | 6378 | pos_rtx = GEN_INT (pos); |
230d793d RS |
6379 | |
6380 | /* Make the required operation. See if we can use existing rtx. */ | |
f1c6ba8b | 6381 | new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, |
5f4f0e22 | 6382 | extraction_mode, inner, GEN_INT (len), pos_rtx); |
230d793d RS |
6383 | if (! in_dest) |
6384 | new = gen_lowpart_for_combine (mode, new); | |
6385 | ||
6386 | return new; | |
6387 | } | |
6388 | \f | |
71923da7 RK |
6389 | /* See if X contains an ASHIFT of COUNT or more bits that can be commuted |
6390 | with any other operations in X. Return X without that shift if so. */ | |
6391 | ||
6392 | static rtx | |
6393 | extract_left_shift (x, count) | |
6394 | rtx x; | |
6395 | int count; | |
6396 | { | |
6397 | enum rtx_code code = GET_CODE (x); | |
6398 | enum machine_mode mode = GET_MODE (x); | |
6399 | rtx tem; | |
6400 | ||
6401 | switch (code) | |
6402 | { | |
6403 | case ASHIFT: | |
6404 | /* This is the shift itself. If it is wide enough, we will return | |
6405 | either the value being shifted if the shift count is equal to | |
6406 | COUNT or a shift for the difference. */ | |
6407 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6408 | && INTVAL (XEXP (x, 1)) >= count) | |
6409 | return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), | |
6410 | INTVAL (XEXP (x, 1)) - count); | |
6411 | break; | |
6412 | ||
6413 | case NEG: case NOT: | |
6414 | if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) | |
f1c6ba8b | 6415 | return simplify_gen_unary (code, mode, tem, mode); |
71923da7 RK |
6416 | |
6417 | break; | |
6418 | ||
6419 | case PLUS: case IOR: case XOR: case AND: | |
6420 | /* If we can safely shift this constant and we find the inner shift, | |
6421 | make a new operation. */ | |
6422 | if (GET_CODE (XEXP (x,1)) == CONST_INT | |
b729186a | 6423 | && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 |
71923da7 | 6424 | && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) |
663522cb | 6425 | return gen_binary (code, mode, tem, |
71923da7 RK |
6426 | GEN_INT (INTVAL (XEXP (x, 1)) >> count)); |
6427 | ||
6428 | break; | |
663522cb | 6429 | |
e9a25f70 JL |
6430 | default: |
6431 | break; | |
71923da7 RK |
6432 | } |
6433 | ||
6434 | return 0; | |
6435 | } | |
6436 | \f | |
230d793d RS |
6437 | /* Look at the expression rooted at X. Look for expressions |
6438 | equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. | |
6439 | Form these expressions. | |
6440 | ||
6441 | Return the new rtx, usually just X. | |
6442 | ||
8aeea6e6 | 6443 | Also, for machines like the VAX that don't have logical shift insns, |
230d793d RS |
6444 | try to convert logical to arithmetic shift operations in cases where |
6445 | they are equivalent. This undoes the canonicalizations to logical | |
6446 | shifts done elsewhere. | |
6447 | ||
6448 | We try, as much as possible, to re-use rtl expressions to save memory. | |
6449 | ||
6450 | IN_CODE says what kind of expression we are processing. Normally, it is | |
42495ca0 RK |
6451 | SET. In a memory address (inside a MEM, PLUS or minus, the latter two |
6452 | being kludges), it is MEM. When processing the arguments of a comparison | |
230d793d RS |
6453 | or a COMPARE against zero, it is COMPARE. */ |
6454 | ||
6455 | static rtx | |
6456 | make_compound_operation (x, in_code) | |
6457 | rtx x; | |
6458 | enum rtx_code in_code; | |
6459 | { | |
6460 | enum rtx_code code = GET_CODE (x); | |
6461 | enum machine_mode mode = GET_MODE (x); | |
6462 | int mode_width = GET_MODE_BITSIZE (mode); | |
71923da7 | 6463 | rtx rhs, lhs; |
230d793d | 6464 | enum rtx_code next_code; |
f24ad0e4 | 6465 | int i; |
230d793d | 6466 | rtx new = 0; |
280f58ba | 6467 | rtx tem; |
6f7d635c | 6468 | const char *fmt; |
230d793d RS |
6469 | |
6470 | /* Select the code to be used in recursive calls. Once we are inside an | |
6471 | address, we stay there. If we have a comparison, set to COMPARE, | |
6472 | but once inside, go back to our default of SET. */ | |
6473 | ||
42495ca0 | 6474 | next_code = (code == MEM || code == PLUS || code == MINUS ? MEM |
230d793d RS |
6475 | : ((code == COMPARE || GET_RTX_CLASS (code) == '<') |
6476 | && XEXP (x, 1) == const0_rtx) ? COMPARE | |
6477 | : in_code == COMPARE ? SET : in_code); | |
6478 | ||
6479 | /* Process depending on the code of this operation. If NEW is set | |
da7d8304 | 6480 | nonzero, it will be returned. */ |
230d793d RS |
6481 | |
6482 | switch (code) | |
6483 | { | |
6484 | case ASHIFT: | |
230d793d RS |
6485 | /* Convert shifts by constants into multiplications if inside |
6486 | an address. */ | |
6487 | if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT | |
5f4f0e22 | 6488 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
230d793d | 6489 | && INTVAL (XEXP (x, 1)) >= 0) |
280f58ba RK |
6490 | { |
6491 | new = make_compound_operation (XEXP (x, 0), next_code); | |
f1c6ba8b RK |
6492 | new = gen_rtx_MULT (mode, new, |
6493 | GEN_INT ((HOST_WIDE_INT) 1 | |
6494 | << INTVAL (XEXP (x, 1)))); | |
280f58ba | 6495 | } |
230d793d RS |
6496 | break; |
6497 | ||
6498 | case AND: | |
6499 | /* If the second operand is not a constant, we can't do anything | |
6500 | with it. */ | |
6501 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6502 | break; | |
6503 | ||
6504 | /* If the constant is a power of two minus one and the first operand | |
6505 | is a logical right shift, make an extraction. */ | |
6506 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
6507 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6508 | { |
6509 | new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); | |
6510 | new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, | |
6511 | 0, in_code == COMPARE); | |
6512 | } | |
dfbe1b2f | 6513 | |
230d793d RS |
6514 | /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ |
6515 | else if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6516 | && subreg_lowpart_p (XEXP (x, 0)) | |
6517 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT | |
6518 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6519 | { |
6520 | new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), | |
6521 | next_code); | |
2f99f437 | 6522 | new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, |
280f58ba RK |
6523 | XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, |
6524 | 0, in_code == COMPARE); | |
6525 | } | |
45620ed4 | 6526 | /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ |
c2f9f64e JW |
6527 | else if ((GET_CODE (XEXP (x, 0)) == XOR |
6528 | || GET_CODE (XEXP (x, 0)) == IOR) | |
6529 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT | |
6530 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT | |
6531 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
6532 | { | |
6533 | /* Apply the distributive law, and then try to make extractions. */ | |
f1c6ba8b RK |
6534 | new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, |
6535 | gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), | |
6536 | XEXP (x, 1)), | |
6537 | gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), | |
6538 | XEXP (x, 1))); | |
c2f9f64e JW |
6539 | new = make_compound_operation (new, in_code); |
6540 | } | |
a7c99304 RK |
6541 | |
6542 | /* If we are have (and (rotate X C) M) and C is larger than the number | |
6543 | of bits in M, this is an extraction. */ | |
6544 | ||
6545 | else if (GET_CODE (XEXP (x, 0)) == ROTATE | |
6546 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
6547 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 | |
6548 | && i <= INTVAL (XEXP (XEXP (x, 0), 1))) | |
280f58ba RK |
6549 | { |
6550 | new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); | |
6551 | new = make_extraction (mode, new, | |
6552 | (GET_MODE_BITSIZE (mode) | |
6553 | - INTVAL (XEXP (XEXP (x, 0), 1))), | |
6554 | NULL_RTX, i, 1, 0, in_code == COMPARE); | |
6555 | } | |
a7c99304 RK |
6556 | |
6557 | /* On machines without logical shifts, if the operand of the AND is | |
230d793d RS |
6558 | a logical shift and our mask turns off all the propagated sign |
6559 | bits, we can replace the logical shift with an arithmetic shift. */ | |
ef89d648 ZW |
6560 | else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT |
6561 | && !have_insn_for (LSHIFTRT, mode) | |
6562 | && have_insn_for (ASHIFTRT, mode) | |
230d793d RS |
6563 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT |
6564 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
5f4f0e22 CH |
6565 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT |
6566 | && mode_width <= HOST_BITS_PER_WIDE_INT) | |
230d793d | 6567 | { |
5f4f0e22 | 6568 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
6569 | |
6570 | mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); | |
6571 | if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) | |
6572 | SUBST (XEXP (x, 0), | |
f1c6ba8b RK |
6573 | gen_rtx_ASHIFTRT (mode, |
6574 | make_compound_operation | |
6575 | (XEXP (XEXP (x, 0), 0), next_code), | |
6576 | XEXP (XEXP (x, 0), 1))); | |
230d793d RS |
6577 | } |
6578 | ||
6579 | /* If the constant is one less than a power of two, this might be | |
6580 | representable by an extraction even if no shift is present. | |
6581 | If it doesn't end up being a ZERO_EXTEND, we will ignore it unless | |
6582 | we are in a COMPARE. */ | |
6583 | else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6584 | new = make_extraction (mode, |
6585 | make_compound_operation (XEXP (x, 0), | |
6586 | next_code), | |
6587 | 0, NULL_RTX, i, 1, 0, in_code == COMPARE); | |
230d793d RS |
6588 | |
6589 | /* If we are in a comparison and this is an AND with a power of two, | |
6590 | convert this into the appropriate bit extract. */ | |
6591 | else if (in_code == COMPARE | |
6592 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
280f58ba RK |
6593 | new = make_extraction (mode, |
6594 | make_compound_operation (XEXP (x, 0), | |
6595 | next_code), | |
6596 | i, NULL_RTX, 1, 1, 0, 1); | |
230d793d RS |
6597 | |
6598 | break; | |
6599 | ||
6600 | case LSHIFTRT: | |
6601 | /* If the sign bit is known to be zero, replace this with an | |
6602 | arithmetic shift. */ | |
ef89d648 ZW |
6603 | if (have_insn_for (ASHIFTRT, mode) |
6604 | && ! have_insn_for (LSHIFTRT, mode) | |
5f4f0e22 | 6605 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 6606 | && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) |
230d793d | 6607 | { |
f1c6ba8b RK |
6608 | new = gen_rtx_ASHIFTRT (mode, |
6609 | make_compound_operation (XEXP (x, 0), | |
6610 | next_code), | |
6611 | XEXP (x, 1)); | |
230d793d RS |
6612 | break; |
6613 | } | |
6614 | ||
0f41302f | 6615 | /* ... fall through ... */ |
230d793d RS |
6616 | |
6617 | case ASHIFTRT: | |
71923da7 RK |
6618 | lhs = XEXP (x, 0); |
6619 | rhs = XEXP (x, 1); | |
6620 | ||
230d793d RS |
6621 | /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, |
6622 | this is a SIGN_EXTRACT. */ | |
71923da7 RK |
6623 | if (GET_CODE (rhs) == CONST_INT |
6624 | && GET_CODE (lhs) == ASHIFT | |
6625 | && GET_CODE (XEXP (lhs, 1)) == CONST_INT | |
6626 | && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) | |
280f58ba | 6627 | { |
71923da7 | 6628 | new = make_compound_operation (XEXP (lhs, 0), next_code); |
280f58ba | 6629 | new = make_extraction (mode, new, |
71923da7 RK |
6630 | INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), |
6631 | NULL_RTX, mode_width - INTVAL (rhs), | |
d0ab8cd3 | 6632 | code == LSHIFTRT, 0, in_code == COMPARE); |
8231ad94 | 6633 | break; |
d0ab8cd3 RK |
6634 | } |
6635 | ||
71923da7 RK |
6636 | /* See if we have operations between an ASHIFTRT and an ASHIFT. |
6637 | If so, try to merge the shifts into a SIGN_EXTEND. We could | |
6638 | also do this for some cases of SIGN_EXTRACT, but it doesn't | |
6639 | seem worth the effort; the case checked for occurs on Alpha. */ | |
663522cb | 6640 | |
71923da7 RK |
6641 | if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o' |
6642 | && ! (GET_CODE (lhs) == SUBREG | |
6643 | && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o')) | |
6644 | && GET_CODE (rhs) == CONST_INT | |
6645 | && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT | |
6646 | && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) | |
6647 | new = make_extraction (mode, make_compound_operation (new, next_code), | |
6648 | 0, NULL_RTX, mode_width - INTVAL (rhs), | |
6649 | code == LSHIFTRT, 0, in_code == COMPARE); | |
663522cb | 6650 | |
230d793d | 6651 | break; |
280f58ba RK |
6652 | |
6653 | case SUBREG: | |
6654 | /* Call ourselves recursively on the inner expression. If we are | |
6655 | narrowing the object and it has a different RTL code from | |
6656 | what it originally did, do this SUBREG as a force_to_mode. */ | |
6657 | ||
0a5cbff6 | 6658 | tem = make_compound_operation (SUBREG_REG (x), in_code); |
280f58ba RK |
6659 | if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) |
6660 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) | |
6661 | && subreg_lowpart_p (x)) | |
0a5cbff6 | 6662 | { |
e8dc6d50 JH |
6663 | rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, |
6664 | NULL_RTX, 0); | |
0a5cbff6 RK |
6665 | |
6666 | /* If we have something other than a SUBREG, we might have | |
eaec9b3d | 6667 | done an expansion, so rerun ourselves. */ |
0a5cbff6 RK |
6668 | if (GET_CODE (newer) != SUBREG) |
6669 | newer = make_compound_operation (newer, in_code); | |
6670 | ||
6671 | return newer; | |
6672 | } | |
6f28d3e9 RH |
6673 | |
6674 | /* If this is a paradoxical subreg, and the new code is a sign or | |
6675 | zero extension, omit the subreg and widen the extension. If it | |
6676 | is a regular subreg, we can still get rid of the subreg by not | |
6677 | widening so much, or in fact removing the extension entirely. */ | |
6678 | if ((GET_CODE (tem) == SIGN_EXTEND | |
6679 | || GET_CODE (tem) == ZERO_EXTEND) | |
6680 | && subreg_lowpart_p (x)) | |
6681 | { | |
6682 | if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem)) | |
6683 | || (GET_MODE_SIZE (mode) > | |
6684 | GET_MODE_SIZE (GET_MODE (XEXP (tem, 0))))) | |
b10f2187 R |
6685 | { |
6686 | if (! INTEGRAL_MODE_P (mode)) | |
6687 | break; | |
6688 | tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0)); | |
6689 | } | |
6f28d3e9 RH |
6690 | else |
6691 | tem = gen_lowpart_for_combine (mode, XEXP (tem, 0)); | |
6692 | return tem; | |
6693 | } | |
e9a25f70 | 6694 | break; |
663522cb | 6695 | |
e9a25f70 JL |
6696 | default: |
6697 | break; | |
230d793d RS |
6698 | } |
6699 | ||
6700 | if (new) | |
6701 | { | |
df62f951 | 6702 | x = gen_lowpart_for_combine (mode, new); |
230d793d RS |
6703 | code = GET_CODE (x); |
6704 | } | |
6705 | ||
6706 | /* Now recursively process each operand of this operation. */ | |
6707 | fmt = GET_RTX_FORMAT (code); | |
6708 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
6709 | if (fmt[i] == 'e') | |
6710 | { | |
6711 | new = make_compound_operation (XEXP (x, i), next_code); | |
6712 | SUBST (XEXP (x, i), new); | |
6713 | } | |
6714 | ||
6715 | return x; | |
6716 | } | |
6717 | \f | |
6718 | /* Given M see if it is a value that would select a field of bits | |
663522cb KH |
6719 | within an item, but not the entire word. Return -1 if not. |
6720 | Otherwise, return the starting position of the field, where 0 is the | |
6721 | low-order bit. | |
230d793d RS |
6722 | |
6723 | *PLEN is set to the length of the field. */ | |
6724 | ||
6725 | static int | |
6726 | get_pos_from_mask (m, plen) | |
5f4f0e22 | 6727 | unsigned HOST_WIDE_INT m; |
770ae6cc | 6728 | unsigned HOST_WIDE_INT *plen; |
230d793d RS |
6729 | { |
6730 | /* Get the bit number of the first 1 bit from the right, -1 if none. */ | |
663522cb | 6731 | int pos = exact_log2 (m & -m); |
d3bc8938 | 6732 | int len; |
230d793d RS |
6733 | |
6734 | if (pos < 0) | |
6735 | return -1; | |
6736 | ||
6737 | /* Now shift off the low-order zero bits and see if we have a power of | |
6738 | two minus 1. */ | |
d3bc8938 | 6739 | len = exact_log2 ((m >> pos) + 1); |
230d793d | 6740 | |
d3bc8938 | 6741 | if (len <= 0) |
230d793d RS |
6742 | return -1; |
6743 | ||
d3bc8938 | 6744 | *plen = len; |
230d793d RS |
6745 | return pos; |
6746 | } | |
6747 | \f | |
6139ff20 RK |
6748 | /* See if X can be simplified knowing that we will only refer to it in |
6749 | MODE and will only refer to those bits that are nonzero in MASK. | |
6750 | If other bits are being computed or if masking operations are done | |
6751 | that select a superset of the bits in MASK, they can sometimes be | |
6752 | ignored. | |
6753 | ||
6754 | Return a possibly simplified expression, but always convert X to | |
6755 | MODE. If X is a CONST_INT, AND the CONST_INT with MASK. | |
dfbe1b2f | 6756 | |
da7d8304 | 6757 | Also, if REG is nonzero and X is a register equal in value to REG, |
e3d616e3 RK |
6758 | replace X with REG. |
6759 | ||
6760 | If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK | |
6761 | are all off in X. This is used when X will be complemented, by either | |
180b8e4b | 6762 | NOT, NEG, or XOR. */ |
dfbe1b2f RK |
6763 | |
6764 | static rtx | |
e3d616e3 | 6765 | force_to_mode (x, mode, mask, reg, just_select) |
dfbe1b2f RK |
6766 | rtx x; |
6767 | enum machine_mode mode; | |
6139ff20 | 6768 | unsigned HOST_WIDE_INT mask; |
dfbe1b2f | 6769 | rtx reg; |
e3d616e3 | 6770 | int just_select; |
dfbe1b2f RK |
6771 | { |
6772 | enum rtx_code code = GET_CODE (x); | |
180b8e4b | 6773 | int next_select = just_select || code == XOR || code == NOT || code == NEG; |
ef026f91 RS |
6774 | enum machine_mode op_mode; |
6775 | unsigned HOST_WIDE_INT fuller_mask, nonzero; | |
6139ff20 RK |
6776 | rtx op0, op1, temp; |
6777 | ||
132d2040 RK |
6778 | /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the |
6779 | code below will do the wrong thing since the mode of such an | |
663522cb | 6780 | expression is VOIDmode. |
be3d27d6 CI |
6781 | |
6782 | Also do nothing if X is a CLOBBER; this can happen if X was | |
6783 | the return value from a call to gen_lowpart_for_combine. */ | |
6784 | if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) | |
246e00f2 RK |
6785 | return x; |
6786 | ||
6139ff20 RK |
6787 | /* We want to perform the operation is its present mode unless we know |
6788 | that the operation is valid in MODE, in which case we do the operation | |
6789 | in MODE. */ | |
1c75dfa4 | 6790 | op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) |
ef89d648 | 6791 | && have_insn_for (code, mode)) |
ef026f91 | 6792 | ? mode : GET_MODE (x)); |
e3d616e3 | 6793 | |
aa988991 RS |
6794 | /* It is not valid to do a right-shift in a narrower mode |
6795 | than the one it came in with. */ | |
6796 | if ((code == LSHIFTRT || code == ASHIFTRT) | |
6797 | && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) | |
6798 | op_mode = GET_MODE (x); | |
ef026f91 RS |
6799 | |
6800 | /* Truncate MASK to fit OP_MODE. */ | |
6801 | if (op_mode) | |
6802 | mask &= GET_MODE_MASK (op_mode); | |
6139ff20 RK |
6803 | |
6804 | /* When we have an arithmetic operation, or a shift whose count we | |
6805 | do not know, we need to assume that all bit the up to the highest-order | |
6806 | bit in MASK will be needed. This is how we form such a mask. */ | |
ef026f91 RS |
6807 | if (op_mode) |
6808 | fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT | |
6809 | ? GET_MODE_MASK (op_mode) | |
729a2125 RK |
6810 | : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) |
6811 | - 1)); | |
ef026f91 | 6812 | else |
663522cb | 6813 | fuller_mask = ~(HOST_WIDE_INT) 0; |
ef026f91 RS |
6814 | |
6815 | /* Determine what bits of X are guaranteed to be (non)zero. */ | |
6816 | nonzero = nonzero_bits (x, mode); | |
6139ff20 RK |
6817 | |
6818 | /* If none of the bits in X are needed, return a zero. */ | |
e3d616e3 | 6819 | if (! just_select && (nonzero & mask) == 0) |
6139ff20 | 6820 | return const0_rtx; |
dfbe1b2f | 6821 | |
6139ff20 RK |
6822 | /* If X is a CONST_INT, return a new one. Do this here since the |
6823 | test below will fail. */ | |
6824 | if (GET_CODE (x) == CONST_INT) | |
2dd36f90 | 6825 | return gen_int_mode (INTVAL (x) & mask, mode); |
dfbe1b2f | 6826 | |
180b8e4b RK |
6827 | /* If X is narrower than MODE and we want all the bits in X's mode, just |
6828 | get X in the proper mode. */ | |
6829 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) | |
663522cb | 6830 | && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) |
dfbe1b2f RK |
6831 | return gen_lowpart_for_combine (mode, x); |
6832 | ||
71923da7 RK |
6833 | /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in |
6834 | MASK are already known to be zero in X, we need not do anything. */ | |
663522cb | 6835 | if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0) |
6139ff20 RK |
6836 | return x; |
6837 | ||
dfbe1b2f RK |
6838 | switch (code) |
6839 | { | |
6139ff20 RK |
6840 | case CLOBBER: |
6841 | /* If X is a (clobber (const_int)), return it since we know we are | |
0f41302f | 6842 | generating something that won't match. */ |
6139ff20 RK |
6843 | return x; |
6844 | ||
6139ff20 RK |
6845 | case USE: |
6846 | /* X is a (use (mem ..)) that was made from a bit-field extraction that | |
6847 | spanned the boundary of the MEM. If we are now masking so it is | |
6848 | within that boundary, we don't need the USE any more. */ | |
f76b9db2 | 6849 | if (! BITS_BIG_ENDIAN |
663522cb | 6850 | && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
e3d616e3 | 6851 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
f76b9db2 | 6852 | break; |
6139ff20 | 6853 | |
dfbe1b2f RK |
6854 | case SIGN_EXTEND: |
6855 | case ZERO_EXTEND: | |
6856 | case ZERO_EXTRACT: | |
6857 | case SIGN_EXTRACT: | |
6858 | x = expand_compound_operation (x); | |
6859 | if (GET_CODE (x) != code) | |
e3d616e3 | 6860 | return force_to_mode (x, mode, mask, reg, next_select); |
dfbe1b2f RK |
6861 | break; |
6862 | ||
6863 | case REG: | |
6864 | if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) | |
6865 | || rtx_equal_p (reg, get_last_value (x)))) | |
6866 | x = reg; | |
6867 | break; | |
6868 | ||
dfbe1b2f | 6869 | case SUBREG: |
6139ff20 | 6870 | if (subreg_lowpart_p (x) |
180b8e4b RK |
6871 | /* We can ignore the effect of this SUBREG if it narrows the mode or |
6872 | if the constant masks to zero all the bits the mode doesn't | |
6873 | have. */ | |
6139ff20 RK |
6874 | && ((GET_MODE_SIZE (GET_MODE (x)) |
6875 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
6139ff20 RK |
6876 | || (0 == (mask |
6877 | & GET_MODE_MASK (GET_MODE (x)) | |
663522cb | 6878 | & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) |
e3d616e3 | 6879 | return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select); |
dfbe1b2f RK |
6880 | break; |
6881 | ||
6882 | case AND: | |
6139ff20 RK |
6883 | /* If this is an AND with a constant, convert it into an AND |
6884 | whose constant is the AND of that constant with MASK. If it | |
6885 | remains an AND of MASK, delete it since it is redundant. */ | |
dfbe1b2f | 6886 | |
2ca9ae17 | 6887 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
dfbe1b2f | 6888 | { |
6139ff20 RK |
6889 | x = simplify_and_const_int (x, op_mode, XEXP (x, 0), |
6890 | mask & INTVAL (XEXP (x, 1))); | |
dfbe1b2f RK |
6891 | |
6892 | /* If X is still an AND, see if it is an AND with a mask that | |
71923da7 RK |
6893 | is just some low-order bits. If so, and it is MASK, we don't |
6894 | need it. */ | |
dfbe1b2f RK |
6895 | |
6896 | if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
d0c9db30 | 6897 | && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) |
3129af4c | 6898 | == mask)) |
dfbe1b2f | 6899 | x = XEXP (x, 0); |
d0ab8cd3 | 6900 | |
71923da7 RK |
6901 | /* If it remains an AND, try making another AND with the bits |
6902 | in the mode mask that aren't in MASK turned on. If the | |
6903 | constant in the AND is wide enough, this might make a | |
6904 | cheaper constant. */ | |
6905 | ||
6906 | if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2ca9ae17 JW |
6907 | && GET_MODE_MASK (GET_MODE (x)) != mask |
6908 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) | |
71923da7 RK |
6909 | { |
6910 | HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) | |
663522cb | 6911 | | (GET_MODE_MASK (GET_MODE (x)) & ~mask)); |
71923da7 RK |
6912 | int width = GET_MODE_BITSIZE (GET_MODE (x)); |
6913 | rtx y; | |
6914 | ||
6915 | /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative | |
6916 | number, sign extend it. */ | |
6917 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
6918 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
6919 | cval |= (HOST_WIDE_INT) -1 << width; | |
6920 | ||
6921 | y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval)); | |
6922 | if (rtx_cost (y, SET) < rtx_cost (x, SET)) | |
6923 | x = y; | |
6924 | } | |
6925 | ||
d0ab8cd3 | 6926 | break; |
dfbe1b2f RK |
6927 | } |
6928 | ||
6139ff20 | 6929 | goto binop; |
dfbe1b2f RK |
6930 | |
6931 | case PLUS: | |
6139ff20 RK |
6932 | /* In (and (plus FOO C1) M), if M is a mask that just turns off |
6933 | low-order bits (as in an alignment operation) and FOO is already | |
6934 | aligned to that boundary, mask C1 to that boundary as well. | |
6935 | This may eliminate that PLUS and, later, the AND. */ | |
9fa6d012 TG |
6936 | |
6937 | { | |
770ae6cc | 6938 | unsigned int width = GET_MODE_BITSIZE (mode); |
9fa6d012 TG |
6939 | unsigned HOST_WIDE_INT smask = mask; |
6940 | ||
6941 | /* If MODE is narrower than HOST_WIDE_INT and mask is a negative | |
6942 | number, sign extend it. */ | |
6943 | ||
6944 | if (width < HOST_BITS_PER_WIDE_INT | |
6945 | && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
6946 | smask |= (HOST_WIDE_INT) -1 << width; | |
6947 | ||
6948 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
563c12b0 RH |
6949 | && exact_log2 (- smask) >= 0 |
6950 | && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 | |
6951 | && (INTVAL (XEXP (x, 1)) & ~smask) != 0) | |
6952 | return force_to_mode (plus_constant (XEXP (x, 0), | |
6953 | (INTVAL (XEXP (x, 1)) & smask)), | |
6954 | mode, smask, reg, next_select); | |
9fa6d012 | 6955 | } |
6139ff20 | 6956 | |
0f41302f | 6957 | /* ... fall through ... */ |
6139ff20 | 6958 | |
dfbe1b2f | 6959 | case MULT: |
6139ff20 RK |
6960 | /* For PLUS, MINUS and MULT, we need any bits less significant than the |
6961 | most significant bit in MASK since carries from those bits will | |
6962 | affect the bits we are interested in. */ | |
6963 | mask = fuller_mask; | |
6964 | goto binop; | |
6965 | ||
d41638e4 RH |
6966 | case MINUS: |
6967 | /* If X is (minus C Y) where C's least set bit is larger than any bit | |
6968 | in the mask, then we may replace with (neg Y). */ | |
6969 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
0345195a RK |
6970 | && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0)) |
6971 | & -INTVAL (XEXP (x, 0)))) | |
6972 | > mask)) | |
d41638e4 | 6973 | { |
f1c6ba8b RK |
6974 | x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), |
6975 | GET_MODE (x)); | |
d41638e4 RH |
6976 | return force_to_mode (x, mode, mask, reg, next_select); |
6977 | } | |
6978 | ||
6979 | /* Similarly, if C contains every bit in the mask, then we may | |
6980 | replace with (not Y). */ | |
6981 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
0345195a RK |
6982 | && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask) |
6983 | == INTVAL (XEXP (x, 0)))) | |
d41638e4 | 6984 | { |
f1c6ba8b RK |
6985 | x = simplify_gen_unary (NOT, GET_MODE (x), |
6986 | XEXP (x, 1), GET_MODE (x)); | |
d41638e4 RH |
6987 | return force_to_mode (x, mode, mask, reg, next_select); |
6988 | } | |
6989 | ||
6990 | mask = fuller_mask; | |
6991 | goto binop; | |
6992 | ||
dfbe1b2f RK |
6993 | case IOR: |
6994 | case XOR: | |
6139ff20 RK |
6995 | /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and |
6996 | LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) | |
6997 | operation which may be a bitfield extraction. Ensure that the | |
6998 | constant we form is not wider than the mode of X. */ | |
6999 | ||
7000 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
7001 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7002 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
7003 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT | |
7004 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
7005 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) | |
7006 | + floor_log2 (INTVAL (XEXP (x, 1)))) | |
7007 | < GET_MODE_BITSIZE (GET_MODE (x))) | |
7008 | && (INTVAL (XEXP (x, 1)) | |
663522cb | 7009 | & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) |
6139ff20 RK |
7010 | { |
7011 | temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) | |
663522cb | 7012 | << INTVAL (XEXP (XEXP (x, 0), 1))); |
6139ff20 RK |
7013 | temp = gen_binary (GET_CODE (x), GET_MODE (x), |
7014 | XEXP (XEXP (x, 0), 0), temp); | |
d4d2b13f RK |
7015 | x = gen_binary (LSHIFTRT, GET_MODE (x), temp, |
7016 | XEXP (XEXP (x, 0), 1)); | |
e3d616e3 | 7017 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7018 | } |
7019 | ||
7020 | binop: | |
dfbe1b2f | 7021 | /* For most binary operations, just propagate into the operation and |
6d2f8887 | 7022 | change the mode if we have an operation of that mode. */ |
6139ff20 | 7023 | |
e3d616e3 RK |
7024 | op0 = gen_lowpart_for_combine (op_mode, |
7025 | force_to_mode (XEXP (x, 0), mode, mask, | |
7026 | reg, next_select)); | |
7027 | op1 = gen_lowpart_for_combine (op_mode, | |
7028 | force_to_mode (XEXP (x, 1), mode, mask, | |
7029 | reg, next_select)); | |
6139ff20 RK |
7030 | |
7031 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
7032 | x = gen_binary (code, op_mode, op0, op1); | |
d0ab8cd3 | 7033 | break; |
dfbe1b2f RK |
7034 | |
7035 | case ASHIFT: | |
dfbe1b2f | 7036 | /* For left shifts, do the same, but just for the first operand. |
f6785026 RK |
7037 | However, we cannot do anything with shifts where we cannot |
7038 | guarantee that the counts are smaller than the size of the mode | |
7039 | because such a count will have a different meaning in a | |
6139ff20 | 7040 | wider mode. */ |
f6785026 RK |
7041 | |
7042 | if (! (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6139ff20 | 7043 | && INTVAL (XEXP (x, 1)) >= 0 |
f6785026 RK |
7044 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) |
7045 | && ! (GET_MODE (XEXP (x, 1)) != VOIDmode | |
7046 | && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) | |
adb7a1cb | 7047 | < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) |
f6785026 | 7048 | break; |
663522cb | 7049 | |
6139ff20 RK |
7050 | /* If the shift count is a constant and we can do arithmetic in |
7051 | the mode of the shift, refine which bits we need. Otherwise, use the | |
7052 | conservative form of the mask. */ | |
7053 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7054 | && INTVAL (XEXP (x, 1)) >= 0 | |
7055 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) | |
7056 | && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) | |
7057 | mask >>= INTVAL (XEXP (x, 1)); | |
7058 | else | |
7059 | mask = fuller_mask; | |
7060 | ||
7061 | op0 = gen_lowpart_for_combine (op_mode, | |
7062 | force_to_mode (XEXP (x, 0), op_mode, | |
e3d616e3 | 7063 | mask, reg, next_select)); |
6139ff20 RK |
7064 | |
7065 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) | |
663522cb | 7066 | x = gen_binary (code, op_mode, op0, XEXP (x, 1)); |
d0ab8cd3 | 7067 | break; |
dfbe1b2f RK |
7068 | |
7069 | case LSHIFTRT: | |
1347292b JW |
7070 | /* Here we can only do something if the shift count is a constant, |
7071 | this shift constant is valid for the host, and we can do arithmetic | |
7072 | in OP_MODE. */ | |
dfbe1b2f RK |
7073 | |
7074 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1347292b | 7075 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
6139ff20 | 7076 | && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) |
d0ab8cd3 | 7077 | { |
6139ff20 | 7078 | rtx inner = XEXP (x, 0); |
402b6c2a | 7079 | unsigned HOST_WIDE_INT inner_mask; |
6139ff20 RK |
7080 | |
7081 | /* Select the mask of the bits we need for the shift operand. */ | |
402b6c2a | 7082 | inner_mask = mask << INTVAL (XEXP (x, 1)); |
d0ab8cd3 | 7083 | |
6139ff20 | 7084 | /* We can only change the mode of the shift if we can do arithmetic |
402b6c2a JW |
7085 | in the mode of the shift and INNER_MASK is no wider than the |
7086 | width of OP_MODE. */ | |
6139ff20 | 7087 | if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT |
663522cb | 7088 | || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0) |
d0ab8cd3 RK |
7089 | op_mode = GET_MODE (x); |
7090 | ||
402b6c2a | 7091 | inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select); |
6139ff20 RK |
7092 | |
7093 | if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) | |
7094 | x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); | |
d0ab8cd3 | 7095 | } |
6139ff20 RK |
7096 | |
7097 | /* If we have (and (lshiftrt FOO C1) C2) where the combination of the | |
7098 | shift and AND produces only copies of the sign bit (C2 is one less | |
7099 | than a power of two), we can do this with just a shift. */ | |
7100 | ||
7101 | if (GET_CODE (x) == LSHIFTRT | |
7102 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
cfff35c1 JW |
7103 | /* The shift puts one of the sign bit copies in the least significant |
7104 | bit. */ | |
6139ff20 RK |
7105 | && ((INTVAL (XEXP (x, 1)) |
7106 | + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) | |
7107 | >= GET_MODE_BITSIZE (GET_MODE (x))) | |
7108 | && exact_log2 (mask + 1) >= 0 | |
cfff35c1 JW |
7109 | /* Number of bits left after the shift must be more than the mask |
7110 | needs. */ | |
7111 | && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) | |
7112 | <= GET_MODE_BITSIZE (GET_MODE (x))) | |
7113 | /* Must be more sign bit copies than the mask needs. */ | |
770ae6cc | 7114 | && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) |
6139ff20 RK |
7115 | >= exact_log2 (mask + 1))) |
7116 | x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), | |
7117 | GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) | |
7118 | - exact_log2 (mask + 1))); | |
fae2db47 JW |
7119 | |
7120 | goto shiftrt; | |
d0ab8cd3 RK |
7121 | |
7122 | case ASHIFTRT: | |
6139ff20 RK |
7123 | /* If we are just looking for the sign bit, we don't need this shift at |
7124 | all, even if it has a variable count. */ | |
9bf22b75 | 7125 | if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT |
e51712db | 7126 | && (mask == ((unsigned HOST_WIDE_INT) 1 |
9bf22b75 | 7127 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) |
e3d616e3 | 7128 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
6139ff20 RK |
7129 | |
7130 | /* If this is a shift by a constant, get a mask that contains those bits | |
7131 | that are not copies of the sign bit. We then have two cases: If | |
7132 | MASK only includes those bits, this can be a logical shift, which may | |
7133 | allow simplifications. If MASK is a single-bit field not within | |
7134 | those bits, we are requesting a copy of the sign bit and hence can | |
7135 | shift the sign bit to the appropriate location. */ | |
7136 | ||
7137 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 | |
7138 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) | |
7139 | { | |
7140 | int i = -1; | |
7141 | ||
3e92902c | 7142 | /* If the considered data is wider than HOST_WIDE_INT, we can't |
b69960ac RK |
7143 | represent a mask for all its bits in a single scalar. |
7144 | But we only care about the lower bits, so calculate these. */ | |
7145 | ||
6a11342f | 7146 | if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) |
b69960ac | 7147 | { |
663522cb | 7148 | nonzero = ~(HOST_WIDE_INT) 0; |
b69960ac RK |
7149 | |
7150 | /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) | |
7151 | is the number of bits a full-width mask would have set. | |
7152 | We need only shift if these are fewer than nonzero can | |
7153 | hold. If not, we must keep all bits set in nonzero. */ | |
7154 | ||
7155 | if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) | |
7156 | < HOST_BITS_PER_WIDE_INT) | |
7157 | nonzero >>= INTVAL (XEXP (x, 1)) | |
7158 | + HOST_BITS_PER_WIDE_INT | |
7159 | - GET_MODE_BITSIZE (GET_MODE (x)) ; | |
7160 | } | |
7161 | else | |
7162 | { | |
7163 | nonzero = GET_MODE_MASK (GET_MODE (x)); | |
7164 | nonzero >>= INTVAL (XEXP (x, 1)); | |
7165 | } | |
6139ff20 | 7166 | |
663522cb | 7167 | if ((mask & ~nonzero) == 0 |
6139ff20 RK |
7168 | || (i = exact_log2 (mask)) >= 0) |
7169 | { | |
7170 | x = simplify_shift_const | |
7171 | (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0), | |
7172 | i < 0 ? INTVAL (XEXP (x, 1)) | |
7173 | : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); | |
7174 | ||
7175 | if (GET_CODE (x) != ASHIFTRT) | |
e3d616e3 | 7176 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7177 | } |
7178 | } | |
7179 | ||
e0a2f705 | 7180 | /* If MASK is 1, convert this to an LSHIFTRT. This can be done |
6139ff20 RK |
7181 | even if the shift count isn't a constant. */ |
7182 | if (mask == 1) | |
7183 | x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)); | |
7184 | ||
fae2db47 JW |
7185 | shiftrt: |
7186 | ||
7187 | /* If this is a zero- or sign-extension operation that just affects bits | |
4c002f29 RK |
7188 | we don't care about, remove it. Be sure the call above returned |
7189 | something that is still a shift. */ | |
d0ab8cd3 | 7190 | |
4c002f29 RK |
7191 | if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) |
7192 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
d0ab8cd3 | 7193 | && INTVAL (XEXP (x, 1)) >= 0 |
6139ff20 RK |
7194 | && (INTVAL (XEXP (x, 1)) |
7195 | <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) | |
d0ab8cd3 RK |
7196 | && GET_CODE (XEXP (x, 0)) == ASHIFT |
7197 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7198 | && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1))) | |
e3d616e3 RK |
7199 | return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, |
7200 | reg, next_select); | |
6139ff20 | 7201 | |
dfbe1b2f RK |
7202 | break; |
7203 | ||
6139ff20 RK |
7204 | case ROTATE: |
7205 | case ROTATERT: | |
7206 | /* If the shift count is constant and we can do computations | |
7207 | in the mode of X, compute where the bits we care about are. | |
7208 | Otherwise, we can't do anything. Don't change the mode of | |
7209 | the shift or propagate MODE into the shift, though. */ | |
7210 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7211 | && INTVAL (XEXP (x, 1)) >= 0) | |
7212 | { | |
7213 | temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, | |
7214 | GET_MODE (x), GEN_INT (mask), | |
7215 | XEXP (x, 1)); | |
7d171a1e | 7216 | if (temp && GET_CODE(temp) == CONST_INT) |
6139ff20 RK |
7217 | SUBST (XEXP (x, 0), |
7218 | force_to_mode (XEXP (x, 0), GET_MODE (x), | |
e3d616e3 | 7219 | INTVAL (temp), reg, next_select)); |
6139ff20 RK |
7220 | } |
7221 | break; | |
663522cb | 7222 | |
dfbe1b2f | 7223 | case NEG: |
180b8e4b | 7224 | /* If we just want the low-order bit, the NEG isn't needed since it |
3ef42a0c | 7225 | won't change the low-order bit. */ |
180b8e4b RK |
7226 | if (mask == 1) |
7227 | return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select); | |
7228 | ||
6139ff20 RK |
7229 | /* We need any bits less significant than the most significant bit in |
7230 | MASK since carries from those bits will affect the bits we are | |
7231 | interested in. */ | |
7232 | mask = fuller_mask; | |
7233 | goto unop; | |
7234 | ||
dfbe1b2f | 7235 | case NOT: |
6139ff20 RK |
7236 | /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the |
7237 | same as the XOR case above. Ensure that the constant we form is not | |
7238 | wider than the mode of X. */ | |
7239 | ||
7240 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
7241 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7242 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
7243 | && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) | |
7244 | < GET_MODE_BITSIZE (GET_MODE (x))) | |
7245 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) | |
7246 | { | |
7247 | temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1))); | |
7248 | temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp); | |
7249 | x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1)); | |
7250 | ||
e3d616e3 | 7251 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7252 | } |
7253 | ||
f82da7d2 JW |
7254 | /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must |
7255 | use the full mask inside the NOT. */ | |
7256 | mask = fuller_mask; | |
7257 | ||
6139ff20 | 7258 | unop: |
e3d616e3 RK |
7259 | op0 = gen_lowpart_for_combine (op_mode, |
7260 | force_to_mode (XEXP (x, 0), mode, mask, | |
7261 | reg, next_select)); | |
6139ff20 | 7262 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) |
f1c6ba8b | 7263 | x = simplify_gen_unary (code, op_mode, op0, op_mode); |
6139ff20 RK |
7264 | break; |
7265 | ||
7266 | case NE: | |
7267 | /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included | |
3aceff0d | 7268 | in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, |
1a6ec070 | 7269 | which is equal to STORE_FLAG_VALUE. */ |
663522cb | 7270 | if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx |
3aceff0d | 7271 | && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 |
1a6ec070 | 7272 | && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE) |
e3d616e3 | 7273 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
6139ff20 | 7274 | |
d0ab8cd3 RK |
7275 | break; |
7276 | ||
7277 | case IF_THEN_ELSE: | |
7278 | /* We have no way of knowing if the IF_THEN_ELSE can itself be | |
7279 | written in a narrower mode. We play it safe and do not do so. */ | |
7280 | ||
7281 | SUBST (XEXP (x, 1), | |
7282 | gen_lowpart_for_combine (GET_MODE (x), | |
7283 | force_to_mode (XEXP (x, 1), mode, | |
e3d616e3 | 7284 | mask, reg, next_select))); |
d0ab8cd3 RK |
7285 | SUBST (XEXP (x, 2), |
7286 | gen_lowpart_for_combine (GET_MODE (x), | |
7287 | force_to_mode (XEXP (x, 2), mode, | |
e3d616e3 | 7288 | mask, reg,next_select))); |
d0ab8cd3 | 7289 | break; |
663522cb | 7290 | |
e9a25f70 JL |
7291 | default: |
7292 | break; | |
dfbe1b2f RK |
7293 | } |
7294 | ||
d0ab8cd3 | 7295 | /* Ensure we return a value of the proper mode. */ |
dfbe1b2f RK |
7296 | return gen_lowpart_for_combine (mode, x); |
7297 | } | |
7298 | \f | |
abe6e52f RK |
7299 | /* Return nonzero if X is an expression that has one of two values depending on |
7300 | whether some other value is zero or nonzero. In that case, we return the | |
7301 | value that is being tested, *PTRUE is set to the value if the rtx being | |
7302 | returned has a nonzero value, and *PFALSE is set to the other alternative. | |
7303 | ||
7304 | If we return zero, we set *PTRUE and *PFALSE to X. */ | |
7305 | ||
7306 | static rtx | |
7307 | if_then_else_cond (x, ptrue, pfalse) | |
7308 | rtx x; | |
7309 | rtx *ptrue, *pfalse; | |
7310 | { | |
7311 | enum machine_mode mode = GET_MODE (x); | |
7312 | enum rtx_code code = GET_CODE (x); | |
abe6e52f RK |
7313 | rtx cond0, cond1, true0, true1, false0, false1; |
7314 | unsigned HOST_WIDE_INT nz; | |
7315 | ||
14a774a9 RK |
7316 | /* If we are comparing a value against zero, we are done. */ |
7317 | if ((code == NE || code == EQ) | |
7318 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0) | |
7319 | { | |
e8758a3a JL |
7320 | *ptrue = (code == NE) ? const_true_rtx : const0_rtx; |
7321 | *pfalse = (code == NE) ? const0_rtx : const_true_rtx; | |
14a774a9 RK |
7322 | return XEXP (x, 0); |
7323 | } | |
7324 | ||
abe6e52f RK |
7325 | /* If this is a unary operation whose operand has one of two values, apply |
7326 | our opcode to compute those values. */ | |
14a774a9 RK |
7327 | else if (GET_RTX_CLASS (code) == '1' |
7328 | && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) | |
abe6e52f | 7329 | { |
f1c6ba8b RK |
7330 | *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); |
7331 | *pfalse = simplify_gen_unary (code, mode, false0, | |
7332 | GET_MODE (XEXP (x, 0))); | |
abe6e52f RK |
7333 | return cond0; |
7334 | } | |
7335 | ||
3a19aabc | 7336 | /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would |
ddd5a7c1 | 7337 | make can't possibly match and would suppress other optimizations. */ |
3a19aabc RK |
7338 | else if (code == COMPARE) |
7339 | ; | |
7340 | ||
abe6e52f RK |
7341 | /* If this is a binary operation, see if either side has only one of two |
7342 | values. If either one does or if both do and they are conditional on | |
7343 | the same value, compute the new true and false values. */ | |
7344 | else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2' | |
7345 | || GET_RTX_CLASS (code) == '<') | |
7346 | { | |
7347 | cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); | |
7348 | cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); | |
7349 | ||
7350 | if ((cond0 != 0 || cond1 != 0) | |
7351 | && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) | |
7352 | { | |
987e845a JW |
7353 | /* If if_then_else_cond returned zero, then true/false are the |
7354 | same rtl. We must copy one of them to prevent invalid rtl | |
7355 | sharing. */ | |
7356 | if (cond0 == 0) | |
7357 | true0 = copy_rtx (true0); | |
7358 | else if (cond1 == 0) | |
7359 | true1 = copy_rtx (true1); | |
7360 | ||
abe6e52f RK |
7361 | *ptrue = gen_binary (code, mode, true0, true1); |
7362 | *pfalse = gen_binary (code, mode, false0, false1); | |
7363 | return cond0 ? cond0 : cond1; | |
7364 | } | |
9210df58 | 7365 | |
9210df58 | 7366 | /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the |
da7d8304 | 7367 | operands is zero when the other is nonzero, and vice-versa, |
0802d516 | 7368 | and STORE_FLAG_VALUE is 1 or -1. */ |
9210df58 | 7369 | |
0802d516 RK |
7370 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
7371 | && (code == PLUS || code == IOR || code == XOR || code == MINUS | |
663522cb | 7372 | || code == UMAX) |
9210df58 RK |
7373 | && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) |
7374 | { | |
7375 | rtx op0 = XEXP (XEXP (x, 0), 1); | |
7376 | rtx op1 = XEXP (XEXP (x, 1), 1); | |
7377 | ||
7378 | cond0 = XEXP (XEXP (x, 0), 0); | |
7379 | cond1 = XEXP (XEXP (x, 1), 0); | |
7380 | ||
7381 | if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' | |
7382 | && GET_RTX_CLASS (GET_CODE (cond1)) == '<' | |
9a915772 | 7383 | && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1) |
9210df58 RK |
7384 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) |
7385 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
7386 | || ((swap_condition (GET_CODE (cond0)) | |
9a915772 | 7387 | == combine_reversed_comparison_code (cond1)) |
9210df58 RK |
7388 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) |
7389 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
7390 | && ! side_effects_p (x)) | |
7391 | { | |
7392 | *ptrue = gen_binary (MULT, mode, op0, const_true_rtx); | |
663522cb KH |
7393 | *pfalse = gen_binary (MULT, mode, |
7394 | (code == MINUS | |
f1c6ba8b RK |
7395 | ? simplify_gen_unary (NEG, mode, op1, |
7396 | mode) | |
7397 | : op1), | |
9210df58 RK |
7398 | const_true_rtx); |
7399 | return cond0; | |
7400 | } | |
7401 | } | |
7402 | ||
eaec9b3d | 7403 | /* Similarly for MULT, AND and UMIN, except that for these the result |
9210df58 | 7404 | is always zero. */ |
0802d516 RK |
7405 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
7406 | && (code == MULT || code == AND || code == UMIN) | |
9210df58 RK |
7407 | && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) |
7408 | { | |
7409 | cond0 = XEXP (XEXP (x, 0), 0); | |
7410 | cond1 = XEXP (XEXP (x, 1), 0); | |
7411 | ||
7412 | if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' | |
7413 | && GET_RTX_CLASS (GET_CODE (cond1)) == '<' | |
9a915772 | 7414 | && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1) |
9210df58 RK |
7415 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) |
7416 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
7417 | || ((swap_condition (GET_CODE (cond0)) | |
9a915772 | 7418 | == combine_reversed_comparison_code (cond1)) |
9210df58 RK |
7419 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) |
7420 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
7421 | && ! side_effects_p (x)) | |
7422 | { | |
7423 | *ptrue = *pfalse = const0_rtx; | |
7424 | return cond0; | |
7425 | } | |
7426 | } | |
abe6e52f RK |
7427 | } |
7428 | ||
7429 | else if (code == IF_THEN_ELSE) | |
7430 | { | |
7431 | /* If we have IF_THEN_ELSE already, extract the condition and | |
7432 | canonicalize it if it is NE or EQ. */ | |
7433 | cond0 = XEXP (x, 0); | |
7434 | *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); | |
7435 | if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) | |
7436 | return XEXP (cond0, 0); | |
7437 | else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) | |
7438 | { | |
7439 | *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); | |
7440 | return XEXP (cond0, 0); | |
7441 | } | |
7442 | else | |
7443 | return cond0; | |
7444 | } | |
7445 | ||
0631e0bf JH |
7446 | /* If X is a SUBREG, we can narrow both the true and false values |
7447 | if the inner expression, if there is a condition. */ | |
7448 | else if (code == SUBREG | |
abe6e52f RK |
7449 | && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), |
7450 | &true0, &false0))) | |
7451 | { | |
0631e0bf JH |
7452 | *ptrue = simplify_gen_subreg (mode, true0, |
7453 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
7454 | *pfalse = simplify_gen_subreg (mode, false0, | |
7455 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
abe6e52f | 7456 | |
abe6e52f RK |
7457 | return cond0; |
7458 | } | |
7459 | ||
7460 | /* If X is a constant, this isn't special and will cause confusions | |
7461 | if we treat it as such. Likewise if it is equivalent to a constant. */ | |
7462 | else if (CONSTANT_P (x) | |
7463 | || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) | |
7464 | ; | |
7465 | ||
1f3f36d1 RH |
7466 | /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that |
7467 | will be least confusing to the rest of the compiler. */ | |
7468 | else if (mode == BImode) | |
7469 | { | |
7470 | *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; | |
7471 | return x; | |
7472 | } | |
7473 | ||
663522cb | 7474 | /* If X is known to be either 0 or -1, those are the true and |
abe6e52f | 7475 | false values when testing X. */ |
49219895 JH |
7476 | else if (x == constm1_rtx || x == const0_rtx |
7477 | || (mode != VOIDmode | |
7478 | && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode))) | |
abe6e52f RK |
7479 | { |
7480 | *ptrue = constm1_rtx, *pfalse = const0_rtx; | |
7481 | return x; | |
7482 | } | |
7483 | ||
7484 | /* Likewise for 0 or a single bit. */ | |
49219895 JH |
7485 | else if (mode != VOIDmode |
7486 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
7487 | && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) | |
abe6e52f | 7488 | { |
578fc63d | 7489 | *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; |
abe6e52f RK |
7490 | return x; |
7491 | } | |
7492 | ||
7493 | /* Otherwise fail; show no condition with true and false values the same. */ | |
7494 | *ptrue = *pfalse = x; | |
7495 | return 0; | |
7496 | } | |
7497 | \f | |
1a26b032 RK |
7498 | /* Return the value of expression X given the fact that condition COND |
7499 | is known to be true when applied to REG as its first operand and VAL | |
7500 | as its second. X is known to not be shared and so can be modified in | |
7501 | place. | |
7502 | ||
7503 | We only handle the simplest cases, and specifically those cases that | |
7504 | arise with IF_THEN_ELSE expressions. */ | |
7505 | ||
7506 | static rtx | |
7507 | known_cond (x, cond, reg, val) | |
7508 | rtx x; | |
7509 | enum rtx_code cond; | |
7510 | rtx reg, val; | |
7511 | { | |
7512 | enum rtx_code code = GET_CODE (x); | |
f24ad0e4 | 7513 | rtx temp; |
6f7d635c | 7514 | const char *fmt; |
1a26b032 RK |
7515 | int i, j; |
7516 | ||
7517 | if (side_effects_p (x)) | |
7518 | return x; | |
7519 | ||
805f1694 JL |
7520 | /* If either operand of the condition is a floating point value, |
7521 | then we have to avoid collapsing an EQ comparison. */ | |
7522 | if (cond == EQ | |
7523 | && rtx_equal_p (x, reg) | |
7524 | && ! FLOAT_MODE_P (GET_MODE (x)) | |
7525 | && ! FLOAT_MODE_P (GET_MODE (val))) | |
69bc0a1f | 7526 | return val; |
805f1694 | 7527 | |
69bc0a1f | 7528 | if (cond == UNEQ && rtx_equal_p (x, reg)) |
1a26b032 RK |
7529 | return val; |
7530 | ||
7531 | /* If X is (abs REG) and we know something about REG's relationship | |
7532 | with zero, we may be able to simplify this. */ | |
7533 | ||
7534 | if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) | |
7535 | switch (cond) | |
7536 | { | |
7537 | case GE: case GT: case EQ: | |
7538 | return XEXP (x, 0); | |
7539 | case LT: case LE: | |
f1c6ba8b RK |
7540 | return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), |
7541 | XEXP (x, 0), | |
7542 | GET_MODE (XEXP (x, 0))); | |
e9a25f70 JL |
7543 | default: |
7544 | break; | |
1a26b032 RK |
7545 | } |
7546 | ||
7547 | /* The only other cases we handle are MIN, MAX, and comparisons if the | |
7548 | operands are the same as REG and VAL. */ | |
7549 | ||
7550 | else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') | |
7551 | { | |
7552 | if (rtx_equal_p (XEXP (x, 0), val)) | |
7553 | cond = swap_condition (cond), temp = val, val = reg, reg = temp; | |
7554 | ||
7555 | if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) | |
7556 | { | |
7557 | if (GET_RTX_CLASS (code) == '<') | |
1eb8759b RH |
7558 | { |
7559 | if (comparison_dominates_p (cond, code)) | |
7560 | return const_true_rtx; | |
1a26b032 | 7561 | |
9a915772 | 7562 | code = combine_reversed_comparison_code (x); |
1eb8759b RH |
7563 | if (code != UNKNOWN |
7564 | && comparison_dominates_p (cond, code)) | |
7565 | return const0_rtx; | |
7566 | else | |
7567 | return x; | |
7568 | } | |
1a26b032 RK |
7569 | else if (code == SMAX || code == SMIN |
7570 | || code == UMIN || code == UMAX) | |
7571 | { | |
7572 | int unsignedp = (code == UMIN || code == UMAX); | |
7573 | ||
ac4cdf40 JE |
7574 | /* Do not reverse the condition when it is NE or EQ. |
7575 | This is because we cannot conclude anything about | |
7576 | the value of 'SMAX (x, y)' when x is not equal to y, | |
23190837 | 7577 | but we can when x equals y. */ |
ac4cdf40 JE |
7578 | if ((code == SMAX || code == UMAX) |
7579 | && ! (cond == EQ || cond == NE)) | |
1a26b032 RK |
7580 | cond = reverse_condition (cond); |
7581 | ||
7582 | switch (cond) | |
7583 | { | |
7584 | case GE: case GT: | |
7585 | return unsignedp ? x : XEXP (x, 1); | |
7586 | case LE: case LT: | |
7587 | return unsignedp ? x : XEXP (x, 0); | |
7588 | case GEU: case GTU: | |
7589 | return unsignedp ? XEXP (x, 1) : x; | |
7590 | case LEU: case LTU: | |
7591 | return unsignedp ? XEXP (x, 0) : x; | |
e9a25f70 JL |
7592 | default: |
7593 | break; | |
1a26b032 RK |
7594 | } |
7595 | } | |
7596 | } | |
7597 | } | |
9a360704 AO |
7598 | else if (code == SUBREG) |
7599 | { | |
7600 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); | |
7601 | rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val); | |
7602 | ||
7603 | if (SUBREG_REG (x) != r) | |
7604 | { | |
7605 | /* We must simplify subreg here, before we lose track of the | |
7606 | original inner_mode. */ | |
7607 | new = simplify_subreg (GET_MODE (x), r, | |
7608 | inner_mode, SUBREG_BYTE (x)); | |
7609 | if (new) | |
7610 | return new; | |
7611 | else | |
7612 | SUBST (SUBREG_REG (x), r); | |
7613 | } | |
7614 | ||
7615 | return x; | |
7616 | } | |
4161da12 AO |
7617 | /* We don't have to handle SIGN_EXTEND here, because even in the |
7618 | case of replacing something with a modeless CONST_INT, a | |
7619 | CONST_INT is already (supposed to be) a valid sign extension for | |
7620 | its narrower mode, which implies it's already properly | |
7621 | sign-extended for the wider mode. Now, for ZERO_EXTEND, the | |
7622 | story is different. */ | |
7623 | else if (code == ZERO_EXTEND) | |
7624 | { | |
7625 | enum machine_mode inner_mode = GET_MODE (XEXP (x, 0)); | |
7626 | rtx new, r = known_cond (XEXP (x, 0), cond, reg, val); | |
7627 | ||
7628 | if (XEXP (x, 0) != r) | |
7629 | { | |
7630 | /* We must simplify the zero_extend here, before we lose | |
7631 | track of the original inner_mode. */ | |
7632 | new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
7633 | r, inner_mode); | |
7634 | if (new) | |
7635 | return new; | |
7636 | else | |
7637 | SUBST (XEXP (x, 0), r); | |
7638 | } | |
7639 | ||
7640 | return x; | |
7641 | } | |
1a26b032 RK |
7642 | |
7643 | fmt = GET_RTX_FORMAT (code); | |
7644 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7645 | { | |
7646 | if (fmt[i] == 'e') | |
7647 | SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); | |
7648 | else if (fmt[i] == 'E') | |
7649 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7650 | SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), | |
7651 | cond, reg, val)); | |
7652 | } | |
7653 | ||
7654 | return x; | |
7655 | } | |
7656 | \f | |
e11fa86f RK |
7657 | /* See if X and Y are equal for the purposes of seeing if we can rewrite an |
7658 | assignment as a field assignment. */ | |
7659 | ||
7660 | static int | |
7661 | rtx_equal_for_field_assignment_p (x, y) | |
7662 | rtx x; | |
7663 | rtx y; | |
7664 | { | |
e11fa86f RK |
7665 | if (x == y || rtx_equal_p (x, y)) |
7666 | return 1; | |
7667 | ||
7668 | if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) | |
7669 | return 0; | |
7670 | ||
7671 | /* Check for a paradoxical SUBREG of a MEM compared with the MEM. | |
7672 | Note that all SUBREGs of MEM are paradoxical; otherwise they | |
7673 | would have been rewritten. */ | |
7674 | if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG | |
7675 | && GET_CODE (SUBREG_REG (y)) == MEM | |
7676 | && rtx_equal_p (SUBREG_REG (y), | |
7677 | gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x))) | |
7678 | return 1; | |
7679 | ||
7680 | if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG | |
7681 | && GET_CODE (SUBREG_REG (x)) == MEM | |
7682 | && rtx_equal_p (SUBREG_REG (x), | |
7683 | gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y))) | |
7684 | return 1; | |
7685 | ||
9ec36da5 JL |
7686 | /* We used to see if get_last_value of X and Y were the same but that's |
7687 | not correct. In one direction, we'll cause the assignment to have | |
7688 | the wrong destination and in the case, we'll import a register into this | |
7689 | insn that might have already have been dead. So fail if none of the | |
7690 | above cases are true. */ | |
7691 | return 0; | |
e11fa86f RK |
7692 | } |
7693 | \f | |
230d793d RS |
7694 | /* See if X, a SET operation, can be rewritten as a bit-field assignment. |
7695 | Return that assignment if so. | |
7696 | ||
7697 | We only handle the most common cases. */ | |
7698 | ||
7699 | static rtx | |
7700 | make_field_assignment (x) | |
7701 | rtx x; | |
7702 | { | |
7703 | rtx dest = SET_DEST (x); | |
7704 | rtx src = SET_SRC (x); | |
dfbe1b2f | 7705 | rtx assign; |
e11fa86f | 7706 | rtx rhs, lhs; |
5f4f0e22 | 7707 | HOST_WIDE_INT c1; |
770ae6cc RK |
7708 | HOST_WIDE_INT pos; |
7709 | unsigned HOST_WIDE_INT len; | |
dfbe1b2f RK |
7710 | rtx other; |
7711 | enum machine_mode mode; | |
230d793d RS |
7712 | |
7713 | /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is | |
7714 | a clear of a one-bit field. We will have changed it to | |
7715 | (and (rotate (const_int -2) POS) DEST), so check for that. Also check | |
7716 | for a SUBREG. */ | |
7717 | ||
7718 | if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE | |
7719 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT | |
7720 | && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 | |
e11fa86f | 7721 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) |
230d793d | 7722 | { |
8999a12e | 7723 | assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), |
230d793d | 7724 | 1, 1, 1, 0); |
76184def | 7725 | if (assign != 0) |
38a448ca | 7726 | return gen_rtx_SET (VOIDmode, assign, const0_rtx); |
76184def | 7727 | return x; |
230d793d RS |
7728 | } |
7729 | ||
7730 | else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG | |
7731 | && subreg_lowpart_p (XEXP (src, 0)) | |
663522cb | 7732 | && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) |
230d793d RS |
7733 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) |
7734 | && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE | |
7735 | && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 | |
e11fa86f | 7736 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) |
230d793d | 7737 | { |
8999a12e | 7738 | assign = make_extraction (VOIDmode, dest, 0, |
230d793d RS |
7739 | XEXP (SUBREG_REG (XEXP (src, 0)), 1), |
7740 | 1, 1, 1, 0); | |
76184def | 7741 | if (assign != 0) |
38a448ca | 7742 | return gen_rtx_SET (VOIDmode, assign, const0_rtx); |
76184def | 7743 | return x; |
230d793d RS |
7744 | } |
7745 | ||
9dd11dcb | 7746 | /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a |
230d793d RS |
7747 | one-bit field. */ |
7748 | else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT | |
7749 | && XEXP (XEXP (src, 0), 0) == const1_rtx | |
e11fa86f | 7750 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) |
230d793d | 7751 | { |
8999a12e | 7752 | assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), |
230d793d | 7753 | 1, 1, 1, 0); |
76184def | 7754 | if (assign != 0) |
38a448ca | 7755 | return gen_rtx_SET (VOIDmode, assign, const1_rtx); |
76184def | 7756 | return x; |
230d793d RS |
7757 | } |
7758 | ||
dfbe1b2f | 7759 | /* The other case we handle is assignments into a constant-position |
9dd11dcb | 7760 | field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents |
dfbe1b2f RK |
7761 | a mask that has all one bits except for a group of zero bits and |
7762 | OTHER is known to have zeros where C1 has ones, this is such an | |
7763 | assignment. Compute the position and length from C1. Shift OTHER | |
7764 | to the appropriate position, force it to the required mode, and | |
7765 | make the extraction. Check for the AND in both operands. */ | |
7766 | ||
9dd11dcb | 7767 | if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) |
e11fa86f RK |
7768 | return x; |
7769 | ||
7770 | rhs = expand_compound_operation (XEXP (src, 0)); | |
7771 | lhs = expand_compound_operation (XEXP (src, 1)); | |
7772 | ||
7773 | if (GET_CODE (rhs) == AND | |
7774 | && GET_CODE (XEXP (rhs, 1)) == CONST_INT | |
7775 | && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) | |
7776 | c1 = INTVAL (XEXP (rhs, 1)), other = lhs; | |
7777 | else if (GET_CODE (lhs) == AND | |
7778 | && GET_CODE (XEXP (lhs, 1)) == CONST_INT | |
7779 | && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) | |
7780 | c1 = INTVAL (XEXP (lhs, 1)), other = rhs; | |
dfbe1b2f RK |
7781 | else |
7782 | return x; | |
230d793d | 7783 | |
663522cb | 7784 | pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); |
dfbe1b2f | 7785 | if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) |
e5e809f4 JL |
7786 | || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT |
7787 | || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) | |
dfbe1b2f | 7788 | return x; |
230d793d | 7789 | |
5f4f0e22 | 7790 | assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); |
76184def DE |
7791 | if (assign == 0) |
7792 | return x; | |
230d793d | 7793 | |
dfbe1b2f RK |
7794 | /* The mode to use for the source is the mode of the assignment, or of |
7795 | what is inside a possible STRICT_LOW_PART. */ | |
663522cb | 7796 | mode = (GET_CODE (assign) == STRICT_LOW_PART |
dfbe1b2f | 7797 | ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); |
230d793d | 7798 | |
dfbe1b2f RK |
7799 | /* Shift OTHER right POS places and make it the source, restricting it |
7800 | to the proper length and mode. */ | |
230d793d | 7801 | |
5f4f0e22 CH |
7802 | src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, |
7803 | GET_MODE (src), other, pos), | |
6139ff20 RK |
7804 | mode, |
7805 | GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT | |
0345195a | 7806 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 | 7807 | : ((unsigned HOST_WIDE_INT) 1 << len) - 1, |
e3d616e3 | 7808 | dest, 0); |
230d793d | 7809 | |
f1c6ba8b | 7810 | return gen_rtx_SET (VOIDmode, assign, src); |
230d793d RS |
7811 | } |
7812 | \f | |
7813 | /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) | |
7814 | if so. */ | |
7815 | ||
7816 | static rtx | |
7817 | apply_distributive_law (x) | |
7818 | rtx x; | |
7819 | { | |
7820 | enum rtx_code code = GET_CODE (x); | |
7821 | rtx lhs, rhs, other; | |
7822 | rtx tem; | |
7823 | enum rtx_code inner_code; | |
7824 | ||
d8a8a4da RS |
7825 | /* Distributivity is not true for floating point. |
7826 | It can change the value. So don't do it. | |
7827 | -- rms and moshier@world.std.com. */ | |
3ad2180a | 7828 | if (FLOAT_MODE_P (GET_MODE (x))) |
d8a8a4da RS |
7829 | return x; |
7830 | ||
230d793d RS |
7831 | /* The outer operation can only be one of the following: */ |
7832 | if (code != IOR && code != AND && code != XOR | |
7833 | && code != PLUS && code != MINUS) | |
7834 | return x; | |
7835 | ||
7836 | lhs = XEXP (x, 0), rhs = XEXP (x, 1); | |
7837 | ||
0f41302f MS |
7838 | /* If either operand is a primitive we can't do anything, so get out |
7839 | fast. */ | |
230d793d | 7840 | if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o' |
dfbe1b2f | 7841 | || GET_RTX_CLASS (GET_CODE (rhs)) == 'o') |
230d793d RS |
7842 | return x; |
7843 | ||
7844 | lhs = expand_compound_operation (lhs); | |
7845 | rhs = expand_compound_operation (rhs); | |
7846 | inner_code = GET_CODE (lhs); | |
7847 | if (inner_code != GET_CODE (rhs)) | |
7848 | return x; | |
7849 | ||
7850 | /* See if the inner and outer operations distribute. */ | |
7851 | switch (inner_code) | |
7852 | { | |
7853 | case LSHIFTRT: | |
7854 | case ASHIFTRT: | |
7855 | case AND: | |
7856 | case IOR: | |
7857 | /* These all distribute except over PLUS. */ | |
7858 | if (code == PLUS || code == MINUS) | |
7859 | return x; | |
7860 | break; | |
7861 | ||
7862 | case MULT: | |
7863 | if (code != PLUS && code != MINUS) | |
7864 | return x; | |
7865 | break; | |
7866 | ||
7867 | case ASHIFT: | |
45620ed4 | 7868 | /* This is also a multiply, so it distributes over everything. */ |
230d793d RS |
7869 | break; |
7870 | ||
7871 | case SUBREG: | |
dfbe1b2f | 7872 | /* Non-paradoxical SUBREGs distributes over all operations, provided |
ddef6bc7 | 7873 | the inner modes and byte offsets are the same, this is an extraction |
2b4bd1bc JW |
7874 | of a low-order part, we don't convert an fp operation to int or |
7875 | vice versa, and we would not be converting a single-word | |
dfbe1b2f | 7876 | operation into a multi-word operation. The latter test is not |
2b4bd1bc | 7877 | required, but it prevents generating unneeded multi-word operations. |
dfbe1b2f RK |
7878 | Some of the previous tests are redundant given the latter test, but |
7879 | are retained because they are required for correctness. | |
7880 | ||
7881 | We produce the result slightly differently in this case. */ | |
7882 | ||
7883 | if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) | |
ddef6bc7 | 7884 | || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs) |
dfbe1b2f | 7885 | || ! subreg_lowpart_p (lhs) |
2b4bd1bc JW |
7886 | || (GET_MODE_CLASS (GET_MODE (lhs)) |
7887 | != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) | |
dfbe1b2f | 7888 | || (GET_MODE_SIZE (GET_MODE (lhs)) |
8af24e26 | 7889 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) |
dfbe1b2f | 7890 | || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) |
230d793d RS |
7891 | return x; |
7892 | ||
7893 | tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)), | |
7894 | SUBREG_REG (lhs), SUBREG_REG (rhs)); | |
7895 | return gen_lowpart_for_combine (GET_MODE (x), tem); | |
7896 | ||
7897 | default: | |
7898 | return x; | |
7899 | } | |
7900 | ||
7901 | /* Set LHS and RHS to the inner operands (A and B in the example | |
7902 | above) and set OTHER to the common operand (C in the example). | |
7903 | These is only one way to do this unless the inner operation is | |
7904 | commutative. */ | |
7905 | if (GET_RTX_CLASS (inner_code) == 'c' | |
7906 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) | |
7907 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); | |
7908 | else if (GET_RTX_CLASS (inner_code) == 'c' | |
7909 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) | |
7910 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); | |
7911 | else if (GET_RTX_CLASS (inner_code) == 'c' | |
7912 | && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) | |
7913 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); | |
7914 | else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) | |
7915 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); | |
7916 | else | |
7917 | return x; | |
7918 | ||
7919 | /* Form the new inner operation, seeing if it simplifies first. */ | |
7920 | tem = gen_binary (code, GET_MODE (x), lhs, rhs); | |
7921 | ||
7922 | /* There is one exception to the general way of distributing: | |
7923 | (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */ | |
7924 | if (code == XOR && inner_code == IOR) | |
7925 | { | |
7926 | inner_code = AND; | |
f1c6ba8b | 7927 | other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); |
230d793d RS |
7928 | } |
7929 | ||
7930 | /* We may be able to continuing distributing the result, so call | |
7931 | ourselves recursively on the inner operation before forming the | |
7932 | outer operation, which we return. */ | |
7933 | return gen_binary (inner_code, GET_MODE (x), | |
7934 | apply_distributive_law (tem), other); | |
7935 | } | |
7936 | \f | |
7937 | /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done | |
7938 | in MODE. | |
7939 | ||
7940 | Return an equivalent form, if different from X. Otherwise, return X. If | |
7941 | X is zero, we are to always construct the equivalent form. */ | |
7942 | ||
7943 | static rtx | |
7944 | simplify_and_const_int (x, mode, varop, constop) | |
7945 | rtx x; | |
7946 | enum machine_mode mode; | |
7947 | rtx varop; | |
5f4f0e22 | 7948 | unsigned HOST_WIDE_INT constop; |
230d793d | 7949 | { |
951553af | 7950 | unsigned HOST_WIDE_INT nonzero; |
42301240 | 7951 | int i; |
230d793d | 7952 | |
6139ff20 | 7953 | /* Simplify VAROP knowing that we will be only looking at some of the |
8bc52806 JL |
7954 | bits in it. |
7955 | ||
7956 | Note by passing in CONSTOP, we guarantee that the bits not set in | |
7957 | CONSTOP are not significant and will never be examined. We must | |
7958 | ensure that is the case by explicitly masking out those bits | |
7959 | before returning. */ | |
e3d616e3 | 7960 | varop = force_to_mode (varop, mode, constop, NULL_RTX, 0); |
230d793d | 7961 | |
8bc52806 JL |
7962 | /* If VAROP is a CLOBBER, we will fail so return it. */ |
7963 | if (GET_CODE (varop) == CLOBBER) | |
6139ff20 | 7964 | return varop; |
230d793d | 7965 | |
8bc52806 JL |
7966 | /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP |
7967 | to VAROP and return the new constant. */ | |
7968 | if (GET_CODE (varop) == CONST_INT) | |
7969 | return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode)); | |
7970 | ||
fc06d7aa RK |
7971 | /* See what bits may be nonzero in VAROP. Unlike the general case of |
7972 | a call to nonzero_bits, here we don't care about bits outside | |
7973 | MODE. */ | |
7974 | ||
7975 | nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); | |
9fa6d012 | 7976 | |
230d793d | 7977 | /* Turn off all bits in the constant that are known to already be zero. |
951553af | 7978 | Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS |
230d793d RS |
7979 | which is tested below. */ |
7980 | ||
951553af | 7981 | constop &= nonzero; |
230d793d RS |
7982 | |
7983 | /* If we don't have any bits left, return zero. */ | |
7984 | if (constop == 0) | |
7985 | return const0_rtx; | |
7986 | ||
42301240 | 7987 | /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is |
e0a2f705 | 7988 | a power of two, we can replace this with an ASHIFT. */ |
42301240 RK |
7989 | if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 |
7990 | && (i = exact_log2 (constop)) >= 0) | |
7991 | return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); | |
663522cb | 7992 | |
6139ff20 RK |
7993 | /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR |
7994 | or XOR, then try to apply the distributive law. This may eliminate | |
7995 | operations if either branch can be simplified because of the AND. | |
7996 | It may also make some cases more complex, but those cases probably | |
7997 | won't match a pattern either with or without this. */ | |
7998 | ||
7999 | if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) | |
8000 | return | |
8001 | gen_lowpart_for_combine | |
8002 | (mode, | |
8003 | apply_distributive_law | |
8004 | (gen_binary (GET_CODE (varop), GET_MODE (varop), | |
8005 | simplify_and_const_int (NULL_RTX, GET_MODE (varop), | |
8006 | XEXP (varop, 0), constop), | |
8007 | simplify_and_const_int (NULL_RTX, GET_MODE (varop), | |
8008 | XEXP (varop, 1), constop)))); | |
8009 | ||
8deb7514 RH |
8010 | /* If VAROP is PLUS, and the constant is a mask of low bite, distribute |
8011 | the AND and see if one of the operands simplifies to zero. If so, we | |
8012 | may eliminate it. */ | |
8013 | ||
8014 | if (GET_CODE (varop) == PLUS | |
8015 | && exact_log2 (constop + 1) >= 0) | |
8016 | { | |
8017 | rtx o0, o1; | |
8018 | ||
8019 | o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); | |
8020 | o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); | |
8021 | if (o0 == const0_rtx) | |
8022 | return o1; | |
8023 | if (o1 == const0_rtx) | |
8024 | return o0; | |
8025 | } | |
8026 | ||
230d793d RS |
8027 | /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG |
8028 | if we already had one (just check for the simplest cases). */ | |
8029 | if (x && GET_CODE (XEXP (x, 0)) == SUBREG | |
8030 | && GET_MODE (XEXP (x, 0)) == mode | |
8031 | && SUBREG_REG (XEXP (x, 0)) == varop) | |
8032 | varop = XEXP (x, 0); | |
8033 | else | |
8034 | varop = gen_lowpart_for_combine (mode, varop); | |
8035 | ||
0f41302f | 8036 | /* If we can't make the SUBREG, try to return what we were given. */ |
230d793d RS |
8037 | if (GET_CODE (varop) == CLOBBER) |
8038 | return x ? x : varop; | |
8039 | ||
8040 | /* If we are only masking insignificant bits, return VAROP. */ | |
951553af | 8041 | if (constop == nonzero) |
230d793d | 8042 | x = varop; |
230d793d RS |
8043 | else |
8044 | { | |
d0c9db30 | 8045 | /* Otherwise, return an AND. */ |
3b5708e7 | 8046 | constop = trunc_int_for_mode (constop, mode); |
d0c9db30 AM |
8047 | /* See how much, if any, of X we can use. */ |
8048 | if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) | |
8049 | x = gen_binary (AND, mode, varop, GEN_INT (constop)); | |
230d793d | 8050 | |
d0c9db30 AM |
8051 | else |
8052 | { | |
8053 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
8054 | || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop) | |
8055 | SUBST (XEXP (x, 1), GEN_INT (constop)); | |
8056 | ||
8057 | SUBST (XEXP (x, 0), varop); | |
8058 | } | |
230d793d RS |
8059 | } |
8060 | ||
8061 | return x; | |
8062 | } | |
8063 | \f | |
b3728b0e JW |
8064 | /* We let num_sign_bit_copies recur into nonzero_bits as that is useful. |
8065 | We don't let nonzero_bits recur into num_sign_bit_copies, because that | |
8066 | is less useful. We can't allow both, because that results in exponential | |
956d6950 | 8067 | run time recursion. There is a nullstone testcase that triggered |
b3728b0e JW |
8068 | this. This macro avoids accidental uses of num_sign_bit_copies. */ |
8069 | #define num_sign_bit_copies() | |
8070 | ||
da7d8304 | 8071 | /* Given an expression, X, compute which bits in X can be nonzero. |
230d793d RS |
8072 | We don't care about bits outside of those defined in MODE. |
8073 | ||
8074 | For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is | |
8075 | a shift, AND, or zero_extract, we can do better. */ | |
8076 | ||
5f4f0e22 | 8077 | static unsigned HOST_WIDE_INT |
951553af | 8078 | nonzero_bits (x, mode) |
230d793d RS |
8079 | rtx x; |
8080 | enum machine_mode mode; | |
8081 | { | |
951553af RK |
8082 | unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); |
8083 | unsigned HOST_WIDE_INT inner_nz; | |
230d793d | 8084 | enum rtx_code code; |
770ae6cc | 8085 | unsigned int mode_width = GET_MODE_BITSIZE (mode); |
230d793d RS |
8086 | rtx tem; |
8087 | ||
1c75dfa4 RK |
8088 | /* For floating-point values, assume all bits are needed. */ |
8089 | if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode)) | |
8090 | return nonzero; | |
8091 | ||
230d793d RS |
8092 | /* If X is wider than MODE, use its mode instead. */ |
8093 | if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width) | |
8094 | { | |
8095 | mode = GET_MODE (x); | |
951553af | 8096 | nonzero = GET_MODE_MASK (mode); |
230d793d RS |
8097 | mode_width = GET_MODE_BITSIZE (mode); |
8098 | } | |
8099 | ||
5f4f0e22 | 8100 | if (mode_width > HOST_BITS_PER_WIDE_INT) |
230d793d RS |
8101 | /* Our only callers in this case look for single bit values. So |
8102 | just return the mode mask. Those tests will then be false. */ | |
951553af | 8103 | return nonzero; |
230d793d | 8104 | |
8baf60bb | 8105 | #ifndef WORD_REGISTER_OPERATIONS |
c6965c0f | 8106 | /* If MODE is wider than X, but both are a single word for both the host |
663522cb | 8107 | and target machines, we can compute this from which bits of the |
0840fd91 RK |
8108 | object might be nonzero in its own mode, taking into account the fact |
8109 | that on many CISC machines, accessing an object in a wider mode | |
8110 | causes the high-order bits to become undefined. So they are | |
8111 | not known to be zero. */ | |
8112 | ||
8113 | if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode | |
8114 | && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD | |
8115 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
c6965c0f | 8116 | && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x))) |
0840fd91 RK |
8117 | { |
8118 | nonzero &= nonzero_bits (x, GET_MODE (x)); | |
663522cb | 8119 | nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)); |
0840fd91 RK |
8120 | return nonzero; |
8121 | } | |
8122 | #endif | |
8123 | ||
230d793d RS |
8124 | code = GET_CODE (x); |
8125 | switch (code) | |
8126 | { | |
8127 | case REG: | |
6dd12198 | 8128 | #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) |
320dd7a7 RK |
8129 | /* If pointers extend unsigned and this is a pointer in Pmode, say that |
8130 | all the bits above ptr_mode are known to be zero. */ | |
8131 | if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode | |
3502dc9c | 8132 | && REG_POINTER (x)) |
320dd7a7 RK |
8133 | nonzero &= GET_MODE_MASK (ptr_mode); |
8134 | #endif | |
8135 | ||
563c12b0 | 8136 | /* Include declared information about alignment of pointers. */ |
ebbb0a63 RH |
8137 | /* ??? We don't properly preserve REG_POINTER changes across |
8138 | pointer-to-integer casts, so we can't trust it except for | |
8139 | things that we know must be pointers. See execute/960116-1.c. */ | |
8140 | if ((x == stack_pointer_rtx | |
8141 | || x == frame_pointer_rtx | |
8142 | || x == arg_pointer_rtx) | |
8143 | && REGNO_POINTER_ALIGN (REGNO (x))) | |
230d793d | 8144 | { |
563c12b0 RH |
8145 | unsigned HOST_WIDE_INT alignment |
8146 | = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT; | |
230d793d RS |
8147 | |
8148 | #ifdef PUSH_ROUNDING | |
563c12b0 RH |
8149 | /* If PUSH_ROUNDING is defined, it is possible for the |
8150 | stack to be momentarily aligned only to that amount, | |
8151 | so we pick the least alignment. */ | |
8152 | if (x == stack_pointer_rtx && PUSH_ARGS) | |
8153 | alignment = MIN (PUSH_ROUNDING (1), alignment); | |
230d793d RS |
8154 | #endif |
8155 | ||
563c12b0 | 8156 | nonzero &= ~(alignment - 1); |
230d793d | 8157 | } |
230d793d | 8158 | |
55310dad RK |
8159 | /* If X is a register whose nonzero bits value is current, use it. |
8160 | Otherwise, if X is a register whose value we can find, use that | |
8161 | value. Otherwise, use the previously-computed global nonzero bits | |
8162 | for this register. */ | |
8163 | ||
8164 | if (reg_last_set_value[REGNO (x)] != 0 | |
0a0440c9 JJ |
8165 | && (reg_last_set_mode[REGNO (x)] == mode |
8166 | || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT | |
8167 | && GET_MODE_CLASS (mode) == MODE_INT)) | |
57cf50a4 GRK |
8168 | && (reg_last_set_label[REGNO (x)] == label_tick |
8169 | || (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
8170 | && REG_N_SETS (REGNO (x)) == 1 | |
f6366fc7 | 8171 | && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, |
57cf50a4 | 8172 | REGNO (x)))) |
55310dad | 8173 | && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) |
563c12b0 | 8174 | return reg_last_set_nonzero_bits[REGNO (x)] & nonzero; |
230d793d RS |
8175 | |
8176 | tem = get_last_value (x); | |
9afa3d54 | 8177 | |
230d793d | 8178 | if (tem) |
9afa3d54 RK |
8179 | { |
8180 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND | |
8181 | /* If X is narrower than MODE and TEM is a non-negative | |
8182 | constant that would appear negative in the mode of X, | |
8183 | sign-extend it for use in reg_nonzero_bits because some | |
8184 | machines (maybe most) will actually do the sign-extension | |
663522cb | 8185 | and this is the conservative approach. |
9afa3d54 RK |
8186 | |
8187 | ??? For 2.5, try to tighten up the MD files in this regard | |
8188 | instead of this kludge. */ | |
8189 | ||
8190 | if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width | |
8191 | && GET_CODE (tem) == CONST_INT | |
8192 | && INTVAL (tem) > 0 | |
8193 | && 0 != (INTVAL (tem) | |
8194 | & ((HOST_WIDE_INT) 1 | |
9e69be8c | 8195 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) |
9afa3d54 RK |
8196 | tem = GEN_INT (INTVAL (tem) |
8197 | | ((HOST_WIDE_INT) (-1) | |
8198 | << GET_MODE_BITSIZE (GET_MODE (x)))); | |
8199 | #endif | |
563c12b0 | 8200 | return nonzero_bits (tem, mode) & nonzero; |
9afa3d54 | 8201 | } |
951553af | 8202 | else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)]) |
7958f3c7 JJ |
8203 | { |
8204 | unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)]; | |
8205 | ||
8206 | if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width) | |
8207 | /* We don't know anything about the upper bits. */ | |
8208 | mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); | |
8209 | return nonzero & mask; | |
8210 | } | |
230d793d | 8211 | else |
951553af | 8212 | return nonzero; |
230d793d RS |
8213 | |
8214 | case CONST_INT: | |
9afa3d54 RK |
8215 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND |
8216 | /* If X is negative in MODE, sign-extend the value. */ | |
9e69be8c RK |
8217 | if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD |
8218 | && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1)))) | |
8219 | return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width)); | |
9afa3d54 RK |
8220 | #endif |
8221 | ||
230d793d RS |
8222 | return INTVAL (x); |
8223 | ||
230d793d | 8224 | case MEM: |
8baf60bb | 8225 | #ifdef LOAD_EXTEND_OP |
230d793d RS |
8226 | /* In many, if not most, RISC machines, reading a byte from memory |
8227 | zeros the rest of the register. Noticing that fact saves a lot | |
8228 | of extra zero-extends. */ | |
8baf60bb RK |
8229 | if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) |
8230 | nonzero &= GET_MODE_MASK (GET_MODE (x)); | |
230d793d | 8231 | #endif |
8baf60bb | 8232 | break; |
230d793d | 8233 | |
230d793d | 8234 | case EQ: case NE: |
69bc0a1f JH |
8235 | case UNEQ: case LTGT: |
8236 | case GT: case GTU: case UNGT: | |
8237 | case LT: case LTU: case UNLT: | |
8238 | case GE: case GEU: case UNGE: | |
8239 | case LE: case LEU: case UNLE: | |
8240 | case UNORDERED: case ORDERED: | |
3f508eca | 8241 | |
c6965c0f RK |
8242 | /* If this produces an integer result, we know which bits are set. |
8243 | Code here used to clear bits outside the mode of X, but that is | |
8244 | now done above. */ | |
230d793d | 8245 | |
c6965c0f RK |
8246 | if (GET_MODE_CLASS (mode) == MODE_INT |
8247 | && mode_width <= HOST_BITS_PER_WIDE_INT) | |
8248 | nonzero = STORE_FLAG_VALUE; | |
230d793d | 8249 | break; |
230d793d | 8250 | |
230d793d | 8251 | case NEG: |
b3728b0e JW |
8252 | #if 0 |
8253 | /* Disabled to avoid exponential mutual recursion between nonzero_bits | |
8254 | and num_sign_bit_copies. */ | |
d0ab8cd3 RK |
8255 | if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) |
8256 | == GET_MODE_BITSIZE (GET_MODE (x))) | |
951553af | 8257 | nonzero = 1; |
b3728b0e | 8258 | #endif |
230d793d RS |
8259 | |
8260 | if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) | |
663522cb | 8261 | nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x))); |
230d793d | 8262 | break; |
d0ab8cd3 RK |
8263 | |
8264 | case ABS: | |
b3728b0e JW |
8265 | #if 0 |
8266 | /* Disabled to avoid exponential mutual recursion between nonzero_bits | |
8267 | and num_sign_bit_copies. */ | |
d0ab8cd3 RK |
8268 | if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) |
8269 | == GET_MODE_BITSIZE (GET_MODE (x))) | |
951553af | 8270 | nonzero = 1; |
b3728b0e | 8271 | #endif |
d0ab8cd3 | 8272 | break; |
230d793d RS |
8273 | |
8274 | case TRUNCATE: | |
951553af | 8275 | nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode)); |
230d793d RS |
8276 | break; |
8277 | ||
8278 | case ZERO_EXTEND: | |
951553af | 8279 | nonzero &= nonzero_bits (XEXP (x, 0), mode); |
230d793d | 8280 | if (GET_MODE (XEXP (x, 0)) != VOIDmode) |
951553af | 8281 | nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); |
230d793d RS |
8282 | break; |
8283 | ||
8284 | case SIGN_EXTEND: | |
8285 | /* If the sign bit is known clear, this is the same as ZERO_EXTEND. | |
8286 | Otherwise, show all the bits in the outer mode but not the inner | |
da7d8304 | 8287 | may be nonzero. */ |
951553af | 8288 | inner_nz = nonzero_bits (XEXP (x, 0), mode); |
230d793d RS |
8289 | if (GET_MODE (XEXP (x, 0)) != VOIDmode) |
8290 | { | |
951553af | 8291 | inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); |
e3da301d MS |
8292 | if (inner_nz |
8293 | & (((HOST_WIDE_INT) 1 | |
8294 | << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))) | |
951553af | 8295 | inner_nz |= (GET_MODE_MASK (mode) |
663522cb | 8296 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); |
230d793d RS |
8297 | } |
8298 | ||
951553af | 8299 | nonzero &= inner_nz; |
230d793d RS |
8300 | break; |
8301 | ||
8302 | case AND: | |
951553af RK |
8303 | nonzero &= (nonzero_bits (XEXP (x, 0), mode) |
8304 | & nonzero_bits (XEXP (x, 1), mode)); | |
230d793d RS |
8305 | break; |
8306 | ||
d0ab8cd3 RK |
8307 | case XOR: case IOR: |
8308 | case UMIN: case UMAX: case SMIN: case SMAX: | |
0a0440c9 JJ |
8309 | { |
8310 | unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode); | |
8311 | ||
8312 | /* Don't call nonzero_bits for the second time if it cannot change | |
8313 | anything. */ | |
8314 | if ((nonzero & nonzero0) != nonzero) | |
8315 | nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode)); | |
8316 | } | |
230d793d RS |
8317 | break; |
8318 | ||
8319 | case PLUS: case MINUS: | |
8320 | case MULT: | |
8321 | case DIV: case UDIV: | |
8322 | case MOD: case UMOD: | |
8323 | /* We can apply the rules of arithmetic to compute the number of | |
8324 | high- and low-order zero bits of these operations. We start by | |
da7d8304 | 8325 | computing the width (position of the highest-order nonzero bit) |
230d793d RS |
8326 | and the number of low-order zero bits for each value. */ |
8327 | { | |
951553af RK |
8328 | unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode); |
8329 | unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode); | |
8330 | int width0 = floor_log2 (nz0) + 1; | |
8331 | int width1 = floor_log2 (nz1) + 1; | |
8332 | int low0 = floor_log2 (nz0 & -nz0); | |
8333 | int low1 = floor_log2 (nz1 & -nz1); | |
318b149c RK |
8334 | HOST_WIDE_INT op0_maybe_minusp |
8335 | = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); | |
8336 | HOST_WIDE_INT op1_maybe_minusp | |
8337 | = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); | |
770ae6cc | 8338 | unsigned int result_width = mode_width; |
230d793d RS |
8339 | int result_low = 0; |
8340 | ||
8341 | switch (code) | |
8342 | { | |
8343 | case PLUS: | |
8344 | result_width = MAX (width0, width1) + 1; | |
8345 | result_low = MIN (low0, low1); | |
8346 | break; | |
8347 | case MINUS: | |
8348 | result_low = MIN (low0, low1); | |
8349 | break; | |
8350 | case MULT: | |
8351 | result_width = width0 + width1; | |
8352 | result_low = low0 + low1; | |
8353 | break; | |
8354 | case DIV: | |
2a8bb5cf AH |
8355 | if (width1 == 0) |
8356 | break; | |
230d793d RS |
8357 | if (! op0_maybe_minusp && ! op1_maybe_minusp) |
8358 | result_width = width0; | |
8359 | break; | |
8360 | case UDIV: | |
2a8bb5cf AH |
8361 | if (width1 == 0) |
8362 | break; | |
230d793d RS |
8363 | result_width = width0; |
8364 | break; | |
8365 | case MOD: | |
2a8bb5cf AH |
8366 | if (width1 == 0) |
8367 | break; | |
230d793d RS |
8368 | if (! op0_maybe_minusp && ! op1_maybe_minusp) |
8369 | result_width = MIN (width0, width1); | |
8370 | result_low = MIN (low0, low1); | |
8371 | break; | |
8372 | case UMOD: | |
2a8bb5cf AH |
8373 | if (width1 == 0) |
8374 | break; | |
230d793d RS |
8375 | result_width = MIN (width0, width1); |
8376 | result_low = MIN (low0, low1); | |
8377 | break; | |
e9a25f70 JL |
8378 | default: |
8379 | abort (); | |
230d793d RS |
8380 | } |
8381 | ||
8382 | if (result_width < mode_width) | |
951553af | 8383 | nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1; |
230d793d RS |
8384 | |
8385 | if (result_low > 0) | |
663522cb | 8386 | nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1); |
d1405722 RK |
8387 | |
8388 | #ifdef POINTERS_EXTEND_UNSIGNED | |
8389 | /* If pointers extend unsigned and this is an addition or subtraction | |
8390 | to a pointer in Pmode, all the bits above ptr_mode are known to be | |
8391 | zero. */ | |
6dd12198 | 8392 | if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode |
d1405722 RK |
8393 | && (code == PLUS || code == MINUS) |
8394 | && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0))) | |
8395 | nonzero &= GET_MODE_MASK (ptr_mode); | |
8396 | #endif | |
230d793d RS |
8397 | } |
8398 | break; | |
8399 | ||
8400 | case ZERO_EXTRACT: | |
8401 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5f4f0e22 | 8402 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) |
951553af | 8403 | nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; |
230d793d RS |
8404 | break; |
8405 | ||
8406 | case SUBREG: | |
c3c2cb37 RK |
8407 | /* If this is a SUBREG formed for a promoted variable that has |
8408 | been zero-extended, we know that at least the high-order bits | |
8409 | are zero, though others might be too. */ | |
8410 | ||
7879b81e | 8411 | if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0) |
951553af RK |
8412 | nonzero = (GET_MODE_MASK (GET_MODE (x)) |
8413 | & nonzero_bits (SUBREG_REG (x), GET_MODE (x))); | |
c3c2cb37 | 8414 | |
230d793d RS |
8415 | /* If the inner mode is a single word for both the host and target |
8416 | machines, we can compute this from which bits of the inner | |
951553af | 8417 | object might be nonzero. */ |
230d793d | 8418 | if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD |
5f4f0e22 CH |
8419 | && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) |
8420 | <= HOST_BITS_PER_WIDE_INT)) | |
230d793d | 8421 | { |
951553af | 8422 | nonzero &= nonzero_bits (SUBREG_REG (x), mode); |
8baf60bb | 8423 | |
b52ce03d R |
8424 | #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP) |
8425 | /* If this is a typical RISC machine, we only have to worry | |
8426 | about the way loads are extended. */ | |
0e603223 RS |
8427 | if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND |
8428 | ? (((nonzero | |
8429 | & (((unsigned HOST_WIDE_INT) 1 | |
8430 | << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))) | |
8431 | != 0)) | |
8432 | : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND) | |
8433 | || GET_CODE (SUBREG_REG (x)) != MEM) | |
230d793d | 8434 | #endif |
b52ce03d R |
8435 | { |
8436 | /* On many CISC machines, accessing an object in a wider mode | |
8437 | causes the high-order bits to become undefined. So they are | |
8438 | not known to be zero. */ | |
8439 | if (GET_MODE_SIZE (GET_MODE (x)) | |
8440 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
8441 | nonzero |= (GET_MODE_MASK (GET_MODE (x)) | |
663522cb | 8442 | & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))); |
b52ce03d | 8443 | } |
230d793d RS |
8444 | } |
8445 | break; | |
8446 | ||
8447 | case ASHIFTRT: | |
8448 | case LSHIFTRT: | |
8449 | case ASHIFT: | |
230d793d | 8450 | case ROTATE: |
951553af | 8451 | /* The nonzero bits are in two classes: any bits within MODE |
230d793d | 8452 | that aren't in GET_MODE (x) are always significant. The rest of the |
951553af | 8453 | nonzero bits are those that are significant in the operand of |
230d793d RS |
8454 | the shift when shifted the appropriate number of bits. This |
8455 | shows that high-order bits are cleared by the right shift and | |
8456 | low-order bits by left shifts. */ | |
8457 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
8458 | && INTVAL (XEXP (x, 1)) >= 0 | |
5f4f0e22 | 8459 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) |
230d793d RS |
8460 | { |
8461 | enum machine_mode inner_mode = GET_MODE (x); | |
770ae6cc | 8462 | unsigned int width = GET_MODE_BITSIZE (inner_mode); |
230d793d | 8463 | int count = INTVAL (XEXP (x, 1)); |
5f4f0e22 | 8464 | unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); |
951553af RK |
8465 | unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode); |
8466 | unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; | |
5f4f0e22 | 8467 | unsigned HOST_WIDE_INT outer = 0; |
230d793d RS |
8468 | |
8469 | if (mode_width > width) | |
663522cb | 8470 | outer = (op_nonzero & nonzero & ~mode_mask); |
230d793d RS |
8471 | |
8472 | if (code == LSHIFTRT) | |
8473 | inner >>= count; | |
8474 | else if (code == ASHIFTRT) | |
8475 | { | |
8476 | inner >>= count; | |
8477 | ||
951553af | 8478 | /* If the sign bit may have been nonzero before the shift, we |
230d793d | 8479 | need to mark all the places it could have been copied to |
951553af | 8480 | by the shift as possibly nonzero. */ |
5f4f0e22 CH |
8481 | if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count))) |
8482 | inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count); | |
230d793d | 8483 | } |
45620ed4 | 8484 | else if (code == ASHIFT) |
230d793d RS |
8485 | inner <<= count; |
8486 | else | |
8487 | inner = ((inner << (count % width) | |
8488 | | (inner >> (width - (count % width)))) & mode_mask); | |
8489 | ||
951553af | 8490 | nonzero &= (outer | inner); |
230d793d RS |
8491 | } |
8492 | break; | |
8493 | ||
8494 | case FFS: | |
8495 | /* This is at most the number of bits in the mode. */ | |
951553af | 8496 | nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1; |
230d793d | 8497 | break; |
d0ab8cd3 RK |
8498 | |
8499 | case IF_THEN_ELSE: | |
951553af RK |
8500 | nonzero &= (nonzero_bits (XEXP (x, 1), mode) |
8501 | | nonzero_bits (XEXP (x, 2), mode)); | |
d0ab8cd3 | 8502 | break; |
663522cb | 8503 | |
e9a25f70 JL |
8504 | default: |
8505 | break; | |
230d793d RS |
8506 | } |
8507 | ||
951553af | 8508 | return nonzero; |
230d793d | 8509 | } |
b3728b0e JW |
8510 | |
8511 | /* See the macro definition above. */ | |
8512 | #undef num_sign_bit_copies | |
230d793d | 8513 | \f |
d0ab8cd3 | 8514 | /* Return the number of bits at the high-order end of X that are known to |
5109d49f RK |
8515 | be equal to the sign bit. X will be used in mode MODE; if MODE is |
8516 | VOIDmode, X will be used in its own mode. The returned value will always | |
8517 | be between 1 and the number of bits in MODE. */ | |
d0ab8cd3 | 8518 | |
770ae6cc | 8519 | static unsigned int |
d0ab8cd3 RK |
8520 | num_sign_bit_copies (x, mode) |
8521 | rtx x; | |
8522 | enum machine_mode mode; | |
8523 | { | |
8524 | enum rtx_code code = GET_CODE (x); | |
770ae6cc | 8525 | unsigned int bitwidth; |
d0ab8cd3 | 8526 | int num0, num1, result; |
951553af | 8527 | unsigned HOST_WIDE_INT nonzero; |
d0ab8cd3 RK |
8528 | rtx tem; |
8529 | ||
8530 | /* If we weren't given a mode, use the mode of X. If the mode is still | |
1c75dfa4 RK |
8531 | VOIDmode, we don't know anything. Likewise if one of the modes is |
8532 | floating-point. */ | |
d0ab8cd3 RK |
8533 | |
8534 | if (mode == VOIDmode) | |
8535 | mode = GET_MODE (x); | |
8536 | ||
1c75dfa4 | 8537 | if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x))) |
6752e8d2 | 8538 | return 1; |
d0ab8cd3 RK |
8539 | |
8540 | bitwidth = GET_MODE_BITSIZE (mode); | |
8541 | ||
0f41302f | 8542 | /* For a smaller object, just ignore the high bits. */ |
312def2e | 8543 | if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x))) |
770ae6cc RK |
8544 | { |
8545 | num0 = num_sign_bit_copies (x, GET_MODE (x)); | |
8546 | return MAX (1, | |
8547 | num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)); | |
8548 | } | |
663522cb | 8549 | |
e9a25f70 JL |
8550 | if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x))) |
8551 | { | |
0c314d1a RK |
8552 | #ifndef WORD_REGISTER_OPERATIONS |
8553 | /* If this machine does not do all register operations on the entire | |
8554 | register and MODE is wider than the mode of X, we can say nothing | |
8555 | at all about the high-order bits. */ | |
e9a25f70 JL |
8556 | return 1; |
8557 | #else | |
8558 | /* Likewise on machines that do, if the mode of the object is smaller | |
8559 | than a word and loads of that size don't sign extend, we can say | |
8560 | nothing about the high order bits. */ | |
8561 | if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD | |
8562 | #ifdef LOAD_EXTEND_OP | |
8563 | && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND | |
8564 | #endif | |
8565 | ) | |
8566 | return 1; | |
0c314d1a | 8567 | #endif |
e9a25f70 | 8568 | } |
0c314d1a | 8569 | |
d0ab8cd3 RK |
8570 | switch (code) |
8571 | { | |
8572 | case REG: | |
55310dad | 8573 | |
6dd12198 | 8574 | #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) |
ff0dbdd1 RK |
8575 | /* If pointers extend signed and this is a pointer in Pmode, say that |
8576 | all the bits above ptr_mode are known to be sign bit copies. */ | |
8577 | if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode | |
3502dc9c | 8578 | && REG_POINTER (x)) |
ff0dbdd1 RK |
8579 | return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1; |
8580 | #endif | |
8581 | ||
55310dad RK |
8582 | if (reg_last_set_value[REGNO (x)] != 0 |
8583 | && reg_last_set_mode[REGNO (x)] == mode | |
57cf50a4 GRK |
8584 | && (reg_last_set_label[REGNO (x)] == label_tick |
8585 | || (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
8586 | && REG_N_SETS (REGNO (x)) == 1 | |
f6366fc7 | 8587 | && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, |
57cf50a4 | 8588 | REGNO (x)))) |
55310dad RK |
8589 | && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) |
8590 | return reg_last_set_sign_bit_copies[REGNO (x)]; | |
d0ab8cd3 | 8591 | |
663522cb | 8592 | tem = get_last_value (x); |
d0ab8cd3 RK |
8593 | if (tem != 0) |
8594 | return num_sign_bit_copies (tem, mode); | |
55310dad | 8595 | |
7958f3c7 JJ |
8596 | if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0 |
8597 | && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth) | |
55310dad | 8598 | return reg_sign_bit_copies[REGNO (x)]; |
d0ab8cd3 RK |
8599 | break; |
8600 | ||
457816e2 | 8601 | case MEM: |
8baf60bb | 8602 | #ifdef LOAD_EXTEND_OP |
457816e2 | 8603 | /* Some RISC machines sign-extend all loads of smaller than a word. */ |
8baf60bb | 8604 | if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) |
770ae6cc RK |
8605 | return MAX (1, ((int) bitwidth |
8606 | - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1)); | |
457816e2 | 8607 | #endif |
8baf60bb | 8608 | break; |
457816e2 | 8609 | |
d0ab8cd3 RK |
8610 | case CONST_INT: |
8611 | /* If the constant is negative, take its 1's complement and remask. | |
8612 | Then see how many zero bits we have. */ | |
951553af | 8613 | nonzero = INTVAL (x) & GET_MODE_MASK (mode); |
ac49a949 | 8614 | if (bitwidth <= HOST_BITS_PER_WIDE_INT |
951553af | 8615 | && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) |
663522cb | 8616 | nonzero = (~nonzero) & GET_MODE_MASK (mode); |
d0ab8cd3 | 8617 | |
951553af | 8618 | return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); |
d0ab8cd3 RK |
8619 | |
8620 | case SUBREG: | |
c3c2cb37 RK |
8621 | /* If this is a SUBREG for a promoted object that is sign-extended |
8622 | and we are looking at it in a wider mode, we know that at least the | |
8623 | high-order bits are known to be sign bit copies. */ | |
8624 | ||
8625 | if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) | |
770ae6cc RK |
8626 | { |
8627 | num0 = num_sign_bit_copies (SUBREG_REG (x), mode); | |
8628 | return MAX ((int) bitwidth | |
8629 | - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1, | |
8630 | num0); | |
8631 | } | |
663522cb | 8632 | |
0f41302f | 8633 | /* For a smaller object, just ignore the high bits. */ |
d0ab8cd3 RK |
8634 | if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))) |
8635 | { | |
8636 | num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode); | |
8637 | return MAX (1, (num0 | |
770ae6cc RK |
8638 | - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) |
8639 | - bitwidth))); | |
d0ab8cd3 | 8640 | } |
457816e2 | 8641 | |
8baf60bb | 8642 | #ifdef WORD_REGISTER_OPERATIONS |
2aec5b7a | 8643 | #ifdef LOAD_EXTEND_OP |
8baf60bb RK |
8644 | /* For paradoxical SUBREGs on machines where all register operations |
8645 | affect the entire register, just look inside. Note that we are | |
8646 | passing MODE to the recursive call, so the number of sign bit copies | |
8647 | will remain relative to that mode, not the inner mode. */ | |
457816e2 | 8648 | |
2aec5b7a JW |
8649 | /* This works only if loads sign extend. Otherwise, if we get a |
8650 | reload for the inner part, it may be loaded from the stack, and | |
8651 | then we lose all sign bit copies that existed before the store | |
8652 | to the stack. */ | |
8653 | ||
8654 | if ((GET_MODE_SIZE (GET_MODE (x)) | |
8655 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
0e603223 RS |
8656 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND |
8657 | && GET_CODE (SUBREG_REG (x)) == MEM) | |
457816e2 | 8658 | return num_sign_bit_copies (SUBREG_REG (x), mode); |
2aec5b7a | 8659 | #endif |
457816e2 | 8660 | #endif |
d0ab8cd3 RK |
8661 | break; |
8662 | ||
8663 | case SIGN_EXTRACT: | |
8664 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
770ae6cc | 8665 | return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1))); |
d0ab8cd3 RK |
8666 | break; |
8667 | ||
663522cb | 8668 | case SIGN_EXTEND: |
d0ab8cd3 RK |
8669 | return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) |
8670 | + num_sign_bit_copies (XEXP (x, 0), VOIDmode)); | |
8671 | ||
8672 | case TRUNCATE: | |
0f41302f | 8673 | /* For a smaller object, just ignore the high bits. */ |
d0ab8cd3 | 8674 | num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode); |
770ae6cc RK |
8675 | return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) |
8676 | - bitwidth))); | |
d0ab8cd3 RK |
8677 | |
8678 | case NOT: | |
8679 | return num_sign_bit_copies (XEXP (x, 0), mode); | |
8680 | ||
8681 | case ROTATE: case ROTATERT: | |
8682 | /* If we are rotating left by a number of bits less than the number | |
8683 | of sign bit copies, we can just subtract that amount from the | |
8684 | number. */ | |
8685 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
ae0ed63a JM |
8686 | && INTVAL (XEXP (x, 1)) >= 0 |
8687 | && INTVAL (XEXP (x, 1)) < (int) bitwidth) | |
d0ab8cd3 RK |
8688 | { |
8689 | num0 = num_sign_bit_copies (XEXP (x, 0), mode); | |
8690 | return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) | |
770ae6cc | 8691 | : (int) bitwidth - INTVAL (XEXP (x, 1)))); |
d0ab8cd3 RK |
8692 | } |
8693 | break; | |
8694 | ||
8695 | case NEG: | |
8696 | /* In general, this subtracts one sign bit copy. But if the value | |
8697 | is known to be positive, the number of sign bit copies is the | |
951553af RK |
8698 | same as that of the input. Finally, if the input has just one bit |
8699 | that might be nonzero, all the bits are copies of the sign bit. */ | |
70186b34 BS |
8700 | num0 = num_sign_bit_copies (XEXP (x, 0), mode); |
8701 | if (bitwidth > HOST_BITS_PER_WIDE_INT) | |
8702 | return num0 > 1 ? num0 - 1 : 1; | |
8703 | ||
951553af RK |
8704 | nonzero = nonzero_bits (XEXP (x, 0), mode); |
8705 | if (nonzero == 1) | |
d0ab8cd3 RK |
8706 | return bitwidth; |
8707 | ||
d0ab8cd3 | 8708 | if (num0 > 1 |
951553af | 8709 | && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) |
d0ab8cd3 RK |
8710 | num0--; |
8711 | ||
8712 | return num0; | |
8713 | ||
8714 | case IOR: case AND: case XOR: | |
8715 | case SMIN: case SMAX: case UMIN: case UMAX: | |
8716 | /* Logical operations will preserve the number of sign-bit copies. | |
8717 | MIN and MAX operations always return one of the operands. */ | |
8718 | num0 = num_sign_bit_copies (XEXP (x, 0), mode); | |
8719 | num1 = num_sign_bit_copies (XEXP (x, 1), mode); | |
8720 | return MIN (num0, num1); | |
8721 | ||
8722 | case PLUS: case MINUS: | |
8723 | /* For addition and subtraction, we can have a 1-bit carry. However, | |
8724 | if we are subtracting 1 from a positive number, there will not | |
8725 | be such a carry. Furthermore, if the positive number is known to | |
8726 | be 0 or 1, we know the result is either -1 or 0. */ | |
8727 | ||
3e3ea975 | 8728 | if (code == PLUS && XEXP (x, 1) == constm1_rtx |
9295e6af | 8729 | && bitwidth <= HOST_BITS_PER_WIDE_INT) |
d0ab8cd3 | 8730 | { |
951553af RK |
8731 | nonzero = nonzero_bits (XEXP (x, 0), mode); |
8732 | if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) | |
8733 | return (nonzero == 1 || nonzero == 0 ? bitwidth | |
8734 | : bitwidth - floor_log2 (nonzero) - 1); | |
d0ab8cd3 RK |
8735 | } |
8736 | ||
8737 | num0 = num_sign_bit_copies (XEXP (x, 0), mode); | |
8738 | num1 = num_sign_bit_copies (XEXP (x, 1), mode); | |
d1405722 RK |
8739 | result = MAX (1, MIN (num0, num1) - 1); |
8740 | ||
8741 | #ifdef POINTERS_EXTEND_UNSIGNED | |
8742 | /* If pointers extend signed and this is an addition or subtraction | |
8743 | to a pointer in Pmode, all the bits above ptr_mode are known to be | |
8744 | sign bit copies. */ | |
8745 | if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode | |
8746 | && (code == PLUS || code == MINUS) | |
8747 | && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0))) | |
505ddab6 KH |
8748 | result = MAX ((int) (GET_MODE_BITSIZE (Pmode) |
8749 | - GET_MODE_BITSIZE (ptr_mode) + 1), | |
d1405722 RK |
8750 | result); |
8751 | #endif | |
8752 | return result; | |
663522cb | 8753 | |
d0ab8cd3 RK |
8754 | case MULT: |
8755 | /* The number of bits of the product is the sum of the number of | |
8756 | bits of both terms. However, unless one of the terms if known | |
8757 | to be positive, we must allow for an additional bit since negating | |
8758 | a negative number can remove one sign bit copy. */ | |
8759 | ||
8760 | num0 = num_sign_bit_copies (XEXP (x, 0), mode); | |
8761 | num1 = num_sign_bit_copies (XEXP (x, 1), mode); | |
8762 | ||
8763 | result = bitwidth - (bitwidth - num0) - (bitwidth - num1); | |
8764 | if (result > 0 | |
70186b34 BS |
8765 | && (bitwidth > HOST_BITS_PER_WIDE_INT |
8766 | || (((nonzero_bits (XEXP (x, 0), mode) | |
8767 | & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) | |
8768 | && ((nonzero_bits (XEXP (x, 1), mode) | |
8769 | & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)))) | |
d0ab8cd3 RK |
8770 | result--; |
8771 | ||
8772 | return MAX (1, result); | |
8773 | ||
8774 | case UDIV: | |
70186b34 BS |
8775 | /* The result must be <= the first operand. If the first operand |
8776 | has the high bit set, we know nothing about the number of sign | |
8777 | bit copies. */ | |
8778 | if (bitwidth > HOST_BITS_PER_WIDE_INT) | |
8779 | return 1; | |
8780 | else if ((nonzero_bits (XEXP (x, 0), mode) | |
8781 | & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) | |
8782 | return 1; | |
8783 | else | |
8784 | return num_sign_bit_copies (XEXP (x, 0), mode); | |
663522cb | 8785 | |
d0ab8cd3 | 8786 | case UMOD: |
eaec9b3d | 8787 | /* The result must be <= the second operand. */ |
d0ab8cd3 RK |
8788 | return num_sign_bit_copies (XEXP (x, 1), mode); |
8789 | ||
8790 | case DIV: | |
8791 | /* Similar to unsigned division, except that we have to worry about | |
8792 | the case where the divisor is negative, in which case we have | |
8793 | to add 1. */ | |
8794 | result = num_sign_bit_copies (XEXP (x, 0), mode); | |
8795 | if (result > 1 | |
70186b34 BS |
8796 | && (bitwidth > HOST_BITS_PER_WIDE_INT |
8797 | || (nonzero_bits (XEXP (x, 1), mode) | |
8798 | & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) | |
8799 | result--; | |
d0ab8cd3 RK |
8800 | |
8801 | return result; | |
8802 | ||
8803 | case MOD: | |
8804 | result = num_sign_bit_copies (XEXP (x, 1), mode); | |
8805 | if (result > 1 | |
70186b34 BS |
8806 | && (bitwidth > HOST_BITS_PER_WIDE_INT |
8807 | || (nonzero_bits (XEXP (x, 1), mode) | |
8808 | & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) | |
8809 | result--; | |
d0ab8cd3 RK |
8810 | |
8811 | return result; | |
8812 | ||
8813 | case ASHIFTRT: | |
8814 | /* Shifts by a constant add to the number of bits equal to the | |
8815 | sign bit. */ | |
8816 | num0 = num_sign_bit_copies (XEXP (x, 0), mode); | |
8817 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
8818 | && INTVAL (XEXP (x, 1)) > 0) | |
ae0ed63a | 8819 | num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1))); |
d0ab8cd3 RK |
8820 | |
8821 | return num0; | |
8822 | ||
8823 | case ASHIFT: | |
d0ab8cd3 RK |
8824 | /* Left shifts destroy copies. */ |
8825 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
8826 | || INTVAL (XEXP (x, 1)) < 0 | |
ae0ed63a | 8827 | || INTVAL (XEXP (x, 1)) >= (int) bitwidth) |
d0ab8cd3 RK |
8828 | return 1; |
8829 | ||
8830 | num0 = num_sign_bit_copies (XEXP (x, 0), mode); | |
8831 | return MAX (1, num0 - INTVAL (XEXP (x, 1))); | |
8832 | ||
8833 | case IF_THEN_ELSE: | |
8834 | num0 = num_sign_bit_copies (XEXP (x, 1), mode); | |
8835 | num1 = num_sign_bit_copies (XEXP (x, 2), mode); | |
8836 | return MIN (num0, num1); | |
8837 | ||
d0ab8cd3 | 8838 | case EQ: case NE: case GE: case GT: case LE: case LT: |
69bc0a1f | 8839 | case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT: |
d0ab8cd3 | 8840 | case GEU: case GTU: case LEU: case LTU: |
69bc0a1f JH |
8841 | case UNORDERED: case ORDERED: |
8842 | /* If the constant is negative, take its 1's complement and remask. | |
8843 | Then see how many zero bits we have. */ | |
8844 | nonzero = STORE_FLAG_VALUE; | |
8845 | if (bitwidth <= HOST_BITS_PER_WIDE_INT | |
8846 | && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) | |
8847 | nonzero = (~nonzero) & GET_MODE_MASK (mode); | |
8848 | ||
8849 | return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); | |
e9a25f70 | 8850 | break; |
663522cb | 8851 | |
e9a25f70 JL |
8852 | default: |
8853 | break; | |
d0ab8cd3 RK |
8854 | } |
8855 | ||
8856 | /* If we haven't been able to figure it out by one of the above rules, | |
8857 | see if some of the high-order bits are known to be zero. If so, | |
ac49a949 RS |
8858 | count those bits and return one less than that amount. If we can't |
8859 | safely compute the mask for this mode, always return BITWIDTH. */ | |
8860 | ||
8861 | if (bitwidth > HOST_BITS_PER_WIDE_INT) | |
6752e8d2 | 8862 | return 1; |
d0ab8cd3 | 8863 | |
951553af | 8864 | nonzero = nonzero_bits (x, mode); |
df6f4086 | 8865 | return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) |
951553af | 8866 | ? 1 : bitwidth - floor_log2 (nonzero) - 1); |
d0ab8cd3 RK |
8867 | } |
8868 | \f | |
1a26b032 RK |
8869 | /* Return the number of "extended" bits there are in X, when interpreted |
8870 | as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For | |
8871 | unsigned quantities, this is the number of high-order zero bits. | |
8872 | For signed quantities, this is the number of copies of the sign bit | |
8873 | minus 1. In both case, this function returns the number of "spare" | |
8874 | bits. For example, if two quantities for which this function returns | |
8875 | at least 1 are added, the addition is known not to overflow. | |
8876 | ||
8877 | This function will always return 0 unless called during combine, which | |
8878 | implies that it must be called from a define_split. */ | |
8879 | ||
770ae6cc | 8880 | unsigned int |
1a26b032 RK |
8881 | extended_count (x, mode, unsignedp) |
8882 | rtx x; | |
8883 | enum machine_mode mode; | |
8884 | int unsignedp; | |
8885 | { | |
951553af | 8886 | if (nonzero_sign_valid == 0) |
1a26b032 RK |
8887 | return 0; |
8888 | ||
8889 | return (unsignedp | |
ac49a949 | 8890 | ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
26c34780 RS |
8891 | ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1 |
8892 | - floor_log2 (nonzero_bits (x, mode))) | |
770ae6cc | 8893 | : 0) |
1a26b032 RK |
8894 | : num_sign_bit_copies (x, mode) - 1); |
8895 | } | |
8896 | \f | |
230d793d RS |
8897 | /* This function is called from `simplify_shift_const' to merge two |
8898 | outer operations. Specifically, we have already found that we need | |
8899 | to perform operation *POP0 with constant *PCONST0 at the outermost | |
8900 | position. We would now like to also perform OP1 with constant CONST1 | |
8901 | (with *POP0 being done last). | |
8902 | ||
8903 | Return 1 if we can do the operation and update *POP0 and *PCONST0 with | |
663522cb | 8904 | the resulting operation. *PCOMP_P is set to 1 if we would need to |
230d793d RS |
8905 | complement the innermost operand, otherwise it is unchanged. |
8906 | ||
8907 | MODE is the mode in which the operation will be done. No bits outside | |
8908 | the width of this mode matter. It is assumed that the width of this mode | |
5f4f0e22 | 8909 | is smaller than or equal to HOST_BITS_PER_WIDE_INT. |
230d793d RS |
8910 | |
8911 | If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, | |
8912 | IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper | |
8913 | result is simply *PCONST0. | |
8914 | ||
8915 | If the resulting operation cannot be expressed as one operation, we | |
8916 | return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ | |
8917 | ||
8918 | static int | |
8919 | merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p) | |
8920 | enum rtx_code *pop0; | |
5f4f0e22 | 8921 | HOST_WIDE_INT *pconst0; |
230d793d | 8922 | enum rtx_code op1; |
5f4f0e22 | 8923 | HOST_WIDE_INT const1; |
230d793d RS |
8924 | enum machine_mode mode; |
8925 | int *pcomp_p; | |
8926 | { | |
8927 | enum rtx_code op0 = *pop0; | |
5f4f0e22 | 8928 | HOST_WIDE_INT const0 = *pconst0; |
230d793d RS |
8929 | |
8930 | const0 &= GET_MODE_MASK (mode); | |
8931 | const1 &= GET_MODE_MASK (mode); | |
8932 | ||
8933 | /* If OP0 is an AND, clear unimportant bits in CONST1. */ | |
8934 | if (op0 == AND) | |
8935 | const1 &= const0; | |
8936 | ||
8937 | /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or | |
8938 | if OP0 is SET. */ | |
8939 | ||
8940 | if (op1 == NIL || op0 == SET) | |
8941 | return 1; | |
8942 | ||
8943 | else if (op0 == NIL) | |
8944 | op0 = op1, const0 = const1; | |
8945 | ||
8946 | else if (op0 == op1) | |
8947 | { | |
8948 | switch (op0) | |
8949 | { | |
8950 | case AND: | |
8951 | const0 &= const1; | |
8952 | break; | |
8953 | case IOR: | |
8954 | const0 |= const1; | |
8955 | break; | |
8956 | case XOR: | |
8957 | const0 ^= const1; | |
8958 | break; | |
8959 | case PLUS: | |
8960 | const0 += const1; | |
8961 | break; | |
8962 | case NEG: | |
8963 | op0 = NIL; | |
8964 | break; | |
e9a25f70 JL |
8965 | default: |
8966 | break; | |
230d793d RS |
8967 | } |
8968 | } | |
8969 | ||
8970 | /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ | |
8971 | else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) | |
8972 | return 0; | |
8973 | ||
8974 | /* If the two constants aren't the same, we can't do anything. The | |
8975 | remaining six cases can all be done. */ | |
8976 | else if (const0 != const1) | |
8977 | return 0; | |
8978 | ||
8979 | else | |
8980 | switch (op0) | |
8981 | { | |
8982 | case IOR: | |
8983 | if (op1 == AND) | |
8984 | /* (a & b) | b == b */ | |
8985 | op0 = SET; | |
8986 | else /* op1 == XOR */ | |
8987 | /* (a ^ b) | b == a | b */ | |
b729186a | 8988 | {;} |
230d793d RS |
8989 | break; |
8990 | ||
8991 | case XOR: | |
8992 | if (op1 == AND) | |
8993 | /* (a & b) ^ b == (~a) & b */ | |
8994 | op0 = AND, *pcomp_p = 1; | |
8995 | else /* op1 == IOR */ | |
8996 | /* (a | b) ^ b == a & ~b */ | |
663522cb | 8997 | op0 = AND, *pconst0 = ~const0; |
230d793d RS |
8998 | break; |
8999 | ||
9000 | case AND: | |
9001 | if (op1 == IOR) | |
9002 | /* (a | b) & b == b */ | |
9003 | op0 = SET; | |
9004 | else /* op1 == XOR */ | |
9005 | /* (a ^ b) & b) == (~a) & b */ | |
9006 | *pcomp_p = 1; | |
9007 | break; | |
e9a25f70 JL |
9008 | default: |
9009 | break; | |
230d793d RS |
9010 | } |
9011 | ||
9012 | /* Check for NO-OP cases. */ | |
9013 | const0 &= GET_MODE_MASK (mode); | |
9014 | if (const0 == 0 | |
9015 | && (op0 == IOR || op0 == XOR || op0 == PLUS)) | |
9016 | op0 = NIL; | |
9017 | else if (const0 == 0 && op0 == AND) | |
9018 | op0 = SET; | |
e51712db KG |
9019 | else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) |
9020 | && op0 == AND) | |
230d793d RS |
9021 | op0 = NIL; |
9022 | ||
7e4ce834 RH |
9023 | /* ??? Slightly redundant with the above mask, but not entirely. |
9024 | Moving this above means we'd have to sign-extend the mode mask | |
9025 | for the final test. */ | |
9026 | const0 = trunc_int_for_mode (const0, mode); | |
9fa6d012 | 9027 | |
230d793d RS |
9028 | *pop0 = op0; |
9029 | *pconst0 = const0; | |
9030 | ||
9031 | return 1; | |
9032 | } | |
9033 | \f | |
9034 | /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. | |
da7d8304 | 9035 | The result of the shift is RESULT_MODE. X, if nonzero, is an expression |
230d793d RS |
9036 | that we started with. |
9037 | ||
9038 | The shift is normally computed in the widest mode we find in VAROP, as | |
9039 | long as it isn't a different number of words than RESULT_MODE. Exceptions | |
9040 | are ASHIFTRT and ROTATE, which are always done in their original mode, */ | |
9041 | ||
9042 | static rtx | |
0051b6ca | 9043 | simplify_shift_const (x, code, result_mode, varop, orig_count) |
230d793d RS |
9044 | rtx x; |
9045 | enum rtx_code code; | |
9046 | enum machine_mode result_mode; | |
9047 | rtx varop; | |
0051b6ca | 9048 | int orig_count; |
230d793d RS |
9049 | { |
9050 | enum rtx_code orig_code = code; | |
770ae6cc RK |
9051 | unsigned int count; |
9052 | int signed_count; | |
230d793d RS |
9053 | enum machine_mode mode = result_mode; |
9054 | enum machine_mode shift_mode, tmode; | |
770ae6cc | 9055 | unsigned int mode_words |
230d793d RS |
9056 | = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; |
9057 | /* We form (outer_op (code varop count) (outer_const)). */ | |
9058 | enum rtx_code outer_op = NIL; | |
c4e861e8 | 9059 | HOST_WIDE_INT outer_const = 0; |
230d793d RS |
9060 | rtx const_rtx; |
9061 | int complement_p = 0; | |
9062 | rtx new; | |
9063 | ||
0051b6ca RH |
9064 | /* Make sure and truncate the "natural" shift on the way in. We don't |
9065 | want to do this inside the loop as it makes it more difficult to | |
9066 | combine shifts. */ | |
9067 | #ifdef SHIFT_COUNT_TRUNCATED | |
9068 | if (SHIFT_COUNT_TRUNCATED) | |
9069 | orig_count &= GET_MODE_BITSIZE (mode) - 1; | |
9070 | #endif | |
9071 | ||
230d793d RS |
9072 | /* If we were given an invalid count, don't do anything except exactly |
9073 | what was requested. */ | |
9074 | ||
0051b6ca | 9075 | if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode)) |
230d793d RS |
9076 | { |
9077 | if (x) | |
9078 | return x; | |
9079 | ||
0051b6ca | 9080 | return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count)); |
230d793d RS |
9081 | } |
9082 | ||
0051b6ca | 9083 | count = orig_count; |
853d8828 | 9084 | |
230d793d RS |
9085 | /* Unless one of the branches of the `if' in this loop does a `continue', |
9086 | we will `break' the loop after the `if'. */ | |
9087 | ||
9088 | while (count != 0) | |
9089 | { | |
9090 | /* If we have an operand of (clobber (const_int 0)), just return that | |
9091 | value. */ | |
9092 | if (GET_CODE (varop) == CLOBBER) | |
9093 | return varop; | |
9094 | ||
9095 | /* If we discovered we had to complement VAROP, leave. Making a NOT | |
9096 | here would cause an infinite loop. */ | |
9097 | if (complement_p) | |
9098 | break; | |
9099 | ||
abc95ed3 | 9100 | /* Convert ROTATERT to ROTATE. */ |
230d793d | 9101 | if (code == ROTATERT) |
ad9df12f IS |
9102 | { |
9103 | unsigned int bitsize = GET_MODE_BITSIZE (result_mode);; | |
9104 | code = ROTATE; | |
9105 | if (VECTOR_MODE_P (result_mode)) | |
9106 | count = bitsize / GET_MODE_NUNITS (result_mode) - count; | |
9107 | else | |
9108 | count = bitsize - count; | |
9109 | } | |
230d793d | 9110 | |
230d793d | 9111 | /* We need to determine what mode we will do the shift in. If the |
f6789c77 RK |
9112 | shift is a right shift or a ROTATE, we must always do it in the mode |
9113 | it was originally done in. Otherwise, we can do it in MODE, the | |
0f41302f | 9114 | widest mode encountered. */ |
f6789c77 RK |
9115 | shift_mode |
9116 | = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE | |
9117 | ? result_mode : mode); | |
230d793d RS |
9118 | |
9119 | /* Handle cases where the count is greater than the size of the mode | |
853d8828 RH |
9120 | minus 1. For ASHIFT, use the size minus one as the count (this can |
9121 | occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, | |
9122 | take the count modulo the size. For other shifts, the result is | |
9123 | zero. | |
230d793d RS |
9124 | |
9125 | Since these shifts are being produced by the compiler by combining | |
9126 | multiple operations, each of which are defined, we know what the | |
9127 | result is supposed to be. */ | |
663522cb | 9128 | |
26c34780 | 9129 | if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1)) |
230d793d RS |
9130 | { |
9131 | if (code == ASHIFTRT) | |
9132 | count = GET_MODE_BITSIZE (shift_mode) - 1; | |
9133 | else if (code == ROTATE || code == ROTATERT) | |
9134 | count %= GET_MODE_BITSIZE (shift_mode); | |
9135 | else | |
9136 | { | |
9137 | /* We can't simply return zero because there may be an | |
9138 | outer op. */ | |
9139 | varop = const0_rtx; | |
9140 | count = 0; | |
9141 | break; | |
9142 | } | |
9143 | } | |
9144 | ||
312def2e RK |
9145 | /* An arithmetic right shift of a quantity known to be -1 or 0 |
9146 | is a no-op. */ | |
9147 | if (code == ASHIFTRT | |
9148 | && (num_sign_bit_copies (varop, shift_mode) | |
9149 | == GET_MODE_BITSIZE (shift_mode))) | |
d0ab8cd3 | 9150 | { |
312def2e RK |
9151 | count = 0; |
9152 | break; | |
9153 | } | |
d0ab8cd3 | 9154 | |
312def2e RK |
9155 | /* If we are doing an arithmetic right shift and discarding all but |
9156 | the sign bit copies, this is equivalent to doing a shift by the | |
9157 | bitsize minus one. Convert it into that shift because it will often | |
9158 | allow other simplifications. */ | |
500c518b | 9159 | |
312def2e RK |
9160 | if (code == ASHIFTRT |
9161 | && (count + num_sign_bit_copies (varop, shift_mode) | |
9162 | >= GET_MODE_BITSIZE (shift_mode))) | |
9163 | count = GET_MODE_BITSIZE (shift_mode) - 1; | |
500c518b | 9164 | |
230d793d RS |
9165 | /* We simplify the tests below and elsewhere by converting |
9166 | ASHIFTRT to LSHIFTRT if we know the sign bit is clear. | |
e0a2f705 KH |
9167 | `make_compound_operation' will convert it to an ASHIFTRT for |
9168 | those machines (such as VAX) that don't have an LSHIFTRT. */ | |
5f4f0e22 | 9169 | if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT |
230d793d | 9170 | && code == ASHIFTRT |
951553af | 9171 | && ((nonzero_bits (varop, shift_mode) |
5f4f0e22 CH |
9172 | & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) |
9173 | == 0)) | |
230d793d RS |
9174 | code = LSHIFTRT; |
9175 | ||
9176 | switch (GET_CODE (varop)) | |
9177 | { | |
9178 | case SIGN_EXTEND: | |
9179 | case ZERO_EXTEND: | |
9180 | case SIGN_EXTRACT: | |
9181 | case ZERO_EXTRACT: | |
9182 | new = expand_compound_operation (varop); | |
9183 | if (new != varop) | |
9184 | { | |
9185 | varop = new; | |
9186 | continue; | |
9187 | } | |
9188 | break; | |
9189 | ||
9190 | case MEM: | |
9191 | /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH | |
9192 | minus the width of a smaller mode, we can do this with a | |
9193 | SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ | |
9194 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
9195 | && ! mode_dependent_address_p (XEXP (varop, 0)) | |
9196 | && ! MEM_VOLATILE_P (varop) | |
9197 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
9198 | MODE_INT, 1)) != BLKmode) | |
9199 | { | |
f1ec5147 RK |
9200 | new = adjust_address_nv (varop, tmode, |
9201 | BYTES_BIG_ENDIAN ? 0 | |
9202 | : count / BITS_PER_UNIT); | |
bf49b139 | 9203 | |
f1c6ba8b RK |
9204 | varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND |
9205 | : ZERO_EXTEND, mode, new); | |
230d793d RS |
9206 | count = 0; |
9207 | continue; | |
9208 | } | |
9209 | break; | |
9210 | ||
9211 | case USE: | |
9212 | /* Similar to the case above, except that we can only do this if | |
9213 | the resulting mode is the same as that of the underlying | |
9214 | MEM and adjust the address depending on the *bits* endianness | |
9215 | because of the way that bit-field extract insns are defined. */ | |
9216 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
9217 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
9218 | MODE_INT, 1)) != BLKmode | |
9219 | && tmode == GET_MODE (XEXP (varop, 0))) | |
9220 | { | |
f76b9db2 ILT |
9221 | if (BITS_BIG_ENDIAN) |
9222 | new = XEXP (varop, 0); | |
9223 | else | |
9224 | { | |
9225 | new = copy_rtx (XEXP (varop, 0)); | |
663522cb | 9226 | SUBST (XEXP (new, 0), |
f76b9db2 ILT |
9227 | plus_constant (XEXP (new, 0), |
9228 | count / BITS_PER_UNIT)); | |
9229 | } | |
230d793d | 9230 | |
f1c6ba8b RK |
9231 | varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND |
9232 | : ZERO_EXTEND, mode, new); | |
230d793d RS |
9233 | count = 0; |
9234 | continue; | |
9235 | } | |
9236 | break; | |
9237 | ||
9238 | case SUBREG: | |
9239 | /* If VAROP is a SUBREG, strip it as long as the inner operand has | |
9240 | the same number of words as what we've seen so far. Then store | |
9241 | the widest mode in MODE. */ | |
f9e67232 RS |
9242 | if (subreg_lowpart_p (varop) |
9243 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) | |
9244 | > GET_MODE_SIZE (GET_MODE (varop))) | |
26c34780 RS |
9245 | && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) |
9246 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
9247 | == mode_words) | |
230d793d RS |
9248 | { |
9249 | varop = SUBREG_REG (varop); | |
9250 | if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) | |
9251 | mode = GET_MODE (varop); | |
9252 | continue; | |
9253 | } | |
9254 | break; | |
9255 | ||
9256 | case MULT: | |
9257 | /* Some machines use MULT instead of ASHIFT because MULT | |
9258 | is cheaper. But it is still better on those machines to | |
9259 | merge two shifts into one. */ | |
9260 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9261 | && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
9262 | { | |
770ae6cc RK |
9263 | varop |
9264 | = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0), | |
9265 | GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); | |
230d793d RS |
9266 | continue; |
9267 | } | |
9268 | break; | |
9269 | ||
9270 | case UDIV: | |
9271 | /* Similar, for when divides are cheaper. */ | |
9272 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9273 | && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
9274 | { | |
770ae6cc RK |
9275 | varop |
9276 | = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), | |
9277 | GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); | |
230d793d RS |
9278 | continue; |
9279 | } | |
9280 | break; | |
9281 | ||
9282 | case ASHIFTRT: | |
8f8d8d6e AO |
9283 | /* If we are extracting just the sign bit of an arithmetic |
9284 | right shift, that shift is not needed. However, the sign | |
9285 | bit of a wider mode may be different from what would be | |
9286 | interpreted as the sign bit in a narrower mode, so, if | |
9287 | the result is narrower, don't discard the shift. */ | |
26c34780 RS |
9288 | if (code == LSHIFTRT |
9289 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
8f8d8d6e AO |
9290 | && (GET_MODE_BITSIZE (result_mode) |
9291 | >= GET_MODE_BITSIZE (GET_MODE (varop)))) | |
230d793d RS |
9292 | { |
9293 | varop = XEXP (varop, 0); | |
9294 | continue; | |
9295 | } | |
9296 | ||
0f41302f | 9297 | /* ... fall through ... */ |
230d793d RS |
9298 | |
9299 | case LSHIFTRT: | |
9300 | case ASHIFT: | |
230d793d RS |
9301 | case ROTATE: |
9302 | /* Here we have two nested shifts. The result is usually the | |
9303 | AND of a new shift with a mask. We compute the result below. */ | |
9304 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9305 | && INTVAL (XEXP (varop, 1)) >= 0 | |
9306 | && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) | |
5f4f0e22 CH |
9307 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
9308 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
230d793d RS |
9309 | { |
9310 | enum rtx_code first_code = GET_CODE (varop); | |
770ae6cc | 9311 | unsigned int first_count = INTVAL (XEXP (varop, 1)); |
5f4f0e22 | 9312 | unsigned HOST_WIDE_INT mask; |
230d793d | 9313 | rtx mask_rtx; |
230d793d | 9314 | |
230d793d RS |
9315 | /* We have one common special case. We can't do any merging if |
9316 | the inner code is an ASHIFTRT of a smaller mode. However, if | |
9317 | we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) | |
9318 | with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), | |
9319 | we can convert it to | |
9320 | (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). | |
9321 | This simplifies certain SIGN_EXTEND operations. */ | |
9322 | if (code == ASHIFT && first_code == ASHIFTRT | |
26c34780 RS |
9323 | && count == (unsigned int) |
9324 | (GET_MODE_BITSIZE (result_mode) | |
9325 | - GET_MODE_BITSIZE (GET_MODE (varop)))) | |
230d793d RS |
9326 | { |
9327 | /* C3 has the low-order C1 bits zero. */ | |
663522cb | 9328 | |
5f4f0e22 | 9329 | mask = (GET_MODE_MASK (mode) |
663522cb | 9330 | & ~(((HOST_WIDE_INT) 1 << first_count) - 1)); |
230d793d | 9331 | |
5f4f0e22 | 9332 | varop = simplify_and_const_int (NULL_RTX, result_mode, |
230d793d | 9333 | XEXP (varop, 0), mask); |
5f4f0e22 | 9334 | varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, |
230d793d RS |
9335 | varop, count); |
9336 | count = first_count; | |
9337 | code = ASHIFTRT; | |
9338 | continue; | |
9339 | } | |
663522cb | 9340 | |
d0ab8cd3 RK |
9341 | /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more |
9342 | than C1 high-order bits equal to the sign bit, we can convert | |
e0a2f705 | 9343 | this to either an ASHIFT or an ASHIFTRT depending on the |
663522cb | 9344 | two counts. |
230d793d RS |
9345 | |
9346 | We cannot do this if VAROP's mode is not SHIFT_MODE. */ | |
9347 | ||
9348 | if (code == ASHIFTRT && first_code == ASHIFT | |
9349 | && GET_MODE (varop) == shift_mode | |
d0ab8cd3 RK |
9350 | && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) |
9351 | > first_count)) | |
230d793d | 9352 | { |
d0ab8cd3 | 9353 | varop = XEXP (varop, 0); |
770ae6cc RK |
9354 | |
9355 | signed_count = count - first_count; | |
9356 | if (signed_count < 0) | |
663522cb | 9357 | count = -signed_count, code = ASHIFT; |
770ae6cc RK |
9358 | else |
9359 | count = signed_count; | |
9360 | ||
d0ab8cd3 | 9361 | continue; |
230d793d RS |
9362 | } |
9363 | ||
9364 | /* There are some cases we can't do. If CODE is ASHIFTRT, | |
9365 | we can only do this if FIRST_CODE is also ASHIFTRT. | |
9366 | ||
9367 | We can't do the case when CODE is ROTATE and FIRST_CODE is | |
9368 | ASHIFTRT. | |
9369 | ||
9370 | If the mode of this shift is not the mode of the outer shift, | |
bdaae9a0 | 9371 | we can't do this if either shift is a right shift or ROTATE. |
230d793d RS |
9372 | |
9373 | Finally, we can't do any of these if the mode is too wide | |
9374 | unless the codes are the same. | |
9375 | ||
9376 | Handle the case where the shift codes are the same | |
9377 | first. */ | |
9378 | ||
9379 | if (code == first_code) | |
9380 | { | |
9381 | if (GET_MODE (varop) != result_mode | |
bdaae9a0 RK |
9382 | && (code == ASHIFTRT || code == LSHIFTRT |
9383 | || code == ROTATE)) | |
230d793d RS |
9384 | break; |
9385 | ||
9386 | count += first_count; | |
9387 | varop = XEXP (varop, 0); | |
9388 | continue; | |
9389 | } | |
9390 | ||
9391 | if (code == ASHIFTRT | |
9392 | || (code == ROTATE && first_code == ASHIFTRT) | |
5f4f0e22 | 9393 | || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT |
230d793d | 9394 | || (GET_MODE (varop) != result_mode |
bdaae9a0 RK |
9395 | && (first_code == ASHIFTRT || first_code == LSHIFTRT |
9396 | || first_code == ROTATE | |
230d793d RS |
9397 | || code == ROTATE))) |
9398 | break; | |
9399 | ||
9400 | /* To compute the mask to apply after the shift, shift the | |
663522cb | 9401 | nonzero bits of the inner shift the same way the |
230d793d RS |
9402 | outer shift will. */ |
9403 | ||
951553af | 9404 | mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); |
230d793d RS |
9405 | |
9406 | mask_rtx | |
9407 | = simplify_binary_operation (code, result_mode, mask_rtx, | |
5f4f0e22 | 9408 | GEN_INT (count)); |
663522cb | 9409 | |
230d793d RS |
9410 | /* Give up if we can't compute an outer operation to use. */ |
9411 | if (mask_rtx == 0 | |
9412 | || GET_CODE (mask_rtx) != CONST_INT | |
9413 | || ! merge_outer_ops (&outer_op, &outer_const, AND, | |
9414 | INTVAL (mask_rtx), | |
9415 | result_mode, &complement_p)) | |
9416 | break; | |
9417 | ||
9418 | /* If the shifts are in the same direction, we add the | |
9419 | counts. Otherwise, we subtract them. */ | |
770ae6cc | 9420 | signed_count = count; |
230d793d RS |
9421 | if ((code == ASHIFTRT || code == LSHIFTRT) |
9422 | == (first_code == ASHIFTRT || first_code == LSHIFTRT)) | |
770ae6cc | 9423 | signed_count += first_count; |
230d793d | 9424 | else |
770ae6cc | 9425 | signed_count -= first_count; |
230d793d | 9426 | |
663522cb | 9427 | /* If COUNT is positive, the new shift is usually CODE, |
230d793d RS |
9428 | except for the two exceptions below, in which case it is |
9429 | FIRST_CODE. If the count is negative, FIRST_CODE should | |
9430 | always be used */ | |
770ae6cc | 9431 | if (signed_count > 0 |
230d793d RS |
9432 | && ((first_code == ROTATE && code == ASHIFT) |
9433 | || (first_code == ASHIFTRT && code == LSHIFTRT))) | |
770ae6cc RK |
9434 | code = first_code, count = signed_count; |
9435 | else if (signed_count < 0) | |
663522cb | 9436 | code = first_code, count = -signed_count; |
770ae6cc RK |
9437 | else |
9438 | count = signed_count; | |
230d793d RS |
9439 | |
9440 | varop = XEXP (varop, 0); | |
9441 | continue; | |
9442 | } | |
9443 | ||
9444 | /* If we have (A << B << C) for any shift, we can convert this to | |
9445 | (A << C << B). This wins if A is a constant. Only try this if | |
9446 | B is not a constant. */ | |
9447 | ||
9448 | else if (GET_CODE (varop) == code | |
9449 | && GET_CODE (XEXP (varop, 1)) != CONST_INT | |
9450 | && 0 != (new | |
9451 | = simplify_binary_operation (code, mode, | |
9452 | XEXP (varop, 0), | |
5f4f0e22 | 9453 | GEN_INT (count)))) |
230d793d | 9454 | { |
f1c6ba8b | 9455 | varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1)); |
230d793d RS |
9456 | count = 0; |
9457 | continue; | |
9458 | } | |
9459 | break; | |
9460 | ||
9461 | case NOT: | |
9462 | /* Make this fit the case below. */ | |
f1c6ba8b RK |
9463 | varop = gen_rtx_XOR (mode, XEXP (varop, 0), |
9464 | GEN_INT (GET_MODE_MASK (mode))); | |
230d793d RS |
9465 | continue; |
9466 | ||
9467 | case IOR: | |
9468 | case AND: | |
9469 | case XOR: | |
9470 | /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) | |
9471 | with C the size of VAROP - 1 and the shift is logical if | |
9472 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
9473 | we have an (le X 0) operation. If we have an arithmetic shift | |
9474 | and STORE_FLAG_VALUE is 1 or we have a logical shift with | |
9475 | STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ | |
9476 | ||
9477 | if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS | |
9478 | && XEXP (XEXP (varop, 0), 1) == constm1_rtx | |
9479 | && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
9480 | && (code == LSHIFTRT || code == ASHIFTRT) | |
26c34780 RS |
9481 | && count == (unsigned int) |
9482 | (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) | |
230d793d RS |
9483 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) |
9484 | { | |
9485 | count = 0; | |
f1c6ba8b RK |
9486 | varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), |
9487 | const0_rtx); | |
230d793d RS |
9488 | |
9489 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
f1c6ba8b | 9490 | varop = gen_rtx_NEG (GET_MODE (varop), varop); |
230d793d RS |
9491 | |
9492 | continue; | |
9493 | } | |
9494 | ||
9495 | /* If we have (shift (logical)), move the logical to the outside | |
9496 | to allow it to possibly combine with another logical and the | |
9497 | shift to combine with another shift. This also canonicalizes to | |
9498 | what a ZERO_EXTRACT looks like. Also, some machines have | |
9499 | (and (shift)) insns. */ | |
9500 | ||
9501 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9502 | && (new = simplify_binary_operation (code, result_mode, | |
9503 | XEXP (varop, 1), | |
5f4f0e22 | 9504 | GEN_INT (count))) != 0 |
663522cb | 9505 | && GET_CODE (new) == CONST_INT |
230d793d RS |
9506 | && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), |
9507 | INTVAL (new), result_mode, &complement_p)) | |
9508 | { | |
9509 | varop = XEXP (varop, 0); | |
9510 | continue; | |
9511 | } | |
9512 | ||
9513 | /* If we can't do that, try to simplify the shift in each arm of the | |
9514 | logical expression, make a new logical expression, and apply | |
9515 | the inverse distributive law. */ | |
9516 | { | |
00d4ca1c | 9517 | rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, |
230d793d | 9518 | XEXP (varop, 0), count); |
00d4ca1c | 9519 | rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, |
230d793d RS |
9520 | XEXP (varop, 1), count); |
9521 | ||
21a64bf1 | 9522 | varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs); |
230d793d RS |
9523 | varop = apply_distributive_law (varop); |
9524 | ||
9525 | count = 0; | |
9526 | } | |
9527 | break; | |
9528 | ||
9529 | case EQ: | |
45620ed4 | 9530 | /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE |
230d793d | 9531 | says that the sign bit can be tested, FOO has mode MODE, C is |
45620ed4 RK |
9532 | GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit |
9533 | that may be nonzero. */ | |
9534 | if (code == LSHIFTRT | |
230d793d RS |
9535 | && XEXP (varop, 1) == const0_rtx |
9536 | && GET_MODE (XEXP (varop, 0)) == result_mode | |
26c34780 | 9537 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) |
5f4f0e22 | 9538 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
230d793d | 9539 | && ((STORE_FLAG_VALUE |
663522cb | 9540 | & ((HOST_WIDE_INT) 1 |
770ae6cc | 9541 | < (GET_MODE_BITSIZE (result_mode) - 1)))) |
951553af | 9542 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1 |
5f4f0e22 CH |
9543 | && merge_outer_ops (&outer_op, &outer_const, XOR, |
9544 | (HOST_WIDE_INT) 1, result_mode, | |
9545 | &complement_p)) | |
230d793d RS |
9546 | { |
9547 | varop = XEXP (varop, 0); | |
9548 | count = 0; | |
9549 | continue; | |
9550 | } | |
9551 | break; | |
9552 | ||
9553 | case NEG: | |
d0ab8cd3 RK |
9554 | /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less |
9555 | than the number of bits in the mode is equivalent to A. */ | |
26c34780 RS |
9556 | if (code == LSHIFTRT |
9557 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
951553af | 9558 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1) |
230d793d | 9559 | { |
d0ab8cd3 | 9560 | varop = XEXP (varop, 0); |
230d793d RS |
9561 | count = 0; |
9562 | continue; | |
9563 | } | |
9564 | ||
9565 | /* NEG commutes with ASHIFT since it is multiplication. Move the | |
9566 | NEG outside to allow shifts to combine. */ | |
9567 | if (code == ASHIFT | |
5f4f0e22 CH |
9568 | && merge_outer_ops (&outer_op, &outer_const, NEG, |
9569 | (HOST_WIDE_INT) 0, result_mode, | |
9570 | &complement_p)) | |
230d793d RS |
9571 | { |
9572 | varop = XEXP (varop, 0); | |
9573 | continue; | |
9574 | } | |
9575 | break; | |
9576 | ||
9577 | case PLUS: | |
d0ab8cd3 RK |
9578 | /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C |
9579 | is one less than the number of bits in the mode is | |
9580 | equivalent to (xor A 1). */ | |
26c34780 RS |
9581 | if (code == LSHIFTRT |
9582 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
230d793d | 9583 | && XEXP (varop, 1) == constm1_rtx |
951553af | 9584 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1 |
5f4f0e22 CH |
9585 | && merge_outer_ops (&outer_op, &outer_const, XOR, |
9586 | (HOST_WIDE_INT) 1, result_mode, | |
9587 | &complement_p)) | |
230d793d RS |
9588 | { |
9589 | count = 0; | |
9590 | varop = XEXP (varop, 0); | |
9591 | continue; | |
9592 | } | |
9593 | ||
3f508eca | 9594 | /* If we have (xshiftrt (plus FOO BAR) C), and the only bits |
951553af | 9595 | that might be nonzero in BAR are those being shifted out and those |
3f508eca RK |
9596 | bits are known zero in FOO, we can replace the PLUS with FOO. |
9597 | Similarly in the other operand order. This code occurs when | |
9598 | we are computing the size of a variable-size array. */ | |
9599 | ||
9600 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
5f4f0e22 | 9601 | && count < HOST_BITS_PER_WIDE_INT |
951553af RK |
9602 | && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 |
9603 | && (nonzero_bits (XEXP (varop, 1), result_mode) | |
9604 | & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) | |
3f508eca RK |
9605 | { |
9606 | varop = XEXP (varop, 0); | |
9607 | continue; | |
9608 | } | |
9609 | else if ((code == ASHIFTRT || code == LSHIFTRT) | |
5f4f0e22 | 9610 | && count < HOST_BITS_PER_WIDE_INT |
ac49a949 | 9611 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
951553af | 9612 | && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) |
3f508eca | 9613 | >> count) |
951553af RK |
9614 | && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) |
9615 | & nonzero_bits (XEXP (varop, 1), | |
3f508eca RK |
9616 | result_mode))) |
9617 | { | |
9618 | varop = XEXP (varop, 1); | |
9619 | continue; | |
9620 | } | |
9621 | ||
230d793d RS |
9622 | /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ |
9623 | if (code == ASHIFT | |
9624 | && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9625 | && (new = simplify_binary_operation (ASHIFT, result_mode, | |
9626 | XEXP (varop, 1), | |
5f4f0e22 | 9627 | GEN_INT (count))) != 0 |
770ae6cc | 9628 | && GET_CODE (new) == CONST_INT |
230d793d RS |
9629 | && merge_outer_ops (&outer_op, &outer_const, PLUS, |
9630 | INTVAL (new), result_mode, &complement_p)) | |
9631 | { | |
9632 | varop = XEXP (varop, 0); | |
9633 | continue; | |
9634 | } | |
9635 | break; | |
9636 | ||
9637 | case MINUS: | |
9638 | /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) | |
9639 | with C the size of VAROP - 1 and the shift is logical if | |
9640 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
9641 | we have a (gt X 0) operation. If the shift is arithmetic with | |
9642 | STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, | |
9643 | we have a (neg (gt X 0)) operation. */ | |
9644 | ||
0802d516 RK |
9645 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
9646 | && GET_CODE (XEXP (varop, 0)) == ASHIFTRT | |
26c34780 RS |
9647 | && count == (unsigned int) |
9648 | (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) | |
230d793d RS |
9649 | && (code == LSHIFTRT || code == ASHIFTRT) |
9650 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
26c34780 RS |
9651 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1)) |
9652 | == count | |
230d793d RS |
9653 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) |
9654 | { | |
9655 | count = 0; | |
f1c6ba8b RK |
9656 | varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), |
9657 | const0_rtx); | |
230d793d RS |
9658 | |
9659 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
f1c6ba8b | 9660 | varop = gen_rtx_NEG (GET_MODE (varop), varop); |
230d793d RS |
9661 | |
9662 | continue; | |
9663 | } | |
9664 | break; | |
6e0ef100 JC |
9665 | |
9666 | case TRUNCATE: | |
9667 | /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) | |
9668 | if the truncate does not affect the value. */ | |
9669 | if (code == LSHIFTRT | |
9670 | && GET_CODE (XEXP (varop, 0)) == LSHIFTRT | |
9671 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
9672 | && (INTVAL (XEXP (XEXP (varop, 0), 1)) | |
b577a8ff JL |
9673 | >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) |
9674 | - GET_MODE_BITSIZE (GET_MODE (varop))))) | |
6e0ef100 JC |
9675 | { |
9676 | rtx varop_inner = XEXP (varop, 0); | |
9677 | ||
770ae6cc | 9678 | varop_inner |
f1c6ba8b RK |
9679 | = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), |
9680 | XEXP (varop_inner, 0), | |
9681 | GEN_INT | |
9682 | (count + INTVAL (XEXP (varop_inner, 1)))); | |
9683 | varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); | |
6e0ef100 JC |
9684 | count = 0; |
9685 | continue; | |
9686 | } | |
9687 | break; | |
663522cb | 9688 | |
e9a25f70 JL |
9689 | default: |
9690 | break; | |
230d793d RS |
9691 | } |
9692 | ||
9693 | break; | |
9694 | } | |
9695 | ||
9696 | /* We need to determine what mode to do the shift in. If the shift is | |
f6789c77 RK |
9697 | a right shift or ROTATE, we must always do it in the mode it was |
9698 | originally done in. Otherwise, we can do it in MODE, the widest mode | |
9699 | encountered. The code we care about is that of the shift that will | |
9700 | actually be done, not the shift that was originally requested. */ | |
9701 | shift_mode | |
9702 | = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE | |
9703 | ? result_mode : mode); | |
230d793d RS |
9704 | |
9705 | /* We have now finished analyzing the shift. The result should be | |
9706 | a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If | |
9707 | OUTER_OP is non-NIL, it is an operation that needs to be applied | |
9708 | to the result of the shift. OUTER_CONST is the relevant constant, | |
9709 | but we must turn off all bits turned off in the shift. | |
9710 | ||
9711 | If we were passed a value for X, see if we can use any pieces of | |
9712 | it. If not, make new rtx. */ | |
9713 | ||
9714 | if (x && GET_RTX_CLASS (GET_CODE (x)) == '2' | |
9715 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
26c34780 | 9716 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count) |
230d793d RS |
9717 | const_rtx = XEXP (x, 1); |
9718 | else | |
5f4f0e22 | 9719 | const_rtx = GEN_INT (count); |
230d793d RS |
9720 | |
9721 | if (x && GET_CODE (XEXP (x, 0)) == SUBREG | |
9722 | && GET_MODE (XEXP (x, 0)) == shift_mode | |
9723 | && SUBREG_REG (XEXP (x, 0)) == varop) | |
9724 | varop = XEXP (x, 0); | |
9725 | else if (GET_MODE (varop) != shift_mode) | |
9726 | varop = gen_lowpart_for_combine (shift_mode, varop); | |
9727 | ||
0f41302f | 9728 | /* If we can't make the SUBREG, try to return what we were given. */ |
230d793d RS |
9729 | if (GET_CODE (varop) == CLOBBER) |
9730 | return x ? x : varop; | |
9731 | ||
9732 | new = simplify_binary_operation (code, shift_mode, varop, const_rtx); | |
9733 | if (new != 0) | |
9734 | x = new; | |
9735 | else | |
6c2d03d0 | 9736 | x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx); |
230d793d | 9737 | |
224eeff2 RK |
9738 | /* If we have an outer operation and we just made a shift, it is |
9739 | possible that we could have simplified the shift were it not | |
9740 | for the outer operation. So try to do the simplification | |
9741 | recursively. */ | |
9742 | ||
9743 | if (outer_op != NIL && GET_CODE (x) == code | |
9744 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
9745 | x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), | |
9746 | INTVAL (XEXP (x, 1))); | |
9747 | ||
e0a2f705 | 9748 | /* If we were doing an LSHIFTRT in a wider mode than it was originally, |
230d793d RS |
9749 | turn off all the bits that the shift would have turned off. */ |
9750 | if (orig_code == LSHIFTRT && result_mode != shift_mode) | |
5f4f0e22 | 9751 | x = simplify_and_const_int (NULL_RTX, shift_mode, x, |
230d793d | 9752 | GET_MODE_MASK (result_mode) >> orig_count); |
663522cb | 9753 | |
230d793d RS |
9754 | /* Do the remainder of the processing in RESULT_MODE. */ |
9755 | x = gen_lowpart_for_combine (result_mode, x); | |
9756 | ||
9757 | /* If COMPLEMENT_P is set, we have to complement X before doing the outer | |
9758 | operation. */ | |
9759 | if (complement_p) | |
f1c6ba8b | 9760 | x =simplify_gen_unary (NOT, result_mode, x, result_mode); |
230d793d RS |
9761 | |
9762 | if (outer_op != NIL) | |
9763 | { | |
5f4f0e22 | 9764 | if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) |
7e4ce834 | 9765 | outer_const = trunc_int_for_mode (outer_const, result_mode); |
230d793d RS |
9766 | |
9767 | if (outer_op == AND) | |
5f4f0e22 | 9768 | x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); |
230d793d RS |
9769 | else if (outer_op == SET) |
9770 | /* This means that we have determined that the result is | |
9771 | equivalent to a constant. This should be rare. */ | |
5f4f0e22 | 9772 | x = GEN_INT (outer_const); |
230d793d | 9773 | else if (GET_RTX_CLASS (outer_op) == '1') |
f1c6ba8b | 9774 | x = simplify_gen_unary (outer_op, result_mode, x, result_mode); |
230d793d | 9775 | else |
5f4f0e22 | 9776 | x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const)); |
230d793d RS |
9777 | } |
9778 | ||
9779 | return x; | |
663522cb | 9780 | } |
230d793d RS |
9781 | \f |
9782 | /* Like recog, but we receive the address of a pointer to a new pattern. | |
9783 | We try to match the rtx that the pointer points to. | |
9784 | If that fails, we may try to modify or replace the pattern, | |
9785 | storing the replacement into the same pointer object. | |
9786 | ||
9787 | Modifications include deletion or addition of CLOBBERs. | |
9788 | ||
9789 | PNOTES is a pointer to a location where any REG_UNUSED notes added for | |
9790 | the CLOBBERs are placed. | |
9791 | ||
9792 | The value is the final insn code from the pattern ultimately matched, | |
9793 | or -1. */ | |
9794 | ||
9795 | static int | |
8e2f6e35 | 9796 | recog_for_combine (pnewpat, insn, pnotes) |
230d793d RS |
9797 | rtx *pnewpat; |
9798 | rtx insn; | |
9799 | rtx *pnotes; | |
9800 | { | |
b3694847 | 9801 | rtx pat = *pnewpat; |
230d793d RS |
9802 | int insn_code_number; |
9803 | int num_clobbers_to_add = 0; | |
9804 | int i; | |
9805 | rtx notes = 0; | |
fa852403 | 9806 | rtx dummy_insn; |
230d793d | 9807 | |
974f4146 RK |
9808 | /* If PAT is a PARALLEL, check to see if it contains the CLOBBER |
9809 | we use to indicate that something didn't match. If we find such a | |
9810 | thing, force rejection. */ | |
d96023cf | 9811 | if (GET_CODE (pat) == PARALLEL) |
974f4146 | 9812 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) |
d96023cf RK |
9813 | if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER |
9814 | && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) | |
974f4146 RK |
9815 | return -1; |
9816 | ||
fa852403 JJ |
9817 | /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy |
9818 | instruction for pattern recognition. */ | |
9819 | dummy_insn = shallow_copy_rtx (insn); | |
9820 | PATTERN (dummy_insn) = pat; | |
9821 | REG_NOTES (dummy_insn) = 0; | |
c1194d74 | 9822 | |
fa852403 | 9823 | insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add); |
230d793d RS |
9824 | |
9825 | /* If it isn't, there is the possibility that we previously had an insn | |
9826 | that clobbered some register as a side effect, but the combined | |
9827 | insn doesn't need to do that. So try once more without the clobbers | |
9828 | unless this represents an ASM insn. */ | |
9829 | ||
9830 | if (insn_code_number < 0 && ! check_asm_operands (pat) | |
9831 | && GET_CODE (pat) == PARALLEL) | |
9832 | { | |
9833 | int pos; | |
9834 | ||
9835 | for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) | |
9836 | if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) | |
9837 | { | |
9838 | if (i != pos) | |
9839 | SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); | |
9840 | pos++; | |
9841 | } | |
9842 | ||
9843 | SUBST_INT (XVECLEN (pat, 0), pos); | |
9844 | ||
9845 | if (pos == 1) | |
9846 | pat = XVECEXP (pat, 0, 0); | |
9847 | ||
fa852403 JJ |
9848 | PATTERN (dummy_insn) = pat; |
9849 | insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add); | |
230d793d RS |
9850 | } |
9851 | ||
b5832b43 JH |
9852 | /* Recognize all noop sets, these will be killed by followup pass. */ |
9853 | if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) | |
9854 | insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; | |
9855 | ||
230d793d RS |
9856 | /* If we had any clobbers to add, make a new pattern than contains |
9857 | them. Then check to make sure that all of them are dead. */ | |
9858 | if (num_clobbers_to_add) | |
9859 | { | |
38a448ca | 9860 | rtx newpat = gen_rtx_PARALLEL (VOIDmode, |
bf103ec2 R |
9861 | rtvec_alloc (GET_CODE (pat) == PARALLEL |
9862 | ? (XVECLEN (pat, 0) | |
9863 | + num_clobbers_to_add) | |
9864 | : num_clobbers_to_add + 1)); | |
230d793d RS |
9865 | |
9866 | if (GET_CODE (pat) == PARALLEL) | |
9867 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
9868 | XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); | |
9869 | else | |
9870 | XVECEXP (newpat, 0, 0) = pat; | |
9871 | ||
9872 | add_clobbers (newpat, insn_code_number); | |
9873 | ||
9874 | for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; | |
9875 | i < XVECLEN (newpat, 0); i++) | |
9876 | { | |
9877 | if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG | |
9878 | && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) | |
9879 | return -1; | |
38a448ca RH |
9880 | notes = gen_rtx_EXPR_LIST (REG_UNUSED, |
9881 | XEXP (XVECEXP (newpat, 0, i), 0), notes); | |
230d793d RS |
9882 | } |
9883 | pat = newpat; | |
9884 | } | |
9885 | ||
9886 | *pnewpat = pat; | |
9887 | *pnotes = notes; | |
9888 | ||
9889 | return insn_code_number; | |
9890 | } | |
9891 | \f | |
9892 | /* Like gen_lowpart but for use by combine. In combine it is not possible | |
9893 | to create any new pseudoregs. However, it is safe to create | |
9894 | invalid memory addresses, because combine will try to recognize | |
9895 | them and all they will do is make the combine attempt fail. | |
9896 | ||
9897 | If for some reason this cannot do its job, an rtx | |
9898 | (clobber (const_int 0)) is returned. | |
9899 | An insn containing that will not be recognized. */ | |
9900 | ||
9901 | #undef gen_lowpart | |
9902 | ||
9903 | static rtx | |
9904 | gen_lowpart_for_combine (mode, x) | |
9905 | enum machine_mode mode; | |
b3694847 | 9906 | rtx x; |
230d793d RS |
9907 | { |
9908 | rtx result; | |
9909 | ||
9910 | if (GET_MODE (x) == mode) | |
9911 | return x; | |
9912 | ||
eae957a8 RK |
9913 | /* We can only support MODE being wider than a word if X is a |
9914 | constant integer or has a mode the same size. */ | |
9915 | ||
9916 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
9917 | && ! ((GET_MODE (x) == VOIDmode | |
9918 | && (GET_CODE (x) == CONST_INT | |
9919 | || GET_CODE (x) == CONST_DOUBLE)) | |
9920 | || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode))) | |
38a448ca | 9921 | return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
230d793d RS |
9922 | |
9923 | /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart | |
9924 | won't know what to do. So we will strip off the SUBREG here and | |
9925 | process normally. */ | |
9926 | if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) | |
9927 | { | |
9928 | x = SUBREG_REG (x); | |
9929 | if (GET_MODE (x) == mode) | |
9930 | return x; | |
9931 | } | |
9932 | ||
9933 | result = gen_lowpart_common (mode, x); | |
02188693 | 9934 | #ifdef CLASS_CANNOT_CHANGE_MODE |
64bf47a2 RK |
9935 | if (result != 0 |
9936 | && GET_CODE (result) == SUBREG | |
9937 | && GET_CODE (SUBREG_REG (result)) == REG | |
9938 | && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER | |
02188693 RH |
9939 | && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result), |
9940 | GET_MODE (SUBREG_REG (result)))) | |
9941 | REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1; | |
9942 | #endif | |
64bf47a2 | 9943 | |
230d793d RS |
9944 | if (result) |
9945 | return result; | |
9946 | ||
9947 | if (GET_CODE (x) == MEM) | |
9948 | { | |
b3694847 | 9949 | int offset = 0; |
230d793d RS |
9950 | |
9951 | /* Refuse to work on a volatile memory ref or one with a mode-dependent | |
9952 | address. */ | |
9953 | if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) | |
38a448ca | 9954 | return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
230d793d RS |
9955 | |
9956 | /* If we want to refer to something bigger than the original memref, | |
9957 | generate a perverse subreg instead. That will force a reload | |
9958 | of the original memref X. */ | |
9959 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) | |
38a448ca | 9960 | return gen_rtx_SUBREG (mode, x, 0); |
230d793d | 9961 | |
f76b9db2 ILT |
9962 | if (WORDS_BIG_ENDIAN) |
9963 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
9964 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
c5c76735 | 9965 | |
f76b9db2 ILT |
9966 | if (BYTES_BIG_ENDIAN) |
9967 | { | |
9968 | /* Adjust the address so that the address-after-the-data is | |
9969 | unchanged. */ | |
9970 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
9971 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
9972 | } | |
f1ec5147 RK |
9973 | |
9974 | return adjust_address_nv (x, mode, offset); | |
230d793d RS |
9975 | } |
9976 | ||
9977 | /* If X is a comparison operator, rewrite it in a new mode. This | |
9978 | probably won't match, but may allow further simplifications. */ | |
9979 | else if (GET_RTX_CLASS (GET_CODE (x)) == '<') | |
f1c6ba8b | 9980 | return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1)); |
230d793d RS |
9981 | |
9982 | /* If we couldn't simplify X any other way, just enclose it in a | |
9983 | SUBREG. Normally, this SUBREG won't match, but some patterns may | |
a7c99304 | 9984 | include an explicit SUBREG or we may simplify it further in combine. */ |
230d793d | 9985 | else |
dfbe1b2f | 9986 | { |
ddef6bc7 | 9987 | int offset = 0; |
e0e08ac2 | 9988 | rtx res; |
80ba02b1 | 9989 | enum machine_mode sub_mode = GET_MODE (x); |
dfbe1b2f | 9990 | |
80ba02b1 R |
9991 | offset = subreg_lowpart_offset (mode, sub_mode); |
9992 | if (sub_mode == VOIDmode) | |
9993 | { | |
9994 | sub_mode = int_mode_for_mode (mode); | |
9995 | x = gen_lowpart_common (sub_mode, x); | |
9996 | } | |
9997 | res = simplify_gen_subreg (mode, x, sub_mode, offset); | |
e0e08ac2 JH |
9998 | if (res) |
9999 | return res; | |
10000 | return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); | |
dfbe1b2f | 10001 | } |
230d793d RS |
10002 | } |
10003 | \f | |
230d793d RS |
10004 | /* These routines make binary and unary operations by first seeing if they |
10005 | fold; if not, a new expression is allocated. */ | |
10006 | ||
10007 | static rtx | |
10008 | gen_binary (code, mode, op0, op1) | |
10009 | enum rtx_code code; | |
10010 | enum machine_mode mode; | |
10011 | rtx op0, op1; | |
10012 | { | |
10013 | rtx result; | |
1a26b032 RK |
10014 | rtx tem; |
10015 | ||
10016 | if (GET_RTX_CLASS (code) == 'c' | |
8c9864f3 | 10017 | && swap_commutative_operands_p (op0, op1)) |
1a26b032 | 10018 | tem = op0, op0 = op1, op1 = tem; |
230d793d | 10019 | |
663522cb | 10020 | if (GET_RTX_CLASS (code) == '<') |
230d793d RS |
10021 | { |
10022 | enum machine_mode op_mode = GET_MODE (op0); | |
9210df58 | 10023 | |
663522cb | 10024 | /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get |
0f41302f | 10025 | just (REL_OP X Y). */ |
9210df58 RK |
10026 | if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) |
10027 | { | |
10028 | op1 = XEXP (op0, 1); | |
10029 | op0 = XEXP (op0, 0); | |
10030 | op_mode = GET_MODE (op0); | |
10031 | } | |
10032 | ||
230d793d RS |
10033 | if (op_mode == VOIDmode) |
10034 | op_mode = GET_MODE (op1); | |
10035 | result = simplify_relational_operation (code, op_mode, op0, op1); | |
10036 | } | |
10037 | else | |
10038 | result = simplify_binary_operation (code, mode, op0, op1); | |
10039 | ||
10040 | if (result) | |
10041 | return result; | |
10042 | ||
10043 | /* Put complex operands first and constants second. */ | |
10044 | if (GET_RTX_CLASS (code) == 'c' | |
e5c56fd9 | 10045 | && swap_commutative_operands_p (op0, op1)) |
f1c6ba8b | 10046 | return gen_rtx_fmt_ee (code, mode, op1, op0); |
230d793d | 10047 | |
e5e809f4 JL |
10048 | /* If we are turning off bits already known off in OP0, we need not do |
10049 | an AND. */ | |
10050 | else if (code == AND && GET_CODE (op1) == CONST_INT | |
10051 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
663522cb | 10052 | && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) |
e5e809f4 JL |
10053 | return op0; |
10054 | ||
f1c6ba8b | 10055 | return gen_rtx_fmt_ee (code, mode, op0, op1); |
230d793d RS |
10056 | } |
10057 | \f | |
10058 | /* Simplify a comparison between *POP0 and *POP1 where CODE is the | |
10059 | comparison code that will be tested. | |
10060 | ||
10061 | The result is a possibly different comparison code to use. *POP0 and | |
10062 | *POP1 may be updated. | |
10063 | ||
10064 | It is possible that we might detect that a comparison is either always | |
10065 | true or always false. However, we do not perform general constant | |
5089e22e | 10066 | folding in combine, so this knowledge isn't useful. Such tautologies |
230d793d RS |
10067 | should have been detected earlier. Hence we ignore all such cases. */ |
10068 | ||
10069 | static enum rtx_code | |
10070 | simplify_comparison (code, pop0, pop1) | |
10071 | enum rtx_code code; | |
10072 | rtx *pop0; | |
10073 | rtx *pop1; | |
10074 | { | |
10075 | rtx op0 = *pop0; | |
10076 | rtx op1 = *pop1; | |
10077 | rtx tem, tem1; | |
10078 | int i; | |
10079 | enum machine_mode mode, tmode; | |
10080 | ||
10081 | /* Try a few ways of applying the same transformation to both operands. */ | |
10082 | while (1) | |
10083 | { | |
3a19aabc RK |
10084 | #ifndef WORD_REGISTER_OPERATIONS |
10085 | /* The test below this one won't handle SIGN_EXTENDs on these machines, | |
10086 | so check specially. */ | |
10087 | if (code != GTU && code != GEU && code != LTU && code != LEU | |
10088 | && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT | |
10089 | && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
10090 | && GET_CODE (XEXP (op1, 0)) == ASHIFT | |
10091 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG | |
10092 | && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG | |
10093 | && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) | |
ad25ba17 | 10094 | == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) |
3a19aabc RK |
10095 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
10096 | && GET_CODE (XEXP (op1, 1)) == CONST_INT | |
10097 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10098 | && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT | |
10099 | && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1)) | |
10100 | && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1)) | |
10101 | && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1)) | |
10102 | && (INTVAL (XEXP (op0, 1)) | |
10103 | == (GET_MODE_BITSIZE (GET_MODE (op0)) | |
10104 | - (GET_MODE_BITSIZE | |
10105 | (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) | |
10106 | { | |
10107 | op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); | |
10108 | op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); | |
10109 | } | |
10110 | #endif | |
10111 | ||
230d793d RS |
10112 | /* If both operands are the same constant shift, see if we can ignore the |
10113 | shift. We can if the shift is a rotate or if the bits shifted out of | |
951553af | 10114 | this shift are known to be zero for both inputs and if the type of |
230d793d | 10115 | comparison is compatible with the shift. */ |
67232b23 RK |
10116 | if (GET_CODE (op0) == GET_CODE (op1) |
10117 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT | |
10118 | && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) | |
45620ed4 | 10119 | || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) |
67232b23 RK |
10120 | && (code != GT && code != LT && code != GE && code != LE)) |
10121 | || (GET_CODE (op0) == ASHIFTRT | |
10122 | && (code != GTU && code != LTU | |
99dc5306 | 10123 | && code != GEU && code != LEU))) |
67232b23 RK |
10124 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
10125 | && INTVAL (XEXP (op0, 1)) >= 0 | |
10126 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT | |
10127 | && XEXP (op0, 1) == XEXP (op1, 1)) | |
230d793d RS |
10128 | { |
10129 | enum machine_mode mode = GET_MODE (op0); | |
5f4f0e22 | 10130 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
10131 | int shift_count = INTVAL (XEXP (op0, 1)); |
10132 | ||
10133 | if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) | |
10134 | mask &= (mask >> shift_count) << shift_count; | |
45620ed4 | 10135 | else if (GET_CODE (op0) == ASHIFT) |
230d793d RS |
10136 | mask = (mask & (mask << shift_count)) >> shift_count; |
10137 | ||
663522cb KH |
10138 | if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 |
10139 | && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) | |
230d793d RS |
10140 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); |
10141 | else | |
10142 | break; | |
10143 | } | |
10144 | ||
10145 | /* If both operands are AND's of a paradoxical SUBREG by constant, the | |
10146 | SUBREGs are of the same mode, and, in both cases, the AND would | |
10147 | be redundant if the comparison was done in the narrower mode, | |
10148 | do the comparison in the narrower mode (e.g., we are AND'ing with 1 | |
951553af RK |
10149 | and the operand's possibly nonzero bits are 0xffffff01; in that case |
10150 | if we only care about QImode, we don't need the AND). This case | |
10151 | occurs if the output mode of an scc insn is not SImode and | |
7e4dc511 RK |
10152 | STORE_FLAG_VALUE == 1 (e.g., the 386). |
10153 | ||
10154 | Similarly, check for a case where the AND's are ZERO_EXTEND | |
10155 | operations from some narrower mode even though a SUBREG is not | |
10156 | present. */ | |
230d793d | 10157 | |
663522cb KH |
10158 | else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND |
10159 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10160 | && GET_CODE (XEXP (op1, 1)) == CONST_INT) | |
230d793d | 10161 | { |
7e4dc511 RK |
10162 | rtx inner_op0 = XEXP (op0, 0); |
10163 | rtx inner_op1 = XEXP (op1, 0); | |
10164 | HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); | |
10165 | HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); | |
10166 | int changed = 0; | |
663522cb | 10167 | |
7e4dc511 RK |
10168 | if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG |
10169 | && (GET_MODE_SIZE (GET_MODE (inner_op0)) | |
10170 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) | |
10171 | && (GET_MODE (SUBREG_REG (inner_op0)) | |
10172 | == GET_MODE (SUBREG_REG (inner_op1))) | |
729a2bc6 | 10173 | && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) |
7e4dc511 | 10174 | <= HOST_BITS_PER_WIDE_INT) |
01c82bbb | 10175 | && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), |
729a2bc6 | 10176 | GET_MODE (SUBREG_REG (inner_op0))))) |
01c82bbb RK |
10177 | && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), |
10178 | GET_MODE (SUBREG_REG (inner_op1)))))) | |
7e4dc511 RK |
10179 | { |
10180 | op0 = SUBREG_REG (inner_op0); | |
10181 | op1 = SUBREG_REG (inner_op1); | |
10182 | ||
10183 | /* The resulting comparison is always unsigned since we masked | |
0f41302f | 10184 | off the original sign bit. */ |
7e4dc511 RK |
10185 | code = unsigned_condition (code); |
10186 | ||
10187 | changed = 1; | |
10188 | } | |
230d793d | 10189 | |
7e4dc511 RK |
10190 | else if (c0 == c1) |
10191 | for (tmode = GET_CLASS_NARROWEST_MODE | |
10192 | (GET_MODE_CLASS (GET_MODE (op0))); | |
10193 | tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) | |
e51712db | 10194 | if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) |
7e4dc511 RK |
10195 | { |
10196 | op0 = gen_lowpart_for_combine (tmode, inner_op0); | |
10197 | op1 = gen_lowpart_for_combine (tmode, inner_op1); | |
66415c8b | 10198 | code = unsigned_condition (code); |
7e4dc511 RK |
10199 | changed = 1; |
10200 | break; | |
10201 | } | |
10202 | ||
10203 | if (! changed) | |
10204 | break; | |
230d793d | 10205 | } |
3a19aabc | 10206 | |
ad25ba17 RK |
10207 | /* If both operands are NOT, we can strip off the outer operation |
10208 | and adjust the comparison code for swapped operands; similarly for | |
10209 | NEG, except that this must be an equality comparison. */ | |
10210 | else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) | |
10211 | || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG | |
10212 | && (code == EQ || code == NE))) | |
10213 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); | |
3a19aabc | 10214 | |
230d793d RS |
10215 | else |
10216 | break; | |
10217 | } | |
663522cb | 10218 | |
230d793d | 10219 | /* If the first operand is a constant, swap the operands and adjust the |
3aceff0d RK |
10220 | comparison code appropriately, but don't do this if the second operand |
10221 | is already a constant integer. */ | |
8c9864f3 | 10222 | if (swap_commutative_operands_p (op0, op1)) |
230d793d RS |
10223 | { |
10224 | tem = op0, op0 = op1, op1 = tem; | |
10225 | code = swap_condition (code); | |
10226 | } | |
10227 | ||
10228 | /* We now enter a loop during which we will try to simplify the comparison. | |
10229 | For the most part, we only are concerned with comparisons with zero, | |
10230 | but some things may really be comparisons with zero but not start | |
10231 | out looking that way. */ | |
10232 | ||
10233 | while (GET_CODE (op1) == CONST_INT) | |
10234 | { | |
10235 | enum machine_mode mode = GET_MODE (op0); | |
770ae6cc | 10236 | unsigned int mode_width = GET_MODE_BITSIZE (mode); |
5f4f0e22 | 10237 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
10238 | int equality_comparison_p; |
10239 | int sign_bit_comparison_p; | |
10240 | int unsigned_comparison_p; | |
5f4f0e22 | 10241 | HOST_WIDE_INT const_op; |
230d793d RS |
10242 | |
10243 | /* We only want to handle integral modes. This catches VOIDmode, | |
10244 | CCmode, and the floating-point modes. An exception is that we | |
10245 | can handle VOIDmode if OP0 is a COMPARE or a comparison | |
10246 | operation. */ | |
10247 | ||
10248 | if (GET_MODE_CLASS (mode) != MODE_INT | |
10249 | && ! (mode == VOIDmode | |
10250 | && (GET_CODE (op0) == COMPARE | |
10251 | || GET_RTX_CLASS (GET_CODE (op0)) == '<'))) | |
10252 | break; | |
10253 | ||
10254 | /* Get the constant we are comparing against and turn off all bits | |
10255 | not on in our mode. */ | |
71012d97 GK |
10256 | const_op = INTVAL (op1); |
10257 | if (mode != VOIDmode) | |
10258 | const_op = trunc_int_for_mode (const_op, mode); | |
b4fbaca7 | 10259 | op1 = GEN_INT (const_op); |
230d793d RS |
10260 | |
10261 | /* If we are comparing against a constant power of two and the value | |
951553af | 10262 | being compared can only have that single bit nonzero (e.g., it was |
230d793d RS |
10263 | `and'ed with that bit), we can replace this with a comparison |
10264 | with zero. */ | |
10265 | if (const_op | |
10266 | && (code == EQ || code == NE || code == GE || code == GEU | |
10267 | || code == LT || code == LTU) | |
5f4f0e22 | 10268 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d | 10269 | && exact_log2 (const_op) >= 0 |
e51712db | 10270 | && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) |
230d793d RS |
10271 | { |
10272 | code = (code == EQ || code == GE || code == GEU ? NE : EQ); | |
10273 | op1 = const0_rtx, const_op = 0; | |
10274 | } | |
10275 | ||
d0ab8cd3 RK |
10276 | /* Similarly, if we are comparing a value known to be either -1 or |
10277 | 0 with -1, change it to the opposite comparison against zero. */ | |
10278 | ||
10279 | if (const_op == -1 | |
10280 | && (code == EQ || code == NE || code == GT || code == LE | |
10281 | || code == GEU || code == LTU) | |
10282 | && num_sign_bit_copies (op0, mode) == mode_width) | |
10283 | { | |
10284 | code = (code == EQ || code == LE || code == GEU ? NE : EQ); | |
10285 | op1 = const0_rtx, const_op = 0; | |
10286 | } | |
10287 | ||
230d793d | 10288 | /* Do some canonicalizations based on the comparison code. We prefer |
663522cb | 10289 | comparisons against zero and then prefer equality comparisons. |
4803a34a | 10290 | If we can reduce the size of a constant, we will do that too. */ |
230d793d RS |
10291 | |
10292 | switch (code) | |
10293 | { | |
10294 | case LT: | |
4803a34a RK |
10295 | /* < C is equivalent to <= (C - 1) */ |
10296 | if (const_op > 0) | |
230d793d | 10297 | { |
4803a34a | 10298 | const_op -= 1; |
5f4f0e22 | 10299 | op1 = GEN_INT (const_op); |
230d793d RS |
10300 | code = LE; |
10301 | /* ... fall through to LE case below. */ | |
10302 | } | |
10303 | else | |
10304 | break; | |
10305 | ||
10306 | case LE: | |
4803a34a RK |
10307 | /* <= C is equivalent to < (C + 1); we do this for C < 0 */ |
10308 | if (const_op < 0) | |
10309 | { | |
10310 | const_op += 1; | |
5f4f0e22 | 10311 | op1 = GEN_INT (const_op); |
4803a34a RK |
10312 | code = LT; |
10313 | } | |
230d793d RS |
10314 | |
10315 | /* If we are doing a <= 0 comparison on a value known to have | |
10316 | a zero sign bit, we can replace this with == 0. */ | |
10317 | else if (const_op == 0 | |
5f4f0e22 | 10318 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 10319 | && (nonzero_bits (op0, mode) |
5f4f0e22 | 10320 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) |
230d793d RS |
10321 | code = EQ; |
10322 | break; | |
10323 | ||
10324 | case GE: | |
0f41302f | 10325 | /* >= C is equivalent to > (C - 1). */ |
4803a34a | 10326 | if (const_op > 0) |
230d793d | 10327 | { |
4803a34a | 10328 | const_op -= 1; |
5f4f0e22 | 10329 | op1 = GEN_INT (const_op); |
230d793d RS |
10330 | code = GT; |
10331 | /* ... fall through to GT below. */ | |
10332 | } | |
10333 | else | |
10334 | break; | |
10335 | ||
10336 | case GT: | |
663522cb | 10337 | /* > C is equivalent to >= (C + 1); we do this for C < 0. */ |
4803a34a RK |
10338 | if (const_op < 0) |
10339 | { | |
10340 | const_op += 1; | |
5f4f0e22 | 10341 | op1 = GEN_INT (const_op); |
4803a34a RK |
10342 | code = GE; |
10343 | } | |
230d793d RS |
10344 | |
10345 | /* If we are doing a > 0 comparison on a value known to have | |
10346 | a zero sign bit, we can replace this with != 0. */ | |
10347 | else if (const_op == 0 | |
5f4f0e22 | 10348 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 10349 | && (nonzero_bits (op0, mode) |
5f4f0e22 | 10350 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) |
230d793d RS |
10351 | code = NE; |
10352 | break; | |
10353 | ||
230d793d | 10354 | case LTU: |
4803a34a RK |
10355 | /* < C is equivalent to <= (C - 1). */ |
10356 | if (const_op > 0) | |
10357 | { | |
10358 | const_op -= 1; | |
5f4f0e22 | 10359 | op1 = GEN_INT (const_op); |
4803a34a | 10360 | code = LEU; |
0f41302f | 10361 | /* ... fall through ... */ |
4803a34a | 10362 | } |
d0ab8cd3 RK |
10363 | |
10364 | /* (unsigned) < 0x80000000 is equivalent to >= 0. */ | |
f77aada2 JW |
10365 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
10366 | && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) | |
d0ab8cd3 RK |
10367 | { |
10368 | const_op = 0, op1 = const0_rtx; | |
10369 | code = GE; | |
10370 | break; | |
10371 | } | |
4803a34a RK |
10372 | else |
10373 | break; | |
230d793d RS |
10374 | |
10375 | case LEU: | |
10376 | /* unsigned <= 0 is equivalent to == 0 */ | |
10377 | if (const_op == 0) | |
10378 | code = EQ; | |
d0ab8cd3 | 10379 | |
0f41302f | 10380 | /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ |
f77aada2 JW |
10381 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
10382 | && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) | |
d0ab8cd3 RK |
10383 | { |
10384 | const_op = 0, op1 = const0_rtx; | |
10385 | code = GE; | |
10386 | } | |
230d793d RS |
10387 | break; |
10388 | ||
4803a34a RK |
10389 | case GEU: |
10390 | /* >= C is equivalent to < (C - 1). */ | |
10391 | if (const_op > 1) | |
10392 | { | |
10393 | const_op -= 1; | |
5f4f0e22 | 10394 | op1 = GEN_INT (const_op); |
4803a34a | 10395 | code = GTU; |
0f41302f | 10396 | /* ... fall through ... */ |
4803a34a | 10397 | } |
d0ab8cd3 RK |
10398 | |
10399 | /* (unsigned) >= 0x80000000 is equivalent to < 0. */ | |
f77aada2 JW |
10400 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
10401 | && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) | |
d0ab8cd3 RK |
10402 | { |
10403 | const_op = 0, op1 = const0_rtx; | |
10404 | code = LT; | |
8b2e69e1 | 10405 | break; |
d0ab8cd3 | 10406 | } |
4803a34a RK |
10407 | else |
10408 | break; | |
10409 | ||
230d793d RS |
10410 | case GTU: |
10411 | /* unsigned > 0 is equivalent to != 0 */ | |
10412 | if (const_op == 0) | |
10413 | code = NE; | |
d0ab8cd3 RK |
10414 | |
10415 | /* (unsigned) > 0x7fffffff is equivalent to < 0. */ | |
f77aada2 JW |
10416 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
10417 | && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) | |
d0ab8cd3 RK |
10418 | { |
10419 | const_op = 0, op1 = const0_rtx; | |
10420 | code = LT; | |
10421 | } | |
230d793d | 10422 | break; |
e9a25f70 JL |
10423 | |
10424 | default: | |
10425 | break; | |
230d793d RS |
10426 | } |
10427 | ||
10428 | /* Compute some predicates to simplify code below. */ | |
10429 | ||
10430 | equality_comparison_p = (code == EQ || code == NE); | |
10431 | sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); | |
10432 | unsigned_comparison_p = (code == LTU || code == LEU || code == GTU | |
d5010e66 | 10433 | || code == GEU); |
230d793d | 10434 | |
6139ff20 RK |
10435 | /* If this is a sign bit comparison and we can do arithmetic in |
10436 | MODE, say that we will only be needing the sign bit of OP0. */ | |
10437 | if (sign_bit_comparison_p | |
10438 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
10439 | op0 = force_to_mode (op0, mode, | |
10440 | ((HOST_WIDE_INT) 1 | |
10441 | << (GET_MODE_BITSIZE (mode) - 1)), | |
e3d616e3 | 10442 | NULL_RTX, 0); |
6139ff20 | 10443 | |
230d793d RS |
10444 | /* Now try cases based on the opcode of OP0. If none of the cases |
10445 | does a "continue", we exit this loop immediately after the | |
10446 | switch. */ | |
10447 | ||
10448 | switch (GET_CODE (op0)) | |
10449 | { | |
10450 | case ZERO_EXTRACT: | |
10451 | /* If we are extracting a single bit from a variable position in | |
10452 | a constant that has only a single bit set and are comparing it | |
663522cb | 10453 | with zero, we can convert this into an equality comparison |
d7cd794f | 10454 | between the position and the location of the single bit. */ |
230d793d | 10455 | |
230d793d RS |
10456 | if (GET_CODE (XEXP (op0, 0)) == CONST_INT |
10457 | && XEXP (op0, 1) == const1_rtx | |
10458 | && equality_comparison_p && const_op == 0 | |
d7cd794f | 10459 | && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) |
230d793d | 10460 | { |
f76b9db2 | 10461 | if (BITS_BIG_ENDIAN) |
0d8e55d8 | 10462 | { |
da920570 ZW |
10463 | enum machine_mode new_mode |
10464 | = mode_for_extraction (EP_extzv, 1); | |
10465 | if (new_mode == MAX_MACHINE_MODE) | |
10466 | i = BITS_PER_WORD - 1 - i; | |
10467 | else | |
10468 | { | |
10469 | mode = new_mode; | |
10470 | i = (GET_MODE_BITSIZE (mode) - 1 - i); | |
10471 | } | |
0d8e55d8 | 10472 | } |
230d793d RS |
10473 | |
10474 | op0 = XEXP (op0, 2); | |
5f4f0e22 | 10475 | op1 = GEN_INT (i); |
230d793d RS |
10476 | const_op = i; |
10477 | ||
10478 | /* Result is nonzero iff shift count is equal to I. */ | |
10479 | code = reverse_condition (code); | |
10480 | continue; | |
10481 | } | |
230d793d | 10482 | |
0f41302f | 10483 | /* ... fall through ... */ |
230d793d RS |
10484 | |
10485 | case SIGN_EXTRACT: | |
10486 | tem = expand_compound_operation (op0); | |
10487 | if (tem != op0) | |
10488 | { | |
10489 | op0 = tem; | |
10490 | continue; | |
10491 | } | |
10492 | break; | |
10493 | ||
10494 | case NOT: | |
10495 | /* If testing for equality, we can take the NOT of the constant. */ | |
10496 | if (equality_comparison_p | |
10497 | && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) | |
10498 | { | |
10499 | op0 = XEXP (op0, 0); | |
10500 | op1 = tem; | |
10501 | continue; | |
10502 | } | |
10503 | ||
10504 | /* If just looking at the sign bit, reverse the sense of the | |
10505 | comparison. */ | |
10506 | if (sign_bit_comparison_p) | |
10507 | { | |
10508 | op0 = XEXP (op0, 0); | |
10509 | code = (code == GE ? LT : GE); | |
10510 | continue; | |
10511 | } | |
10512 | break; | |
10513 | ||
10514 | case NEG: | |
10515 | /* If testing for equality, we can take the NEG of the constant. */ | |
10516 | if (equality_comparison_p | |
10517 | && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) | |
10518 | { | |
10519 | op0 = XEXP (op0, 0); | |
10520 | op1 = tem; | |
10521 | continue; | |
10522 | } | |
10523 | ||
10524 | /* The remaining cases only apply to comparisons with zero. */ | |
10525 | if (const_op != 0) | |
10526 | break; | |
10527 | ||
10528 | /* When X is ABS or is known positive, | |
10529 | (neg X) is < 0 if and only if X != 0. */ | |
10530 | ||
10531 | if (sign_bit_comparison_p | |
10532 | && (GET_CODE (XEXP (op0, 0)) == ABS | |
5f4f0e22 | 10533 | || (mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 10534 | && (nonzero_bits (XEXP (op0, 0), mode) |
5f4f0e22 | 10535 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) |
230d793d RS |
10536 | { |
10537 | op0 = XEXP (op0, 0); | |
10538 | code = (code == LT ? NE : EQ); | |
10539 | continue; | |
10540 | } | |
10541 | ||
3bed8141 | 10542 | /* If we have NEG of something whose two high-order bits are the |
0f41302f | 10543 | same, we know that "(-a) < 0" is equivalent to "a > 0". */ |
3bed8141 | 10544 | if (num_sign_bit_copies (op0, mode) >= 2) |
230d793d RS |
10545 | { |
10546 | op0 = XEXP (op0, 0); | |
10547 | code = swap_condition (code); | |
10548 | continue; | |
10549 | } | |
10550 | break; | |
10551 | ||
10552 | case ROTATE: | |
10553 | /* If we are testing equality and our count is a constant, we | |
10554 | can perform the inverse operation on our RHS. */ | |
10555 | if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10556 | && (tem = simplify_binary_operation (ROTATERT, mode, | |
10557 | op1, XEXP (op0, 1))) != 0) | |
10558 | { | |
10559 | op0 = XEXP (op0, 0); | |
10560 | op1 = tem; | |
10561 | continue; | |
10562 | } | |
10563 | ||
10564 | /* If we are doing a < 0 or >= 0 comparison, it means we are testing | |
10565 | a particular bit. Convert it to an AND of a constant of that | |
10566 | bit. This will be converted into a ZERO_EXTRACT. */ | |
10567 | if (const_op == 0 && sign_bit_comparison_p | |
10568 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5f4f0e22 | 10569 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
230d793d | 10570 | { |
5f4f0e22 CH |
10571 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10572 | ((HOST_WIDE_INT) 1 | |
10573 | << (mode_width - 1 | |
10574 | - INTVAL (XEXP (op0, 1))))); | |
230d793d RS |
10575 | code = (code == LT ? NE : EQ); |
10576 | continue; | |
10577 | } | |
10578 | ||
663522cb | 10579 | /* Fall through. */ |
230d793d RS |
10580 | |
10581 | case ABS: | |
10582 | /* ABS is ignorable inside an equality comparison with zero. */ | |
10583 | if (const_op == 0 && equality_comparison_p) | |
10584 | { | |
10585 | op0 = XEXP (op0, 0); | |
10586 | continue; | |
10587 | } | |
10588 | break; | |
230d793d RS |
10589 | |
10590 | case SIGN_EXTEND: | |
10591 | /* Can simplify (compare (zero/sign_extend FOO) CONST) | |
663522cb | 10592 | to (compare FOO CONST) if CONST fits in FOO's mode and we |
230d793d RS |
10593 | are either testing inequality or have an unsigned comparison |
10594 | with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */ | |
10595 | if (! unsigned_comparison_p | |
10596 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) | |
5f4f0e22 CH |
10597 | <= HOST_BITS_PER_WIDE_INT) |
10598 | && ((unsigned HOST_WIDE_INT) const_op | |
e51712db | 10599 | < (((unsigned HOST_WIDE_INT) 1 |
5f4f0e22 | 10600 | << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))) |
230d793d RS |
10601 | { |
10602 | op0 = XEXP (op0, 0); | |
10603 | continue; | |
10604 | } | |
10605 | break; | |
10606 | ||
10607 | case SUBREG: | |
a687e897 | 10608 | /* Check for the case where we are comparing A - C1 with C2, |
abc95ed3 | 10609 | both constants are smaller than 1/2 the maximum positive |
a687e897 RK |
10610 | value in MODE, and the comparison is equality or unsigned. |
10611 | In that case, if A is either zero-extended to MODE or has | |
10612 | sufficient sign bits so that the high-order bit in MODE | |
10613 | is a copy of the sign in the inner mode, we can prove that it is | |
10614 | safe to do the operation in the wider mode. This simplifies | |
10615 | many range checks. */ | |
10616 | ||
10617 | if (mode_width <= HOST_BITS_PER_WIDE_INT | |
10618 | && subreg_lowpart_p (op0) | |
10619 | && GET_CODE (SUBREG_REG (op0)) == PLUS | |
10620 | && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT | |
10621 | && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0 | |
663522cb KH |
10622 | && (-INTVAL (XEXP (SUBREG_REG (op0), 1)) |
10623 | < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2)) | |
adb7a1cb | 10624 | && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2 |
951553af RK |
10625 | && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0), |
10626 | GET_MODE (SUBREG_REG (op0))) | |
663522cb | 10627 | & ~GET_MODE_MASK (mode)) |
a687e897 RK |
10628 | || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0), |
10629 | GET_MODE (SUBREG_REG (op0))) | |
26c34780 RS |
10630 | > (unsigned int) |
10631 | (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) | |
a687e897 RK |
10632 | - GET_MODE_BITSIZE (mode))))) |
10633 | { | |
10634 | op0 = SUBREG_REG (op0); | |
10635 | continue; | |
10636 | } | |
10637 | ||
fe0cf571 RK |
10638 | /* If the inner mode is narrower and we are extracting the low part, |
10639 | we can treat the SUBREG as if it were a ZERO_EXTEND. */ | |
10640 | if (subreg_lowpart_p (op0) | |
89f1c7f2 RS |
10641 | && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) |
10642 | /* Fall through */ ; | |
10643 | else | |
230d793d RS |
10644 | break; |
10645 | ||
0f41302f | 10646 | /* ... fall through ... */ |
230d793d RS |
10647 | |
10648 | case ZERO_EXTEND: | |
10649 | if ((unsigned_comparison_p || equality_comparison_p) | |
10650 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) | |
5f4f0e22 CH |
10651 | <= HOST_BITS_PER_WIDE_INT) |
10652 | && ((unsigned HOST_WIDE_INT) const_op | |
230d793d RS |
10653 | < GET_MODE_MASK (GET_MODE (XEXP (op0, 0))))) |
10654 | { | |
10655 | op0 = XEXP (op0, 0); | |
10656 | continue; | |
10657 | } | |
10658 | break; | |
10659 | ||
10660 | case PLUS: | |
20fdd649 | 10661 | /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do |
5089e22e | 10662 | this for equality comparisons due to pathological cases involving |
230d793d | 10663 | overflows. */ |
20fdd649 RK |
10664 | if (equality_comparison_p |
10665 | && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
10666 | op1, XEXP (op0, 1)))) | |
230d793d RS |
10667 | { |
10668 | op0 = XEXP (op0, 0); | |
10669 | op1 = tem; | |
10670 | continue; | |
10671 | } | |
10672 | ||
10673 | /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ | |
10674 | if (const_op == 0 && XEXP (op0, 1) == constm1_rtx | |
10675 | && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) | |
10676 | { | |
10677 | op0 = XEXP (XEXP (op0, 0), 0); | |
10678 | code = (code == LT ? EQ : NE); | |
10679 | continue; | |
10680 | } | |
10681 | break; | |
10682 | ||
10683 | case MINUS: | |
65945ec1 HPN |
10684 | /* We used to optimize signed comparisons against zero, but that |
10685 | was incorrect. Unsigned comparisons against zero (GTU, LEU) | |
10686 | arrive here as equality comparisons, or (GEU, LTU) are | |
10687 | optimized away. No need to special-case them. */ | |
0bd4b461 | 10688 | |
20fdd649 RK |
10689 | /* (eq (minus A B) C) -> (eq A (plus B C)) or |
10690 | (eq B (minus A C)), whichever simplifies. We can only do | |
10691 | this for equality comparisons due to pathological cases involving | |
10692 | overflows. */ | |
10693 | if (equality_comparison_p | |
10694 | && 0 != (tem = simplify_binary_operation (PLUS, mode, | |
10695 | XEXP (op0, 1), op1))) | |
10696 | { | |
10697 | op0 = XEXP (op0, 0); | |
10698 | op1 = tem; | |
10699 | continue; | |
10700 | } | |
10701 | ||
10702 | if (equality_comparison_p | |
10703 | && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
10704 | XEXP (op0, 0), op1))) | |
10705 | { | |
10706 | op0 = XEXP (op0, 1); | |
10707 | op1 = tem; | |
10708 | continue; | |
10709 | } | |
10710 | ||
230d793d RS |
10711 | /* The sign bit of (minus (ashiftrt X C) X), where C is the number |
10712 | of bits in X minus 1, is one iff X > 0. */ | |
10713 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT | |
10714 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
26c34780 RS |
10715 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1)) |
10716 | == mode_width - 1 | |
230d793d RS |
10717 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) |
10718 | { | |
10719 | op0 = XEXP (op0, 1); | |
10720 | code = (code == GE ? LE : GT); | |
10721 | continue; | |
10722 | } | |
10723 | break; | |
10724 | ||
10725 | case XOR: | |
10726 | /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification | |
10727 | if C is zero or B is a constant. */ | |
10728 | if (equality_comparison_p | |
10729 | && 0 != (tem = simplify_binary_operation (XOR, mode, | |
10730 | XEXP (op0, 1), op1))) | |
10731 | { | |
10732 | op0 = XEXP (op0, 0); | |
10733 | op1 = tem; | |
10734 | continue; | |
10735 | } | |
10736 | break; | |
10737 | ||
10738 | case EQ: case NE: | |
69bc0a1f JH |
10739 | case UNEQ: case LTGT: |
10740 | case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: | |
10741 | case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: | |
10742 | case UNORDERED: case ORDERED: | |
230d793d RS |
10743 | /* We can't do anything if OP0 is a condition code value, rather |
10744 | than an actual data value. */ | |
10745 | if (const_op != 0 | |
10746 | #ifdef HAVE_cc0 | |
10747 | || XEXP (op0, 0) == cc0_rtx | |
10748 | #endif | |
10749 | || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) | |
10750 | break; | |
10751 | ||
10752 | /* Get the two operands being compared. */ | |
10753 | if (GET_CODE (XEXP (op0, 0)) == COMPARE) | |
10754 | tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); | |
10755 | else | |
10756 | tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); | |
10757 | ||
10758 | /* Check for the cases where we simply want the result of the | |
10759 | earlier test or the opposite of that result. */ | |
9a915772 | 10760 | if (code == NE || code == EQ |
5f4f0e22 | 10761 | || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT |
3f508eca | 10762 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT |
230d793d | 10763 | && (STORE_FLAG_VALUE |
5f4f0e22 CH |
10764 | & (((HOST_WIDE_INT) 1 |
10765 | << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
aa6683f7 | 10766 | && (code == LT || code == GE))) |
230d793d | 10767 | { |
aa6683f7 GK |
10768 | enum rtx_code new_code; |
10769 | if (code == LT || code == NE) | |
10770 | new_code = GET_CODE (op0); | |
10771 | else | |
10772 | new_code = combine_reversed_comparison_code (op0); | |
23190837 | 10773 | |
aa6683f7 | 10774 | if (new_code != UNKNOWN) |
9a915772 | 10775 | { |
aa6683f7 GK |
10776 | code = new_code; |
10777 | op0 = tem; | |
10778 | op1 = tem1; | |
9a915772 JH |
10779 | continue; |
10780 | } | |
230d793d RS |
10781 | } |
10782 | break; | |
10783 | ||
10784 | case IOR: | |
da7d8304 | 10785 | /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero |
230d793d RS |
10786 | iff X <= 0. */ |
10787 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS | |
10788 | && XEXP (XEXP (op0, 0), 1) == constm1_rtx | |
10789 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) | |
10790 | { | |
10791 | op0 = XEXP (op0, 1); | |
10792 | code = (code == GE ? GT : LE); | |
10793 | continue; | |
10794 | } | |
10795 | break; | |
10796 | ||
10797 | case AND: | |
10798 | /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This | |
10799 | will be converted to a ZERO_EXTRACT later. */ | |
10800 | if (const_op == 0 && equality_comparison_p | |
45620ed4 | 10801 | && GET_CODE (XEXP (op0, 0)) == ASHIFT |
230d793d RS |
10802 | && XEXP (XEXP (op0, 0), 0) == const1_rtx) |
10803 | { | |
10804 | op0 = simplify_and_const_int | |
f1c6ba8b RK |
10805 | (op0, mode, gen_rtx_LSHIFTRT (mode, |
10806 | XEXP (op0, 1), | |
10807 | XEXP (XEXP (op0, 0), 1)), | |
5f4f0e22 | 10808 | (HOST_WIDE_INT) 1); |
230d793d RS |
10809 | continue; |
10810 | } | |
10811 | ||
10812 | /* If we are comparing (and (lshiftrt X C1) C2) for equality with | |
10813 | zero and X is a comparison and C1 and C2 describe only bits set | |
10814 | in STORE_FLAG_VALUE, we can compare with X. */ | |
10815 | if (const_op == 0 && equality_comparison_p | |
5f4f0e22 | 10816 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d RS |
10817 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
10818 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT | |
10819 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10820 | && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 | |
5f4f0e22 | 10821 | && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) |
230d793d RS |
10822 | { |
10823 | mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) | |
10824 | << INTVAL (XEXP (XEXP (op0, 0), 1))); | |
663522cb | 10825 | if ((~STORE_FLAG_VALUE & mask) == 0 |
230d793d RS |
10826 | && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<' |
10827 | || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 | |
10828 | && GET_RTX_CLASS (GET_CODE (tem)) == '<'))) | |
10829 | { | |
10830 | op0 = XEXP (XEXP (op0, 0), 0); | |
10831 | continue; | |
10832 | } | |
10833 | } | |
10834 | ||
10835 | /* If we are doing an equality comparison of an AND of a bit equal | |
10836 | to the sign bit, replace this with a LT or GE comparison of | |
10837 | the underlying value. */ | |
10838 | if (equality_comparison_p | |
10839 | && const_op == 0 | |
10840 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5f4f0e22 | 10841 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d | 10842 | && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) |
e51712db | 10843 | == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) |
230d793d RS |
10844 | { |
10845 | op0 = XEXP (op0, 0); | |
10846 | code = (code == EQ ? GE : LT); | |
10847 | continue; | |
10848 | } | |
10849 | ||
10850 | /* If this AND operation is really a ZERO_EXTEND from a narrower | |
10851 | mode, the constant fits within that mode, and this is either an | |
10852 | equality or unsigned comparison, try to do this comparison in | |
10853 | the narrower mode. */ | |
10854 | if ((equality_comparison_p || unsigned_comparison_p) | |
10855 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10856 | && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) | |
10857 | & GET_MODE_MASK (mode)) | |
10858 | + 1)) >= 0 | |
10859 | && const_op >> i == 0 | |
10860 | && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) | |
10861 | { | |
10862 | op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0)); | |
10863 | continue; | |
10864 | } | |
e5e809f4 JL |
10865 | |
10866 | /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits | |
10867 | in both M1 and M2 and the SUBREG is either paradoxical or | |
10868 | represents the low part, permute the SUBREG and the AND and | |
10869 | try again. */ | |
10870 | if (GET_CODE (XEXP (op0, 0)) == SUBREG | |
c5c76735 | 10871 | && (0 |
9ec36da5 | 10872 | #ifdef WORD_REGISTER_OPERATIONS |
c5c76735 JL |
10873 | || ((mode_width |
10874 | > (GET_MODE_BITSIZE | |
10875 | (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) | |
10876 | && mode_width <= BITS_PER_WORD) | |
9ec36da5 | 10877 | #endif |
c5c76735 JL |
10878 | || ((mode_width |
10879 | <= (GET_MODE_BITSIZE | |
10880 | (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) | |
10881 | && subreg_lowpart_p (XEXP (op0, 0)))) | |
adc05e6c JL |
10882 | #ifndef WORD_REGISTER_OPERATIONS |
10883 | /* It is unsafe to commute the AND into the SUBREG if the SUBREG | |
10884 | is paradoxical and WORD_REGISTER_OPERATIONS is not defined. | |
10885 | As originally written the upper bits have a defined value | |
10886 | due to the AND operation. However, if we commute the AND | |
10887 | inside the SUBREG then they no longer have defined values | |
10888 | and the meaning of the code has been changed. */ | |
10889 | && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) | |
10890 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) | |
10891 | #endif | |
e5e809f4 JL |
10892 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
10893 | && mode_width <= HOST_BITS_PER_WIDE_INT | |
10894 | && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) | |
10895 | <= HOST_BITS_PER_WIDE_INT) | |
663522cb KH |
10896 | && (INTVAL (XEXP (op0, 1)) & ~mask) == 0 |
10897 | && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) | |
9ec36da5 | 10898 | & INTVAL (XEXP (op0, 1))) |
e51712db KG |
10899 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask |
10900 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) | |
9ec36da5 | 10901 | != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) |
663522cb | 10902 | |
e5e809f4 JL |
10903 | { |
10904 | op0 | |
10905 | = gen_lowpart_for_combine | |
10906 | (mode, | |
10907 | gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))), | |
10908 | SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1))); | |
10909 | continue; | |
10910 | } | |
10911 | ||
9f8e169e RH |
10912 | /* Convert (ne (and (lshiftrt (not X)) 1) 0) to |
10913 | (eq (and (lshiftrt X) 1) 0). */ | |
10914 | if (const_op == 0 && equality_comparison_p | |
10915 | && XEXP (op0, 1) == const1_rtx | |
10916 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT | |
10917 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT) | |
10918 | { | |
10919 | op0 = simplify_and_const_int | |
f1c6ba8b RK |
10920 | (op0, mode, |
10921 | gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0), | |
10922 | XEXP (XEXP (op0, 0), 1)), | |
9f8e169e RH |
10923 | (HOST_WIDE_INT) 1); |
10924 | code = (code == NE ? EQ : NE); | |
10925 | continue; | |
10926 | } | |
230d793d RS |
10927 | break; |
10928 | ||
10929 | case ASHIFT: | |
45620ed4 | 10930 | /* If we have (compare (ashift FOO N) (const_int C)) and |
230d793d | 10931 | the high order N bits of FOO (N+1 if an inequality comparison) |
951553af | 10932 | are known to be zero, we can do this by comparing FOO with C |
230d793d RS |
10933 | shifted right N bits so long as the low-order N bits of C are |
10934 | zero. */ | |
10935 | if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10936 | && INTVAL (XEXP (op0, 1)) >= 0 | |
10937 | && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) | |
5f4f0e22 CH |
10938 | < HOST_BITS_PER_WIDE_INT) |
10939 | && ((const_op | |
34785d05 | 10940 | & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) |
5f4f0e22 | 10941 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 10942 | && (nonzero_bits (XEXP (op0, 0), mode) |
663522cb KH |
10943 | & ~(mask >> (INTVAL (XEXP (op0, 1)) |
10944 | + ! equality_comparison_p))) == 0) | |
230d793d | 10945 | { |
7ce787fe NC |
10946 | /* We must perform a logical shift, not an arithmetic one, |
10947 | as we want the top N bits of C to be zero. */ | |
aaaec114 | 10948 | unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); |
663522cb | 10949 | |
7ce787fe | 10950 | temp >>= INTVAL (XEXP (op0, 1)); |
2496c7bd | 10951 | op1 = gen_int_mode (temp, mode); |
230d793d RS |
10952 | op0 = XEXP (op0, 0); |
10953 | continue; | |
10954 | } | |
10955 | ||
dfbe1b2f | 10956 | /* If we are doing a sign bit comparison, it means we are testing |
230d793d | 10957 | a particular bit. Convert it to the appropriate AND. */ |
dfbe1b2f | 10958 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT |
5f4f0e22 | 10959 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
230d793d | 10960 | { |
5f4f0e22 CH |
10961 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10962 | ((HOST_WIDE_INT) 1 | |
10963 | << (mode_width - 1 | |
10964 | - INTVAL (XEXP (op0, 1))))); | |
230d793d RS |
10965 | code = (code == LT ? NE : EQ); |
10966 | continue; | |
10967 | } | |
dfbe1b2f RK |
10968 | |
10969 | /* If this an equality comparison with zero and we are shifting | |
10970 | the low bit to the sign bit, we can convert this to an AND of the | |
10971 | low-order bit. */ | |
10972 | if (const_op == 0 && equality_comparison_p | |
10973 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
26c34780 RS |
10974 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) |
10975 | == mode_width - 1) | |
dfbe1b2f | 10976 | { |
5f4f0e22 CH |
10977 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10978 | (HOST_WIDE_INT) 1); | |
dfbe1b2f RK |
10979 | continue; |
10980 | } | |
230d793d RS |
10981 | break; |
10982 | ||
10983 | case ASHIFTRT: | |
d0ab8cd3 RK |
10984 | /* If this is an equality comparison with zero, we can do this |
10985 | as a logical shift, which might be much simpler. */ | |
10986 | if (equality_comparison_p && const_op == 0 | |
10987 | && GET_CODE (XEXP (op0, 1)) == CONST_INT) | |
10988 | { | |
10989 | op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, | |
10990 | XEXP (op0, 0), | |
10991 | INTVAL (XEXP (op0, 1))); | |
10992 | continue; | |
10993 | } | |
10994 | ||
230d793d RS |
10995 | /* If OP0 is a sign extension and CODE is not an unsigned comparison, |
10996 | do the comparison in a narrower mode. */ | |
10997 | if (! unsigned_comparison_p | |
10998 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10999 | && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
11000 | && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
11001 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
22331794 | 11002 | MODE_INT, 1)) != BLKmode |
67e469d7 AM |
11003 | && (((unsigned HOST_WIDE_INT) const_op |
11004 | + (GET_MODE_MASK (tmode) >> 1) + 1) | |
11005 | <= GET_MODE_MASK (tmode))) | |
230d793d RS |
11006 | { |
11007 | op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0)); | |
11008 | continue; | |
11009 | } | |
11010 | ||
14a774a9 RK |
11011 | /* Likewise if OP0 is a PLUS of a sign extension with a |
11012 | constant, which is usually represented with the PLUS | |
11013 | between the shifts. */ | |
11014 | if (! unsigned_comparison_p | |
11015 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
11016 | && GET_CODE (XEXP (op0, 0)) == PLUS | |
11017 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
11018 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT | |
11019 | && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) | |
11020 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
11021 | MODE_INT, 1)) != BLKmode | |
67e469d7 AM |
11022 | && (((unsigned HOST_WIDE_INT) const_op |
11023 | + (GET_MODE_MASK (tmode) >> 1) + 1) | |
11024 | <= GET_MODE_MASK (tmode))) | |
14a774a9 RK |
11025 | { |
11026 | rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); | |
11027 | rtx add_const = XEXP (XEXP (op0, 0), 1); | |
11028 | rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const, | |
11029 | XEXP (op0, 1)); | |
11030 | ||
11031 | op0 = gen_binary (PLUS, tmode, | |
11032 | gen_lowpart_for_combine (tmode, inner), | |
11033 | new_const); | |
11034 | continue; | |
11035 | } | |
11036 | ||
0f41302f | 11037 | /* ... fall through ... */ |
230d793d RS |
11038 | case LSHIFTRT: |
11039 | /* If we have (compare (xshiftrt FOO N) (const_int C)) and | |
951553af | 11040 | the low order N bits of FOO are known to be zero, we can do this |
230d793d RS |
11041 | by comparing FOO with C shifted left N bits so long as no |
11042 | overflow occurs. */ | |
11043 | if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
11044 | && INTVAL (XEXP (op0, 1)) >= 0 | |
5f4f0e22 CH |
11045 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT |
11046 | && mode_width <= HOST_BITS_PER_WIDE_INT | |
951553af | 11047 | && (nonzero_bits (XEXP (op0, 0), mode) |
5f4f0e22 | 11048 | & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 |
67e469d7 AM |
11049 | && (((unsigned HOST_WIDE_INT) const_op |
11050 | + (GET_CODE (op0) != LSHIFTRT | |
11051 | ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) | |
11052 | + 1) | |
11053 | : 0)) | |
11054 | <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) | |
230d793d | 11055 | { |
145d3bf2 RE |
11056 | /* If the shift was logical, then we must make the condition |
11057 | unsigned. */ | |
11058 | if (GET_CODE (op0) == LSHIFTRT) | |
11059 | code = unsigned_condition (code); | |
11060 | ||
230d793d | 11061 | const_op <<= INTVAL (XEXP (op0, 1)); |
5f4f0e22 | 11062 | op1 = GEN_INT (const_op); |
230d793d RS |
11063 | op0 = XEXP (op0, 0); |
11064 | continue; | |
11065 | } | |
11066 | ||
11067 | /* If we are using this shift to extract just the sign bit, we | |
11068 | can replace this with an LT or GE comparison. */ | |
11069 | if (const_op == 0 | |
11070 | && (equality_comparison_p || sign_bit_comparison_p) | |
11071 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
26c34780 RS |
11072 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) |
11073 | == mode_width - 1) | |
230d793d RS |
11074 | { |
11075 | op0 = XEXP (op0, 0); | |
11076 | code = (code == NE || code == GT ? LT : GE); | |
11077 | continue; | |
11078 | } | |
11079 | break; | |
663522cb | 11080 | |
e9a25f70 JL |
11081 | default: |
11082 | break; | |
230d793d RS |
11083 | } |
11084 | ||
11085 | break; | |
11086 | } | |
11087 | ||
11088 | /* Now make any compound operations involved in this comparison. Then, | |
76d31c63 | 11089 | check for an outmost SUBREG on OP0 that is not doing anything or is |
5add6d1a JL |
11090 | paradoxical. The latter transformation must only be performed when |
11091 | it is known that the "extra" bits will be the same in op0 and op1 or | |
11092 | that they don't matter. There are three cases to consider: | |
11093 | ||
11094 | 1. SUBREG_REG (op0) is a register. In this case the bits are don't | |
11095 | care bits and we can assume they have any convenient value. So | |
11096 | making the transformation is safe. | |
11097 | ||
11098 | 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. | |
11099 | In this case the upper bits of op0 are undefined. We should not make | |
11100 | the simplification in that case as we do not know the contents of | |
11101 | those bits. | |
11102 | ||
11103 | 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not | |
11104 | NIL. In that case we know those bits are zeros or ones. We must | |
11105 | also be sure that they are the same as the upper bits of op1. | |
11106 | ||
11107 | We can never remove a SUBREG for a non-equality comparison because | |
11108 | the sign bit is in a different place in the underlying object. */ | |
230d793d RS |
11109 | |
11110 | op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); | |
11111 | op1 = make_compound_operation (op1, SET); | |
11112 | ||
11113 | if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) | |
5add6d1a JL |
11114 | /* Case 3 above, to sometimes allow (subreg (mem x)), isn't |
11115 | implemented. */ | |
11116 | && GET_CODE (SUBREG_REG (op0)) == REG | |
230d793d | 11117 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT |
fa4e13e0 | 11118 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT |
5add6d1a | 11119 | && (code == NE || code == EQ)) |
230d793d | 11120 | { |
5add6d1a JL |
11121 | if (GET_MODE_SIZE (GET_MODE (op0)) |
11122 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))) | |
11123 | { | |
11124 | op0 = SUBREG_REG (op0); | |
11125 | op1 = gen_lowpart_for_combine (GET_MODE (op0), op1); | |
11126 | } | |
11127 | else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) | |
11128 | <= HOST_BITS_PER_WIDE_INT) | |
11129 | && (nonzero_bits (SUBREG_REG (op0), | |
11130 | GET_MODE (SUBREG_REG (op0))) | |
11131 | & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
11132 | { | |
11133 | tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1); | |
230d793d | 11134 | |
5add6d1a JL |
11135 | if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) |
11136 | & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
11137 | op0 = SUBREG_REG (op0), op1 = tem; | |
11138 | } | |
11139 | } | |
230d793d RS |
11140 | |
11141 | /* We now do the opposite procedure: Some machines don't have compare | |
11142 | insns in all modes. If OP0's mode is an integer mode smaller than a | |
11143 | word and we can't do a compare in that mode, see if there is a larger | |
a687e897 RK |
11144 | mode for which we can do the compare. There are a number of cases in |
11145 | which we can use the wider mode. */ | |
230d793d RS |
11146 | |
11147 | mode = GET_MODE (op0); | |
11148 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
11149 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
ef89d648 | 11150 | && ! have_insn_for (COMPARE, mode)) |
230d793d | 11151 | for (tmode = GET_MODE_WIDER_MODE (mode); |
5f4f0e22 CH |
11152 | (tmode != VOIDmode |
11153 | && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); | |
230d793d | 11154 | tmode = GET_MODE_WIDER_MODE (tmode)) |
ef89d648 | 11155 | if (have_insn_for (COMPARE, tmode)) |
230d793d | 11156 | { |
d4c5ac1f AM |
11157 | int zero_extended; |
11158 | ||
951553af | 11159 | /* If the only nonzero bits in OP0 and OP1 are those in the |
a687e897 RK |
11160 | narrower mode and this is an equality or unsigned comparison, |
11161 | we can use the wider mode. Similarly for sign-extended | |
7e4dc511 | 11162 | values, in which case it is true for all comparisons. */ |
d4c5ac1f AM |
11163 | zero_extended = ((code == EQ || code == NE |
11164 | || code == GEU || code == GTU | |
11165 | || code == LEU || code == LTU) | |
11166 | && (nonzero_bits (op0, tmode) | |
11167 | & ~GET_MODE_MASK (mode)) == 0 | |
11168 | && ((GET_CODE (op1) == CONST_INT | |
11169 | || (nonzero_bits (op1, tmode) | |
11170 | & ~GET_MODE_MASK (mode)) == 0))); | |
11171 | ||
11172 | if (zero_extended | |
7e4dc511 | 11173 | || ((num_sign_bit_copies (op0, tmode) |
26c34780 RS |
11174 | > (unsigned int) (GET_MODE_BITSIZE (tmode) |
11175 | - GET_MODE_BITSIZE (mode))) | |
a687e897 | 11176 | && (num_sign_bit_copies (op1, tmode) |
26c34780 RS |
11177 | > (unsigned int) (GET_MODE_BITSIZE (tmode) |
11178 | - GET_MODE_BITSIZE (mode))))) | |
a687e897 | 11179 | { |
14a774a9 RK |
11180 | /* If OP0 is an AND and we don't have an AND in MODE either, |
11181 | make a new AND in the proper mode. */ | |
11182 | if (GET_CODE (op0) == AND | |
ef89d648 | 11183 | && !have_insn_for (AND, mode)) |
14a774a9 RK |
11184 | op0 = gen_binary (AND, tmode, |
11185 | gen_lowpart_for_combine (tmode, | |
11186 | XEXP (op0, 0)), | |
11187 | gen_lowpart_for_combine (tmode, | |
11188 | XEXP (op0, 1))); | |
11189 | ||
a687e897 | 11190 | op0 = gen_lowpart_for_combine (tmode, op0); |
d4c5ac1f AM |
11191 | if (zero_extended && GET_CODE (op1) == CONST_INT) |
11192 | op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode)); | |
a687e897 RK |
11193 | op1 = gen_lowpart_for_combine (tmode, op1); |
11194 | break; | |
11195 | } | |
230d793d | 11196 | |
a687e897 RK |
11197 | /* If this is a test for negative, we can make an explicit |
11198 | test of the sign bit. */ | |
11199 | ||
11200 | if (op1 == const0_rtx && (code == LT || code == GE) | |
11201 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
230d793d | 11202 | { |
a687e897 RK |
11203 | op0 = gen_binary (AND, tmode, |
11204 | gen_lowpart_for_combine (tmode, op0), | |
5f4f0e22 CH |
11205 | GEN_INT ((HOST_WIDE_INT) 1 |
11206 | << (GET_MODE_BITSIZE (mode) - 1))); | |
230d793d | 11207 | code = (code == LT) ? NE : EQ; |
a687e897 | 11208 | break; |
230d793d | 11209 | } |
230d793d RS |
11210 | } |
11211 | ||
b7a775b2 RK |
11212 | #ifdef CANONICALIZE_COMPARISON |
11213 | /* If this machine only supports a subset of valid comparisons, see if we | |
11214 | can convert an unsupported one into a supported one. */ | |
11215 | CANONICALIZE_COMPARISON (code, op0, op1); | |
11216 | #endif | |
11217 | ||
230d793d RS |
11218 | *pop0 = op0; |
11219 | *pop1 = op1; | |
11220 | ||
11221 | return code; | |
11222 | } | |
11223 | \f | |
9a915772 JH |
11224 | /* Like jump.c' reversed_comparison_code, but use combine infrastructure for |
11225 | searching backward. */ | |
c3ffea50 | 11226 | static enum rtx_code |
9a915772 JH |
11227 | combine_reversed_comparison_code (exp) |
11228 | rtx exp; | |
230d793d | 11229 | { |
cf0d9408 KH |
11230 | enum rtx_code code1 = reversed_comparison_code (exp, NULL); |
11231 | rtx x; | |
11232 | ||
11233 | if (code1 != UNKNOWN | |
11234 | || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC) | |
11235 | return code1; | |
11236 | /* Otherwise try and find where the condition codes were last set and | |
11237 | use that. */ | |
11238 | x = get_last_value (XEXP (exp, 0)); | |
11239 | if (!x || GET_CODE (x) != COMPARE) | |
11240 | return UNKNOWN; | |
11241 | return reversed_comparison_code_parts (GET_CODE (exp), | |
11242 | XEXP (x, 0), XEXP (x, 1), NULL); | |
9a915772 JH |
11243 | } |
11244 | /* Return comparison with reversed code of EXP and operands OP0 and OP1. | |
11245 | Return NULL_RTX in case we fail to do the reversal. */ | |
11246 | static rtx | |
11247 | reversed_comparison (exp, mode, op0, op1) | |
11248 | rtx exp, op0, op1; | |
11249 | enum machine_mode mode; | |
11250 | { | |
11251 | enum rtx_code reversed_code = combine_reversed_comparison_code (exp); | |
11252 | if (reversed_code == UNKNOWN) | |
11253 | return NULL_RTX; | |
11254 | else | |
11255 | return gen_binary (reversed_code, mode, op0, op1); | |
230d793d RS |
11256 | } |
11257 | \f | |
11258 | /* Utility function for following routine. Called when X is part of a value | |
11259 | being stored into reg_last_set_value. Sets reg_last_set_table_tick | |
11260 | for each register mentioned. Similar to mention_regs in cse.c */ | |
11261 | ||
11262 | static void | |
11263 | update_table_tick (x) | |
11264 | rtx x; | |
11265 | { | |
b3694847 SS |
11266 | enum rtx_code code = GET_CODE (x); |
11267 | const char *fmt = GET_RTX_FORMAT (code); | |
11268 | int i; | |
230d793d RS |
11269 | |
11270 | if (code == REG) | |
11271 | { | |
770ae6cc RK |
11272 | unsigned int regno = REGNO (x); |
11273 | unsigned int endregno | |
11274 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
11275 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
11276 | unsigned int r; | |
230d793d | 11277 | |
770ae6cc RK |
11278 | for (r = regno; r < endregno; r++) |
11279 | reg_last_set_table_tick[r] = label_tick; | |
230d793d RS |
11280 | |
11281 | return; | |
11282 | } | |
663522cb | 11283 | |
230d793d RS |
11284 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
11285 | /* Note that we can't have an "E" in values stored; see | |
11286 | get_last_value_validate. */ | |
11287 | if (fmt[i] == 'e') | |
11288 | update_table_tick (XEXP (x, i)); | |
11289 | } | |
11290 | ||
11291 | /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we | |
11292 | are saying that the register is clobbered and we no longer know its | |
7988fd36 RK |
11293 | value. If INSN is zero, don't update reg_last_set; this is only permitted |
11294 | with VALUE also zero and is used to invalidate the register. */ | |
230d793d RS |
11295 | |
11296 | static void | |
11297 | record_value_for_reg (reg, insn, value) | |
11298 | rtx reg; | |
11299 | rtx insn; | |
11300 | rtx value; | |
11301 | { | |
770ae6cc RK |
11302 | unsigned int regno = REGNO (reg); |
11303 | unsigned int endregno | |
11304 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
11305 | ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1); | |
11306 | unsigned int i; | |
230d793d RS |
11307 | |
11308 | /* If VALUE contains REG and we have a previous value for REG, substitute | |
11309 | the previous value. */ | |
11310 | if (value && insn && reg_overlap_mentioned_p (reg, value)) | |
11311 | { | |
11312 | rtx tem; | |
11313 | ||
11314 | /* Set things up so get_last_value is allowed to see anything set up to | |
11315 | our insn. */ | |
11316 | subst_low_cuid = INSN_CUID (insn); | |
663522cb | 11317 | tem = get_last_value (reg); |
230d793d | 11318 | |
14a774a9 RK |
11319 | /* If TEM is simply a binary operation with two CLOBBERs as operands, |
11320 | it isn't going to be useful and will take a lot of time to process, | |
11321 | so just use the CLOBBER. */ | |
11322 | ||
230d793d | 11323 | if (tem) |
14a774a9 RK |
11324 | { |
11325 | if ((GET_RTX_CLASS (GET_CODE (tem)) == '2' | |
11326 | || GET_RTX_CLASS (GET_CODE (tem)) == 'c') | |
11327 | && GET_CODE (XEXP (tem, 0)) == CLOBBER | |
11328 | && GET_CODE (XEXP (tem, 1)) == CLOBBER) | |
11329 | tem = XEXP (tem, 0); | |
11330 | ||
11331 | value = replace_rtx (copy_rtx (value), reg, tem); | |
11332 | } | |
230d793d RS |
11333 | } |
11334 | ||
11335 | /* For each register modified, show we don't know its value, that | |
ef026f91 RS |
11336 | we don't know about its bitwise content, that its value has been |
11337 | updated, and that we don't know the location of the death of the | |
11338 | register. */ | |
770ae6cc | 11339 | for (i = regno; i < endregno; i++) |
230d793d RS |
11340 | { |
11341 | if (insn) | |
11342 | reg_last_set[i] = insn; | |
770ae6cc | 11343 | |
230d793d | 11344 | reg_last_set_value[i] = 0; |
ef026f91 RS |
11345 | reg_last_set_mode[i] = 0; |
11346 | reg_last_set_nonzero_bits[i] = 0; | |
11347 | reg_last_set_sign_bit_copies[i] = 0; | |
230d793d RS |
11348 | reg_last_death[i] = 0; |
11349 | } | |
11350 | ||
11351 | /* Mark registers that are being referenced in this value. */ | |
11352 | if (value) | |
11353 | update_table_tick (value); | |
11354 | ||
11355 | /* Now update the status of each register being set. | |
11356 | If someone is using this register in this block, set this register | |
11357 | to invalid since we will get confused between the two lives in this | |
11358 | basic block. This makes using this register always invalid. In cse, we | |
11359 | scan the table to invalidate all entries using this register, but this | |
11360 | is too much work for us. */ | |
11361 | ||
11362 | for (i = regno; i < endregno; i++) | |
11363 | { | |
11364 | reg_last_set_label[i] = label_tick; | |
11365 | if (value && reg_last_set_table_tick[i] == label_tick) | |
11366 | reg_last_set_invalid[i] = 1; | |
11367 | else | |
11368 | reg_last_set_invalid[i] = 0; | |
11369 | } | |
11370 | ||
11371 | /* The value being assigned might refer to X (like in "x++;"). In that | |
11372 | case, we must replace it with (clobber (const_int 0)) to prevent | |
11373 | infinite loops. */ | |
9a893315 | 11374 | if (value && ! get_last_value_validate (&value, insn, |
230d793d RS |
11375 | reg_last_set_label[regno], 0)) |
11376 | { | |
11377 | value = copy_rtx (value); | |
9a893315 JW |
11378 | if (! get_last_value_validate (&value, insn, |
11379 | reg_last_set_label[regno], 1)) | |
230d793d RS |
11380 | value = 0; |
11381 | } | |
11382 | ||
55310dad RK |
11383 | /* For the main register being modified, update the value, the mode, the |
11384 | nonzero bits, and the number of sign bit copies. */ | |
11385 | ||
230d793d RS |
11386 | reg_last_set_value[regno] = value; |
11387 | ||
55310dad RK |
11388 | if (value) |
11389 | { | |
0a0440c9 | 11390 | enum machine_mode mode = GET_MODE (reg); |
2afabb48 | 11391 | subst_low_cuid = INSN_CUID (insn); |
0a0440c9 JJ |
11392 | reg_last_set_mode[regno] = mode; |
11393 | if (GET_MODE_CLASS (mode) == MODE_INT | |
11394 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
11395 | mode = nonzero_bits_mode; | |
11396 | reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode); | |
55310dad RK |
11397 | reg_last_set_sign_bit_copies[regno] |
11398 | = num_sign_bit_copies (value, GET_MODE (reg)); | |
11399 | } | |
230d793d RS |
11400 | } |
11401 | ||
230d793d | 11402 | /* Called via note_stores from record_dead_and_set_regs to handle one |
84832317 MM |
11403 | SET or CLOBBER in an insn. DATA is the instruction in which the |
11404 | set is occurring. */ | |
230d793d RS |
11405 | |
11406 | static void | |
84832317 | 11407 | record_dead_and_set_regs_1 (dest, setter, data) |
230d793d | 11408 | rtx dest, setter; |
84832317 | 11409 | void *data; |
230d793d | 11410 | { |
84832317 MM |
11411 | rtx record_dead_insn = (rtx) data; |
11412 | ||
ca89d290 RK |
11413 | if (GET_CODE (dest) == SUBREG) |
11414 | dest = SUBREG_REG (dest); | |
11415 | ||
230d793d RS |
11416 | if (GET_CODE (dest) == REG) |
11417 | { | |
11418 | /* If we are setting the whole register, we know its value. Otherwise | |
11419 | show that we don't know the value. We can handle SUBREG in | |
11420 | some cases. */ | |
11421 | if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) | |
11422 | record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); | |
11423 | else if (GET_CODE (setter) == SET | |
11424 | && GET_CODE (SET_DEST (setter)) == SUBREG | |
11425 | && SUBREG_REG (SET_DEST (setter)) == dest | |
90bf8081 | 11426 | && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD |
230d793d | 11427 | && subreg_lowpart_p (SET_DEST (setter))) |
d0ab8cd3 RK |
11428 | record_value_for_reg (dest, record_dead_insn, |
11429 | gen_lowpart_for_combine (GET_MODE (dest), | |
11430 | SET_SRC (setter))); | |
230d793d | 11431 | else |
5f4f0e22 | 11432 | record_value_for_reg (dest, record_dead_insn, NULL_RTX); |
230d793d RS |
11433 | } |
11434 | else if (GET_CODE (dest) == MEM | |
11435 | /* Ignore pushes, they clobber nothing. */ | |
11436 | && ! push_operand (dest, GET_MODE (dest))) | |
11437 | mem_last_set = INSN_CUID (record_dead_insn); | |
11438 | } | |
11439 | ||
11440 | /* Update the records of when each REG was most recently set or killed | |
11441 | for the things done by INSN. This is the last thing done in processing | |
11442 | INSN in the combiner loop. | |
11443 | ||
ef026f91 RS |
11444 | We update reg_last_set, reg_last_set_value, reg_last_set_mode, |
11445 | reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death, | |
11446 | and also the similar information mem_last_set (which insn most recently | |
11447 | modified memory) and last_call_cuid (which insn was the most recent | |
11448 | subroutine call). */ | |
230d793d RS |
11449 | |
11450 | static void | |
11451 | record_dead_and_set_regs (insn) | |
11452 | rtx insn; | |
11453 | { | |
b3694847 | 11454 | rtx link; |
770ae6cc | 11455 | unsigned int i; |
55310dad | 11456 | |
230d793d RS |
11457 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
11458 | { | |
dbc131f3 RK |
11459 | if (REG_NOTE_KIND (link) == REG_DEAD |
11460 | && GET_CODE (XEXP (link, 0)) == REG) | |
11461 | { | |
770ae6cc RK |
11462 | unsigned int regno = REGNO (XEXP (link, 0)); |
11463 | unsigned int endregno | |
dbc131f3 RK |
11464 | = regno + (regno < FIRST_PSEUDO_REGISTER |
11465 | ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0))) | |
11466 | : 1); | |
dbc131f3 RK |
11467 | |
11468 | for (i = regno; i < endregno; i++) | |
11469 | reg_last_death[i] = insn; | |
11470 | } | |
230d793d | 11471 | else if (REG_NOTE_KIND (link) == REG_INC) |
5f4f0e22 | 11472 | record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); |
230d793d RS |
11473 | } |
11474 | ||
11475 | if (GET_CODE (insn) == CALL_INSN) | |
55310dad RK |
11476 | { |
11477 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
29655d3d | 11478 | if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) |
55310dad RK |
11479 | { |
11480 | reg_last_set_value[i] = 0; | |
ef026f91 RS |
11481 | reg_last_set_mode[i] = 0; |
11482 | reg_last_set_nonzero_bits[i] = 0; | |
11483 | reg_last_set_sign_bit_copies[i] = 0; | |
55310dad RK |
11484 | reg_last_death[i] = 0; |
11485 | } | |
11486 | ||
11487 | last_call_cuid = mem_last_set = INSN_CUID (insn); | |
29655d3d ZW |
11488 | |
11489 | /* Don't bother recording what this insn does. It might set the | |
11490 | return value register, but we can't combine into a call | |
11491 | pattern anyway, so there's no point trying (and it may cause | |
11492 | a crash, if e.g. we wind up asking for last_set_value of a | |
11493 | SUBREG of the return value register). */ | |
11494 | return; | |
55310dad | 11495 | } |
230d793d | 11496 | |
84832317 | 11497 | note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); |
230d793d | 11498 | } |
732f2ac9 | 11499 | |
732f2ac9 JJ |
11500 | /* If a SUBREG has the promoted bit set, it is in fact a property of the |
11501 | register present in the SUBREG, so for each such SUBREG go back and | |
11502 | adjust nonzero and sign bit information of the registers that are | |
11503 | known to have some zero/sign bits set. | |
11504 | ||
11505 | This is needed because when combine blows the SUBREGs away, the | |
11506 | information on zero/sign bits is lost and further combines can be | |
11507 | missed because of that. */ | |
11508 | ||
11509 | static void | |
11510 | record_promoted_value (insn, subreg) | |
663522cb KH |
11511 | rtx insn; |
11512 | rtx subreg; | |
732f2ac9 | 11513 | { |
4a71b24f | 11514 | rtx links, set; |
770ae6cc | 11515 | unsigned int regno = REGNO (SUBREG_REG (subreg)); |
732f2ac9 JJ |
11516 | enum machine_mode mode = GET_MODE (subreg); |
11517 | ||
25af74a0 | 11518 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
732f2ac9 JJ |
11519 | return; |
11520 | ||
663522cb | 11521 | for (links = LOG_LINKS (insn); links;) |
732f2ac9 JJ |
11522 | { |
11523 | insn = XEXP (links, 0); | |
11524 | set = single_set (insn); | |
11525 | ||
11526 | if (! set || GET_CODE (SET_DEST (set)) != REG | |
11527 | || REGNO (SET_DEST (set)) != regno | |
11528 | || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) | |
11529 | { | |
11530 | links = XEXP (links, 1); | |
11531 | continue; | |
11532 | } | |
11533 | ||
663522cb KH |
11534 | if (reg_last_set[regno] == insn) |
11535 | { | |
7879b81e | 11536 | if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0) |
663522cb KH |
11537 | reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode); |
11538 | } | |
732f2ac9 JJ |
11539 | |
11540 | if (GET_CODE (SET_SRC (set)) == REG) | |
11541 | { | |
11542 | regno = REGNO (SET_SRC (set)); | |
11543 | links = LOG_LINKS (insn); | |
11544 | } | |
11545 | else | |
11546 | break; | |
11547 | } | |
11548 | } | |
11549 | ||
11550 | /* Scan X for promoted SUBREGs. For each one found, | |
11551 | note what it implies to the registers used in it. */ | |
11552 | ||
11553 | static void | |
11554 | check_promoted_subreg (insn, x) | |
663522cb KH |
11555 | rtx insn; |
11556 | rtx x; | |
732f2ac9 JJ |
11557 | { |
11558 | if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x) | |
11559 | && GET_CODE (SUBREG_REG (x)) == REG) | |
11560 | record_promoted_value (insn, x); | |
11561 | else | |
11562 | { | |
11563 | const char *format = GET_RTX_FORMAT (GET_CODE (x)); | |
11564 | int i, j; | |
11565 | ||
11566 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) | |
663522cb | 11567 | switch (format[i]) |
732f2ac9 JJ |
11568 | { |
11569 | case 'e': | |
11570 | check_promoted_subreg (insn, XEXP (x, i)); | |
11571 | break; | |
11572 | case 'V': | |
11573 | case 'E': | |
11574 | if (XVEC (x, i) != 0) | |
11575 | for (j = 0; j < XVECLEN (x, i); j++) | |
11576 | check_promoted_subreg (insn, XVECEXP (x, i, j)); | |
11577 | break; | |
11578 | } | |
11579 | } | |
11580 | } | |
230d793d RS |
11581 | \f |
11582 | /* Utility routine for the following function. Verify that all the registers | |
11583 | mentioned in *LOC are valid when *LOC was part of a value set when | |
11584 | label_tick == TICK. Return 0 if some are not. | |
11585 | ||
da7d8304 | 11586 | If REPLACE is nonzero, replace the invalid reference with |
230d793d RS |
11587 | (clobber (const_int 0)) and return 1. This replacement is useful because |
11588 | we often can get useful information about the form of a value (e.g., if | |
11589 | it was produced by a shift that always produces -1 or 0) even though | |
11590 | we don't know exactly what registers it was produced from. */ | |
11591 | ||
11592 | static int | |
9a893315 | 11593 | get_last_value_validate (loc, insn, tick, replace) |
230d793d | 11594 | rtx *loc; |
9a893315 | 11595 | rtx insn; |
230d793d RS |
11596 | int tick; |
11597 | int replace; | |
11598 | { | |
11599 | rtx x = *loc; | |
6f7d635c | 11600 | const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); |
230d793d RS |
11601 | int len = GET_RTX_LENGTH (GET_CODE (x)); |
11602 | int i; | |
11603 | ||
11604 | if (GET_CODE (x) == REG) | |
11605 | { | |
770ae6cc RK |
11606 | unsigned int regno = REGNO (x); |
11607 | unsigned int endregno | |
11608 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
11609 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
11610 | unsigned int j; | |
230d793d RS |
11611 | |
11612 | for (j = regno; j < endregno; j++) | |
11613 | if (reg_last_set_invalid[j] | |
57cf50a4 GRK |
11614 | /* If this is a pseudo-register that was only set once and not |
11615 | live at the beginning of the function, it is always valid. */ | |
663522cb | 11616 | || (! (regno >= FIRST_PSEUDO_REGISTER |
57cf50a4 | 11617 | && REG_N_SETS (regno) == 1 |
770ae6cc | 11618 | && (! REGNO_REG_SET_P |
f6366fc7 | 11619 | (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno))) |
230d793d RS |
11620 | && reg_last_set_label[j] > tick)) |
11621 | { | |
11622 | if (replace) | |
38a448ca | 11623 | *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
230d793d RS |
11624 | return replace; |
11625 | } | |
11626 | ||
11627 | return 1; | |
11628 | } | |
9a893315 JW |
11629 | /* If this is a memory reference, make sure that there were |
11630 | no stores after it that might have clobbered the value. We don't | |
11631 | have alias info, so we assume any store invalidates it. */ | |
11632 | else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x) | |
11633 | && INSN_CUID (insn) <= mem_last_set) | |
11634 | { | |
11635 | if (replace) | |
38a448ca | 11636 | *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
9a893315 JW |
11637 | return replace; |
11638 | } | |
230d793d RS |
11639 | |
11640 | for (i = 0; i < len; i++) | |
11641 | if ((fmt[i] == 'e' | |
9a893315 | 11642 | && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0) |
230d793d RS |
11643 | /* Don't bother with these. They shouldn't occur anyway. */ |
11644 | || fmt[i] == 'E') | |
11645 | return 0; | |
11646 | ||
11647 | /* If we haven't found a reason for it to be invalid, it is valid. */ | |
11648 | return 1; | |
11649 | } | |
11650 | ||
11651 | /* Get the last value assigned to X, if known. Some registers | |
11652 | in the value may be replaced with (clobber (const_int 0)) if their value | |
11653 | is known longer known reliably. */ | |
11654 | ||
11655 | static rtx | |
11656 | get_last_value (x) | |
11657 | rtx x; | |
11658 | { | |
770ae6cc | 11659 | unsigned int regno; |
230d793d RS |
11660 | rtx value; |
11661 | ||
11662 | /* If this is a non-paradoxical SUBREG, get the value of its operand and | |
11663 | then convert it to the desired mode. If this is a paradoxical SUBREG, | |
0f41302f | 11664 | we cannot predict what values the "extra" bits might have. */ |
230d793d RS |
11665 | if (GET_CODE (x) == SUBREG |
11666 | && subreg_lowpart_p (x) | |
11667 | && (GET_MODE_SIZE (GET_MODE (x)) | |
11668 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
11669 | && (value = get_last_value (SUBREG_REG (x))) != 0) | |
11670 | return gen_lowpart_for_combine (GET_MODE (x), value); | |
11671 | ||
11672 | if (GET_CODE (x) != REG) | |
11673 | return 0; | |
11674 | ||
11675 | regno = REGNO (x); | |
11676 | value = reg_last_set_value[regno]; | |
11677 | ||
57cf50a4 GRK |
11678 | /* If we don't have a value, or if it isn't for this basic block and |
11679 | it's either a hard register, set more than once, or it's a live | |
663522cb | 11680 | at the beginning of the function, return 0. |
57cf50a4 | 11681 | |
eaec9b3d | 11682 | Because if it's not live at the beginning of the function then the reg |
57cf50a4 GRK |
11683 | is always set before being used (is never used without being set). |
11684 | And, if it's set only once, and it's always set before use, then all | |
11685 | uses must have the same last value, even if it's not from this basic | |
11686 | block. */ | |
230d793d RS |
11687 | |
11688 | if (value == 0 | |
57cf50a4 GRK |
11689 | || (reg_last_set_label[regno] != label_tick |
11690 | && (regno < FIRST_PSEUDO_REGISTER | |
11691 | || REG_N_SETS (regno) != 1 | |
770ae6cc | 11692 | || (REGNO_REG_SET_P |
f6366fc7 | 11693 | (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno))))) |
230d793d RS |
11694 | return 0; |
11695 | ||
4255220d | 11696 | /* If the value was set in a later insn than the ones we are processing, |
ca4cd906 | 11697 | we can't use it even if the register was only set once. */ |
bcd49eb7 | 11698 | if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid) |
ca4cd906 | 11699 | return 0; |
d0ab8cd3 RK |
11700 | |
11701 | /* If the value has all its registers valid, return it. */ | |
9a893315 JW |
11702 | if (get_last_value_validate (&value, reg_last_set[regno], |
11703 | reg_last_set_label[regno], 0)) | |
230d793d RS |
11704 | return value; |
11705 | ||
11706 | /* Otherwise, make a copy and replace any invalid register with | |
11707 | (clobber (const_int 0)). If that fails for some reason, return 0. */ | |
11708 | ||
11709 | value = copy_rtx (value); | |
9a893315 JW |
11710 | if (get_last_value_validate (&value, reg_last_set[regno], |
11711 | reg_last_set_label[regno], 1)) | |
230d793d RS |
11712 | return value; |
11713 | ||
11714 | return 0; | |
11715 | } | |
11716 | \f | |
11717 | /* Return nonzero if expression X refers to a REG or to memory | |
11718 | that is set in an instruction more recent than FROM_CUID. */ | |
11719 | ||
11720 | static int | |
11721 | use_crosses_set_p (x, from_cuid) | |
b3694847 | 11722 | rtx x; |
230d793d RS |
11723 | int from_cuid; |
11724 | { | |
b3694847 SS |
11725 | const char *fmt; |
11726 | int i; | |
11727 | enum rtx_code code = GET_CODE (x); | |
230d793d RS |
11728 | |
11729 | if (code == REG) | |
11730 | { | |
770ae6cc RK |
11731 | unsigned int regno = REGNO (x); |
11732 | unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER | |
663522cb KH |
11733 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); |
11734 | ||
230d793d RS |
11735 | #ifdef PUSH_ROUNDING |
11736 | /* Don't allow uses of the stack pointer to be moved, | |
11737 | because we don't know whether the move crosses a push insn. */ | |
f73ad30e | 11738 | if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) |
230d793d RS |
11739 | return 1; |
11740 | #endif | |
770ae6cc | 11741 | for (; regno < endreg; regno++) |
e28f5732 RK |
11742 | if (reg_last_set[regno] |
11743 | && INSN_CUID (reg_last_set[regno]) > from_cuid) | |
11744 | return 1; | |
11745 | return 0; | |
230d793d RS |
11746 | } |
11747 | ||
11748 | if (code == MEM && mem_last_set > from_cuid) | |
11749 | return 1; | |
11750 | ||
11751 | fmt = GET_RTX_FORMAT (code); | |
11752 | ||
11753 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11754 | { | |
11755 | if (fmt[i] == 'E') | |
11756 | { | |
b3694847 | 11757 | int j; |
230d793d RS |
11758 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
11759 | if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) | |
11760 | return 1; | |
11761 | } | |
11762 | else if (fmt[i] == 'e' | |
11763 | && use_crosses_set_p (XEXP (x, i), from_cuid)) | |
11764 | return 1; | |
11765 | } | |
11766 | return 0; | |
11767 | } | |
11768 | \f | |
11769 | /* Define three variables used for communication between the following | |
11770 | routines. */ | |
11771 | ||
770ae6cc | 11772 | static unsigned int reg_dead_regno, reg_dead_endregno; |
230d793d RS |
11773 | static int reg_dead_flag; |
11774 | ||
11775 | /* Function called via note_stores from reg_dead_at_p. | |
11776 | ||
663522cb | 11777 | If DEST is within [reg_dead_regno, reg_dead_endregno), set |
230d793d RS |
11778 | reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ |
11779 | ||
11780 | static void | |
84832317 | 11781 | reg_dead_at_p_1 (dest, x, data) |
230d793d RS |
11782 | rtx dest; |
11783 | rtx x; | |
84832317 | 11784 | void *data ATTRIBUTE_UNUSED; |
230d793d | 11785 | { |
770ae6cc | 11786 | unsigned int regno, endregno; |
230d793d RS |
11787 | |
11788 | if (GET_CODE (dest) != REG) | |
11789 | return; | |
11790 | ||
11791 | regno = REGNO (dest); | |
663522cb | 11792 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER |
230d793d RS |
11793 | ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1); |
11794 | ||
11795 | if (reg_dead_endregno > regno && reg_dead_regno < endregno) | |
11796 | reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; | |
11797 | } | |
11798 | ||
da7d8304 | 11799 | /* Return nonzero if REG is known to be dead at INSN. |
230d793d RS |
11800 | |
11801 | We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER | |
11802 | referencing REG, it is dead. If we hit a SET referencing REG, it is | |
11803 | live. Otherwise, see if it is live or dead at the start of the basic | |
6e25d159 RK |
11804 | block we are in. Hard regs marked as being live in NEWPAT_USED_REGS |
11805 | must be assumed to be always live. */ | |
230d793d RS |
11806 | |
11807 | static int | |
11808 | reg_dead_at_p (reg, insn) | |
11809 | rtx reg; | |
11810 | rtx insn; | |
11811 | { | |
e0082a72 | 11812 | basic_block block; |
770ae6cc | 11813 | unsigned int i; |
230d793d RS |
11814 | |
11815 | /* Set variables for reg_dead_at_p_1. */ | |
11816 | reg_dead_regno = REGNO (reg); | |
11817 | reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER | |
11818 | ? HARD_REGNO_NREGS (reg_dead_regno, | |
11819 | GET_MODE (reg)) | |
11820 | : 1); | |
11821 | ||
11822 | reg_dead_flag = 0; | |
11823 | ||
6e25d159 RK |
11824 | /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */ |
11825 | if (reg_dead_regno < FIRST_PSEUDO_REGISTER) | |
11826 | { | |
11827 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
11828 | if (TEST_HARD_REG_BIT (newpat_used_regs, i)) | |
11829 | return 0; | |
11830 | } | |
11831 | ||
230d793d RS |
11832 | /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or |
11833 | beginning of function. */ | |
60715d0b | 11834 | for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER; |
230d793d RS |
11835 | insn = prev_nonnote_insn (insn)) |
11836 | { | |
84832317 | 11837 | note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); |
230d793d RS |
11838 | if (reg_dead_flag) |
11839 | return reg_dead_flag == 1 ? 1 : 0; | |
11840 | ||
11841 | if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) | |
11842 | return 1; | |
11843 | } | |
11844 | ||
e0082a72 | 11845 | /* Get the basic block that we were in. */ |
230d793d | 11846 | if (insn == 0) |
e0082a72 | 11847 | block = ENTRY_BLOCK_PTR->next_bb; |
230d793d RS |
11848 | else |
11849 | { | |
e0082a72 ZD |
11850 | FOR_EACH_BB (block) |
11851 | if (insn == block->head) | |
230d793d RS |
11852 | break; |
11853 | ||
e0082a72 | 11854 | if (block == EXIT_BLOCK_PTR) |
230d793d RS |
11855 | return 0; |
11856 | } | |
11857 | ||
11858 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
e0082a72 | 11859 | if (REGNO_REG_SET_P (block->global_live_at_start, i)) |
230d793d RS |
11860 | return 0; |
11861 | ||
11862 | return 1; | |
11863 | } | |
6e25d159 RK |
11864 | \f |
11865 | /* Note hard registers in X that are used. This code is similar to | |
11866 | that in flow.c, but much simpler since we don't care about pseudos. */ | |
11867 | ||
11868 | static void | |
11869 | mark_used_regs_combine (x) | |
11870 | rtx x; | |
11871 | { | |
770ae6cc RK |
11872 | RTX_CODE code = GET_CODE (x); |
11873 | unsigned int regno; | |
6e25d159 RK |
11874 | int i; |
11875 | ||
11876 | switch (code) | |
11877 | { | |
11878 | case LABEL_REF: | |
11879 | case SYMBOL_REF: | |
11880 | case CONST_INT: | |
11881 | case CONST: | |
11882 | case CONST_DOUBLE: | |
69ef87e2 | 11883 | case CONST_VECTOR: |
6e25d159 RK |
11884 | case PC: |
11885 | case ADDR_VEC: | |
11886 | case ADDR_DIFF_VEC: | |
11887 | case ASM_INPUT: | |
11888 | #ifdef HAVE_cc0 | |
11889 | /* CC0 must die in the insn after it is set, so we don't need to take | |
11890 | special note of it here. */ | |
11891 | case CC0: | |
11892 | #endif | |
11893 | return; | |
11894 | ||
11895 | case CLOBBER: | |
11896 | /* If we are clobbering a MEM, mark any hard registers inside the | |
11897 | address as used. */ | |
11898 | if (GET_CODE (XEXP (x, 0)) == MEM) | |
11899 | mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); | |
11900 | return; | |
11901 | ||
11902 | case REG: | |
11903 | regno = REGNO (x); | |
11904 | /* A hard reg in a wide mode may really be multiple registers. | |
11905 | If so, mark all of them just like the first. */ | |
11906 | if (regno < FIRST_PSEUDO_REGISTER) | |
11907 | { | |
770ae6cc RK |
11908 | unsigned int endregno, r; |
11909 | ||
6e25d159 RK |
11910 | /* None of this applies to the stack, frame or arg pointers */ |
11911 | if (regno == STACK_POINTER_REGNUM | |
11912 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
11913 | || regno == HARD_FRAME_POINTER_REGNUM | |
11914 | #endif | |
11915 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
11916 | || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
11917 | #endif | |
11918 | || regno == FRAME_POINTER_REGNUM) | |
11919 | return; | |
11920 | ||
770ae6cc RK |
11921 | endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); |
11922 | for (r = regno; r < endregno; r++) | |
11923 | SET_HARD_REG_BIT (newpat_used_regs, r); | |
6e25d159 RK |
11924 | } |
11925 | return; | |
11926 | ||
11927 | case SET: | |
11928 | { | |
11929 | /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in | |
11930 | the address. */ | |
b3694847 | 11931 | rtx testreg = SET_DEST (x); |
6e25d159 | 11932 | |
e048778f RK |
11933 | while (GET_CODE (testreg) == SUBREG |
11934 | || GET_CODE (testreg) == ZERO_EXTRACT | |
11935 | || GET_CODE (testreg) == SIGN_EXTRACT | |
11936 | || GET_CODE (testreg) == STRICT_LOW_PART) | |
6e25d159 RK |
11937 | testreg = XEXP (testreg, 0); |
11938 | ||
11939 | if (GET_CODE (testreg) == MEM) | |
11940 | mark_used_regs_combine (XEXP (testreg, 0)); | |
11941 | ||
11942 | mark_used_regs_combine (SET_SRC (x)); | |
6e25d159 | 11943 | } |
e9a25f70 JL |
11944 | return; |
11945 | ||
11946 | default: | |
11947 | break; | |
6e25d159 RK |
11948 | } |
11949 | ||
11950 | /* Recursively scan the operands of this expression. */ | |
11951 | ||
11952 | { | |
b3694847 | 11953 | const char *fmt = GET_RTX_FORMAT (code); |
6e25d159 RK |
11954 | |
11955 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11956 | { | |
663522cb | 11957 | if (fmt[i] == 'e') |
6e25d159 | 11958 | mark_used_regs_combine (XEXP (x, i)); |
663522cb KH |
11959 | else if (fmt[i] == 'E') |
11960 | { | |
b3694847 | 11961 | int j; |
6e25d159 | 11962 | |
663522cb KH |
11963 | for (j = 0; j < XVECLEN (x, i); j++) |
11964 | mark_used_regs_combine (XVECEXP (x, i, j)); | |
11965 | } | |
6e25d159 RK |
11966 | } |
11967 | } | |
11968 | } | |
230d793d RS |
11969 | \f |
11970 | /* Remove register number REGNO from the dead registers list of INSN. | |
11971 | ||
11972 | Return the note used to record the death, if there was one. */ | |
11973 | ||
11974 | rtx | |
11975 | remove_death (regno, insn) | |
770ae6cc | 11976 | unsigned int regno; |
230d793d RS |
11977 | rtx insn; |
11978 | { | |
b3694847 | 11979 | rtx note = find_regno_note (insn, REG_DEAD, regno); |
230d793d RS |
11980 | |
11981 | if (note) | |
1a26b032 | 11982 | { |
b1f21e0a | 11983 | REG_N_DEATHS (regno)--; |
1a26b032 RK |
11984 | remove_note (insn, note); |
11985 | } | |
230d793d RS |
11986 | |
11987 | return note; | |
11988 | } | |
11989 | ||
11990 | /* For each register (hardware or pseudo) used within expression X, if its | |
11991 | death is in an instruction with cuid between FROM_CUID (inclusive) and | |
11992 | TO_INSN (exclusive), put a REG_DEAD note for that register in the | |
663522cb | 11993 | list headed by PNOTES. |
230d793d | 11994 | |
6eb12cef RK |
11995 | That said, don't move registers killed by maybe_kill_insn. |
11996 | ||
230d793d RS |
11997 | This is done when X is being merged by combination into TO_INSN. These |
11998 | notes will then be distributed as needed. */ | |
11999 | ||
12000 | static void | |
6eb12cef | 12001 | move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes) |
230d793d | 12002 | rtx x; |
6eb12cef | 12003 | rtx maybe_kill_insn; |
230d793d RS |
12004 | int from_cuid; |
12005 | rtx to_insn; | |
12006 | rtx *pnotes; | |
12007 | { | |
b3694847 SS |
12008 | const char *fmt; |
12009 | int len, i; | |
12010 | enum rtx_code code = GET_CODE (x); | |
230d793d RS |
12011 | |
12012 | if (code == REG) | |
12013 | { | |
770ae6cc | 12014 | unsigned int regno = REGNO (x); |
b3694847 SS |
12015 | rtx where_dead = reg_last_death[regno]; |
12016 | rtx before_dead, after_dead; | |
e340018d | 12017 | |
6eb12cef RK |
12018 | /* Don't move the register if it gets killed in between from and to */ |
12019 | if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) | |
770ae6cc | 12020 | && ! reg_referenced_p (x, maybe_kill_insn)) |
6eb12cef RK |
12021 | return; |
12022 | ||
e340018d JW |
12023 | /* WHERE_DEAD could be a USE insn made by combine, so first we |
12024 | make sure that we have insns with valid INSN_CUID values. */ | |
12025 | before_dead = where_dead; | |
12026 | while (before_dead && INSN_UID (before_dead) > max_uid_cuid) | |
12027 | before_dead = PREV_INSN (before_dead); | |
770ae6cc | 12028 | |
e340018d JW |
12029 | after_dead = where_dead; |
12030 | while (after_dead && INSN_UID (after_dead) > max_uid_cuid) | |
12031 | after_dead = NEXT_INSN (after_dead); | |
12032 | ||
12033 | if (before_dead && after_dead | |
12034 | && INSN_CUID (before_dead) >= from_cuid | |
12035 | && (INSN_CUID (after_dead) < INSN_CUID (to_insn) | |
12036 | || (where_dead != after_dead | |
12037 | && INSN_CUID (after_dead) == INSN_CUID (to_insn)))) | |
230d793d | 12038 | { |
dbc131f3 | 12039 | rtx note = remove_death (regno, where_dead); |
230d793d RS |
12040 | |
12041 | /* It is possible for the call above to return 0. This can occur | |
12042 | when reg_last_death points to I2 or I1 that we combined with. | |
dbc131f3 RK |
12043 | In that case make a new note. |
12044 | ||
12045 | We must also check for the case where X is a hard register | |
12046 | and NOTE is a death note for a range of hard registers | |
12047 | including X. In that case, we must put REG_DEAD notes for | |
12048 | the remaining registers in place of NOTE. */ | |
12049 | ||
12050 | if (note != 0 && regno < FIRST_PSEUDO_REGISTER | |
12051 | && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
24e46fc4 | 12052 | > GET_MODE_SIZE (GET_MODE (x)))) |
dbc131f3 | 12053 | { |
770ae6cc RK |
12054 | unsigned int deadregno = REGNO (XEXP (note, 0)); |
12055 | unsigned int deadend | |
dbc131f3 RK |
12056 | = (deadregno + HARD_REGNO_NREGS (deadregno, |
12057 | GET_MODE (XEXP (note, 0)))); | |
770ae6cc RK |
12058 | unsigned int ourend |
12059 | = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
12060 | unsigned int i; | |
dbc131f3 RK |
12061 | |
12062 | for (i = deadregno; i < deadend; i++) | |
12063 | if (i < regno || i >= ourend) | |
12064 | REG_NOTES (where_dead) | |
38a448ca | 12065 | = gen_rtx_EXPR_LIST (REG_DEAD, |
e50126e8 | 12066 | regno_reg_rtx[i], |
38a448ca | 12067 | REG_NOTES (where_dead)); |
dbc131f3 | 12068 | } |
770ae6cc | 12069 | |
24e46fc4 JW |
12070 | /* If we didn't find any note, or if we found a REG_DEAD note that |
12071 | covers only part of the given reg, and we have a multi-reg hard | |
fabd69e8 RK |
12072 | register, then to be safe we must check for REG_DEAD notes |
12073 | for each register other than the first. They could have | |
12074 | their own REG_DEAD notes lying around. */ | |
24e46fc4 JW |
12075 | else if ((note == 0 |
12076 | || (note != 0 | |
12077 | && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
12078 | < GET_MODE_SIZE (GET_MODE (x))))) | |
12079 | && regno < FIRST_PSEUDO_REGISTER | |
fabd69e8 RK |
12080 | && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) |
12081 | { | |
770ae6cc RK |
12082 | unsigned int ourend |
12083 | = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
12084 | unsigned int i, offset; | |
fabd69e8 RK |
12085 | rtx oldnotes = 0; |
12086 | ||
24e46fc4 JW |
12087 | if (note) |
12088 | offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))); | |
12089 | else | |
12090 | offset = 1; | |
12091 | ||
12092 | for (i = regno + offset; i < ourend; i++) | |
e50126e8 | 12093 | move_deaths (regno_reg_rtx[i], |
6eb12cef | 12094 | maybe_kill_insn, from_cuid, to_insn, &oldnotes); |
fabd69e8 | 12095 | } |
230d793d | 12096 | |
dbc131f3 | 12097 | if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) |
230d793d RS |
12098 | { |
12099 | XEXP (note, 1) = *pnotes; | |
12100 | *pnotes = note; | |
12101 | } | |
12102 | else | |
38a448ca | 12103 | *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); |
1a26b032 | 12104 | |
b1f21e0a | 12105 | REG_N_DEATHS (regno)++; |
230d793d RS |
12106 | } |
12107 | ||
12108 | return; | |
12109 | } | |
12110 | ||
12111 | else if (GET_CODE (x) == SET) | |
12112 | { | |
12113 | rtx dest = SET_DEST (x); | |
12114 | ||
6eb12cef | 12115 | move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes); |
230d793d | 12116 | |
a7c99304 RK |
12117 | /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG |
12118 | that accesses one word of a multi-word item, some | |
12119 | piece of everything register in the expression is used by | |
12120 | this insn, so remove any old death. */ | |
ddef6bc7 | 12121 | /* ??? So why do we test for equality of the sizes? */ |
a7c99304 RK |
12122 | |
12123 | if (GET_CODE (dest) == ZERO_EXTRACT | |
12124 | || GET_CODE (dest) == STRICT_LOW_PART | |
12125 | || (GET_CODE (dest) == SUBREG | |
12126 | && (((GET_MODE_SIZE (GET_MODE (dest)) | |
12127 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
12128 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) | |
12129 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) | |
230d793d | 12130 | { |
6eb12cef | 12131 | move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes); |
a7c99304 | 12132 | return; |
230d793d RS |
12133 | } |
12134 | ||
a7c99304 RK |
12135 | /* If this is some other SUBREG, we know it replaces the entire |
12136 | value, so use that as the destination. */ | |
12137 | if (GET_CODE (dest) == SUBREG) | |
12138 | dest = SUBREG_REG (dest); | |
12139 | ||
12140 | /* If this is a MEM, adjust deaths of anything used in the address. | |
12141 | For a REG (the only other possibility), the entire value is | |
12142 | being replaced so the old value is not used in this insn. */ | |
230d793d RS |
12143 | |
12144 | if (GET_CODE (dest) == MEM) | |
6eb12cef RK |
12145 | move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid, |
12146 | to_insn, pnotes); | |
230d793d RS |
12147 | return; |
12148 | } | |
12149 | ||
12150 | else if (GET_CODE (x) == CLOBBER) | |
12151 | return; | |
12152 | ||
12153 | len = GET_RTX_LENGTH (code); | |
12154 | fmt = GET_RTX_FORMAT (code); | |
12155 | ||
12156 | for (i = 0; i < len; i++) | |
12157 | { | |
12158 | if (fmt[i] == 'E') | |
12159 | { | |
b3694847 | 12160 | int j; |
230d793d | 12161 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
6eb12cef RK |
12162 | move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid, |
12163 | to_insn, pnotes); | |
230d793d RS |
12164 | } |
12165 | else if (fmt[i] == 'e') | |
6eb12cef | 12166 | move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes); |
230d793d RS |
12167 | } |
12168 | } | |
12169 | \f | |
a7c99304 RK |
12170 | /* Return 1 if X is the target of a bit-field assignment in BODY, the |
12171 | pattern of an insn. X must be a REG. */ | |
230d793d RS |
12172 | |
12173 | static int | |
a7c99304 RK |
12174 | reg_bitfield_target_p (x, body) |
12175 | rtx x; | |
230d793d RS |
12176 | rtx body; |
12177 | { | |
12178 | int i; | |
12179 | ||
12180 | if (GET_CODE (body) == SET) | |
a7c99304 RK |
12181 | { |
12182 | rtx dest = SET_DEST (body); | |
12183 | rtx target; | |
770ae6cc | 12184 | unsigned int regno, tregno, endregno, endtregno; |
a7c99304 RK |
12185 | |
12186 | if (GET_CODE (dest) == ZERO_EXTRACT) | |
12187 | target = XEXP (dest, 0); | |
12188 | else if (GET_CODE (dest) == STRICT_LOW_PART) | |
12189 | target = SUBREG_REG (XEXP (dest, 0)); | |
12190 | else | |
12191 | return 0; | |
12192 | ||
12193 | if (GET_CODE (target) == SUBREG) | |
12194 | target = SUBREG_REG (target); | |
12195 | ||
12196 | if (GET_CODE (target) != REG) | |
12197 | return 0; | |
12198 | ||
12199 | tregno = REGNO (target), regno = REGNO (x); | |
12200 | if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) | |
12201 | return target == x; | |
12202 | ||
12203 | endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); | |
12204 | endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
12205 | ||
12206 | return endregno > tregno && regno < endtregno; | |
12207 | } | |
230d793d RS |
12208 | |
12209 | else if (GET_CODE (body) == PARALLEL) | |
12210 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
a7c99304 | 12211 | if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) |
230d793d RS |
12212 | return 1; |
12213 | ||
12214 | return 0; | |
663522cb | 12215 | } |
230d793d RS |
12216 | \f |
12217 | /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them | |
12218 | as appropriate. I3 and I2 are the insns resulting from the combination | |
12219 | insns including FROM (I2 may be zero). | |
12220 | ||
12221 | ELIM_I2 and ELIM_I1 are either zero or registers that we know will | |
12222 | not need REG_DEAD notes because they are being substituted for. This | |
12223 | saves searching in the most common cases. | |
12224 | ||
12225 | Each note in the list is either ignored or placed on some insns, depending | |
12226 | on the type of note. */ | |
12227 | ||
12228 | static void | |
12229 | distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1) | |
12230 | rtx notes; | |
12231 | rtx from_insn; | |
12232 | rtx i3, i2; | |
12233 | rtx elim_i2, elim_i1; | |
12234 | { | |
12235 | rtx note, next_note; | |
12236 | rtx tem; | |
12237 | ||
12238 | for (note = notes; note; note = next_note) | |
12239 | { | |
12240 | rtx place = 0, place2 = 0; | |
12241 | ||
12242 | /* If this NOTE references a pseudo register, ensure it references | |
12243 | the latest copy of that register. */ | |
12244 | if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG | |
12245 | && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) | |
12246 | XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; | |
12247 | ||
12248 | next_note = XEXP (note, 1); | |
12249 | switch (REG_NOTE_KIND (note)) | |
12250 | { | |
c9903b44 | 12251 | case REG_BR_PROB: |
4db384c9 | 12252 | case REG_BR_PRED: |
c9903b44 DE |
12253 | case REG_EXEC_COUNT: |
12254 | /* Doesn't matter much where we put this, as long as it's somewhere. | |
12255 | It is preferable to keep these notes on branches, which is most | |
12256 | likely to be i3. */ | |
4a8d0c9c RH |
12257 | place = i3; |
12258 | break; | |
12259 | ||
12260 | case REG_VTABLE_REF: | |
12261 | /* ??? Should remain with *a particular* memory load. Given the | |
12262 | nature of vtable data, the last insn seems relatively safe. */ | |
c9903b44 DE |
12263 | place = i3; |
12264 | break; | |
12265 | ||
f7cfa78d GS |
12266 | case REG_NON_LOCAL_GOTO: |
12267 | if (GET_CODE (i3) == JUMP_INSN) | |
12268 | place = i3; | |
12269 | else if (i2 && GET_CODE (i2) == JUMP_INSN) | |
12270 | place = i2; | |
12271 | else | |
505ddab6 | 12272 | abort (); |
f7cfa78d GS |
12273 | break; |
12274 | ||
4b7c585f | 12275 | case REG_EH_REGION: |
662795a8 RH |
12276 | /* These notes must remain with the call or trapping instruction. */ |
12277 | if (GET_CODE (i3) == CALL_INSN) | |
12278 | place = i3; | |
12279 | else if (i2 && GET_CODE (i2) == CALL_INSN) | |
12280 | place = i2; | |
12281 | else if (flag_non_call_exceptions) | |
12282 | { | |
12283 | if (may_trap_p (i3)) | |
12284 | place = i3; | |
12285 | else if (i2 && may_trap_p (i2)) | |
12286 | place = i2; | |
12287 | /* ??? Otherwise assume we've combined things such that we | |
12288 | can now prove that the instructions can't trap. Drop the | |
12289 | note in this case. */ | |
12290 | } | |
12291 | else | |
12292 | abort (); | |
12293 | break; | |
12294 | ||
ca3920ad | 12295 | case REG_NORETURN: |
ab61c93f | 12296 | case REG_SETJMP: |
0e403ec3 AS |
12297 | /* These notes must remain with the call. It should not be |
12298 | possible for both I2 and I3 to be a call. */ | |
663522cb | 12299 | if (GET_CODE (i3) == CALL_INSN) |
4b7c585f JL |
12300 | place = i3; |
12301 | else if (i2 && GET_CODE (i2) == CALL_INSN) | |
12302 | place = i2; | |
12303 | else | |
12304 | abort (); | |
12305 | break; | |
12306 | ||
230d793d | 12307 | case REG_UNUSED: |
07d0cbdd | 12308 | /* Any clobbers for i3 may still exist, and so we must process |
176c9e6b JW |
12309 | REG_UNUSED notes from that insn. |
12310 | ||
12311 | Any clobbers from i2 or i1 can only exist if they were added by | |
12312 | recog_for_combine. In that case, recog_for_combine created the | |
12313 | necessary REG_UNUSED notes. Trying to keep any original | |
12314 | REG_UNUSED notes from these insns can cause incorrect output | |
12315 | if it is for the same register as the original i3 dest. | |
12316 | In that case, we will notice that the register is set in i3, | |
12317 | and then add a REG_UNUSED note for the destination of i3, which | |
07d0cbdd JW |
12318 | is wrong. However, it is possible to have REG_UNUSED notes from |
12319 | i2 or i1 for register which were both used and clobbered, so | |
12320 | we keep notes from i2 or i1 if they will turn into REG_DEAD | |
12321 | notes. */ | |
176c9e6b | 12322 | |
230d793d RS |
12323 | /* If this register is set or clobbered in I3, put the note there |
12324 | unless there is one already. */ | |
07d0cbdd | 12325 | if (reg_set_p (XEXP (note, 0), PATTERN (i3))) |
230d793d | 12326 | { |
07d0cbdd JW |
12327 | if (from_insn != i3) |
12328 | break; | |
12329 | ||
230d793d RS |
12330 | if (! (GET_CODE (XEXP (note, 0)) == REG |
12331 | ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) | |
12332 | : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) | |
12333 | place = i3; | |
12334 | } | |
12335 | /* Otherwise, if this register is used by I3, then this register | |
12336 | now dies here, so we must put a REG_DEAD note here unless there | |
12337 | is one already. */ | |
12338 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) | |
12339 | && ! (GET_CODE (XEXP (note, 0)) == REG | |
770ae6cc RK |
12340 | ? find_regno_note (i3, REG_DEAD, |
12341 | REGNO (XEXP (note, 0))) | |
230d793d RS |
12342 | : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) |
12343 | { | |
12344 | PUT_REG_NOTE_KIND (note, REG_DEAD); | |
12345 | place = i3; | |
12346 | } | |
12347 | break; | |
12348 | ||
12349 | case REG_EQUAL: | |
12350 | case REG_EQUIV: | |
9ae8ffe7 | 12351 | case REG_NOALIAS: |
230d793d RS |
12352 | /* These notes say something about results of an insn. We can |
12353 | only support them if they used to be on I3 in which case they | |
a687e897 RK |
12354 | remain on I3. Otherwise they are ignored. |
12355 | ||
12356 | If the note refers to an expression that is not a constant, we | |
12357 | must also ignore the note since we cannot tell whether the | |
12358 | equivalence is still true. It might be possible to do | |
12359 | slightly better than this (we only have a problem if I2DEST | |
12360 | or I1DEST is present in the expression), but it doesn't | |
12361 | seem worth the trouble. */ | |
12362 | ||
12363 | if (from_insn == i3 | |
12364 | && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) | |
230d793d RS |
12365 | place = i3; |
12366 | break; | |
12367 | ||
12368 | case REG_INC: | |
12369 | case REG_NO_CONFLICT: | |
230d793d RS |
12370 | /* These notes say something about how a register is used. They must |
12371 | be present on any use of the register in I2 or I3. */ | |
12372 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) | |
12373 | place = i3; | |
12374 | ||
12375 | if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) | |
12376 | { | |
12377 | if (place) | |
12378 | place2 = i2; | |
12379 | else | |
12380 | place = i2; | |
12381 | } | |
12382 | break; | |
12383 | ||
e55b4486 RH |
12384 | case REG_LABEL: |
12385 | /* This can show up in several ways -- either directly in the | |
12386 | pattern, or hidden off in the constant pool with (or without?) | |
12387 | a REG_EQUAL note. */ | |
12388 | /* ??? Ignore the without-reg_equal-note problem for now. */ | |
12389 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) | |
12390 | || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) | |
12391 | && GET_CODE (XEXP (tem, 0)) == LABEL_REF | |
12392 | && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) | |
12393 | place = i3; | |
12394 | ||
12395 | if (i2 | |
12396 | && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) | |
663522cb | 12397 | || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) |
e55b4486 RH |
12398 | && GET_CODE (XEXP (tem, 0)) == LABEL_REF |
12399 | && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) | |
12400 | { | |
12401 | if (place) | |
12402 | place2 = i2; | |
12403 | else | |
12404 | place = i2; | |
12405 | } | |
2a3b43b6 JJ |
12406 | |
12407 | /* Don't attach REG_LABEL note to a JUMP_INSN which has | |
12408 | JUMP_LABEL already. Instead, decrement LABEL_NUSES. */ | |
12409 | if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place)) | |
12410 | { | |
12411 | if (JUMP_LABEL (place) != XEXP (note, 0)) | |
12412 | abort (); | |
12413 | if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL) | |
12414 | LABEL_NUSES (JUMP_LABEL (place))--; | |
12415 | place = 0; | |
12416 | } | |
12417 | if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2)) | |
12418 | { | |
12419 | if (JUMP_LABEL (place2) != XEXP (note, 0)) | |
12420 | abort (); | |
12421 | if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL) | |
12422 | LABEL_NUSES (JUMP_LABEL (place2))--; | |
12423 | place2 = 0; | |
12424 | } | |
e55b4486 RH |
12425 | break; |
12426 | ||
c1194d74 | 12427 | case REG_NONNEG: |
230d793d | 12428 | case REG_WAS_0: |
c1194d74 JW |
12429 | /* These notes say something about the value of a register prior |
12430 | to the execution of an insn. It is too much trouble to see | |
12431 | if the note is still correct in all situations. It is better | |
12432 | to simply delete it. */ | |
230d793d RS |
12433 | break; |
12434 | ||
12435 | case REG_RETVAL: | |
12436 | /* If the insn previously containing this note still exists, | |
12437 | put it back where it was. Otherwise move it to the previous | |
12438 | insn. Adjust the corresponding REG_LIBCALL note. */ | |
12439 | if (GET_CODE (from_insn) != NOTE) | |
12440 | place = from_insn; | |
12441 | else | |
12442 | { | |
5f4f0e22 | 12443 | tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); |
230d793d RS |
12444 | place = prev_real_insn (from_insn); |
12445 | if (tem && place) | |
12446 | XEXP (tem, 0) = place; | |
c71e1201 AO |
12447 | /* If we're deleting the last remaining instruction of a |
12448 | libcall sequence, don't add the notes. */ | |
12449 | else if (XEXP (note, 0) == from_insn) | |
12450 | tem = place = 0; | |
230d793d RS |
12451 | } |
12452 | break; | |
12453 | ||
12454 | case REG_LIBCALL: | |
12455 | /* This is handled similarly to REG_RETVAL. */ | |
12456 | if (GET_CODE (from_insn) != NOTE) | |
12457 | place = from_insn; | |
12458 | else | |
12459 | { | |
5f4f0e22 | 12460 | tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); |
230d793d RS |
12461 | place = next_real_insn (from_insn); |
12462 | if (tem && place) | |
12463 | XEXP (tem, 0) = place; | |
c71e1201 AO |
12464 | /* If we're deleting the last remaining instruction of a |
12465 | libcall sequence, don't add the notes. */ | |
12466 | else if (XEXP (note, 0) == from_insn) | |
12467 | tem = place = 0; | |
230d793d RS |
12468 | } |
12469 | break; | |
12470 | ||
12471 | case REG_DEAD: | |
12472 | /* If the register is used as an input in I3, it dies there. | |
da7d8304 | 12473 | Similarly for I2, if it is nonzero and adjacent to I3. |
230d793d RS |
12474 | |
12475 | If the register is not used as an input in either I3 or I2 | |
12476 | and it is not one of the registers we were supposed to eliminate, | |
12477 | there are two possibilities. We might have a non-adjacent I2 | |
12478 | or we might have somehow eliminated an additional register | |
12479 | from a computation. For example, we might have had A & B where | |
12480 | we discover that B will always be zero. In this case we will | |
12481 | eliminate the reference to A. | |
12482 | ||
12483 | In both cases, we must search to see if we can find a previous | |
12484 | use of A and put the death note there. */ | |
12485 | ||
6e2d1486 RK |
12486 | if (from_insn |
12487 | && GET_CODE (from_insn) == CALL_INSN | |
663522cb | 12488 | && find_reg_fusage (from_insn, USE, XEXP (note, 0))) |
6e2d1486 RK |
12489 | place = from_insn; |
12490 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) | |
230d793d RS |
12491 | place = i3; |
12492 | else if (i2 != 0 && next_nonnote_insn (i2) == i3 | |
12493 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) | |
12494 | place = i2; | |
12495 | ||
03afaf36 R |
12496 | if (rtx_equal_p (XEXP (note, 0), elim_i2) |
12497 | || rtx_equal_p (XEXP (note, 0), elim_i1)) | |
230d793d RS |
12498 | break; |
12499 | ||
12500 | if (place == 0) | |
38d8473f | 12501 | { |
f6366fc7 | 12502 | basic_block bb = this_basic_block; |
d3a923ee RH |
12503 | |
12504 | for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem)) | |
38d8473f | 12505 | { |
2c3c49de | 12506 | if (! INSN_P (tem)) |
d3a923ee RH |
12507 | { |
12508 | if (tem == bb->head) | |
12509 | break; | |
12510 | continue; | |
12511 | } | |
12512 | ||
38d8473f RK |
12513 | /* If the register is being set at TEM, see if that is all |
12514 | TEM is doing. If so, delete TEM. Otherwise, make this | |
12515 | into a REG_UNUSED note instead. */ | |
12516 | if (reg_set_p (XEXP (note, 0), PATTERN (tem))) | |
12517 | { | |
12518 | rtx set = single_set (tem); | |
e5e809f4 | 12519 | rtx inner_dest = 0; |
e51712db | 12520 | #ifdef HAVE_cc0 |
f5c97640 | 12521 | rtx cc0_setter = NULL_RTX; |
e51712db | 12522 | #endif |
e5e809f4 JL |
12523 | |
12524 | if (set != 0) | |
12525 | for (inner_dest = SET_DEST (set); | |
663522cb KH |
12526 | (GET_CODE (inner_dest) == STRICT_LOW_PART |
12527 | || GET_CODE (inner_dest) == SUBREG | |
12528 | || GET_CODE (inner_dest) == ZERO_EXTRACT); | |
e5e809f4 JL |
12529 | inner_dest = XEXP (inner_dest, 0)) |
12530 | ; | |
38d8473f RK |
12531 | |
12532 | /* Verify that it was the set, and not a clobber that | |
663522cb | 12533 | modified the register. |
f5c97640 RH |
12534 | |
12535 | CC0 targets must be careful to maintain setter/user | |
12536 | pairs. If we cannot delete the setter due to side | |
12537 | effects, mark the user with an UNUSED note instead | |
12538 | of deleting it. */ | |
38d8473f RK |
12539 | |
12540 | if (set != 0 && ! side_effects_p (SET_SRC (set)) | |
f5c97640 RH |
12541 | && rtx_equal_p (XEXP (note, 0), inner_dest) |
12542 | #ifdef HAVE_cc0 | |
12543 | && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) | |
12544 | || ((cc0_setter = prev_cc0_setter (tem)) != NULL | |
12545 | && sets_cc0_p (PATTERN (cc0_setter)) > 0)) | |
12546 | #endif | |
12547 | ) | |
38d8473f RK |
12548 | { |
12549 | /* Move the notes and links of TEM elsewhere. | |
663522cb | 12550 | This might delete other dead insns recursively. |
38d8473f RK |
12551 | First set the pattern to something that won't use |
12552 | any register. */ | |
12553 | ||
12554 | PATTERN (tem) = pc_rtx; | |
12555 | ||
12556 | distribute_notes (REG_NOTES (tem), tem, tem, | |
12557 | NULL_RTX, NULL_RTX, NULL_RTX); | |
12558 | distribute_links (LOG_LINKS (tem)); | |
12559 | ||
12560 | PUT_CODE (tem, NOTE); | |
12561 | NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED; | |
12562 | NOTE_SOURCE_FILE (tem) = 0; | |
f5c97640 RH |
12563 | |
12564 | #ifdef HAVE_cc0 | |
12565 | /* Delete the setter too. */ | |
12566 | if (cc0_setter) | |
12567 | { | |
12568 | PATTERN (cc0_setter) = pc_rtx; | |
12569 | ||
12570 | distribute_notes (REG_NOTES (cc0_setter), | |
12571 | cc0_setter, cc0_setter, | |
12572 | NULL_RTX, NULL_RTX, NULL_RTX); | |
12573 | distribute_links (LOG_LINKS (cc0_setter)); | |
12574 | ||
12575 | PUT_CODE (cc0_setter, NOTE); | |
d3a923ee RH |
12576 | NOTE_LINE_NUMBER (cc0_setter) |
12577 | = NOTE_INSN_DELETED; | |
f5c97640 RH |
12578 | NOTE_SOURCE_FILE (cc0_setter) = 0; |
12579 | } | |
12580 | #endif | |
38d8473f | 12581 | } |
e5e809f4 JL |
12582 | /* If the register is both set and used here, put the |
12583 | REG_DEAD note here, but place a REG_UNUSED note | |
12584 | here too unless there already is one. */ | |
12585 | else if (reg_referenced_p (XEXP (note, 0), | |
12586 | PATTERN (tem))) | |
12587 | { | |
12588 | place = tem; | |
12589 | ||
12590 | if (! find_regno_note (tem, REG_UNUSED, | |
12591 | REGNO (XEXP (note, 0)))) | |
12592 | REG_NOTES (tem) | |
c5c76735 | 12593 | = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0), |
9e6a5703 | 12594 | REG_NOTES (tem)); |
e5e809f4 | 12595 | } |
38d8473f RK |
12596 | else |
12597 | { | |
12598 | PUT_REG_NOTE_KIND (note, REG_UNUSED); | |
663522cb | 12599 | |
38d8473f RK |
12600 | /* If there isn't already a REG_UNUSED note, put one |
12601 | here. */ | |
12602 | if (! find_regno_note (tem, REG_UNUSED, | |
12603 | REGNO (XEXP (note, 0)))) | |
12604 | place = tem; | |
12605 | break; | |
d3a923ee RH |
12606 | } |
12607 | } | |
12608 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) | |
12609 | || (GET_CODE (tem) == CALL_INSN | |
12610 | && find_reg_fusage (tem, USE, XEXP (note, 0)))) | |
12611 | { | |
12612 | place = tem; | |
12613 | ||
12614 | /* If we are doing a 3->2 combination, and we have a | |
12615 | register which formerly died in i3 and was not used | |
12616 | by i2, which now no longer dies in i3 and is used in | |
12617 | i2 but does not die in i2, and place is between i2 | |
12618 | and i3, then we may need to move a link from place to | |
12619 | i2. */ | |
12620 | if (i2 && INSN_UID (place) <= max_uid_cuid | |
12621 | && INSN_CUID (place) > INSN_CUID (i2) | |
663522cb KH |
12622 | && from_insn |
12623 | && INSN_CUID (from_insn) > INSN_CUID (i2) | |
d3a923ee RH |
12624 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) |
12625 | { | |
12626 | rtx links = LOG_LINKS (place); | |
12627 | LOG_LINKS (place) = 0; | |
12628 | distribute_links (links); | |
12629 | } | |
12630 | break; | |
12631 | } | |
12632 | ||
12633 | if (tem == bb->head) | |
230d793d | 12634 | break; |
38d8473f | 12635 | } |
663522cb | 12636 | |
d3a923ee RH |
12637 | /* We haven't found an insn for the death note and it |
12638 | is still a REG_DEAD note, but we have hit the beginning | |
12639 | of the block. If the existing life info says the reg | |
715e7fbc | 12640 | was dead, there's nothing left to do. Otherwise, we'll |
e7139885 RH |
12641 | need to do a global life update after combine. */ |
12642 | if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 | |
12643 | && REGNO_REG_SET_P (bb->global_live_at_start, | |
12644 | REGNO (XEXP (note, 0)))) | |
e2cce0cf | 12645 | { |
f6366fc7 | 12646 | SET_BIT (refresh_blocks, this_basic_block->index); |
770ae6cc | 12647 | need_refresh = 1; |
e2cce0cf | 12648 | } |
38d8473f | 12649 | } |
230d793d RS |
12650 | |
12651 | /* If the register is set or already dead at PLACE, we needn't do | |
e5e809f4 JL |
12652 | anything with this note if it is still a REG_DEAD note. |
12653 | We can here if it is set at all, not if is it totally replace, | |
12654 | which is what `dead_or_set_p' checks, so also check for it being | |
12655 | set partially. */ | |
12656 | ||
230d793d RS |
12657 | if (place && REG_NOTE_KIND (note) == REG_DEAD) |
12658 | { | |
770ae6cc | 12659 | unsigned int regno = REGNO (XEXP (note, 0)); |
230d793d | 12660 | |
e7139885 RH |
12661 | /* Similarly, if the instruction on which we want to place |
12662 | the note is a noop, we'll need do a global live update | |
12663 | after we remove them in delete_noop_moves. */ | |
12664 | if (noop_move_p (place)) | |
12665 | { | |
f6366fc7 | 12666 | SET_BIT (refresh_blocks, this_basic_block->index); |
e7139885 RH |
12667 | need_refresh = 1; |
12668 | } | |
12669 | ||
230d793d RS |
12670 | if (dead_or_set_p (place, XEXP (note, 0)) |
12671 | || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) | |
12672 | { | |
12673 | /* Unless the register previously died in PLACE, clear | |
12674 | reg_last_death. [I no longer understand why this is | |
12675 | being done.] */ | |
12676 | if (reg_last_death[regno] != place) | |
12677 | reg_last_death[regno] = 0; | |
12678 | place = 0; | |
12679 | } | |
12680 | else | |
12681 | reg_last_death[regno] = place; | |
12682 | ||
12683 | /* If this is a death note for a hard reg that is occupying | |
12684 | multiple registers, ensure that we are still using all | |
12685 | parts of the object. If we find a piece of the object | |
03afaf36 R |
12686 | that is unused, we must arrange for an appropriate REG_DEAD |
12687 | note to be added for it. However, we can't just emit a USE | |
12688 | and tag the note to it, since the register might actually | |
12689 | be dead; so we recourse, and the recursive call then finds | |
12690 | the previous insn that used this register. */ | |
230d793d RS |
12691 | |
12692 | if (place && regno < FIRST_PSEUDO_REGISTER | |
12693 | && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1) | |
12694 | { | |
770ae6cc | 12695 | unsigned int endregno |
230d793d RS |
12696 | = regno + HARD_REGNO_NREGS (regno, |
12697 | GET_MODE (XEXP (note, 0))); | |
12698 | int all_used = 1; | |
770ae6cc | 12699 | unsigned int i; |
230d793d RS |
12700 | |
12701 | for (i = regno; i < endregno; i++) | |
03afaf36 R |
12702 | if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0) |
12703 | && ! find_regno_fusage (place, USE, i)) | |
12704 | || dead_or_set_regno_p (place, i)) | |
12705 | all_used = 0; | |
a394b17b | 12706 | |
230d793d RS |
12707 | if (! all_used) |
12708 | { | |
12709 | /* Put only REG_DEAD notes for pieces that are | |
03afaf36 | 12710 | not already dead or set. */ |
230d793d | 12711 | |
03afaf36 R |
12712 | for (i = regno; i < endregno; |
12713 | i += HARD_REGNO_NREGS (i, reg_raw_mode[i])) | |
230d793d | 12714 | { |
e50126e8 | 12715 | rtx piece = regno_reg_rtx[i]; |
f6366fc7 | 12716 | basic_block bb = this_basic_block; |
230d793d | 12717 | |
03afaf36 | 12718 | if (! dead_or_set_p (place, piece) |
230d793d RS |
12719 | && ! reg_bitfield_target_p (piece, |
12720 | PATTERN (place))) | |
03afaf36 R |
12721 | { |
12722 | rtx new_note | |
12723 | = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX); | |
12724 | ||
12725 | distribute_notes (new_note, place, place, | |
12726 | NULL_RTX, NULL_RTX, NULL_RTX); | |
12727 | } | |
c762163e R |
12728 | else if (! refers_to_regno_p (i, i + 1, |
12729 | PATTERN (place), 0) | |
12730 | && ! find_regno_fusage (place, USE, i)) | |
12731 | for (tem = PREV_INSN (place); ; | |
12732 | tem = PREV_INSN (tem)) | |
12733 | { | |
12734 | if (! INSN_P (tem)) | |
12735 | { | |
12736 | if (tem == bb->head) | |
12737 | { | |
12738 | SET_BIT (refresh_blocks, | |
f6366fc7 | 12739 | this_basic_block->index); |
c762163e R |
12740 | need_refresh = 1; |
12741 | break; | |
12742 | } | |
12743 | continue; | |
12744 | } | |
12745 | if (dead_or_set_p (tem, piece) | |
12746 | || reg_bitfield_target_p (piece, | |
12747 | PATTERN (tem))) | |
12748 | { | |
12749 | REG_NOTES (tem) | |
71fd5a51 | 12750 | = gen_rtx_EXPR_LIST (REG_UNUSED, piece, |
c762163e R |
12751 | REG_NOTES (tem)); |
12752 | break; | |
12753 | } | |
12754 | } | |
12755 | ||
230d793d RS |
12756 | } |
12757 | ||
12758 | place = 0; | |
12759 | } | |
12760 | } | |
12761 | } | |
12762 | break; | |
12763 | ||
12764 | default: | |
12765 | /* Any other notes should not be present at this point in the | |
12766 | compilation. */ | |
12767 | abort (); | |
12768 | } | |
12769 | ||
12770 | if (place) | |
12771 | { | |
12772 | XEXP (note, 1) = REG_NOTES (place); | |
12773 | REG_NOTES (place) = note; | |
12774 | } | |
1a26b032 RK |
12775 | else if ((REG_NOTE_KIND (note) == REG_DEAD |
12776 | || REG_NOTE_KIND (note) == REG_UNUSED) | |
12777 | && GET_CODE (XEXP (note, 0)) == REG) | |
b1f21e0a | 12778 | REG_N_DEATHS (REGNO (XEXP (note, 0)))--; |
230d793d RS |
12779 | |
12780 | if (place2) | |
1a26b032 RK |
12781 | { |
12782 | if ((REG_NOTE_KIND (note) == REG_DEAD | |
12783 | || REG_NOTE_KIND (note) == REG_UNUSED) | |
12784 | && GET_CODE (XEXP (note, 0)) == REG) | |
b1f21e0a | 12785 | REG_N_DEATHS (REGNO (XEXP (note, 0)))++; |
1a26b032 | 12786 | |
38a448ca RH |
12787 | REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note), |
12788 | REG_NOTE_KIND (note), | |
12789 | XEXP (note, 0), | |
12790 | REG_NOTES (place2)); | |
1a26b032 | 12791 | } |
230d793d RS |
12792 | } |
12793 | } | |
12794 | \f | |
12795 | /* Similarly to above, distribute the LOG_LINKS that used to be present on | |
5089e22e RS |
12796 | I3, I2, and I1 to new locations. This is also called in one case to |
12797 | add a link pointing at I3 when I3's destination is changed. */ | |
230d793d RS |
12798 | |
12799 | static void | |
12800 | distribute_links (links) | |
12801 | rtx links; | |
12802 | { | |
12803 | rtx link, next_link; | |
12804 | ||
12805 | for (link = links; link; link = next_link) | |
12806 | { | |
12807 | rtx place = 0; | |
12808 | rtx insn; | |
12809 | rtx set, reg; | |
12810 | ||
12811 | next_link = XEXP (link, 1); | |
12812 | ||
12813 | /* If the insn that this link points to is a NOTE or isn't a single | |
12814 | set, ignore it. In the latter case, it isn't clear what we | |
663522cb | 12815 | can do other than ignore the link, since we can't tell which |
230d793d RS |
12816 | register it was for. Such links wouldn't be used by combine |
12817 | anyway. | |
12818 | ||
12819 | It is not possible for the destination of the target of the link to | |
12820 | have been changed by combine. The only potential of this is if we | |
12821 | replace I3, I2, and I1 by I3 and I2. But in that case the | |
12822 | destination of I2 also remains unchanged. */ | |
12823 | ||
12824 | if (GET_CODE (XEXP (link, 0)) == NOTE | |
12825 | || (set = single_set (XEXP (link, 0))) == 0) | |
12826 | continue; | |
12827 | ||
12828 | reg = SET_DEST (set); | |
12829 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
12830 | || GET_CODE (reg) == SIGN_EXTRACT | |
12831 | || GET_CODE (reg) == STRICT_LOW_PART) | |
12832 | reg = XEXP (reg, 0); | |
12833 | ||
12834 | /* A LOG_LINK is defined as being placed on the first insn that uses | |
12835 | a register and points to the insn that sets the register. Start | |
12836 | searching at the next insn after the target of the link and stop | |
12837 | when we reach a set of the register or the end of the basic block. | |
12838 | ||
12839 | Note that this correctly handles the link that used to point from | |
5089e22e | 12840 | I3 to I2. Also note that not much searching is typically done here |
230d793d RS |
12841 | since most links don't point very far away. */ |
12842 | ||
12843 | for (insn = NEXT_INSN (XEXP (link, 0)); | |
f6366fc7 ZD |
12844 | (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR |
12845 | || this_basic_block->next_bb->head != insn)); | |
230d793d | 12846 | insn = NEXT_INSN (insn)) |
2c3c49de | 12847 | if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) |
230d793d RS |
12848 | { |
12849 | if (reg_referenced_p (reg, PATTERN (insn))) | |
12850 | place = insn; | |
12851 | break; | |
12852 | } | |
6e2d1486 | 12853 | else if (GET_CODE (insn) == CALL_INSN |
663522cb | 12854 | && find_reg_fusage (insn, USE, reg)) |
6e2d1486 RK |
12855 | { |
12856 | place = insn; | |
12857 | break; | |
12858 | } | |
230d793d RS |
12859 | |
12860 | /* If we found a place to put the link, place it there unless there | |
12861 | is already a link to the same insn as LINK at that point. */ | |
12862 | ||
12863 | if (place) | |
12864 | { | |
12865 | rtx link2; | |
12866 | ||
12867 | for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) | |
12868 | if (XEXP (link2, 0) == XEXP (link, 0)) | |
12869 | break; | |
12870 | ||
12871 | if (link2 == 0) | |
12872 | { | |
12873 | XEXP (link, 1) = LOG_LINKS (place); | |
12874 | LOG_LINKS (place) = link; | |
abe6e52f RK |
12875 | |
12876 | /* Set added_links_insn to the earliest insn we added a | |
12877 | link to. */ | |
663522cb | 12878 | if (added_links_insn == 0 |
abe6e52f RK |
12879 | || INSN_CUID (added_links_insn) > INSN_CUID (place)) |
12880 | added_links_insn = place; | |
230d793d RS |
12881 | } |
12882 | } | |
12883 | } | |
12884 | } | |
12885 | \f | |
1427d6d2 RK |
12886 | /* Compute INSN_CUID for INSN, which is an insn made by combine. */ |
12887 | ||
12888 | static int | |
12889 | insn_cuid (insn) | |
12890 | rtx insn; | |
12891 | { | |
12892 | while (insn != 0 && INSN_UID (insn) > max_uid_cuid | |
12893 | && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE) | |
12894 | insn = NEXT_INSN (insn); | |
12895 | ||
12896 | if (INSN_UID (insn) > max_uid_cuid) | |
12897 | abort (); | |
12898 | ||
12899 | return INSN_CUID (insn); | |
12900 | } | |
12901 | \f | |
230d793d RS |
12902 | void |
12903 | dump_combine_stats (file) | |
12904 | FILE *file; | |
12905 | { | |
ab87f8c8 | 12906 | fnotice |
230d793d RS |
12907 | (file, |
12908 | ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", | |
12909 | combine_attempts, combine_merges, combine_extras, combine_successes); | |
12910 | } | |
12911 | ||
12912 | void | |
12913 | dump_combine_total_stats (file) | |
12914 | FILE *file; | |
12915 | { | |
ab87f8c8 | 12916 | fnotice |
230d793d RS |
12917 | (file, |
12918 | "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", | |
12919 | total_attempts, total_merges, total_extras, total_successes); | |
12920 | } |