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i386-common.c (OPTION_MASK_ISA_RDSEED_SET): New.
[thirdparty/gcc.git] / gcc / common / config / i386 / i386-common.c
CommitLineData
677f3fa8
JM		 1/* IA-32 common hooks.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 3, or (at your option)
11any later version.
12
13GCC is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
21
22#include "config.h"
23#include "system.h"
24#include "coretypes.h"
25#include "diagnostic-core.h"
26#include "tm.h"
27#include "tm_p.h"
28#include "common/common-target.h"
29#include "common/common-target-def.h"
30#include "opts.h"
31#include "flags.h"
32
33/* Define a set of ISAs which are available when a given ISA is
34 enabled. MMX and SSE ISAs are handled separately. */
35
36#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
37#define OPTION_MASK_ISA_3DNOW_SET \
38 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
39
40#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
41#define OPTION_MASK_ISA_SSE2_SET \
42 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
43#define OPTION_MASK_ISA_SSE3_SET \
44 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
45#define OPTION_MASK_ISA_SSSE3_SET \
46 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
47#define OPTION_MASK_ISA_SSE4_1_SET \
48 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
49#define OPTION_MASK_ISA_SSE4_2_SET \
50 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
51#define OPTION_MASK_ISA_AVX_SET \
52 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
53#define OPTION_MASK_ISA_FMA_SET \
54 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
7afac110
KY		 55#define OPTION_MASK_ISA_AVX2_SET \
56 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
bf2eaa3f 57#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
e61c94dd 58#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
4c340b5d 59#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
677f3fa8
JM		 60
61/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
62 as -msse4.2. */
63#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
64
65#define OPTION_MASK_ISA_SSE4A_SET \
66 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
67#define OPTION_MASK_ISA_FMA4_SET \
68 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
69 | OPTION_MASK_ISA_AVX_SET)
70#define OPTION_MASK_ISA_XOP_SET \
71 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
72#define OPTION_MASK_ISA_LWP_SET \
73 OPTION_MASK_ISA_LWP
74
75/* AES and PCLMUL need SSE2 because they use xmm registers */
76#define OPTION_MASK_ISA_AES_SET \
77 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
78#define OPTION_MASK_ISA_PCLMUL_SET \
79 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
80
81#define OPTION_MASK_ISA_ABM_SET \
82 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
83
84#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
82feeb8d 85#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
677f3fa8
JM		 86#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
87#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
88#define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
89#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
90#define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
91#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
92
93#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
94#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
95#define OPTION_MASK_ISA_F16C_SET \
96 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
97
98/* Define a set of ISAs which aren't available when a given ISA is
99 disabled. MMX and SSE ISAs are handled separately. */
100
101#define OPTION_MASK_ISA_MMX_UNSET \
102 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
103#define OPTION_MASK_ISA_3DNOW_UNSET \
104 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
105#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
106
107#define OPTION_MASK_ISA_SSE_UNSET \
108 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
109#define OPTION_MASK_ISA_SSE2_UNSET \
110 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
111#define OPTION_MASK_ISA_SSE3_UNSET \
112 (OPTION_MASK_ISA_SSE3 \
113 | OPTION_MASK_ISA_SSSE3_UNSET \
114 | OPTION_MASK_ISA_SSE4A_UNSET )
115#define OPTION_MASK_ISA_SSSE3_UNSET \
116 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
117#define OPTION_MASK_ISA_SSE4_1_UNSET \
118 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
119#define OPTION_MASK_ISA_SSE4_2_UNSET \
120 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
121#define OPTION_MASK_ISA_AVX_UNSET \
122 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
7afac110
KY		 123 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
124 | OPTION_MASK_ISA_AVX2_UNSET)
677f3fa8 125#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
7afac110 126#define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2
bf2eaa3f 127#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
e61c94dd 128#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
4c340b5d 129#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
677f3fa8
JM		 130
131/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
132 as -mno-sse4.1. */
133#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
134
135#define OPTION_MASK_ISA_SSE4A_UNSET \
136 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
137
138#define OPTION_MASK_ISA_FMA4_UNSET \
139 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
140#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
141#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
142
143#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
144#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
145#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
146#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
82feeb8d 147#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
677f3fa8
JM		 148#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
149#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
150#define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
151#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
152#define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
153#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
154
155#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
156#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
157#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
158
159/* Implement TARGET_HANDLE_OPTION. */
160
161bool
162ix86_handle_option (struct gcc_options *opts,
163 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
164 const struct cl_decoded_option *decoded,
165 location_t loc)
166{
167 size_t code = decoded->opt_index;
168 int value = decoded->value;
169
170 switch (code)
171 {
172 case OPT_mmmx:
173 if (value)
174 {
175 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
176 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
177 }
178 else
179 {
180 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
181 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
182 }
183 return true;
184
185 case OPT_m3dnow:
186 if (value)
187 {
188 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
189 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
190 }
191 else
192 {
193 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
194 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
195 }
196 return true;
197
198 case OPT_m3dnowa:
199 return false;
200
201 case OPT_msse:
202 if (value)
203 {
204 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
205 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
206 }
207 else
208 {
209 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
210 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
211 }
212 return true;
213
214 case OPT_msse2:
215 if (value)
216 {
217 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
218 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
219 }
220 else
221 {
222 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
223 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
224 }
225 return true;
226
227 case OPT_msse3:
228 if (value)
229 {
230 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
231 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
232 }
233 else
234 {
235 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
236 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
237 }
238 return true;
239
240 case OPT_mssse3:
241 if (value)
242 {
243 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
244 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
245 }
246 else
247 {
248 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
249 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
250 }
251 return true;
252
253 case OPT_msse4_1:
254 if (value)
255 {
256 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
257 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
258 }
259 else
260 {
261 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
262 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
263 }
264 return true;
265
266 case OPT_msse4_2:
267 if (value)
268 {
269 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
270 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
271 }
272 else
273 {
274 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
275 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
276 }
277 return true;
278
279 case OPT_mavx:
280 if (value)
281 {
282 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
283 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
284 }
285 else
286 {
287 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
288 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
289 }
290 return true;
291
7afac110
KY		 292 case OPT_mavx2:
293 if (value)
294 {
295 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
296 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
297 }
298 else
299 {
300 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
301 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
302 }
303 return true;
304
677f3fa8
JM		 305 case OPT_mfma:
306 if (value)
307 {
308 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
309 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
310 }
311 else
312 {
313 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
314 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
315 }
316 return true;
317
bf2eaa3f
KY		 318 case OPT_mrtm:
319 if (value)
320 {
321 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
322 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
323 }
324 else
325 {
326 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
327 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
328 }
329 return true;
330
677f3fa8
JM		 331 case OPT_msse4:
332 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
333 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
334 return true;
335
336 case OPT_mno_sse4:
337 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
338 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
339 return true;
340
341 case OPT_msse4a:
342 if (value)
343 {
344 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
345 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
346 }
347 else
348 {
349 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
350 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
351 }
352 return true;
353
354 case OPT_mfma4:
355 if (value)
356 {
357 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
358 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
359 }
360 else
361 {
362 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
363 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
364 }
365 return true;
366
367 case OPT_mxop:
368 if (value)
369 {
370 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
371 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
372 }
373 else
374 {
375 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
376 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
377 }
378 return true;
379
380 case OPT_mlwp:
381 if (value)
382 {
383 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
384 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
385 }
386 else
387 {
388 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
389 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
390 }
391 return true;
392
393 case OPT_mabm:
394 if (value)
395 {
396 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
397 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
398 }
399 else
400 {
401 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
402 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
403 }
404 return true;
405
406 case OPT_mbmi:
407 if (value)
408 {
409 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
410 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
411 }
412 else
413 {
414 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
415 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
416 }
417 return true;
418
82feeb8d
L		 419 case OPT_mbmi2:
420 if (value)
421 {
422 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
423 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
424 }
425 else
426 {
427 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
428 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
429 }
430 return true;
431
677f3fa8
JM		 432 case OPT_mtbm:
433 if (value)
434 {
435 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
436 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
437 }
438 else
439 {
440 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
441 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
442 }
443 return true;
444
445 case OPT_mpopcnt:
446 if (value)
447 {
448 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
449 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
450 }
451 else
452 {
453 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
454 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
455 }
456 return true;
457
458 case OPT_msahf:
459 if (value)
460 {
461 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
462 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
463 }
464 else
465 {
466 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
467 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
468 }
469 return true;
470
471 case OPT_mcx16:
472 if (value)
473 {
474 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
475 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
476 }
477 else
478 {
479 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
480 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
481 }
482 return true;
483
484 case OPT_mmovbe:
485 if (value)
486 {
487 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
488 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
489 }
490 else
491 {
492 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
493 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
494 }
495 return true;
496
497 case OPT_mcrc32:
498 if (value)
499 {
500 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
501 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
502 }
503 else
504 {
505 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
506 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
507 }
508 return true;
509
510 case OPT_maes:
511 if (value)
512 {
513 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
514 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
515 }
516 else
517 {
518 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
519 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
520 }
521 return true;
522
523 case OPT_mpclmul:
524 if (value)
525 {
526 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
527 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
528 }
529 else
530 {
531 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
532 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
533 }
534 return true;
535
536 case OPT_mfsgsbase:
537 if (value)
538 {
539 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
540 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
541 }
542 else
543 {
544 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
545 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
546 }
547 return true;
548
549 case OPT_mrdrnd:
550 if (value)
551 {
552 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
553 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
554 }
555 else
556 {
557 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
558 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
559 }
560 return true;
561
562 case OPT_mf16c:
563 if (value)
564 {
565 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
566 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
567 }
568 else
569 {
570 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
571 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
572 }
573 return true;
574
4c340b5d
KY		 575 case OPT_mrdseed:
576 if (value)
577 {
578 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
579 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
580 }
581 else
582 {
583 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
584 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
585 }
586 return true;
587
e61c94dd
KY		 588 case OPT_mprfchw:
589 if (value)
590 {
591 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
592 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
593 }
594 else
595 {
596 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
597 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
598 }
599 return true;
600
677f3fa8
JM		 601 /* Comes from final.c -- no real reason to change it. */
602#define MAX_CODE_ALIGN 16
603
604 case OPT_malign_loops_:
605 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops");
606 if (value > MAX_CODE_ALIGN)
607 error_at (loc, "-malign-loops=%d is not between 0 and %d",
608 value, MAX_CODE_ALIGN);
609 else
610 opts->x_align_loops = 1 << value;
611 return true;
612
613 case OPT_malign_jumps_:
614 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps");
615 if (value > MAX_CODE_ALIGN)
616 error_at (loc, "-malign-jumps=%d is not between 0 and %d",
617 value, MAX_CODE_ALIGN);
618 else
619 opts->x_align_jumps = 1 << value;
620 return true;
621
622 case OPT_malign_functions_:
623 warning_at (loc, 0,
624 "-malign-functions is obsolete, use -falign-functions");
625 if (value > MAX_CODE_ALIGN)
626 error_at (loc, "-malign-functions=%d is not between 0 and %d",
627 value, MAX_CODE_ALIGN);
628 else
629 opts->x_align_functions = 1 << value;
630 return true;
631
632 case OPT_mbranch_cost_:
633 if (value > 5)
634 {
635 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value);
636 opts->x_ix86_branch_cost = 5;
637 }
638 return true;
639
640 default:
641 return true;
642 }
643}
644
645static const struct default_options ix86_option_optimization_table[] =
646 {
95c64830
UB		 647 /* Enable redundant extension instructions removal at -O2 and higher. */
648 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
677f3fa8
JM		 649 /* Turn off -fschedule-insns by default. It tends to make the
650 problem with not enough registers even worse. */
651 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
652
653#ifdef SUBTARGET_OPTIMIZATION_OPTIONS
654 SUBTARGET_OPTIMIZATION_OPTIONS,
655#endif
656 { OPT_LEVELS_NONE, 0, NULL, 0 }
657 };
658
659/* Implement TARGET_OPTION_INIT_STRUCT. */
660
661static void
662ix86_option_init_struct (struct gcc_options *opts)
663{
664 if (TARGET_MACHO)
665 /* The Darwin libraries never set errno, so we might as well
666 avoid calling them when that's the only reason we would. */
667 opts->x_flag_errno_math = 0;
668
669 opts->x_flag_pcc_struct_return = 2;
670 opts->x_flag_asynchronous_unwind_tables = 2;
671 opts->x_flag_vect_cost_model = 1;
672}
673
674/* On the x86 -fsplit-stack and -fstack-protector both use the same
675 field in the TCB, so they can not be used together. */
676
677static bool
678ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
679 struct gcc_options *opts ATTRIBUTE_UNUSED)
680{
681 bool ret = true;
682
683#ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
684 if (report)
685 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
686 ret = false;
687#else
688 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
689 {
690 if (report)
691 error ("%<-fsplit-stack%> requires "
692 "assembler support for CFI directives");
693 ret = false;
694 }
695#endif
696
697 return ret;
698}
699
bf1431e3
TG		 700/* Implement TARGET_EXCEPT_UNWIND_INFO. */
701
702static enum unwind_info_type
703i386_except_unwind_info (struct gcc_options *opts)
704{
705 /* Honor the --enable-sjlj-exceptions configure switch. */
706#ifdef CONFIG_SJLJ_EXCEPTIONS
707 if (CONFIG_SJLJ_EXCEPTIONS)
708 return UI_SJLJ;
709#endif
710
711 /* On windows 64, prefer SEH exceptions over anything else. */
712 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
713 return UI_SEH;
714
715 if (DWARF2_UNWIND_INFO)
716 return UI_DWARF2;
717
718 return UI_SJLJ;
719}
720
721#undef TARGET_EXCEPT_UNWIND_INFO
722#define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
723
677f3fa8
JM		 724#undef TARGET_DEFAULT_TARGET_FLAGS
725#define TARGET_DEFAULT_TARGET_FLAGS \
726 (TARGET_DEFAULT \
727 | TARGET_SUBTARGET_DEFAULT \
728 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
729
730#undef TARGET_HANDLE_OPTION
731#define TARGET_HANDLE_OPTION ix86_handle_option
732
733#undef TARGET_OPTION_OPTIMIZATION_TABLE
734#define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
735#undef TARGET_OPTION_INIT_STRUCT
736#define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
737
738#undef TARGET_SUPPORTS_SPLIT_STACK
739#define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
740
741struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git