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677f3fa8 1/* IA-32 common hooks.
5624e564 2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
677f3fa8
JM		 3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20#include "config.h"
21#include "system.h"
22#include "coretypes.h"
23#include "diagnostic-core.h"
24#include "tm.h"
25#include "tm_p.h"
26#include "common/common-target.h"
27#include "common/common-target-def.h"
28#include "opts.h"
29#include "flags.h"
30
31/* Define a set of ISAs which are available when a given ISA is
32 enabled. MMX and SSE ISAs are handled separately. */
33
34#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
35#define OPTION_MASK_ISA_3DNOW_SET \
36 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
37
38#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
39#define OPTION_MASK_ISA_SSE2_SET \
40 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
41#define OPTION_MASK_ISA_SSE3_SET \
42 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
43#define OPTION_MASK_ISA_SSSE3_SET \
44 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
45#define OPTION_MASK_ISA_SSE4_1_SET \
46 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
47#define OPTION_MASK_ISA_SSE4_2_SET \
48 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
49#define OPTION_MASK_ISA_AVX_SET \
3a0d99bb
AI		 50 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
51 | OPTION_MASK_ISA_XSAVE_SET)
677f3fa8
JM		 52#define OPTION_MASK_ISA_FMA_SET \
53 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
7afac110
KY		 54#define OPTION_MASK_ISA_AVX2_SET \
55 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
3a0d99bb
AI		 56#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
57#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
58#define OPTION_MASK_ISA_XSAVEOPT_SET \
59 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE)
3f97cb0b
AI		 60#define OPTION_MASK_ISA_AVX512F_SET \
61 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
62#define OPTION_MASK_ISA_AVX512CD_SET \
63 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
64#define OPTION_MASK_ISA_AVX512PF_SET \
65 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
66#define OPTION_MASK_ISA_AVX512ER_SET \
67 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
07165dd7
AI		 68#define OPTION_MASK_ISA_AVX512DQ_SET \
69 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
b525d943
AI		 70#define OPTION_MASK_ISA_AVX512BW_SET \
71 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
f4af595f
AI		 72#define OPTION_MASK_ISA_AVX512VL_SET \
73 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
4190ea38
IT		 74#define OPTION_MASK_ISA_AVX512IFMA_SET \
75 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
3dcc8af5 76#define OPTION_MASK_ISA_AVX512VBMI_SET \
c67917b6 77 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
bf2eaa3f 78#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
e61c94dd 79#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
4c340b5d 80#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
d05e383b 81#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
43b3f52f 82#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
9cdea277
IT		 83#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
84#define OPTION_MASK_ISA_XSAVES_SET \
85 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE)
86#define OPTION_MASK_ISA_XSAVEC_SET \
87 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE)
9c3bca11 88#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
36e9b73e 89#define OPTION_MASK_ISA_PCOMMIT_SET OPTION_MASK_ISA_PCOMMIT
677f3fa8
JM		 90
91/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
92 as -msse4.2. */
93#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
94
95#define OPTION_MASK_ISA_SSE4A_SET \
96 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
97#define OPTION_MASK_ISA_FMA4_SET \
98 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
99 | OPTION_MASK_ISA_AVX_SET)
100#define OPTION_MASK_ISA_XOP_SET \
101 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
102#define OPTION_MASK_ISA_LWP_SET \
103 OPTION_MASK_ISA_LWP
104
c1618f82 105/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
677f3fa8
JM		 106#define OPTION_MASK_ISA_AES_SET \
107 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
c1618f82
AI		 108#define OPTION_MASK_ISA_SHA_SET \
109 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
677f3fa8
JM		 110#define OPTION_MASK_ISA_PCLMUL_SET \
111 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
112
113#define OPTION_MASK_ISA_ABM_SET \
114 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
115
116#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
82feeb8d 117#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
495e6879 118#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
677f3fa8
JM		 119#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
120#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
121#define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
122#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
123#define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
124#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
125
126#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
127#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
128#define OPTION_MASK_ISA_F16C_SET \
129 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
500a08b2 130#define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
677f3fa8
JM		 131
132/* Define a set of ISAs which aren't available when a given ISA is
133 disabled. MMX and SSE ISAs are handled separately. */
134
135#define OPTION_MASK_ISA_MMX_UNSET \
136 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
137#define OPTION_MASK_ISA_3DNOW_UNSET \
138 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
139#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
140
141#define OPTION_MASK_ISA_SSE_UNSET \
142 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
143#define OPTION_MASK_ISA_SSE2_UNSET \
144 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
145#define OPTION_MASK_ISA_SSE3_UNSET \
146 (OPTION_MASK_ISA_SSE3 \
147 | OPTION_MASK_ISA_SSSE3_UNSET \
148 | OPTION_MASK_ISA_SSE4A_UNSET )
149#define OPTION_MASK_ISA_SSSE3_UNSET \
150 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
151#define OPTION_MASK_ISA_SSE4_1_UNSET \
152 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
153#define OPTION_MASK_ISA_SSE4_2_UNSET \
154 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
155#define OPTION_MASK_ISA_AVX_UNSET \
156 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
7afac110 157 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
3a0d99bb 158 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
677f3fa8 159#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
3a0d99bb
AI		 160#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
161#define OPTION_MASK_ISA_XSAVE_UNSET \
162 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET)
163#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
3f97cb0b
AI		 164#define OPTION_MASK_ISA_AVX2_UNSET \
165 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
166#define OPTION_MASK_ISA_AVX512F_UNSET \
167 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
b525d943 168 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
f4af595f
AI		 169 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
170 | OPTION_MASK_ISA_AVX512VL_UNSET)
3f97cb0b
AI		 171#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
172#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
173#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
07165dd7 174#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
c67917b6
IT		 175#define OPTION_MASK_ISA_AVX512BW_UNSET \
176 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
f4af595f 177#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
4190ea38 178#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
3dcc8af5 179#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
bf2eaa3f 180#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
e61c94dd 181#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
4c340b5d 182#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
d05e383b 183#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
43b3f52f 184#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
9cdea277
IT		 185#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
186#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
187#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
36e9b73e 188#define OPTION_MASK_ISA_PCOMMIT_UNSET OPTION_MASK_ISA_PCOMMIT
9c3bca11 189#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
500a08b2 190#define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
677f3fa8
JM		 191
192/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
193 as -mno-sse4.1. */
194#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
195
196#define OPTION_MASK_ISA_SSE4A_UNSET \
197 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
198
199#define OPTION_MASK_ISA_FMA4_UNSET \
200 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
201#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
202#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
203
204#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
c1618f82 205#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
677f3fa8
JM		 206#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
207#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
208#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
82feeb8d 209#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
495e6879 210#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
677f3fa8
JM		 211#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
212#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
213#define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
214#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
215#define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
216#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
217
218#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
219#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
220#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
221
222/* Implement TARGET_HANDLE_OPTION. */
223
224bool
225ix86_handle_option (struct gcc_options *opts,
d9063947 226 struct gcc_options *opts_set,
677f3fa8
JM		 227 const struct cl_decoded_option *decoded,
228 location_t loc)
229{
230 size_t code = decoded->opt_index;
231 int value = decoded->value;
232
233 switch (code)
234 {
d9063947
L		 235 case OPT_miamcu:
236 if (value)
237 {
238 /* Turn off x87/MMX/SSE/AVX codegen for -miamcu. */
239 opts->x_target_flags &= ~MASK_80387;
240 opts_set->x_target_flags |= MASK_80387;
241 opts->x_ix86_isa_flags &= ~(OPTION_MASK_ISA_MMX_UNSET
242 | OPTION_MASK_ISA_SSE_UNSET);
243 opts->x_ix86_isa_flags_explicit |= (OPTION_MASK_ISA_MMX_UNSET
244 | OPTION_MASK_ISA_SSE_UNSET);
245
246 }
247 return true;
248
677f3fa8
JM		 249 case OPT_mmmx:
250 if (value)
251 {
252 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
253 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
254 }
255 else
256 {
257 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
258 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
259 }
260 return true;
261
262 case OPT_m3dnow:
263 if (value)
264 {
265 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
266 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
267 }
268 else
269 {
270 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
271 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
272 }
273 return true;
274
275 case OPT_m3dnowa:
276 return false;
277
278 case OPT_msse:
279 if (value)
280 {
281 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
282 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
283 }
284 else
285 {
286 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
287 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
288 }
289 return true;
290
291 case OPT_msse2:
292 if (value)
293 {
294 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
295 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
296 }
297 else
298 {
299 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
300 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
301 }
302 return true;
303
304 case OPT_msse3:
305 if (value)
306 {
307 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
308 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
309 }
310 else
311 {
312 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
313 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
314 }
315 return true;
316
317 case OPT_mssse3:
318 if (value)
319 {
320 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
321 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
322 }
323 else
324 {
325 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
326 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
327 }
328 return true;
329
330 case OPT_msse4_1:
331 if (value)
332 {
333 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
334 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
335 }
336 else
337 {
338 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
339 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
340 }
341 return true;
342
343 case OPT_msse4_2:
344 if (value)
345 {
346 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
347 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
348 }
349 else
350 {
351 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
352 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
353 }
354 return true;
355
356 case OPT_mavx:
357 if (value)
358 {
359 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
360 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
361 }
362 else
363 {
364 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
365 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
366 }
367 return true;
368
7afac110
KY		 369 case OPT_mavx2:
370 if (value)
371 {
372 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
373 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
374 }
375 else
376 {
377 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
378 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
379 }
380 return true;
381
3f97cb0b
AI		 382 case OPT_mavx512f:
383 if (value)
384 {
385 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
386 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
387 }
388 else
389 {
390 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
391 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
392 }
393 return true;
394
395 case OPT_mavx512cd:
396 if (value)
397 {
398 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
399 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
400 }
401 else
402 {
403 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
404 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
405 }
406 return true;
407
408 case OPT_mavx512pf:
409 if (value)
410 {
411 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
412 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
413 }
414 else
415 {
416 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
417 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
418 }
419 return true;
420
421 case OPT_mavx512er:
422 if (value)
423 {
424 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
425 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
426 }
427 else
428 {
429 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
430 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
431 }
432 return true;
433
07165dd7
AI		 434 case OPT_mavx512dq:
435 if (value)
436 {
437 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
438 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
439 }
440 else
441 {
442 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
443 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
444 }
445 return true;
446
b525d943
AI		 447 case OPT_mavx512bw:
448 if (value)
449 {
450 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
451 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
452 }
453 else
454 {
455 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
456 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
457 }
458 return true;
459
f4af595f
AI		 460 case OPT_mavx512vl:
461 if (value)
462 {
463 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
464 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
465 }
466 else
467 {
468 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
469 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
470 }
471 return true;
472
4190ea38
IT		 473 case OPT_mavx512ifma:
474 if (value)
475 {
476 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
477 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
478 }
479 else
480 {
481 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
482 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
483 }
484 return true;
485
3dcc8af5
IT		 486 case OPT_mavx512vbmi:
487 if (value)
488 {
489 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
490 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
491 }
492 else
493 {
494 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
495 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
496 }
497 return true;
498
677f3fa8
JM		 499 case OPT_mfma:
500 if (value)
501 {
502 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
503 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
504 }
505 else
506 {
507 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
508 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
509 }
510 return true;
511
bf2eaa3f
KY		 512 case OPT_mrtm:
513 if (value)
514 {
515 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
516 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
517 }
518 else
519 {
520 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
521 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
522 }
523 return true;
524
677f3fa8
JM		 525 case OPT_msse4:
526 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
527 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
528 return true;
529
530 case OPT_mno_sse4:
531 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
532 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
533 return true;
534
535 case OPT_msse4a:
536 if (value)
537 {
538 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
539 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
540 }
541 else
542 {
543 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
544 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
545 }
546 return true;
547
548 case OPT_mfma4:
549 if (value)
550 {
551 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
552 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
553 }
554 else
555 {
556 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
557 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
558 }
559 return true;
560
561 case OPT_mxop:
562 if (value)
563 {
564 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
565 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
566 }
567 else
568 {
569 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
570 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
571 }
572 return true;
573
574 case OPT_mlwp:
575 if (value)
576 {
577 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
578 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
579 }
580 else
581 {
582 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
583 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
584 }
585 return true;
586
587 case OPT_mabm:
588 if (value)
589 {
590 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
591 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
592 }
593 else
594 {
595 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
596 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
597 }
598 return true;
599
600 case OPT_mbmi:
601 if (value)
602 {
603 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
604 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
605 }
606 else
607 {
608 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
609 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
610 }
611 return true;
612
82feeb8d
L		 613 case OPT_mbmi2:
614 if (value)
615 {
616 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
617 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
618 }
619 else
620 {
621 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
622 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
623 }
624 return true;
625
495e6879
ST		 626 case OPT_mlzcnt:
627 if (value)
628 {
629 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
630 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
631 }
632 else
633 {
634 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
635 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
636 }
b7df379f 637 return true;
495e6879 638
677f3fa8
JM		 639 case OPT_mtbm:
640 if (value)
641 {
642 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
643 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
644 }
645 else
646 {
647 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
648 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
649 }
650 return true;
651
652 case OPT_mpopcnt:
653 if (value)
654 {
655 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
656 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
657 }
658 else
659 {
660 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
661 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
662 }
663 return true;
664
665 case OPT_msahf:
666 if (value)
667 {
668 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
669 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
670 }
671 else
672 {
673 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
674 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
675 }
676 return true;
677
678 case OPT_mcx16:
679 if (value)
680 {
681 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
682 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
683 }
684 else
685 {
686 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
687 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
688 }
689 return true;
690
691 case OPT_mmovbe:
692 if (value)
693 {
694 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
695 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
696 }
697 else
698 {
699 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
700 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
701 }
702 return true;
703
704 case OPT_mcrc32:
705 if (value)
706 {
707 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
708 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
709 }
710 else
711 {
712 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
713 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
714 }
715 return true;
716
717 case OPT_maes:
718 if (value)
719 {
720 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
721 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
722 }
723 else
724 {
725 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
726 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
727 }
728 return true;
729
c1618f82
AI		 730 case OPT_msha:
731 if (value)
732 {
733 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
734 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
735 }
736 else
737 {
738 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
739 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
740 }
741 return true;
742
677f3fa8
JM		 743 case OPT_mpclmul:
744 if (value)
745 {
746 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
747 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
748 }
749 else
750 {
751 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
752 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
753 }
754 return true;
755
756 case OPT_mfsgsbase:
757 if (value)
758 {
759 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
760 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
761 }
762 else
763 {
764 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
765 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
766 }
767 return true;
768
769 case OPT_mrdrnd:
770 if (value)
771 {
772 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
773 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
774 }
775 else
776 {
777 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
778 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
779 }
780 return true;
781
782 case OPT_mf16c:
783 if (value)
784 {
785 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
786 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
787 }
788 else
789 {
790 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
791 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
792 }
793 return true;
794
3a0d99bb
AI		 795 case OPT_mfxsr:
796 if (value)
797 {
798 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
799 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
800 }
801 else
802 {
803 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
804 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
805 }
806 return true;
807
808 case OPT_mxsave:
809 if (value)
810 {
811 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
812 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
813 }
814 else
815 {
816 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
817 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
818 }
819 return true;
820
821 case OPT_mxsaveopt:
822 if (value)
823 {
824 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
825 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
826 }
827 else
828 {
829 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
830 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
831 }
832 return true;
833
9cdea277
IT		 834 case OPT_mxsavec:
835 if (value)
836 {
837 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
838 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
839 }
840 else
841 {
842 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
843 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
844 }
845 return true;
846
847 case OPT_mxsaves:
848 if (value)
849 {
850 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
851 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
852 }
853 else
854 {
855 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
856 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
857 }
858 return true;
859
4c340b5d
KY		 860 case OPT_mrdseed:
861 if (value)
862 {
863 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
864 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
865 }
866 else
867 {
868 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
869 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
870 }
871 return true;
872
e61c94dd
KY		 873 case OPT_mprfchw:
874 if (value)
875 {
876 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
877 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
878 }
879 else
880 {
881 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
882 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
883 }
884 return true;
885
d05e383b
MZ		 886 case OPT_madx:
887 if (value)
888 {
889 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
890 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
891 }
892 else
893 {
894 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
895 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
896 }
897 return true;
898
43b3f52f
IT		 899 case OPT_mprefetchwt1:
900 if (value)
901 {
902 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
903 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
904 }
905 else
906 {
907 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
908 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
909 }
910 return true;
911
9cdea277
IT		 912 case OPT_mclflushopt:
913 if (value)
914 {
915 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
916 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
917 }
918 else
919 {
920 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
921 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
922 }
923 return true;
924
36e9b73e
IT		 925 case OPT_mpcommit:
926 if (value)
927 {
928 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCOMMIT_SET;
929 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCOMMIT_SET;
930 }
931 else
932 {
933 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCOMMIT_UNSET;
934 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCOMMIT_UNSET;
935 }
936 return true;
937
9c3bca11
IT		 938 case OPT_mclwb:
939 if (value)
940 {
941 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
942 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
943 }
944 else
945 {
946 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
947 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
948 }
949 return true;
950
500a08b2
VK		 951 case OPT_mmwaitx:
952 if (value)
953 {
954 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX_SET;
955 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MWAITX_SET;
956 }
957 else
958 {
959 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MWAITX_UNSET;
960 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MWAITX_UNSET;
961 }
962 return true;
963
677f3fa8
JM		 964 /* Comes from final.c -- no real reason to change it. */
965#define MAX_CODE_ALIGN 16
966
967 case OPT_malign_loops_:
968 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops");
969 if (value > MAX_CODE_ALIGN)
970 error_at (loc, "-malign-loops=%d is not between 0 and %d",
971 value, MAX_CODE_ALIGN);
972 else
973 opts->x_align_loops = 1 << value;
974 return true;
975
976 case OPT_malign_jumps_:
977 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps");
978 if (value > MAX_CODE_ALIGN)
979 error_at (loc, "-malign-jumps=%d is not between 0 and %d",
980 value, MAX_CODE_ALIGN);
981 else
982 opts->x_align_jumps = 1 << value;
983 return true;
984
985 case OPT_malign_functions_:
986 warning_at (loc, 0,
987 "-malign-functions is obsolete, use -falign-functions");
988 if (value > MAX_CODE_ALIGN)
989 error_at (loc, "-malign-functions=%d is not between 0 and %d",
990 value, MAX_CODE_ALIGN);
991 else
992 opts->x_align_functions = 1 << value;
993 return true;
994
995 case OPT_mbranch_cost_:
996 if (value > 5)
997 {
998 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value);
999 opts->x_ix86_branch_cost = 5;
1000 }
1001 return true;
1002
1003 default:
1004 return true;
1005 }
1006}
1007
1008static const struct default_options ix86_option_optimization_table[] =
1009 {
95c64830
UB		 1010 /* Enable redundant extension instructions removal at -O2 and higher. */
1011 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
32ad0f03
TJ		 1012 /* Enable function splitting at -O2 and higher. */
1013 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
677f3fa8
JM		 1014 /* Turn off -fschedule-insns by default. It tends to make the
1015 problem with not enough registers even worse. */
1016 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1017
1018#ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1019 SUBTARGET_OPTIMIZATION_OPTIONS,
1020#endif
1021 { OPT_LEVELS_NONE, 0, NULL, 0 }
1022 };
1023
1024/* Implement TARGET_OPTION_INIT_STRUCT. */
1025
1026static void
1027ix86_option_init_struct (struct gcc_options *opts)
1028{
1029 if (TARGET_MACHO)
1030 /* The Darwin libraries never set errno, so we might as well
1031 avoid calling them when that's the only reason we would. */
1032 opts->x_flag_errno_math = 0;
1033
1034 opts->x_flag_pcc_struct_return = 2;
1035 opts->x_flag_asynchronous_unwind_tables = 2;
677f3fa8
JM		 1036}
1037
1038/* On the x86 -fsplit-stack and -fstack-protector both use the same
1039 field in the TCB, so they can not be used together. */
1040
1041static bool
1042ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1043 struct gcc_options *opts ATTRIBUTE_UNUSED)
1044{
1045 bool ret = true;
1046
1047#ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1048 if (report)
1049 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1050 ret = false;
1051#else
1052 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1053 {
1054 if (report)
1055 error ("%<-fsplit-stack%> requires "
1056 "assembler support for CFI directives");
1057 ret = false;
1058 }
1059#endif
1060
1061 return ret;
1062}
1063
bf1431e3
TG		 1064/* Implement TARGET_EXCEPT_UNWIND_INFO. */
1065
1066static enum unwind_info_type
1067i386_except_unwind_info (struct gcc_options *opts)
1068{
1069 /* Honor the --enable-sjlj-exceptions configure switch. */
1070#ifdef CONFIG_SJLJ_EXCEPTIONS
1071 if (CONFIG_SJLJ_EXCEPTIONS)
1072 return UI_SJLJ;
1073#endif
1074
1075 /* On windows 64, prefer SEH exceptions over anything else. */
1076 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1077 return UI_SEH;
1078
1079 if (DWARF2_UNWIND_INFO)
1080 return UI_DWARF2;
1081
1082 return UI_SJLJ;
1083}
1084
1085#undef TARGET_EXCEPT_UNWIND_INFO
1086#define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1087
677f3fa8
JM		 1088#undef TARGET_DEFAULT_TARGET_FLAGS
1089#define TARGET_DEFAULT_TARGET_FLAGS \
1090 (TARGET_DEFAULT \
1091 | TARGET_SUBTARGET_DEFAULT \
1092 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1093
1094#undef TARGET_HANDLE_OPTION
1095#define TARGET_HANDLE_OPTION ix86_handle_option
1096
1097#undef TARGET_OPTION_OPTIMIZATION_TABLE
1098#define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1099#undef TARGET_OPTION_INIT_STRUCT
1100#define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1101
1102#undef TARGET_SUPPORTS_SPLIT_STACK
1103#define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1104
1105struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git