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218e3e4e 1/* IA-32 common hooks.
fbd26352 2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
218e3e4e 3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20#include "config.h"
21#include "system.h"
22#include "coretypes.h"
23#include "diagnostic-core.h"
24#include "tm.h"
ad7b10a2 25#include "memmodel.h"
218e3e4e 26#include "tm_p.h"
27#include "common/common-target.h"
28#include "common/common-target-def.h"
29#include "opts.h"
30#include "flags.h"
31
32/* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36#define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
2b77b495 38#define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
218e3e4e 40
41#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42#define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44#define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46#define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48#define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50#define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52#define OPTION_MASK_ISA_AVX_SET \
32eca732 53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
218e3e4e 55#define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
d2a15bb8 57#define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
32eca732 59#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61#define OPTION_MASK_ISA_XSAVEOPT_SET \
44e41981 62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
e13e1b39 63#define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65#define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67#define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69#define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
89e0402e 71#define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
38d90d48 73#define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
5bb7556d 75#define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
8a12b665 77#define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
afee0628 79#define OPTION_MASK_ISA_AVX512VBMI_SET \
1c699c14 80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
37d0f067 81#define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
82#define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
743b05ae 83#define OPTION_MASK_ISA_AVX512VBMI2_SET \
84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
1c5a2faa 85#define OPTION_MASK_ISA_AVX512VNNI_SET \
86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
18e3c8c4 87#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
89#define OPTION_MASK_ISA_AVX512BITALG_SET \
90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
bce88dc2 91#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
7962a5b1 92#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
eff9fe28 93#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
41bc5727 94#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
e3659231 95#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
2ed44428 96#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
97#define OPTION_MASK_ISA_XSAVES_SET \
44e41981 98 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
2ed44428 99#define OPTION_MASK_ISA_XSAVEC_SET \
44e41981 100 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
741c191b 101#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
218e3e4e 102
103/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
104 as -msse4.2. */
105#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
106
107#define OPTION_MASK_ISA_SSE4A_SET \
108 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
109#define OPTION_MASK_ISA_FMA4_SET \
110 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
111 | OPTION_MASK_ISA_AVX_SET)
112#define OPTION_MASK_ISA_XOP_SET \
113 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
114#define OPTION_MASK_ISA_LWP_SET \
115 OPTION_MASK_ISA_LWP
116
fc975a40 117/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
218e3e4e 118#define OPTION_MASK_ISA_AES_SET \
119 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
fc975a40 120#define OPTION_MASK_ISA_SHA_SET \
121 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
218e3e4e 122#define OPTION_MASK_ISA_PCLMUL_SET \
123 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
124
125#define OPTION_MASK_ISA_ABM_SET \
126 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
127
e2449138 128#define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG
129#define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD
e012a4fd 130#define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX
218e3e4e 131#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
2339767f 132#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
cab840cb 133#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
218e3e4e 134#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
135#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
136#define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
137#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
138#define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
139#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
140
141#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
142#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
742da499 143#define OPTION_MASK_ISA_PTWRITE_SET OPTION_MASK_ISA_PTWRITE
218e3e4e 144#define OPTION_MASK_ISA_F16C_SET \
145 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
f17272b7 146#define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
1b1db4e0 147#define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
25222ada 148#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
7be207bc 149#define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID
213ed75d 150#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
92ac8192 151#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
932d6527 152#define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES
29ca66ec 153#define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
bc74a837 154#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
155#define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B
c0437050 156#define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG
ecd752b4 157#define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE
218e3e4e 158
159/* Define a set of ISAs which aren't available when a given ISA is
160 disabled. MMX and SSE ISAs are handled separately. */
161
162#define OPTION_MASK_ISA_MMX_UNSET \
163 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
164#define OPTION_MASK_ISA_3DNOW_UNSET \
165 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
166#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
167
168#define OPTION_MASK_ISA_SSE_UNSET \
169 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
170#define OPTION_MASK_ISA_SSE2_UNSET \
171 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
172#define OPTION_MASK_ISA_SSE3_UNSET \
173 (OPTION_MASK_ISA_SSE3 \
174 | OPTION_MASK_ISA_SSSE3_UNSET \
175 | OPTION_MASK_ISA_SSE4A_UNSET )
176#define OPTION_MASK_ISA_SSSE3_UNSET \
177 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
178#define OPTION_MASK_ISA_SSE4_1_UNSET \
179 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
180#define OPTION_MASK_ISA_SSE4_2_UNSET \
181 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
182#define OPTION_MASK_ISA_AVX_UNSET \
183 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
d2a15bb8 184 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
32eca732 185 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
218e3e4e 186#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
32eca732 187#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
188#define OPTION_MASK_ISA_XSAVE_UNSET \
44e41981 189 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
190 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET)
32eca732 191#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
e13e1b39 192#define OPTION_MASK_ISA_AVX2_UNSET \
193 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
194#define OPTION_MASK_ISA_AVX512F_UNSET \
195 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
38d90d48 196 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
5bb7556d 197 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
0ef5554b 198 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
0ef5554b 199 | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
200 | OPTION_MASK_ISA_AVX512VNNI_UNSET \
201 | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
18e3c8c4 202 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
e13e1b39 203#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
204#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
205#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
89e0402e 206#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
1c699c14 207#define OPTION_MASK_ISA_AVX512BW_UNSET \
208 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
5bb7556d 209#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
8a12b665 210#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
afee0628 211#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
37d0f067 212#define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
213#define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
68a8f795 214#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
aee0d4e2 215#define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
e0aa57d6 216#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
391c3f0c 217#define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
bce88dc2 218#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
7962a5b1 219#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
eff9fe28 220#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
41bc5727 221#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
e3659231 222#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
2ed44428 223#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
224#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
225#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
741c191b 226#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
f17272b7 227#define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
1b1db4e0 228#define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
25222ada 229#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
7be207bc 230#define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID
213ed75d 231#define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
92ac8192 232#define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
932d6527 233#define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES
29ca66ec 234#define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
bc74a837 235#define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
236#define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B
c0437050 237#define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG
ecd752b4 238#define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE
218e3e4e 239
240/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
241 as -mno-sse4.1. */
242#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
243
244#define OPTION_MASK_ISA_SSE4A_UNSET \
245 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
246
247#define OPTION_MASK_ISA_FMA4_UNSET \
248 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
249#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
250#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
251
252#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
fc975a40 253#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
218e3e4e 254#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
255#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
e2449138 256#define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG
257#define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD
e012a4fd 258#define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX
218e3e4e 259#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
2339767f 260#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
cab840cb 261#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
218e3e4e 262#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
263#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
264#define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
265#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
266#define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
267#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
268
269#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
270#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
742da499 271#define OPTION_MASK_ISA_PTWRITE_UNSET OPTION_MASK_ISA_PTWRITE
218e3e4e 272#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
273
f4094380 274#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
275 (OPTION_MASK_ISA_MMX_UNSET \
d4e677bf 276 | OPTION_MASK_ISA_SSE_UNSET)
f4094380 277
18e3c8c4 278#define OPTION_MASK_ISA2_AVX512F_UNSET \
279 (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | OPTION_MASK_ISA_AVX5124VNNIW_UNSET)
280#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
1e42d5c6 281 (OPTION_MASK_ISA2_AVX512F_UNSET)
18e3c8c4 282
6848a0ae 283/* Set 1 << value as value of -malign-FLAG option. */
284
285static void
286set_malign_value (const char **flag, unsigned value)
287{
288 char *r = XNEWVEC (char, 6);
289 sprintf (r, "%d", 1 << value);
290 *flag = r;
291}
292
218e3e4e 293/* Implement TARGET_HANDLE_OPTION. */
294
295bool
296ix86_handle_option (struct gcc_options *opts,
80d3e9ad 297 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
218e3e4e 298 const struct cl_decoded_option *decoded,
299 location_t loc)
300{
301 size_t code = decoded->opt_index;
302 int value = decoded->value;
303
304 switch (code)
305 {
f4094380 306 case OPT_mgeneral_regs_only:
307 if (value)
308 {
1e42d5c6 309 /* Disable MMX, SSE and x87 instructions if only
f4094380 310 general registers are allowed. */
311 opts->x_ix86_isa_flags
312 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
d4e677bf 313 opts->x_ix86_isa_flags2
18e3c8c4 314 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
f4094380 315 opts->x_ix86_isa_flags_explicit
316 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
d4e677bf 317 opts->x_ix86_isa_flags2_explicit
18e3c8c4 318 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
f4094380 319
320 opts->x_target_flags &= ~MASK_80387;
321 }
322 else
323 gcc_unreachable ();
324 return true;
325
218e3e4e 326 case OPT_mmmx:
327 if (value)
328 {
329 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
330 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
331 }
332 else
333 {
334 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
335 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
336 }
337 return true;
338
339 case OPT_m3dnow:
340 if (value)
341 {
342 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
343 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
344 }
345 else
346 {
347 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
348 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
349 }
350 return true;
351
352 case OPT_m3dnowa:
2b77b495 353 if (value)
354 {
355 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
356 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
357 }
358 else
359 {
360 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
361 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
362 }
363 return true;
218e3e4e 364
365 case OPT_msse:
366 if (value)
367 {
368 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
369 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
370 }
371 else
372 {
373 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
374 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
18e3c8c4 375 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
376 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
218e3e4e 377 }
378 return true;
379
380 case OPT_msse2:
381 if (value)
382 {
383 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
384 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
385 }
386 else
387 {
388 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
389 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
18e3c8c4 390 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
391 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
218e3e4e 392 }
393 return true;
394
395 case OPT_msse3:
396 if (value)
397 {
398 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
399 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
400 }
401 else
402 {
403 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
404 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
18e3c8c4 405 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
406 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
218e3e4e 407 }
408 return true;
409
410 case OPT_mssse3:
411 if (value)
412 {
413 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
414 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
415 }
416 else
417 {
418 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
419 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
18e3c8c4 420 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
421 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
218e3e4e 422 }
423 return true;
424
425 case OPT_msse4_1:
426 if (value)
427 {
428 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
429 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
430 }
431 else
432 {
433 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
434 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
18e3c8c4 435 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
436 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
218e3e4e 437 }
438 return true;
439
440 case OPT_msse4_2:
441 if (value)
442 {
443 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
444 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
445 }
446 else
447 {
448 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
449 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
18e3c8c4 450 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
451 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
218e3e4e 452 }
453 return true;
454
455 case OPT_mavx:
456 if (value)
457 {
458 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
459 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
460 }
461 else
462 {
463 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
464 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
18e3c8c4 465 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
466 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
218e3e4e 467 }
468 return true;
469
d2a15bb8 470 case OPT_mavx2:
471 if (value)
472 {
473 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
474 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
475 }
476 else
477 {
478 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
479 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
18e3c8c4 480 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
481 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
d2a15bb8 482 }
483 return true;
484
e13e1b39 485 case OPT_mavx512f:
486 if (value)
487 {
488 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
489 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
490 }
491 else
492 {
493 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
494 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
18e3c8c4 495 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
496 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
e13e1b39 497 }
498 return true;
499
500 case OPT_mavx512cd:
501 if (value)
502 {
503 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
504 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
505 }
506 else
507 {
508 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
509 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
510 }
511 return true;
512
513 case OPT_mavx512pf:
514 if (value)
515 {
516 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
517 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
518 }
519 else
520 {
521 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
522 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
523 }
524 return true;
525
526 case OPT_mavx512er:
527 if (value)
528 {
529 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
530 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
531 }
532 else
533 {
534 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
535 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
536 }
537 return true;
538
7be207bc 539 case OPT_mrdpid:
540 if (value)
541 {
542 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET;
543 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET;
544 }
545 else
546 {
547 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET;
548 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET;
549 }
550 return true;
551
213ed75d 552 case OPT_mgfni:
553 if (value)
554 {
d4e677bf 555 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
556 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
213ed75d 557 }
558 else
559 {
d4e677bf 560 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
561 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
213ed75d 562 }
563 return true;
564
92ac8192 565 case OPT_mshstk:
566 if (value)
567 {
743b05ae 568 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
569 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
92ac8192 570 }
571 else
572 {
743b05ae 573 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
574 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
92ac8192 575 }
576 return true;
577
932d6527 578 case OPT_mvaes:
579 if (value)
580 {
581 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET;
582 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET;
583 }
584 else
585 {
586 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET;
587 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET;
588 }
589 return true;
590
29ca66ec 591 case OPT_mvpclmulqdq:
592 if (value)
593 {
594 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
595 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
596 }
597 else
598 {
599 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
600 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
601 }
602 return true;
603
bc74a837 604 case OPT_mmovdiri:
605 if (value)
606 {
607 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
608 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
609 }
610 else
611 {
612 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
613 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
614 }
615 return true;
616
617 case OPT_mmovdir64b:
618 if (value)
619 {
620 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET;
621 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET;
622 }
623 else
624 {
625 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET;
626 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET;
627 }
ecd752b4 628 return true;
629
630 case OPT_mcldemote:
631 if (value)
632 {
633 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLDEMOTE_SET;
634 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_SET;
635 }
636 else
637 {
638 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLDEMOTE_UNSET;
639 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_UNSET;
640 }
bc74a837 641 return true;
642
c0437050 643 case OPT_mwaitpkg:
644 if (value)
645 {
646 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WAITPKG_SET;
647 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_SET;
648 }
649 else
650 {
651 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WAITPKG_UNSET;
652 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_UNSET;
653 }
654 return true;
655
37d0f067 656 case OPT_mavx5124fmaps:
657 if (value)
658 {
659 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
660 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
661 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
662 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
663 }
664 else
665 {
666 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
667 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
668 }
669 return true;
670
671 case OPT_mavx5124vnniw:
672 if (value)
673 {
674 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
675 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
676 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
677 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
678 }
679 else
680 {
681 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
682 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
683 }
684 return true;
685
68a8f795 686 case OPT_mavx512vbmi2:
687 if (value)
688 {
743b05ae 689 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
690 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
68a8f795 691 }
692 else
693 {
743b05ae 694 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
695 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
68a8f795 696 }
697 return true;
698
aee0d4e2 699 case OPT_mavx512vnni:
700 if (value)
701 {
1c5a2faa 702 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
703 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
aee0d4e2 704 }
705 else
706 {
1c5a2faa 707 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
708 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
aee0d4e2 709 }
710 return true;
711
e0aa57d6 712 case OPT_mavx512vpopcntdq:
713 if (value)
714 {
18e3c8c4 715 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
716 opts->x_ix86_isa_flags_explicit
717 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
e0aa57d6 718 }
719 else
720 {
18e3c8c4 721 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
722 opts->x_ix86_isa_flags_explicit
723 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
e0aa57d6 724 }
725 return true;
391c3f0c 726
727 case OPT_mavx512bitalg:
728 if (value)
729 {
18e3c8c4 730 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
731 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
391c3f0c 732 }
733 else
734 {
18e3c8c4 735 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
736 opts->x_ix86_isa_flags_explicit
391c3f0c 737 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
738 }
739 return true;
e0aa57d6 740
e012a4fd 741 case OPT_msgx:
742 if (value)
743 {
744 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET;
745 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET;
746 }
747 else
748 {
749 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET;
750 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET;
751 }
752 return true;
753
e2449138 754 case OPT_mpconfig:
755 if (value)
756 {
757 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET;
758 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET;
759 }
760 else
761 {
762 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET;
763 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET;
764 }
765 return true;
766
767 case OPT_mwbnoinvd:
768 if (value)
769 {
770 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET;
771 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET;
772 }
773 else
774 {
775 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET;
776 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET;
777 }
778 return true;
779
89e0402e 780 case OPT_mavx512dq:
781 if (value)
782 {
783 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
784 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
785 }
786 else
787 {
788 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
789 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
790 }
791 return true;
792
38d90d48 793 case OPT_mavx512bw:
794 if (value)
795 {
796 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
797 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
798 }
799 else
800 {
801 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
802 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
803 }
804 return true;
805
5bb7556d 806 case OPT_mavx512vl:
807 if (value)
808 {
809 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
810 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
811 }
812 else
813 {
814 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
815 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
816 }
817 return true;
818
8a12b665 819 case OPT_mavx512ifma:
820 if (value)
821 {
822 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
823 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
824 }
825 else
826 {
827 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
828 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
829 }
830 return true;
831
afee0628 832 case OPT_mavx512vbmi:
833 if (value)
834 {
835 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
836 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
837 }
838 else
839 {
840 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
841 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
842 }
843 return true;
844
218e3e4e 845 case OPT_mfma:
846 if (value)
847 {
848 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
849 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
850 }
851 else
852 {
853 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
854 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
855 }
856 return true;
857
bce88dc2 858 case OPT_mrtm:
859 if (value)
860 {
861 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
862 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
863 }
864 else
865 {
866 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
867 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
868 }
869 return true;
870
218e3e4e 871 case OPT_msse4:
872 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
873 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
874 return true;
875
876 case OPT_mno_sse4:
877 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
878 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
18e3c8c4 879 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
880 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
218e3e4e 881 return true;
882
883 case OPT_msse4a:
884 if (value)
885 {
886 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
887 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
888 }
889 else
890 {
891 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
892 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
893 }
894 return true;
895
896 case OPT_mfma4:
897 if (value)
898 {
899 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
900 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
901 }
902 else
903 {
904 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
905 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
906 }
907 return true;
908
909 case OPT_mxop:
910 if (value)
911 {
912 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
913 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
914 }
915 else
916 {
917 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
918 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
919 }
920 return true;
921
922 case OPT_mlwp:
923 if (value)
924 {
925 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
926 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
927 }
928 else
929 {
930 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
931 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
932 }
933 return true;
934
935 case OPT_mabm:
936 if (value)
937 {
938 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
939 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
940 }
941 else
942 {
943 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
944 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
945 }
946 return true;
947
948 case OPT_mbmi:
949 if (value)
950 {
951 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
952 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
953 }
954 else
955 {
956 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
957 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
958 }
959 return true;
960
2339767f 961 case OPT_mbmi2:
962 if (value)
963 {
964 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
965 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
966 }
967 else
968 {
969 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
970 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
971 }
972 return true;
973
cab840cb 974 case OPT_mlzcnt:
975 if (value)
976 {
977 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
978 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
979 }
980 else
981 {
982 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
983 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
984 }
15f8efea 985 return true;
cab840cb 986
218e3e4e 987 case OPT_mtbm:
988 if (value)
989 {
990 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
991 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
992 }
993 else
994 {
995 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
996 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
997 }
998 return true;
999
1000 case OPT_mpopcnt:
1001 if (value)
1002 {
1003 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1004 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1005 }
1006 else
1007 {
1008 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1009 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1010 }
1011 return true;
1012
1013 case OPT_msahf:
1014 if (value)
1015 {
1016 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1017 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1018 }
1019 else
1020 {
1021 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1022 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1023 }
1024 return true;
1025
1026 case OPT_mcx16:
1027 if (value)
1028 {
29ca66ec 1029 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET;
1030 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET;
218e3e4e 1031 }
1032 else
1033 {
29ca66ec 1034 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET;
1035 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET;
218e3e4e 1036 }
1037 return true;
1038
1039 case OPT_mmovbe:
1040 if (value)
1041 {
743b05ae 1042 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET;
1043 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET;
218e3e4e 1044 }
1045 else
1046 {
743b05ae 1047 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET;
1048 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
218e3e4e 1049 }
1050 return true;
1051
1052 case OPT_mcrc32:
1053 if (value)
1054 {
1055 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1056 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1057 }
1058 else
1059 {
1060 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1061 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1062 }
1063 return true;
1064
1065 case OPT_maes:
1066 if (value)
1067 {
1068 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1069 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1070 }
1071 else
1072 {
1073 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1074 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1075 }
1076 return true;
1077
fc975a40 1078 case OPT_msha:
1079 if (value)
1080 {
1081 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1082 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1083 }
1084 else
1085 {
1086 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1087 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1088 }
1089 return true;
1090
218e3e4e 1091 case OPT_mpclmul:
1092 if (value)
1093 {
1094 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1095 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1096 }
1097 else
1098 {
1099 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1100 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1101 }
1102 return true;
1103
1104 case OPT_mfsgsbase:
1105 if (value)
1106 {
1107 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1108 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1109 }
1110 else
1111 {
1112 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1113 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1114 }
1115 return true;
1116
1117 case OPT_mrdrnd:
1118 if (value)
1119 {
1120 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1121 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1122 }
1123 else
1124 {
1125 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1126 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1127 }
1128 return true;
1129
742da499 1130 case OPT_mptwrite:
1131 if (value)
1132 {
1133 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PTWRITE_SET;
1134 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PTWRITE_SET;
1135 }
1136 else
1137 {
1138 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PTWRITE_UNSET;
1139 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PTWRITE_UNSET;
1140 }
1141 return true;
1142
218e3e4e 1143 case OPT_mf16c:
1144 if (value)
1145 {
1146 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1147 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1148 }
1149 else
1150 {
1151 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1152 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1153 }
1154 return true;
1155
32eca732 1156 case OPT_mfxsr:
1157 if (value)
1158 {
1159 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1160 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1161 }
1162 else
1163 {
1164 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1165 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1166 }
1167 return true;
1168
1169 case OPT_mxsave:
1170 if (value)
1171 {
1172 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1173 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1174 }
1175 else
1176 {
1177 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1178 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1179 }
1180 return true;
1181
1182 case OPT_mxsaveopt:
1183 if (value)
1184 {
1185 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1186 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1187 }
1188 else
1189 {
1190 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1191 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1192 }
1193 return true;
1194
2ed44428 1195 case OPT_mxsavec:
1196 if (value)
1197 {
1198 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1199 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1200 }
1201 else
1202 {
1203 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1204 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1205 }
1206 return true;
1207
1208 case OPT_mxsaves:
1209 if (value)
1210 {
1211 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1212 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1213 }
1214 else
1215 {
1216 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1217 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1218 }
1219 return true;
1220
eff9fe28 1221 case OPT_mrdseed:
1222 if (value)
1223 {
1224 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1225 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1226 }
1227 else
1228 {
1229 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1230 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1231 }
1232 return true;
1233
7962a5b1 1234 case OPT_mprfchw:
1235 if (value)
1236 {
1237 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1238 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1239 }
1240 else
1241 {
1242 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1243 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1244 }
1245 return true;
1246
41bc5727 1247 case OPT_madx:
1248 if (value)
1249 {
1250 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1251 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1252 }
1253 else
1254 {
1255 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1256 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1257 }
1258 return true;
1259
e3659231 1260 case OPT_mprefetchwt1:
1261 if (value)
1262 {
1263 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1264 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1265 }
1266 else
1267 {
1268 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1269 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1270 }
1271 return true;
1272
2ed44428 1273 case OPT_mclflushopt:
1274 if (value)
1275 {
1276 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1277 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1278 }
1279 else
1280 {
1281 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1282 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1283 }
1284 return true;
1285
741c191b 1286 case OPT_mclwb:
1287 if (value)
1288 {
1289 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1290 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1291 }
1292 else
1293 {
1294 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1295 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1296 }
1297 return true;
1298
f17272b7 1299 case OPT_mmwaitx:
1300 if (value)
1301 {
743b05ae 1302 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET;
1303 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET;
f17272b7 1304 }
1305 else
1306 {
743b05ae 1307 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET;
1308 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET;
f17272b7 1309 }
1310 return true;
1311
1b1db4e0 1312 case OPT_mclzero:
1313 if (value)
1314 {
743b05ae 1315 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET;
1316 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET;
1b1db4e0 1317 }
1318 else
1319 {
743b05ae 1320 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET;
1321 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET;
1b1db4e0 1322 }
1323 return true;
1324
25222ada 1325 case OPT_mpku:
1326 if (value)
1327 {
1328 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1329 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1330 }
1331 else
1332 {
1333 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1334 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1335 }
1336 return true;
1337
1b1db4e0 1338
218e3e4e 1339 case OPT_malign_loops_:
1340 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops");
1341 if (value > MAX_CODE_ALIGN)
1342 error_at (loc, "-malign-loops=%d is not between 0 and %d",
1343 value, MAX_CODE_ALIGN);
1344 else
6848a0ae 1345 set_malign_value (&opts->x_str_align_loops, value);
218e3e4e 1346 return true;
1347
1348 case OPT_malign_jumps_:
1349 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps");
1350 if (value > MAX_CODE_ALIGN)
1351 error_at (loc, "-malign-jumps=%d is not between 0 and %d",
1352 value, MAX_CODE_ALIGN);
1353 else
6848a0ae 1354 set_malign_value (&opts->x_str_align_jumps, value);
218e3e4e 1355 return true;
1356
1357 case OPT_malign_functions_:
1358 warning_at (loc, 0,
1359 "-malign-functions is obsolete, use -falign-functions");
1360 if (value > MAX_CODE_ALIGN)
1361 error_at (loc, "-malign-functions=%d is not between 0 and %d",
1362 value, MAX_CODE_ALIGN);
1363 else
6848a0ae 1364 set_malign_value (&opts->x_str_align_functions, value);
218e3e4e 1365 return true;
1366
1367 case OPT_mbranch_cost_:
1368 if (value > 5)
1369 {
1370 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value);
1371 opts->x_ix86_branch_cost = 5;
1372 }
1373 return true;
1374
1375 default:
1376 return true;
1377 }
1378}
1379
1380static const struct default_options ix86_option_optimization_table[] =
1381 {
4d722a49 1382 /* Enable redundant extension instructions removal at -O2 and higher. */
1383 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
e4bb2b6e 1384 /* Enable function splitting at -O2 and higher. */
1385 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
61ff1ae3 1386 /* The STC algorithm produces the smallest code at -Os, for x86. */
1387 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1388 REORDER_BLOCKS_ALGORITHM_STC },
218e3e4e 1389 /* Turn off -fschedule-insns by default. It tends to make the
1390 problem with not enough registers even worse. */
1391 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1392
1393#ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1394 SUBTARGET_OPTIMIZATION_OPTIONS,
1395#endif
1396 { OPT_LEVELS_NONE, 0, NULL, 0 }
1397 };
1398
1399/* Implement TARGET_OPTION_INIT_STRUCT. */
1400
1401static void
1402ix86_option_init_struct (struct gcc_options *opts)
1403{
1404 if (TARGET_MACHO)
1405 /* The Darwin libraries never set errno, so we might as well
1406 avoid calling them when that's the only reason we would. */
1407 opts->x_flag_errno_math = 0;
1408
1409 opts->x_flag_pcc_struct_return = 2;
1410 opts->x_flag_asynchronous_unwind_tables = 2;
218e3e4e 1411}
1412
1413/* On the x86 -fsplit-stack and -fstack-protector both use the same
1414 field in the TCB, so they can not be used together. */
1415
1416static bool
1417ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1418 struct gcc_options *opts ATTRIBUTE_UNUSED)
1419{
1420 bool ret = true;
1421
1422#ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1423 if (report)
1424 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1425 ret = false;
1426#else
1427 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1428 {
1429 if (report)
1430 error ("%<-fsplit-stack%> requires "
1431 "assembler support for CFI directives");
1432 ret = false;
1433 }
1434#endif
1435
1436 return ret;
1437}
1438
8ad0b530 1439/* Implement TARGET_EXCEPT_UNWIND_INFO. */
1440
1441static enum unwind_info_type
1442i386_except_unwind_info (struct gcc_options *opts)
1443{
1444 /* Honor the --enable-sjlj-exceptions configure switch. */
1445#ifdef CONFIG_SJLJ_EXCEPTIONS
1446 if (CONFIG_SJLJ_EXCEPTIONS)
1447 return UI_SJLJ;
1448#endif
1449
1450 /* On windows 64, prefer SEH exceptions over anything else. */
1451 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1452 return UI_SEH;
1453
1454 if (DWARF2_UNWIND_INFO)
1455 return UI_DWARF2;
1456
1457 return UI_SJLJ;
1458}
1459
1460#undef TARGET_EXCEPT_UNWIND_INFO
1461#define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1462
218e3e4e 1463#undef TARGET_DEFAULT_TARGET_FLAGS
1464#define TARGET_DEFAULT_TARGET_FLAGS \
1465 (TARGET_DEFAULT \
1466 | TARGET_SUBTARGET_DEFAULT \
1467 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1468
1469#undef TARGET_HANDLE_OPTION
1470#define TARGET_HANDLE_OPTION ix86_handle_option
1471
1472#undef TARGET_OPTION_OPTIMIZATION_TABLE
1473#define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1474#undef TARGET_OPTION_INIT_STRUCT
1475#define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1476
1477#undef TARGET_SUPPORTS_SPLIT_STACK
1478#define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1479
b2903606 1480/* This table must be in sync with enum processor_type in i386.h. */
67369544 1481const char *const processor_names[] =
b2903606 1482{
78040ae8 1483 "generic",
1484 "i386",
1485 "i486",
1486 "pentium",
1487 "lakemont",
1488 "pentiumpro",
1489 "pentium4",
1490 "nocona",
1491 "core2",
1492 "nehalem",
1493 "sandybridge",
1494 "haswell",
1495 "bonnell",
1496 "silvermont",
1497 "goldmont",
1498 "goldmont-plus",
1499 "tremont",
1500 "knl",
1501 "knm",
1502 "skylake",
1503 "skylake-avx512",
1504 "cannonlake",
1505 "icelake-client",
1506 "icelake-server",
e9d55eda 1507 "cascadelake",
78040ae8 1508 "intel",
1509 "geode",
1510 "k6",
1511 "athlon",
1512 "k8",
1513 "amdfam10",
1514 "bdver1",
1515 "bdver2",
1516 "bdver3",
1517 "bdver4",
1518 "btver1",
1519 "btver2",
67369544 1520 "znver1",
1521 "znver2"
b2903606 1522};
1523
67369544 1524/* Guarantee that the array is aligned with enum processor_type. */
1525STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
1526
b2903606 1527const pta processor_alias_table[] =
1528{
1529 {"i386", PROCESSOR_I386, CPU_NONE, 0},
1530 {"i486", PROCESSOR_I486, CPU_NONE, 0},
1531 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
1532 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
1533 {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
1534 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
1535 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
1536 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1537 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1538 {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1539 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1540 PTA_MMX | PTA_SSE | PTA_FXSR},
1541 {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1542 PTA_MMX | PTA_SSE | PTA_FXSR},
1543 {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1544 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1545 {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1546 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1547 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
1548 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
1549 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
1550 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1551 PTA_MMX | PTA_SSE | PTA_FXSR},
1552 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1553 PTA_MMX | PTA_SSE | PTA_FXSR},
1554 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1555 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1556 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
1557 PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
1558 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
1559 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1560 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
1561 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1562 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
1563 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1564 | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
1565 {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
1566 {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
1567 {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
1568 {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
1569 {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1570 PTA_SANDYBRIDGE},
1571 {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1572 PTA_SANDYBRIDGE},
1573 {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1574 PTA_IVYBRIDGE},
1575 {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1576 PTA_IVYBRIDGE},
1577 {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
1578 {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
1579 {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
1580 {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
1581 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
1582 PTA_SKYLAKE_AVX512},
1583 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
1584 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
1585 PTA_ICELAKE_CLIENT},
1586 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
1587 PTA_ICELAKE_SERVER},
e9d55eda 1588 {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
1589 PTA_CASCADELAKE},
b2903606 1590 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
1591 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
1592 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
1593 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
1594 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
1595 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
1596 {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
1597 {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
1598 {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
1599 {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
1600 {"geode", PROCESSOR_GEODE, CPU_GEODE,
1601 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1602 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
1603 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
1604 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
1605 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
1606 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1607 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
1608 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1609 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
1610 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1611 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
1612 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1613 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
1614 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1615 {"x86-64", PROCESSOR_K8, CPU_K8,
1616 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1617 {"eden-x2", PROCESSOR_K8, CPU_K8,
1618 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1619 {"nano", PROCESSOR_K8, CPU_K8,
1620 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1621 | PTA_SSSE3 | PTA_FXSR},
1622 {"nano-1000", PROCESSOR_K8, CPU_K8,
1623 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1624 | PTA_SSSE3 | PTA_FXSR},
1625 {"nano-2000", PROCESSOR_K8, CPU_K8,
1626 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1627 | PTA_SSSE3 | PTA_FXSR},
1628 {"nano-3000", PROCESSOR_K8, CPU_K8,
1629 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1630 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1631 {"nano-x2", PROCESSOR_K8, CPU_K8,
1632 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1633 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1634 {"eden-x4", PROCESSOR_K8, CPU_K8,
1635 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1636 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1637 {"nano-x4", PROCESSOR_K8, CPU_K8,
1638 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1639 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1640 {"k8", PROCESSOR_K8, CPU_K8,
1641 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1642 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1643 {"k8-sse3", PROCESSOR_K8, CPU_K8,
1644 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1645 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1646 {"opteron", PROCESSOR_K8, CPU_K8,
1647 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1648 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1649 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
1650 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1651 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1652 {"athlon64", PROCESSOR_K8, CPU_K8,
1653 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1654 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1655 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
1656 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1657 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1658 {"athlon-fx", PROCESSOR_K8, CPU_K8,
1659 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1660 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1661 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
1662 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1663 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
1664 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
1665 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1666 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
1667 {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
1668 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1669 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1670 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1671 | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
1672 {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
1673 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1674 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1675 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1676 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
1677 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
1678 {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
1679 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1680 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1681 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1682 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
1683 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
1684 | PTA_XSAVEOPT | PTA_FSGSBASE},
1685 {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
1686 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1687 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1688 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1689 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
1690 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
1691 | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
1692 | PTA_MOVBE | PTA_MWAITX},
1693 {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
1694 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1695 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1696 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1697 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
1698 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
1699 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
1700 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
1701 | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
703d2f69 1702 {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER1,
1703 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1704 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1705 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1706 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
1707 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
1708 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
1709 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
1710 | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
1711 | PTA_WBNOINVD},
b2903606 1712 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
1713 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1714 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
1715 | PTA_FXSR | PTA_XSAVE},
1716 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
1717 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1718 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
1719 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
1720 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
1721 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
1722
1723 {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
1724 PTA_64BIT
1725 | PTA_HLE /* flags are only used for -march switch. */ },
1726};
1727
1728int const pta_size = ARRAY_SIZE (processor_alias_table);
1729
1730/* Provide valid option values for -march and -mtune options. */
1731
1732vec<const char *>
1733ix86_get_valid_option_values (int option_code,
1734 const char *prefix ATTRIBUTE_UNUSED)
1735{
1736 vec<const char *> v;
1737 v.create (0);
1738 opt_code opt = (opt_code) option_code;
1739
1740 switch (opt)
1741 {
1742 case OPT_march_:
1743 for (unsigned i = 0; i < pta_size; i++)
67369544 1744 {
1745 const char *name = processor_alias_table[i].name;
1746 gcc_checking_assert (name != NULL);
1747 v.safe_push (name);
1748 }
1749#ifdef HAVE_LOCAL_CPU_DETECT
1750 /* Add also "native" as possible value. */
1751 v.safe_push ("native");
1752#endif
1753
b2903606 1754 break;
1755 case OPT_mtune_:
1756 for (unsigned i = 0; i < PROCESSOR_max; i++)
67369544 1757 {
1758 const char *name = processor_names[i];
1759 gcc_checking_assert (name != NULL);
1760 v.safe_push (name);
1761 }
b2903606 1762 break;
1763 default:
1764 break;
1765 }
1766
1767 return v;
1768}
1769
1770#undef TARGET_GET_VALID_OPTION_VALUES
1771#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
1772
218e3e4e 1773struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git