[thirdparty/gcc.git] / gcc / config / aarch64 / aarch64-cores.def

/* Copyright (C) 2011-2019 Free Software Foundation, Inc.
   Contributed by ARM Ltd.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GCC is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

/* This is a list of cores that implement AArch64.

   Before using #include to read this file, define a macro:

      AARCH64_CORE(CORE_NAME, CORE_IDENT, SCHEDULER_IDENT, ARCH_IDENT, FLAGS, COSTS, IMP, PART, VARIANT)

   The CORE_NAME is the name of the core, represented as a string constant.
   The CORE_IDENT is the name of the core, represented as an identifier.
   The SCHEDULER_IDENT is the name of the core for which scheduling decisions
   will be made, represented as an identifier.
   ARCH_IDENT is the architecture implemented by the chip as specified in
   aarch64-arches.def.
   FLAGS are the bitwise-or of the traits that apply to that core.
   This need not include flags implied by the architecture.
   COSTS is the name of the rtx_costs routine to use.
   IMP is the implementer ID of the CPU vendor.  On a GNU/Linux system it
   can be found in /proc/cpuinfo. A partial list of implementer IDs is
   given in the ARM Architecture Reference Manual ARMv8, for
   ARMv8-A architecture profile.
   PART is the part number of the CPU.  On a GNU/Linux system it can be
   found in /proc/cpuinfo.  For big.LITTLE systems this should use the
   macro AARCH64_BIG_LITTLE where the big part number comes as the first
   argument to the macro and little is the second.
   VARIANT is the variant of the CPU.  In a GNU/Linux system it can found
   in /proc/cpuinfo.  If this is -1, this means it can match any variant.  */

/* ARMv8-A Architecture Processors.  */

/* ARM ('A') cores. */
AARCH64_CORE("cortex-a35",  cortexa35, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, 0x41, 0xd04, -1)
AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, 0x41, 0xd03, -1)
AARCH64_CORE("cortex-a57",  cortexa57, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, 0xd07, -1)
AARCH64_CORE("cortex-a72",  cortexa72, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, 0x41, 0xd08, -1)
AARCH64_CORE("cortex-a73",  cortexa73, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, 0xd09, -1)

/* Cavium ('C') cores. */
AARCH64_CORE("thunderx",      thunderx,      thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  0x43, 0x0a0, -1)
/* Do not swap around "thunderxt88p1" and "thunderxt88",
   this order is required to handle variant correctly. */
AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO,	thunderxt88,  0x43, 0x0a1, 0)
AARCH64_CORE("thunderxt88",   thunderxt88,   thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderxt88,  0x43, 0x0a1, -1)

/* OcteonTX is the official name for T81/T83. */
AARCH64_CORE("octeontx",      octeontx,      thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  0x43, 0x0a0, -1)
AARCH64_CORE("octeontx81",    octeontxt81,   thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  0x43, 0x0a2, -1)
AARCH64_CORE("octeontx83",    octeontxt83,   thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  0x43, 0x0a3, -1)

AARCH64_CORE("thunderxt81",   thunderxt81,   thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  0x43, 0x0a2, -1)
AARCH64_CORE("thunderxt83",   thunderxt83,   thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  0x43, 0x0a3, -1)

/* Ampere Computing cores. */
/* Do not swap around "emag" and "xgene1",
   this order is required to handle variant correctly. */
AARCH64_CORE("emag",        emag,      xgene1,    8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, emag, 0x50, 0x000, 3)

/* APM ('P') cores. */
AARCH64_CORE("xgene1",      xgene1,    xgene1,    8A,  AARCH64_FL_FOR_ARCH8, xgene1, 0x50, 0x000, -1)

/* Qualcomm ('Q') cores. */
AARCH64_CORE("falkor",      falkor,    falkor,    8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 0xC00, -1)
AARCH64_CORE("qdf24xx",     qdf24xx,   falkor,    8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx,   0x51, 0xC00, -1)

/* Samsung ('S') cores. */
AARCH64_CORE("exynos-m1",   exynosm1,  exynosm1,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1,  0x53, 0x001, -1)

/* HXT ('h') cores. */
AARCH64_CORE("phecda",      phecda,    falkor,    8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx,   0x68, 0x000, -1)

/* ARMv8.1-A Architecture Processors.  */

/* Broadcom ('B') cores. */
AARCH64_CORE("thunderx2t99p1",  thunderx2t99p1, thunderx2t99, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1)
AARCH64_CORE("vulcan",  vulcan, thunderx2t99, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1)

/* Cavium ('C') cores. */
AARCH64_CORE("thunderx2t99",  thunderx2t99,  thunderx2t99, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1)

/* ARMv8.2-A Architecture Processors.  */

/* ARM ('A') cores. */
AARCH64_CORE("cortex-a55",  cortexa55, cortexa53, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1)
AARCH64_CORE("cortex-a75",  cortexa75, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1)
AARCH64_CORE("cortex-a76",  cortexa76, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1)
AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1)

/* HiSilicon ('H') cores. */
AARCH64_CORE("tsv110",  tsv110, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)

/* ARMv8.4-A Architecture Processors.  */

/* Qualcomm ('Q') cores. */
AARCH64_CORE("saphira",     saphira,    saphira,    8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   0x51, 0xC01, -1)

/* ARMv8-A big.LITTLE implementations.  */

AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1)
AARCH64_CORE("cortex-a72.cortex-a53",  cortexa72cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, 0x41, AARCH64_BIG_LITTLE (0xd08, 0xd03), -1)
AARCH64_CORE("cortex-a73.cortex-a35",  cortexa73cortexa35, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd04), -1)
AARCH64_CORE("cortex-a73.cortex-a53",  cortexa73cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd03), -1)

/* ARM DynamIQ big.LITTLE configurations.  */

AARCH64_CORE("cortex-a75.cortex-a55",  cortexa75cortexa55, cortexa53, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1)
AARCH64_CORE("cortex-a76.cortex-a55",  cortexa76cortexa55, cortexa53, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, AARCH64_BIG_LITTLE (0xd0b, 0xd05), -1)

#undef AARCH64_CORE
Commit	Line	Data
a5544970	1	/* Copyright (C) 2011-2019 Free Software Foundation, Inc.
43e9d192 IB	2	Contributed by ARM Ltd.
	3
	4	This file is part of GCC.
	5
	6	GCC is free software; you can redistribute it and/or modify it
	7	under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 3, or (at your option)
	9	any later version.
	10
	11	GCC is distributed in the hope that it will be useful, but
	12	WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with GCC; see the file COPYING3. If not see
	18	<http://www.gnu.org/licenses/>. */
	19
	20	/* This is a list of cores that implement AArch64.
	21
	22	Before using #include to read this file, define a macro:
	23
e8fcc9fa	24	AARCH64_CORE(CORE_NAME, CORE_IDENT, SCHEDULER_IDENT, ARCH_IDENT, FLAGS, COSTS, IMP, PART, VARIANT)
43e9d192 IB	25
	26	The CORE_NAME is the name of the core, represented as a string constant.
	27	The CORE_IDENT is the name of the core, represented as an identifier.
192ed1dd JG	28	The SCHEDULER_IDENT is the name of the core for which scheduling decisions
192ed1dd JG	29	will be made, represented as an identifier.
393ae126 KT	30	ARCH_IDENT is the architecture implemented by the chip as specified in
393ae126 KT	31	aarch64-arches.def.
43e9d192 IB	32	FLAGS are the bitwise-or of the traits that apply to that core.
43e9d192 IB	33	This need not include flags implied by the architecture.
7e1bcce3	34	COSTS is the name of the rtx_costs routine to use.
2e721daa AP	35	IMP is the implementer ID of the CPU vendor. On a GNU/Linux system it
	36	can be found in /proc/cpuinfo. A partial list of implementer IDs is
	37	given in the ARM Architecture Reference Manual ARMv8, for
	38	ARMv8-A architecture profile.
	39	PART is the part number of the CPU. On a GNU/Linux system it can be
	40	found in /proc/cpuinfo. For big.LITTLE systems this should use the
	41	macro AARCH64_BIG_LITTLE where the big part number comes as the first
e8fcc9fa AP	42	argument to the macro and little is the second.
	43	VARIANT is the variant of the CPU. In a GNU/Linux system it can found
	44	in /proc/cpuinfo. If this is -1, this means it can match any variant. */
43e9d192	45
27b9e8dc	46	/* ARMv8-A Architecture Processors. */
43e9d192	47
4d9205d5	48	/* ARM ('A') cores. */
e8fcc9fa AP	49	AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa35, 0x41, 0xd04, -1)
	50	AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa53, 0x41, 0xd03, -1)
	51	AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa57, 0x41, 0xd07, -1)
	52	AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa72, 0x41, 0xd08, -1)
	53	AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa73, 0x41, 0xd09, -1)
4d9205d5	54
4d9205d5	55	/* Cavium ('C') cores. */
71aba51d	56	AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a0, -1)
e8fcc9fa AP	57	/* Do not swap around "thunderxt88p1" and "thunderxt88",
e8fcc9fa AP	58	this order is required to handle variant correctly. */
f1e247d0 AP	59	AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, thunderxt88, 0x43, 0x0a1, 0)
f1e247d0 AP	60	AARCH64_CORE("thunderxt88", thunderxt88, thunderx, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, thunderxt88, 0x43, 0x0a1, -1)
257992db AP	61
	62	/* OcteonTX is the official name for T81/T83. */
	63	AARCH64_CORE("octeontx", octeontx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a0, -1)
	64	AARCH64_CORE("octeontx81", octeontxt81, thunderx, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a2, -1)
	65	AARCH64_CORE("octeontx83", octeontxt83, thunderx, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a3, -1)
	66
71aba51d AP	67	AARCH64_CORE("thunderxt81", thunderxt81, thunderx, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a2, -1)
71aba51d AP	68	AARCH64_CORE("thunderxt83", thunderxt83, thunderx, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a3, -1)
4d9205d5	69
e02669db CM	70	/* Ampere Computing cores. */
	71	/* Do not swap around "emag" and "xgene1",
	72	this order is required to handle variant correctly. */
	73	AARCH64_CORE("emag", emag, xgene1, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, emag, 0x50, 0x000, 3)
	74
4d9205d5	75	/* APM ('P') cores. */
e8fcc9fa	76	AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, 0x50, 0x000, -1)
f00f3b67	77
27b9e8dc	78	/* Qualcomm ('Q') cores. */
825ada35 JW	79	AARCH64_CORE("falkor", falkor, falkor, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO \| AARCH64_FL_RDMA, qdf24xx, 0x51, 0xC00, -1)
825ada35 JW	80	AARCH64_CORE("qdf24xx", qdf24xx, falkor, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO \| AARCH64_FL_RDMA, qdf24xx, 0x51, 0xC00, -1)
27b9e8dc JG	81
	82	/* Samsung ('S') cores. */
	83	AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001, -1)
	84
dc878fea HZ	85	/* HXT ('h') cores. */
	86	AARCH64_CORE("phecda", phecda, falkor, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC \| AARCH64_FL_CRYPTO, qdf24xx, 0x68, 0x000, -1)
	87
27b9e8dc	88	/* ARMv8.1-A Architecture Processors. */
717b373c	89
4d9205d5	90	/* Broadcom ('B') cores. */
05a46f60	91	AARCH64_CORE("thunderx2t99p1", thunderx2t99p1, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 \| AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1)
f192030d	92	AARCH64_CORE("vulcan", vulcan, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 \| AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1)
717b373c	93
27b9e8dc JG	94	/* Cavium ('C') cores. */
	95	AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 \| AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1)
	96
9a85b75f JG	97	/* ARMv8.2-A Architecture Processors. */
	98
	99	/* ARM ('A') cores. */
30af63d7 KT	100	AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 \| AARCH64_FL_F16 \| AARCH64_FL_RCPC \| AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1)
30af63d7 KT	101	AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 \| AARCH64_FL_F16 \| AARCH64_FL_RCPC \| AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1)
25846b50	102	AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 \| AARCH64_FL_F16 \| AARCH64_FL_RCPC \| AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1)
ce1485c1	103	AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 \| AARCH64_FL_F16 \| AARCH64_FL_RCPC \| AARCH64_FL_DOTPROD \| AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1)
9a85b75f	104
910f72e7	105	/* HiSilicon ('H') cores. */
5a8d95cc SZ	106	AARCH64_CORE("tsv110", tsv110, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 \| AARCH64_FL_CRYPTO \| AARCH64_FL_F16 \| AARCH64_FL_AES \| AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1)
	107
	108	/* ARMv8.4-A Architecture Processors. */
910f72e7	109
52ee8191	110	/* Qualcomm ('Q') cores. */
2e9d500e	111	AARCH64_CORE("saphira", saphira, saphira, 8_4A, AARCH64_FL_FOR_ARCH8_4 \| AARCH64_FL_CRYPTO \| AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1)
52ee8191	112
27b9e8dc	113	/* ARMv8-A big.LITTLE implementations. */
f00f3b67	114
e8fcc9fa AP	115	AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1)
	116	AARCH64_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa72, 0x41, AARCH64_BIG_LITTLE (0xd08, 0xd03), -1)
	117	AARCH64_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd04), -1)
	118	AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 \| AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd03), -1)
cd8b19af	119
9a85b75f JG	120	/* ARM DynamIQ big.LITTLE configurations. */
9a85b75f JG	121
30af63d7	122	AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 \| AARCH64_FL_F16 \| AARCH64_FL_RCPC \| AARCH64_FL_DOTPROD, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1)
25846b50	123	AARCH64_CORE("cortex-a76.cortex-a55", cortexa76cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 \| AARCH64_FL_F16 \| AARCH64_FL_RCPC \| AARCH64_FL_DOTPROD, cortexa72, 0x41, AARCH64_BIG_LITTLE (0xd0b, 0xd05), -1)
9a85b75f	124
cd8b19af	125	#undef AARCH64_CORE