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1 | /* Machine description for AArch64 architecture. |
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2 | Copyright (C) 2009-2016 Free Software Foundation, Inc. |
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3 | Contributed by ARM Ltd. |
| 4 | |
| 5 | This file is part of GCC. |
| 6 | |
| 7 | GCC is free software; you can redistribute it and/or modify it |
| 8 | under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GCC is distributed in the hope that it will be useful, but |
| 13 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GCC; see the file COPYING3. If not see |
| 19 | <http://www.gnu.org/licenses/>. */ |
| 20 | |
| 21 | CC_MODE (CCFP); |
| 22 | CC_MODE (CCFPE); |
| 23 | CC_MODE (CC_SWP); |
| 24 | CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS). */ |
| 25 | CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS). */ |
| 26 | CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */ |
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27 | CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */ |
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28 | CC_MODE (CC_DNE); |
| 29 | CC_MODE (CC_DEQ); |
| 30 | CC_MODE (CC_DLE); |
| 31 | CC_MODE (CC_DLT); |
| 32 | CC_MODE (CC_DGE); |
| 33 | CC_MODE (CC_DGT); |
| 34 | CC_MODE (CC_DLEU); |
| 35 | CC_MODE (CC_DLTU); |
| 36 | CC_MODE (CC_DGEU); |
| 37 | CC_MODE (CC_DGTU); |
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38 | |
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39 | /* Half-precision floating point for __fp16. */ |
| 40 | FLOAT_MODE (HF, 2, 0); |
| 41 | ADJUST_FLOAT_FORMAT (HF, &ieee_half_format); |
| 42 | |
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43 | /* Vector modes. */ |
| 44 | VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */ |
| 45 | VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI. */ |
| 46 | VECTOR_MODES (FLOAT, 8); /* V2SF. */ |
| 47 | VECTOR_MODES (FLOAT, 16); /* V4SF V2DF. */ |
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48 | VECTOR_MODE (FLOAT, DF, 1); /* V1DF. */ |
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49 | |
| 50 | /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */ |
| 51 | INT_MODE (OI, 32); |
| 52 | |
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53 | /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers |
| 54 | (2 d-regs = 1 q-reg = TImode). */ |
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55 | INT_MODE (CI, 48); |
| 56 | INT_MODE (XI, 64); |
| 57 | |
| 58 | /* Vector modes for register lists. */ |
| 59 | VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI. */ |
| 60 | VECTOR_MODES (FLOAT, 32); /* V8SF V4DF. */ |
| 61 | |
| 62 | VECTOR_MODES (INT, 48); /* V32QI V16HI V8SI V4DI. */ |
| 63 | VECTOR_MODES (FLOAT, 48); /* V8SF V4DF. */ |
| 64 | |
| 65 | VECTOR_MODES (INT, 64); /* V32QI V16HI V8SI V4DI. */ |
| 66 | VECTOR_MODES (FLOAT, 64); /* V8SF V4DF. */ |
| 67 | |
| 68 | /* Quad float: 128-bit floating mode for long doubles. */ |
| 69 | FLOAT_MODE (TF, 16, ieee_quad_format); |
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