[thirdparty/gcc.git] / gcc / config / aarch64 / aarch64-modes.def

/* Machine description for AArch64 architecture.
   Copyright (C) 2009-2019 Free Software Foundation, Inc.
   Contributed by ARM Ltd.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GCC is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

CC_MODE (CCFP);
CC_MODE (CCFPE);
CC_MODE (CC_SWP);
CC_MODE (CC_NZ);    /* Only N and Z bits of condition flags are valid.  */
CC_MODE (CC_Z);     /* Only Z bit of condition flags is valid.  */
CC_MODE (CC_C);     /* Only C bit of condition flags is valid.  */
CC_MODE (CC_V);     /* Only V bit of condition flags is valid.  */

/* Half-precision floating point for __fp16.  */
FLOAT_MODE (HF, 2, 0);
ADJUST_FLOAT_FORMAT (HF, &ieee_half_format);

/* Vector modes.  */

VECTOR_BOOL_MODE (VNx16BI, 16, 2);
VECTOR_BOOL_MODE (VNx8BI, 8, 2);
VECTOR_BOOL_MODE (VNx4BI, 4, 2);
VECTOR_BOOL_MODE (VNx2BI, 2, 2);

ADJUST_NUNITS (VNx16BI, aarch64_sve_vg * 8);
ADJUST_NUNITS (VNx8BI, aarch64_sve_vg * 4);
ADJUST_NUNITS (VNx4BI, aarch64_sve_vg * 2);
ADJUST_NUNITS (VNx2BI, aarch64_sve_vg);

ADJUST_ALIGNMENT (VNx16BI, 2);
ADJUST_ALIGNMENT (VNx8BI, 2);
ADJUST_ALIGNMENT (VNx4BI, 2);
ADJUST_ALIGNMENT (VNx2BI, 2);

VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI.  */
VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI.  */
VECTOR_MODES (FLOAT, 8);      /*                 V2SF.  */
VECTOR_MODES (FLOAT, 16);     /*            V4SF V2DF.  */
VECTOR_MODE (FLOAT, DF, 1);   /*                 V1DF.  */
VECTOR_MODE (FLOAT, HF, 2);   /*                 V2HF.  */

/* Oct Int: 256-bit integer mode needed for 32-byte vector arguments.  */
INT_MODE (OI, 32);

/* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
   (2 d-regs = 1 q-reg = TImode).  */
INT_MODE (CI, 48);
INT_MODE (XI, 64);

/* Define SVE modes for NVECS vectors.  VB, VH, VS and VD are the prefixes
   for 8-bit, 16-bit, 32-bit and 64-bit elements respectively.  It isn't
   strictly necessary to set the alignment here, since the default would
   be clamped to BIGGEST_ALIGNMENT anyhow, but it seems clearer.  */
#define SVE_MODES(NVECS, VB, VH, VS, VD) \
  VECTOR_MODES_WITH_PREFIX (VNx, INT, 16 * NVECS); \
  VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 16 * NVECS); \
  \
  ADJUST_NUNITS (VB##QI, aarch64_sve_vg * NVECS * 8); \
  ADJUST_NUNITS (VH##HI, aarch64_sve_vg * NVECS * 4); \
  ADJUST_NUNITS (VS##SI, aarch64_sve_vg * NVECS * 2); \
  ADJUST_NUNITS (VD##DI, aarch64_sve_vg * NVECS); \
  ADJUST_NUNITS (VH##HF, aarch64_sve_vg * NVECS * 4); \
  ADJUST_NUNITS (VS##SF, aarch64_sve_vg * NVECS * 2); \
  ADJUST_NUNITS (VD##DF, aarch64_sve_vg * NVECS); \
  \
  ADJUST_ALIGNMENT (VB##QI, 16); \
  ADJUST_ALIGNMENT (VH##HI, 16); \
  ADJUST_ALIGNMENT (VS##SI, 16); \
  ADJUST_ALIGNMENT (VD##DI, 16); \
  ADJUST_ALIGNMENT (VH##HF, 16); \
  ADJUST_ALIGNMENT (VS##SF, 16); \
  ADJUST_ALIGNMENT (VD##DF, 16);

/* Give SVE vectors the names normally used for 256-bit vectors.
   The actual number depends on command-line flags.  */
SVE_MODES (1, VNx16, VNx8, VNx4, VNx2)
SVE_MODES (2, VNx32, VNx16, VNx8, VNx4)
SVE_MODES (3, VNx48, VNx24, VNx12, VNx6)
SVE_MODES (4, VNx64, VNx32, VNx16, VNx8)

/* Quad float: 128-bit floating mode for long doubles.  */
FLOAT_MODE (TF, 16, ieee_quad_format);

/* A 4-tuple of SVE vectors with the maximum -msve-vector-bits= setting.
   Note that this is a limit only on the compile-time sizes of modes;
   it is not a limit on the runtime sizes, since VL-agnostic code
   must work with arbitary vector lengths.  */
#define MAX_BITSIZE_MODE_ANY_MODE (2048 * 4)

/* Coefficient 1 is multiplied by the number of 128-bit chunks in an
   SVE vector (referred to as "VQ") minus one.  */
#define NUM_POLY_INT_COEFFS 2
Commit	Line	Data
df401d54	1	/* Machine description for AArch64 architecture.
fbd26352	2	Copyright (C) 2009-2019 Free Software Foundation, Inc.
df401d54	3	Contributed by ARM Ltd.
	4
	5	This file is part of GCC.
	6
	7	GCC is free software; you can redistribute it and/or modify it
	8	under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3, or (at your option)
	10	any later version.
	11
	12	GCC is distributed in the hope that it will be useful, but
	13	WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GCC; see the file COPYING3. If not see
	19	<http://www.gnu.org/licenses/>. */
	20
	21	CC_MODE (CCFP);
	22	CC_MODE (CCFPE);
	23	CC_MODE (CC_SWP);
df401d54	24	CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */
46b590a1	25	CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */
25653d4b	26	CC_MODE (CC_C); /* Only C bit of condition flags is valid. */
c6ab95ff	27	CC_MODE (CC_V); /* Only V bit of condition flags is valid. */
df401d54	28
6f520654	29	/* Half-precision floating point for __fp16. */
	30	FLOAT_MODE (HF, 2, 0);
	31	ADJUST_FLOAT_FORMAT (HF, &ieee_half_format);
	32
df401d54	33	/* Vector modes. */
8fa7f434	34
	35	VECTOR_BOOL_MODE (VNx16BI, 16, 2);
	36	VECTOR_BOOL_MODE (VNx8BI, 8, 2);
	37	VECTOR_BOOL_MODE (VNx4BI, 4, 2);
	38	VECTOR_BOOL_MODE (VNx2BI, 2, 2);
	39
	40	ADJUST_NUNITS (VNx16BI, aarch64_sve_vg * 8);
	41	ADJUST_NUNITS (VNx8BI, aarch64_sve_vg * 4);
	42	ADJUST_NUNITS (VNx4BI, aarch64_sve_vg * 2);
	43	ADJUST_NUNITS (VNx2BI, aarch64_sve_vg);
	44
	45	ADJUST_ALIGNMENT (VNx16BI, 2);
	46	ADJUST_ALIGNMENT (VNx8BI, 2);
	47	ADJUST_ALIGNMENT (VNx4BI, 2);
	48	ADJUST_ALIGNMENT (VNx2BI, 2);
	49
df401d54	50	VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */
	51	VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI. */
	52	VECTOR_MODES (FLOAT, 8); /* V2SF. */
	53	VECTOR_MODES (FLOAT, 16); /* V4SF V2DF. */
d70050b8	54	VECTOR_MODE (FLOAT, DF, 1); /* V1DF. */
24f7a05b	55	VECTOR_MODE (FLOAT, HF, 2); /* V2HF. */
df401d54	56
	57	/* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */
	58	INT_MODE (OI, 32);
	59
40fd1973	60	/* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
40fd1973	61	(2 d-regs = 1 q-reg = TImode). */
df401d54	62	INT_MODE (CI, 48);
	63	INT_MODE (XI, 64);
	64
8fa7f434	65	/* Define SVE modes for NVECS vectors. VB, VH, VS and VD are the prefixes
	66	for 8-bit, 16-bit, 32-bit and 64-bit elements respectively. It isn't
	67	strictly necessary to set the alignment here, since the default would
	68	be clamped to BIGGEST_ALIGNMENT anyhow, but it seems clearer. */
	69	#define SVE_MODES(NVECS, VB, VH, VS, VD) \
	70	VECTOR_MODES_WITH_PREFIX (VNx, INT, 16 * NVECS); \
	71	VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 16 * NVECS); \
	72	\
	73	ADJUST_NUNITS (VB##QI, aarch64_sve_vg * NVECS * 8); \
	74	ADJUST_NUNITS (VH##HI, aarch64_sve_vg * NVECS * 4); \
	75	ADJUST_NUNITS (VS##SI, aarch64_sve_vg * NVECS * 2); \
	76	ADJUST_NUNITS (VD##DI, aarch64_sve_vg * NVECS); \
	77	ADJUST_NUNITS (VH##HF, aarch64_sve_vg * NVECS * 4); \
	78	ADJUST_NUNITS (VS##SF, aarch64_sve_vg * NVECS * 2); \
	79	ADJUST_NUNITS (VD##DF, aarch64_sve_vg * NVECS); \
	80	\
	81	ADJUST_ALIGNMENT (VB##QI, 16); \
	82	ADJUST_ALIGNMENT (VH##HI, 16); \
	83	ADJUST_ALIGNMENT (VS##SI, 16); \
	84	ADJUST_ALIGNMENT (VD##DI, 16); \
	85	ADJUST_ALIGNMENT (VH##HF, 16); \
	86	ADJUST_ALIGNMENT (VS##SF, 16); \
	87	ADJUST_ALIGNMENT (VD##DF, 16);
	88
	89	/* Give SVE vectors the names normally used for 256-bit vectors.
	90	The actual number depends on command-line flags. */
	91	SVE_MODES (1, VNx16, VNx8, VNx4, VNx2)
0ac5a51b	92	SVE_MODES (2, VNx32, VNx16, VNx8, VNx4)
	93	SVE_MODES (3, VNx48, VNx24, VNx12, VNx6)
	94	SVE_MODES (4, VNx64, VNx32, VNx16, VNx8)
8fa7f434	95
df401d54	96	/* Quad float: 128-bit floating mode for long doubles. */
df401d54	97	FLOAT_MODE (TF, 16, ieee_quad_format);
cb4d071f	98
8fa7f434	99	/* A 4-tuple of SVE vectors with the maximum -msve-vector-bits= setting.
	100	Note that this is a limit only on the compile-time sizes of modes;
	101	it is not a limit on the runtime sizes, since VL-agnostic code
	102	must work with arbitary vector lengths. */
	103	#define MAX_BITSIZE_MODE_ANY_MODE (2048 * 4)
	104
cb4d071f	105	/* Coefficient 1 is multiplied by the number of 128-bit chunks in an
	106	SVE vector (referred to as "VQ") minus one. */
	107	#define NUM_POLY_INT_COEFFS 2