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43e9d192 | 1 | /* Machine description for AArch64 architecture. |
7adcbafe | 2 | Copyright (C) 2009-2022 Free Software Foundation, Inc. |
43e9d192 IB |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but | |
13 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | #ifndef GCC_AARCH64_H | |
23 | #define GCC_AARCH64_H | |
24 | ||
2a269bda RS |
25 | /* Make these flags read-only so that all uses go via |
26 | aarch64_set_asm_isa_flags. */ | |
27 | #ifndef GENERATOR_FILE | |
28 | #undef aarch64_asm_isa_flags | |
29 | #define aarch64_asm_isa_flags \ | |
30 | ((aarch64_feature_flags) global_options.x_aarch64_asm_isa_flags) | |
31 | #undef aarch64_isa_flags | |
32 | #define aarch64_isa_flags \ | |
33 | ((aarch64_feature_flags) global_options.x_aarch64_isa_flags) | |
34 | #endif | |
35 | ||
43e9d192 | 36 | /* Target CPU builtins. */ |
e4ea20c8 KT |
37 | #define TARGET_CPU_CPP_BUILTINS() \ |
38 | aarch64_cpu_cpp_builtins (pfile) | |
43e9d192 IB |
39 | |
40 | \f | |
41 | ||
e4ea20c8 KT |
42 | #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () |
43 | ||
43e9d192 IB |
44 | /* Target machine storage layout. */ |
45 | ||
46 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
47 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
48 | && GET_MODE_SIZE (MODE) < 4) \ | |
49 | { \ | |
50 | if (MODE == QImode || MODE == HImode) \ | |
51 | { \ | |
52 | MODE = SImode; \ | |
53 | } \ | |
54 | } | |
55 | ||
56 | /* Bits are always numbered from the LSBit. */ | |
57 | #define BITS_BIG_ENDIAN 0 | |
58 | ||
59 | /* Big/little-endian flavour. */ | |
60 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) | |
61 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
62 | ||
63 | /* AdvSIMD is supported in the default configuration, unless disabled by | |
683e3333 | 64 | -mgeneral-regs-only or by the +nosimd extension. */ |
2a269bda RS |
65 | #define TARGET_SIMD (AARCH64_ISA_SIMD) |
66 | #define TARGET_FLOAT (AARCH64_ISA_FP) | |
43e9d192 IB |
67 | |
68 | #define UNITS_PER_WORD 8 | |
69 | ||
70 | #define UNITS_PER_VREG 16 | |
71 | ||
72 | #define PARM_BOUNDARY 64 | |
73 | ||
74 | #define STACK_BOUNDARY 128 | |
75 | ||
76 | #define FUNCTION_BOUNDARY 32 | |
77 | ||
78 | #define EMPTY_FIELD_BOUNDARY 32 | |
79 | ||
80 | #define BIGGEST_ALIGNMENT 128 | |
81 | ||
82 | #define SHORT_TYPE_SIZE 16 | |
83 | ||
84 | #define INT_TYPE_SIZE 32 | |
85 | ||
17a819cb YZ |
86 | #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) |
87 | ||
88 | #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) | |
43e9d192 IB |
89 | |
90 | #define LONG_LONG_TYPE_SIZE 64 | |
91 | ||
92 | #define FLOAT_TYPE_SIZE 32 | |
93 | ||
94 | #define DOUBLE_TYPE_SIZE 64 | |
95 | ||
96 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
97 | ||
cd1bef27 JL |
98 | /* This value is the amount of bytes a caller is allowed to drop the stack |
99 | before probing has to be done for stack clash protection. */ | |
100 | #define STACK_CLASH_CALLER_GUARD 1024 | |
101 | ||
8c6e3b23 TC |
102 | /* This value represents the minimum amount of bytes we expect the function's |
103 | outgoing arguments to be when stack-clash is enabled. */ | |
104 | #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8 | |
105 | ||
cd1bef27 JL |
106 | /* This value controls how many pages we manually unroll the loop for when |
107 | generating stack clash probes. */ | |
108 | #define STACK_CLASH_MAX_UNROLL_PAGES 4 | |
109 | ||
43e9d192 IB |
110 | /* The architecture reserves all bits of the address for hardware use, |
111 | so the vbit must go into the delta field of pointers to member | |
112 | functions. This is the same config as that in the AArch32 | |
113 | port. */ | |
114 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
115 | ||
cd4b6852 KT |
116 | |
117 | /* Emit calls to libgcc helpers for atomic operations for runtime detection | |
118 | of LSE instructions. */ | |
119 | #define TARGET_OUTLINE_ATOMICS (aarch64_flag_outline_atomics) | |
120 | ||
98503487 RR |
121 | /* Align definitions of arrays, unions and structures so that |
122 | initializations and copies can be made more efficient. This is not | |
123 | ABI-changing, so it only affects places where we can see the | |
124 | definition. Increasing the alignment tends to introduce padding, | |
125 | so don't do this when optimizing for size/conserving stack space. */ | |
126 | #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ | |
127 | (((COND) && ((ALIGN) < BITS_PER_WORD) \ | |
128 | && (TREE_CODE (EXP) == ARRAY_TYPE \ | |
129 | || TREE_CODE (EXP) == UNION_TYPE \ | |
130 | || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
131 | ||
132 | /* Align global data. */ | |
133 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
134 | AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN) | |
135 | ||
136 | /* Similarly, make sure that objects on the stack are sensibly aligned. */ | |
137 | #define LOCAL_ALIGNMENT(EXP, ALIGN) \ | |
138 | AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN) | |
43e9d192 IB |
139 | |
140 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
141 | ||
e10dbae3 WD |
142 | /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY). */ |
143 | #define MALLOC_ABI_ALIGNMENT 128 | |
144 | ||
43e9d192 IB |
145 | /* Defined by the ABI */ |
146 | #define WCHAR_TYPE "unsigned int" | |
147 | #define WCHAR_TYPE_SIZE 32 | |
148 | ||
149 | /* Using long long breaks -ansi and -std=c90, so these will need to be | |
150 | made conditional for an LLP64 ABI. */ | |
151 | ||
152 | #define SIZE_TYPE "long unsigned int" | |
153 | ||
154 | #define PTRDIFF_TYPE "long int" | |
155 | ||
156 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
157 | ||
11a113d5 RS |
158 | #ifndef USED_FOR_TARGET |
159 | ||
160 | /* Define an enum of all features (architectures and extensions). */ | |
161 | enum class aarch64_feature : unsigned char { | |
162 | #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) IDENT, | |
163 | #define AARCH64_ARCH(A, B, IDENT, D, E) IDENT, | |
164 | #include "aarch64-option-extensions.def" | |
165 | #include "aarch64-arches.def" | |
166 | }; | |
167 | ||
168 | /* Define unique flags for each of the above. */ | |
169 | #define HANDLE(IDENT) \ | |
170 | constexpr auto AARCH64_FL_##IDENT \ | |
171 | = aarch64_feature_flags (1) << int (aarch64_feature::IDENT); | |
172 | #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) HANDLE (IDENT) | |
173 | #define AARCH64_ARCH(A, B, IDENT, D, E) HANDLE (IDENT) | |
174 | #include "aarch64-option-extensions.def" | |
175 | #include "aarch64-arches.def" | |
176 | #undef HANDLE | |
177 | ||
178 | #endif | |
43e9d192 IB |
179 | |
180 | /* Macros to test ISA flags. */ | |
361fb3ee | 181 | |
5922847b | 182 | #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) |
43e9d192 IB |
183 | #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) |
184 | #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) | |
185 | #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) | |
045c2d32 | 186 | #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) |
43f84f6c | 187 | #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) |
78aaafc3 | 188 | #define AARCH64_ISA_V8_2A (aarch64_isa_flags & AARCH64_FL_V8_2A) |
c61465bd | 189 | #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) |
43cacb12 | 190 | #define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE) |
0617e23c | 191 | #define AARCH64_ISA_SVE2 (aarch64_isa_flags & AARCH64_FL_SVE2) |
0a09a948 RS |
192 | #define AARCH64_ISA_SVE2_AES (aarch64_isa_flags & AARCH64_FL_SVE2_AES) |
193 | #define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM) | |
194 | #define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3) | |
195 | #define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4) | |
78aaafc3 | 196 | #define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A) |
1ddc47c0 | 197 | #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) |
27086ea3 MC |
198 | #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) |
199 | #define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2) | |
78aaafc3 | 200 | #define AARCH64_ISA_V8_4A (aarch64_isa_flags & AARCH64_FL_V8_4A) |
27086ea3 MC |
201 | #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) |
202 | #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) | |
203 | #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) | |
0f244d84 | 204 | #define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_V8_4A) |
c5dc215d | 205 | #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) |
78aaafc3 | 206 | #define AARCH64_ISA_V8_5A (aarch64_isa_flags & AARCH64_FL_V8_5A) |
89626179 | 207 | #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME) |
ef01e6bb | 208 | #define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG) |
78aaafc3 | 209 | #define AARCH64_ISA_V8_6A (aarch64_isa_flags & AARCH64_FL_V8_6A) |
a93e1d5c | 210 | #define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM) |
36696774 | 211 | #define AARCH64_ISA_F32MM (aarch64_isa_flags & AARCH64_FL_F32MM) |
336e1b95 | 212 | #define AARCH64_ISA_F64MM (aarch64_isa_flags & AARCH64_FL_F64MM) |
a93e1d5c | 213 | #define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16) |
be178ecd | 214 | #define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB) |
78aaafc3 | 215 | #define AARCH64_ISA_V8R (aarch64_isa_flags & AARCH64_FL_V8R) |
ef33047a | 216 | #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) |
78aaafc3 RS |
217 | #define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A) |
218 | #define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A) | |
219 | #define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A) | |
220 | #define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A) | |
0caf592d | 221 | #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) |
fdcddba8 | 222 | #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) |
43e9d192 | 223 | |
683e3333 KT |
224 | /* Crypto is an optional extension to AdvSIMD. */ |
225 | #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) | |
43e9d192 | 226 | |
27086ea3 MC |
227 | /* SHA2 is an optional extension to AdvSIMD. */ |
228 | #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO) | |
229 | ||
230 | /* SHA3 is an optional extension to AdvSIMD. */ | |
231 | #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3) | |
232 | ||
233 | /* AES is an optional extension to AdvSIMD. */ | |
234 | #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO) | |
235 | ||
236 | /* SM is an optional extension to AdvSIMD. */ | |
237 | #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4) | |
238 | ||
239 | /* FP16FML is an optional extension to AdvSIMD. */ | |
240 | #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST) | |
241 | ||
5d357f26 KT |
242 | /* CRC instructions that can be enabled through +crc arch extension. */ |
243 | #define TARGET_CRC32 (AARCH64_ISA_CRC) | |
244 | ||
045c2d32 MW |
245 | /* Atomic instructions that can be enabled through the +lse extension. */ |
246 | #define TARGET_LSE (AARCH64_ISA_LSE) | |
247 | ||
c61465bd MW |
248 | /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ |
249 | #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) | |
250 | #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) | |
251 | ||
1ddc47c0 TC |
252 | /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ |
253 | #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD) | |
254 | ||
43cacb12 | 255 | /* SVE instructions, enabled through +sve. */ |
2a269bda | 256 | #define TARGET_SVE (AARCH64_ISA_SVE) |
43cacb12 | 257 | |
0617e23c | 258 | /* SVE2 instructions, enabled through +sve2. */ |
154ae7d4 | 259 | #define TARGET_SVE2 (TARGET_SVE && AARCH64_ISA_SVE2) |
0617e23c | 260 | |
0a09a948 | 261 | /* SVE2 AES instructions, enabled through +sve2-aes. */ |
154ae7d4 | 262 | #define TARGET_SVE2_AES (TARGET_SVE2 && AARCH64_ISA_SVE2_AES) |
0a09a948 RS |
263 | |
264 | /* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */ | |
154ae7d4 | 265 | #define TARGET_SVE2_BITPERM (TARGET_SVE2 && AARCH64_ISA_SVE2_BITPERM) |
0a09a948 RS |
266 | |
267 | /* SVE2 SHA3 instructions, enabled through +sve2-sha3. */ | |
154ae7d4 | 268 | #define TARGET_SVE2_SHA3 (TARGET_SVE2 && AARCH64_ISA_SVE2_SHA3) |
0a09a948 RS |
269 | |
270 | /* SVE2 SM4 instructions, enabled through +sve2-sm4. */ | |
154ae7d4 | 271 | #define TARGET_SVE2_SM4 (TARGET_SVE2 && AARCH64_ISA_SVE2_SM4) |
0a09a948 | 272 | |
d766c52b | 273 | /* ARMv8.3-A features. */ |
2a4788ac | 274 | #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3A) |
d766c52b | 275 | |
e1d5d19e | 276 | /* Javascript conversion instruction from Armv8.3-a. */ |
2a4788ac | 277 | #define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3A) |
e1d5d19e | 278 | |
9d63f43b TC |
279 | /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ |
280 | #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) | |
281 | ||
10bd1d96 | 282 | /* Floating-point rounding instructions from Armv8.5-a. */ |
2a4788ac | 283 | #define TARGET_FRINT (AARCH64_ISA_V8_5A && TARGET_FLOAT) |
10bd1d96 | 284 | |
89626179 SD |
285 | /* TME instructions are enabled. */ |
286 | #define TARGET_TME (AARCH64_ISA_TME) | |
287 | ||
c5dc215d KT |
288 | /* Random number instructions from Armv8.5-a. */ |
289 | #define TARGET_RNG (AARCH64_ISA_RNG) | |
290 | ||
ef01e6bb | 291 | /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */ |
2a4788ac | 292 | #define TARGET_MEMTAG (AARCH64_ISA_V8_5A && AARCH64_ISA_MEMTAG) |
ef01e6bb | 293 | |
a93e1d5c DZ |
294 | /* I8MM instructions are enabled through +i8mm. */ |
295 | #define TARGET_I8MM (AARCH64_ISA_I8MM) | |
36696774 RS |
296 | #define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM) |
297 | ||
298 | /* F32MM instructions are enabled through +f32mm. */ | |
299 | #define TARGET_F32MM (AARCH64_ISA_F32MM) | |
300 | #define TARGET_SVE_F32MM (TARGET_SVE && AARCH64_ISA_F32MM) | |
a93e1d5c | 301 | |
336e1b95 MM |
302 | /* F64MM instructions are enabled through +f64mm. */ |
303 | #define TARGET_F64MM (AARCH64_ISA_F64MM) | |
36696774 | 304 | #define TARGET_SVE_F64MM (TARGET_SVE && AARCH64_ISA_F64MM) |
336e1b95 | 305 | |
a93e1d5c DZ |
306 | /* BF16 instructions are enabled through +bf16. */ |
307 | #define TARGET_BF16_FP (AARCH64_ISA_BF16) | |
308 | #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD) | |
896dff99 | 309 | #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16) |
a93e1d5c | 310 | |
ef33047a PW |
311 | /* PAUTH instructions are enabled through +pauth. */ |
312 | #define TARGET_PAUTH (AARCH64_ISA_PAUTH) | |
313 | ||
0caf592d KT |
314 | /* MOPS instructions are enabled through +mops. */ |
315 | #define TARGET_MOPS (AARCH64_ISA_MOPS) | |
316 | ||
fdcddba8 PW |
317 | /* LS64 instructions are enabled through +ls64. */ |
318 | #define TARGET_LS64 (AARCH64_ISA_LS64) | |
319 | ||
b32c1043 KT |
320 | /* Make sure this is always defined so we don't have to check for ifdefs |
321 | but rather use normal ifs. */ | |
322 | #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT | |
323 | #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 | |
324 | #else | |
325 | #undef TARGET_FIX_ERR_A53_835769_DEFAULT | |
326 | #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 | |
327 | #endif | |
328 | ||
be178ecd MM |
329 | /* SB instruction is enabled through +sb. */ |
330 | #define TARGET_SB (AARCH64_ISA_SB) | |
331 | ||
b32c1043 KT |
332 | /* Apply the workaround for Cortex-A53 erratum 835769. */ |
333 | #define TARGET_FIX_ERR_A53_835769 \ | |
334 | ((aarch64_fix_a53_err835769 == 2) \ | |
335 | ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) | |
336 | ||
48bb1a55 CL |
337 | /* Make sure this is always defined so we don't have to check for ifdefs |
338 | but rather use normal ifs. */ | |
339 | #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT | |
340 | #define TARGET_FIX_ERR_A53_843419_DEFAULT 0 | |
341 | #else | |
342 | #undef TARGET_FIX_ERR_A53_843419_DEFAULT | |
343 | #define TARGET_FIX_ERR_A53_843419_DEFAULT 1 | |
344 | #endif | |
345 | ||
346 | /* Apply the workaround for Cortex-A53 erratum 843419. */ | |
347 | #define TARGET_FIX_ERR_A53_843419 \ | |
348 | ((aarch64_fix_a53_err843419 == 2) \ | |
349 | ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) | |
350 | ||
74bb9de4 | 351 | /* ARMv8.1-A Adv.SIMD support. */ |
a3735e01 MW |
352 | #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) |
353 | ||
43e9d192 IB |
354 | /* Standard register usage. */ |
355 | ||
356 | /* 31 64-bit general purpose registers R0-R30: | |
357 | R30 LR (link register) | |
358 | R29 FP (frame pointer) | |
359 | R19-R28 Callee-saved registers | |
360 | R18 The platform register; use as temporary register. | |
361 | R17 IP1 The second intra-procedure-call temporary register | |
362 | (can be used by call veneers and PLT code); otherwise use | |
363 | as a temporary register | |
364 | R16 IP0 The first intra-procedure-call temporary register (can | |
365 | be used by call veneers and PLT code); otherwise use as a | |
366 | temporary register | |
367 | R9-R15 Temporary registers | |
368 | R8 Structure value parameter / temporary register | |
369 | R0-R7 Parameter/result registers | |
370 | ||
371 | SP stack pointer, encoded as X/R31 where permitted. | |
372 | ZR zero register, encoded as X/R31 elsewhere | |
373 | ||
374 | 32 x 128-bit floating-point/vector registers | |
375 | V16-V31 Caller-saved (temporary) registers | |
376 | V8-V15 Callee-saved registers | |
377 | V0-V7 Parameter/result registers | |
378 | ||
379 | The vector register V0 holds scalar B0, H0, S0 and D0 in its least | |
43cacb12 RS |
380 | significant bits. Unlike AArch32 S1 is not packed into D0, etc. |
381 | ||
382 | P0-P7 Predicate low registers: valid in all predicate contexts | |
383 | P8-P15 Predicate high registers: used as scratch space | |
384 | ||
183bfdaf RS |
385 | FFR First Fault Register, a fixed-use SVE predicate register |
386 | FFRT FFR token: a fake register used for modelling dependencies | |
387 | ||
43cacb12 RS |
388 | VG Pseudo "vector granules" register |
389 | ||
390 | VG is the number of 64-bit elements in an SVE vector. We define | |
391 | it as a hard register so that we can easily map it to the DWARF VG | |
392 | register. GCC internally uses the poly_int variable aarch64_sve_vg | |
393 | instead. */ | |
43e9d192 | 394 | |
43e9d192 IB |
395 | #define FIXED_REGISTERS \ |
396 | { \ | |
397 | 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ | |
398 | 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ | |
399 | 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
400 | 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ | |
401 | 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ | |
402 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
403 | 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ | |
404 | 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ | |
43cacb12 RS |
405 | 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ |
406 | 0, 0, 0, 0, 0, 0, 0, 0, /* P0 - P7 */ \ | |
407 | 0, 0, 0, 0, 0, 0, 0, 0, /* P8 - P15 */ \ | |
183bfdaf | 408 | 1, 1 /* FFR and FFRT */ \ |
43e9d192 IB |
409 | } |
410 | ||
643ef957 SP |
411 | /* X30 is marked as caller-saved which is in line with regular function call |
412 | behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does | |
413 | that for regular function calls and avoids it for sibcalls. X30 is | |
414 | considered live for sibcalls; EPILOGUE_USES helps achieve that by returning | |
415 | true but not until function epilogues have been generated. This ensures | |
416 | that X30 is available for use in leaf functions if needed. */ | |
417 | ||
43e9d192 IB |
418 | #define CALL_USED_REGISTERS \ |
419 | { \ | |
420 | 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ | |
421 | 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ | |
422 | 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
1c923b60 | 423 | 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ |
43e9d192 IB |
424 | 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ |
425 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
426 | 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ | |
427 | 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ | |
43cacb12 RS |
428 | 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ |
429 | 1, 1, 1, 1, 1, 1, 1, 1, /* P0 - P7 */ \ | |
430 | 1, 1, 1, 1, 1, 1, 1, 1, /* P8 - P15 */ \ | |
183bfdaf | 431 | 1, 1 /* FFR and FFRT */ \ |
43e9d192 IB |
432 | } |
433 | ||
434 | #define REGISTER_NAMES \ | |
435 | { \ | |
436 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ | |
437 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ | |
438 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ | |
439 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ | |
440 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ | |
441 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ | |
442 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ | |
443 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ | |
43cacb12 RS |
444 | "sfp", "ap", "cc", "vg", \ |
445 | "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", \ | |
446 | "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", \ | |
183bfdaf | 447 | "ffr", "ffrt" \ |
43e9d192 IB |
448 | } |
449 | ||
450 | /* Generate the register aliases for core register N */ | |
451 | #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ | |
452 | {"w" # N, R0_REGNUM + (N)} | |
453 | ||
454 | #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ | |
455 | {"d" # N, V0_REGNUM + (N)}, \ | |
456 | {"s" # N, V0_REGNUM + (N)}, \ | |
457 | {"h" # N, V0_REGNUM + (N)}, \ | |
43cacb12 RS |
458 | {"b" # N, V0_REGNUM + (N)}, \ |
459 | {"z" # N, V0_REGNUM + (N)} | |
43e9d192 IB |
460 | |
461 | /* Provide aliases for all of the ISA defined register name forms. | |
462 | These aliases are convenient for use in the clobber lists of inline | |
463 | asm statements. */ | |
464 | ||
465 | #define ADDITIONAL_REGISTER_NAMES \ | |
466 | { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ | |
467 | R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ | |
468 | R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ | |
469 | R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ | |
470 | R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ | |
471 | R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ | |
472 | R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ | |
9259db42 | 473 | R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ |
43e9d192 IB |
474 | V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ |
475 | V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ | |
476 | V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ | |
477 | V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ | |
478 | V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ | |
479 | V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ | |
480 | V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ | |
481 | V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ | |
482 | } | |
483 | ||
a0d0b980 | 484 | #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO)) |
43e9d192 IB |
485 | |
486 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
204d2c03 WD |
487 | the stack pointer does not matter. This is only true if the function |
488 | uses alloca. */ | |
489 | #define EXIT_IGNORE_STACK (cfun->calls_alloca) | |
43e9d192 IB |
490 | |
491 | #define STATIC_CHAIN_REGNUM R18_REGNUM | |
492 | #define HARD_FRAME_POINTER_REGNUM R29_REGNUM | |
493 | #define FRAME_POINTER_REGNUM SFP_REGNUM | |
494 | #define STACK_POINTER_REGNUM SP_REGNUM | |
495 | #define ARG_POINTER_REGNUM AP_REGNUM | |
183bfdaf | 496 | #define FIRST_PSEUDO_REGISTER (FFRT_REGNUM + 1) |
43e9d192 | 497 | |
c600df9a | 498 | /* The number of argument registers available for each class. */ |
43e9d192 IB |
499 | #define NUM_ARG_REGS 8 |
500 | #define NUM_FP_ARG_REGS 8 | |
c600df9a | 501 | #define NUM_PR_ARG_REGS 4 |
43e9d192 IB |
502 | |
503 | /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most | |
504 | four members. */ | |
505 | #define HA_MAX_NUM_FLDS 4 | |
506 | ||
507 | /* External dwarf register number scheme. These number are used to | |
508 | identify registers in dwarf debug information, the values are | |
509 | defined by the AArch64 ABI. The numbering scheme is independent of | |
510 | GCC's internal register numbering scheme. */ | |
511 | ||
512 | #define AARCH64_DWARF_R0 0 | |
513 | ||
514 | /* The number of R registers, note 31! not 32. */ | |
515 | #define AARCH64_DWARF_NUMBER_R 31 | |
516 | ||
517 | #define AARCH64_DWARF_SP 31 | |
43cacb12 RS |
518 | #define AARCH64_DWARF_VG 46 |
519 | #define AARCH64_DWARF_P0 48 | |
43e9d192 IB |
520 | #define AARCH64_DWARF_V0 64 |
521 | ||
522 | /* The number of V registers. */ | |
523 | #define AARCH64_DWARF_NUMBER_V 32 | |
524 | ||
525 | /* For signal frames we need to use an alternative return column. This | |
526 | value must not correspond to a hard register and must be out of the | |
527 | range of DWARF_FRAME_REGNUM(). */ | |
528 | #define DWARF_ALT_FRAME_RETURN_COLUMN \ | |
529 | (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) | |
530 | ||
531 | /* We add 1 extra frame register for use as the | |
532 | DWARF_ALT_FRAME_RETURN_COLUMN. */ | |
533 | #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) | |
534 | ||
535 | ||
ca60bd93 | 536 | #define DEBUGGER_REGNO(REGNO) aarch64_debugger_regno (REGNO) |
43e9d192 IB |
537 | /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders |
538 | can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same | |
e53b6e56 | 539 | as the default definition in dwarf2out.cc. */ |
43e9d192 | 540 | #undef DWARF_FRAME_REGNUM |
ca60bd93 | 541 | #define DWARF_FRAME_REGNUM(REGNO) DEBUGGER_REGNO (REGNO) |
43e9d192 IB |
542 | |
543 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
544 | ||
43e9d192 IB |
545 | #define DWARF2_UNWIND_INFO 1 |
546 | ||
547 | /* Use R0 through R3 to pass exception handling information. */ | |
548 | #define EH_RETURN_DATA_REGNO(N) \ | |
549 | ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) | |
550 | ||
551 | /* Select a format to encode pointers in exception handling data. */ | |
552 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
553 | aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) | |
554 | ||
361fb3ee KT |
555 | /* Output the assembly strings we want to add to a function definition. */ |
556 | #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ | |
557 | aarch64_declare_function_name (STR, NAME, DECL) | |
558 | ||
b07fc91c SN |
559 | /* Output assembly strings for alias definition. */ |
560 | #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ | |
561 | aarch64_asm_output_alias (STR, DECL, TARGET) | |
562 | ||
563 | /* Output assembly strings for undefined extern symbols. */ | |
564 | #undef ASM_OUTPUT_EXTERNAL | |
565 | #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ | |
566 | aarch64_asm_output_external (STR, DECL, NAME) | |
567 | ||
8fc16d72 ST |
568 | /* Output assembly strings after .cfi_startproc is emitted. */ |
569 | #define ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc | |
570 | ||
8144a493 WD |
571 | /* For EH returns X4 contains the stack adjustment. */ |
572 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) | |
573 | #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () | |
43e9d192 IB |
574 | |
575 | /* Don't use __builtin_setjmp until we've defined it. */ | |
576 | #undef DONT_USE_BUILTIN_SETJMP | |
577 | #define DONT_USE_BUILTIN_SETJMP 1 | |
578 | ||
0795f659 VL |
579 | #undef TARGET_COMPUTE_FRAME_LAYOUT |
580 | #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame | |
581 | ||
43e9d192 IB |
582 | /* Register in which the structure value is to be returned. */ |
583 | #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM | |
584 | ||
585 | /* Non-zero if REGNO is part of the Core register set. | |
586 | ||
587 | The rather unusual way of expressing this check is to avoid | |
588 | warnings when building the compiler when R0_REGNUM is 0 and REGNO | |
589 | is unsigned. */ | |
590 | #define GP_REGNUM_P(REGNO) \ | |
591 | (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) | |
592 | ||
96b7f495 MM |
593 | /* Registers known to be preserved over a BL instruction. This consists of the |
594 | GENERAL_REGS without x16, x17, and x30. The x30 register is changed by the | |
595 | BL instruction itself, while the x16 and x17 registers may be used by | |
596 | veneers which can be inserted by the linker. */ | |
597 | #define STUB_REGNUM_P(REGNO) \ | |
598 | (GP_REGNUM_P (REGNO) \ | |
599 | && (REGNO) != R16_REGNUM \ | |
600 | && (REGNO) != R17_REGNUM \ | |
601 | && (REGNO) != R30_REGNUM) \ | |
602 | ||
43e9d192 IB |
603 | #define FP_REGNUM_P(REGNO) \ |
604 | (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) | |
605 | ||
606 | #define FP_LO_REGNUM_P(REGNO) \ | |
607 | (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) | |
608 | ||
163b1f6a RS |
609 | #define FP_LO8_REGNUM_P(REGNO) \ |
610 | (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM)) | |
611 | ||
43cacb12 RS |
612 | #define PR_REGNUM_P(REGNO)\ |
613 | (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) | |
614 | ||
615 | #define PR_LO_REGNUM_P(REGNO)\ | |
616 | (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM)) | |
617 | ||
a0d0b980 SE |
618 | #define FP_SIMD_SAVED_REGNUM_P(REGNO) \ |
619 | (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM)) | |
43e9d192 IB |
620 | \f |
621 | /* Register and constant classes. */ | |
622 | ||
623 | enum reg_class | |
624 | { | |
625 | NO_REGS, | |
d677263e | 626 | TAILCALL_ADDR_REGS, |
96b7f495 | 627 | STUB_REGS, |
43e9d192 IB |
628 | GENERAL_REGS, |
629 | STACK_REG, | |
630 | POINTER_REGS, | |
163b1f6a | 631 | FP_LO8_REGS, |
43e9d192 IB |
632 | FP_LO_REGS, |
633 | FP_REGS, | |
f25a140b | 634 | POINTER_AND_FP_REGS, |
43cacb12 RS |
635 | PR_LO_REGS, |
636 | PR_HI_REGS, | |
637 | PR_REGS, | |
183bfdaf RS |
638 | FFR_REGS, |
639 | PR_AND_FFR_REGS, | |
43e9d192 IB |
640 | ALL_REGS, |
641 | LIM_REG_CLASSES /* Last */ | |
642 | }; | |
643 | ||
644 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
645 | ||
646 | #define REG_CLASS_NAMES \ | |
647 | { \ | |
648 | "NO_REGS", \ | |
d677263e | 649 | "TAILCALL_ADDR_REGS", \ |
96b7f495 | 650 | "STUB_REGS", \ |
43e9d192 IB |
651 | "GENERAL_REGS", \ |
652 | "STACK_REG", \ | |
653 | "POINTER_REGS", \ | |
163b1f6a | 654 | "FP_LO8_REGS", \ |
43e9d192 IB |
655 | "FP_LO_REGS", \ |
656 | "FP_REGS", \ | |
f25a140b | 657 | "POINTER_AND_FP_REGS", \ |
43cacb12 RS |
658 | "PR_LO_REGS", \ |
659 | "PR_HI_REGS", \ | |
660 | "PR_REGS", \ | |
183bfdaf RS |
661 | "FFR_REGS", \ |
662 | "PR_AND_FFR_REGS", \ | |
43e9d192 IB |
663 | "ALL_REGS" \ |
664 | } | |
665 | ||
666 | #define REG_CLASS_CONTENTS \ | |
667 | { \ | |
668 | { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
901e66e0 | 669 | { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ |
96b7f495 | 670 | { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \ |
43e9d192 IB |
671 | { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ |
672 | { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
673 | { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ | |
163b1f6a | 674 | { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ |
43e9d192 IB |
675 | { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ |
676 | { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ | |
f25a140b | 677 | { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ |
43cacb12 RS |
678 | { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \ |
679 | { 0x00000000, 0x00000000, 0x000ff000 }, /* PR_HI_REGS */ \ | |
680 | { 0x00000000, 0x00000000, 0x000ffff0 }, /* PR_REGS */ \ | |
183bfdaf RS |
681 | { 0x00000000, 0x00000000, 0x00300000 }, /* FFR_REGS */ \ |
682 | { 0x00000000, 0x00000000, 0x003ffff0 }, /* PR_AND_FFR_REGS */ \ | |
43cacb12 | 683 | { 0xffffffff, 0xffffffff, 0x000fffff } /* ALL_REGS */ \ |
43e9d192 IB |
684 | } |
685 | ||
686 | #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) | |
687 | ||
a4a182c6 | 688 | #define INDEX_REG_CLASS GENERAL_REGS |
43e9d192 IB |
689 | #define BASE_REG_CLASS POINTER_REGS |
690 | ||
6991c977 | 691 | /* Register pairs used to eliminate unneeded registers that point into |
43e9d192 IB |
692 | the stack frame. */ |
693 | #define ELIMINABLE_REGS \ | |
694 | { \ | |
695 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
696 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
697 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
698 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
699 | } | |
700 | ||
701 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
702 | (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) | |
703 | ||
704 | /* CPU/ARCH option handling. */ | |
705 | #include "config/aarch64/aarch64-opts.h" | |
706 | ||
707 | enum target_cpus | |
708 | { | |
e8fcc9fa | 709 | #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ |
192ed1dd | 710 | TARGET_CPU_##INTERNAL_IDENT, |
43e9d192 | 711 | #include "aarch64-cores.def" |
43e9d192 IB |
712 | TARGET_CPU_generic |
713 | }; | |
714 | ||
a3cd0246 | 715 | /* If there is no CPU defined at configure, use generic as default. */ |
43e9d192 | 716 | #ifndef TARGET_CPU_DEFAULT |
1be715f3 | 717 | # define TARGET_CPU_DEFAULT TARGET_CPU_generic |
43e9d192 IB |
718 | #endif |
719 | ||
75cf1494 KT |
720 | /* If inserting NOP before a mult-accumulate insn remember to adjust the |
721 | length so that conditional branching code is updated appropriately. */ | |
722 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
8baff86e KT |
723 | do \ |
724 | { \ | |
725 | if (aarch64_madd_needs_nop (insn)) \ | |
726 | length += 4; \ | |
727 | } while (0) | |
75cf1494 KT |
728 | |
729 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
730 | aarch64_final_prescan_insn (INSN); \ | |
731 | ||
43e9d192 IB |
732 | /* The processor for which instructions should be scheduled. */ |
733 | extern enum aarch64_processor aarch64_tune; | |
734 | ||
735 | /* RTL generation support. */ | |
736 | #define INIT_EXPANDERS aarch64_init_expanders () | |
737 | \f | |
738 | ||
739 | /* Stack layout; function entry, exit and calling. */ | |
740 | #define STACK_GROWS_DOWNWARD 1 | |
741 | ||
6991c977 | 742 | #define FRAME_GROWS_DOWNWARD 1 |
43e9d192 | 743 | |
43e9d192 IB |
744 | #define ACCUMULATE_OUTGOING_ARGS 1 |
745 | ||
746 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
747 | ||
748 | /* Fix for VFP */ | |
749 | #define LIBCALL_VALUE(MODE) \ | |
750 | gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) | |
751 | ||
752 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
753 | ||
6a70badb | 754 | #ifdef HAVE_POLY_INT_H |
43e9d192 IB |
755 | struct GTY (()) aarch64_frame |
756 | { | |
c600df9a | 757 | poly_int64 reg_offset[LAST_SAVED_REGNUM + 1]; |
8799637a MS |
758 | |
759 | /* The number of extra stack bytes taken up by register varargs. | |
760 | This area is allocated by the callee at the very top of the | |
761 | frame. This value is rounded up to a multiple of | |
762 | STACK_BOUNDARY. */ | |
763 | HOST_WIDE_INT saved_varargs_size; | |
764 | ||
c600df9a RS |
765 | /* The size of the callee-save registers with a slot in REG_OFFSET. */ |
766 | poly_int64 saved_regs_size; | |
71bfb77a | 767 | |
c600df9a RS |
768 | /* The size of the callee-save registers with a slot in REG_OFFSET that |
769 | are saved below the hard frame pointer. */ | |
770 | poly_int64 below_hard_fp_saved_regs_size; | |
71bfb77a WD |
771 | |
772 | /* Offset from the base of the frame (incomming SP) to the | |
773 | top of the locals area. This value is always a multiple of | |
774 | STACK_BOUNDARY. */ | |
6a70badb | 775 | poly_int64 locals_offset; |
43e9d192 | 776 | |
1c960e02 MS |
777 | /* Offset from the base of the frame (incomming SP) to the |
778 | hard_frame_pointer. This value is always a multiple of | |
779 | STACK_BOUNDARY. */ | |
6a70badb | 780 | poly_int64 hard_fp_offset; |
1c960e02 MS |
781 | |
782 | /* The size of the frame. This value is the offset from base of the | |
6a70badb RS |
783 | frame (incomming SP) to the stack_pointer. This value is always |
784 | a multiple of STACK_BOUNDARY. */ | |
785 | poly_int64 frame_size; | |
71bfb77a WD |
786 | |
787 | /* The size of the initial stack adjustment before saving callee-saves. */ | |
6a70badb | 788 | poly_int64 initial_adjust; |
71bfb77a WD |
789 | |
790 | /* The writeback value when pushing callee-save registers. | |
791 | It is zero when no push is used. */ | |
792 | HOST_WIDE_INT callee_adjust; | |
793 | ||
794 | /* The offset from SP to the callee-save registers after initial_adjust. | |
795 | It may be non-zero if no push is used (ie. callee_adjust == 0). */ | |
6a70badb | 796 | poly_int64 callee_offset; |
71bfb77a | 797 | |
c600df9a RS |
798 | /* The size of the stack adjustment before saving or after restoring |
799 | SVE registers. */ | |
800 | poly_int64 sve_callee_adjust; | |
801 | ||
71bfb77a | 802 | /* The size of the stack adjustment after saving callee-saves. */ |
6a70badb | 803 | poly_int64 final_adjust; |
1c960e02 | 804 | |
204d2c03 WD |
805 | /* Store FP,LR and setup a frame pointer. */ |
806 | bool emit_frame_chain; | |
807 | ||
59a3d73d RS |
808 | /* In each frame, we can associate up to two register saves with the |
809 | initial stack allocation. This happens in one of two ways: | |
810 | ||
811 | (1) Using an STR or STP with writeback to perform the initial | |
812 | stack allocation. When EMIT_FRAME_CHAIN, the registers will | |
813 | be those needed to create a frame chain. | |
814 | ||
815 | Indicated by CALLEE_ADJUST != 0. | |
816 | ||
817 | (2) Using a separate STP to set up the frame record, after the | |
818 | initial stack allocation but before setting up the frame pointer. | |
819 | This is used if the offset is too large to use writeback. | |
820 | ||
821 | Indicated by CALLEE_ADJUST == 0 && EMIT_FRAME_CHAIN. | |
822 | ||
823 | These fields indicate which registers we've decided to handle using | |
ce09ab17 DL |
824 | (1) or (2), or INVALID_REGNUM if none. |
825 | ||
826 | In some cases we don't always need to pop all registers in the push | |
827 | candidates, pop candidates record which registers need to be popped | |
828 | eventually. The initial value of a pop candidate is copied from its | |
829 | corresponding push candidate. | |
830 | ||
831 | Currently, different pop candidates are only used for shadow call | |
832 | stack. When "-fsanitize=shadow-call-stack" is specified, we replace | |
833 | x30 in the pop candidate with INVALID_REGNUM to ensure that x30 is | |
834 | not popped twice. */ | |
835 | unsigned wb_push_candidate1; | |
836 | unsigned wb_push_candidate2; | |
837 | unsigned wb_pop_candidate1; | |
838 | unsigned wb_pop_candidate2; | |
363ffa50 | 839 | |
c600df9a RS |
840 | /* Big-endian SVE frames need a spare predicate register in order |
841 | to save vector registers in the correct layout for unwinding. | |
842 | This is the register they should use. */ | |
843 | unsigned spare_pred_reg; | |
844 | ||
43e9d192 | 845 | bool laid_out; |
ce09ab17 DL |
846 | |
847 | /* True if shadow call stack should be enabled for the current function. */ | |
848 | bool is_scs_enabled; | |
43e9d192 IB |
849 | }; |
850 | ||
851 | typedef struct GTY (()) machine_function | |
852 | { | |
853 | struct aarch64_frame frame; | |
827ab47a KT |
854 | /* One entry for each hard register. */ |
855 | bool reg_is_wrapped_separately[LAST_SAVED_REGNUM]; | |
96b7f495 MM |
856 | /* One entry for each general purpose register. */ |
857 | rtx call_via[SP_REGNUM]; | |
c292cfe5 | 858 | bool label_is_assembled; |
43e9d192 IB |
859 | } machine_function; |
860 | #endif | |
861 | ||
17a819cb YZ |
862 | /* Which ABI to use. */ |
863 | enum aarch64_abi_type | |
864 | { | |
865 | AARCH64_ABI_LP64 = 0, | |
866 | AARCH64_ABI_ILP32 = 1 | |
867 | }; | |
868 | ||
869 | #ifndef AARCH64_ABI_DEFAULT | |
870 | #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 | |
871 | #endif | |
872 | ||
873 | #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) | |
43e9d192 | 874 | |
43e9d192 IB |
875 | enum arm_pcs |
876 | { | |
877 | ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ | |
002ffd3c | 878 | ARM_PCS_SIMD, /* For aarch64_vector_pcs functions. */ |
c600df9a RS |
879 | ARM_PCS_SVE, /* For functions that pass or return |
880 | values in SVE registers. */ | |
bb6ce448 | 881 | ARM_PCS_TLSDESC, /* For targets of tlsdesc calls. */ |
43e9d192 IB |
882 | ARM_PCS_UNKNOWN |
883 | }; | |
884 | ||
885 | ||
43e9d192 | 886 | |
43e9d192 | 887 | |
ef4bddc2 | 888 | /* We can't use machine_mode inside a generator file because it |
43e9d192 IB |
889 | hasn't been created yet; we shouldn't be using any code that |
890 | needs the real definition though, so this ought to be safe. */ | |
891 | #ifdef GENERATOR_FILE | |
892 | #define MACHMODE int | |
893 | #else | |
894 | #include "insn-modes.h" | |
febd3244 | 895 | #define MACHMODE machine_mode |
43e9d192 IB |
896 | #endif |
897 | ||
febd3244 | 898 | #ifndef USED_FOR_TARGET |
43e9d192 IB |
899 | /* AAPCS related state tracking. */ |
900 | typedef struct | |
901 | { | |
902 | enum arm_pcs pcs_variant; | |
903 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
904 | int aapcs_ncrn; /* Next Core register number. */ | |
905 | int aapcs_nextncrn; /* Next next core register number. */ | |
906 | int aapcs_nvrn; /* Next Vector register number. */ | |
907 | int aapcs_nextnvrn; /* Next Next Vector register number. */ | |
c600df9a RS |
908 | int aapcs_nprn; /* Next Predicate register number. */ |
909 | int aapcs_nextnprn; /* Next Next Predicate register number. */ | |
43e9d192 IB |
910 | rtx aapcs_reg; /* Register assigned to this argument. This |
911 | is NULL_RTX if this parameter goes on | |
912 | the stack. */ | |
913 | MACHMODE aapcs_vfp_rmode; | |
914 | int aapcs_stack_words; /* If the argument is passed on the stack, this | |
915 | is the number of words needed, after rounding | |
916 | up. Only meaningful when | |
917 | aapcs_reg == NULL_RTX. */ | |
918 | int aapcs_stack_size; /* The total size (in words, per 8 byte) of the | |
919 | stack arg area so far. */ | |
c600df9a RS |
920 | bool silent_p; /* True if we should act silently, rather than |
921 | raise an error for invalid calls. */ | |
43e9d192 | 922 | } CUMULATIVE_ARGS; |
febd3244 | 923 | #endif |
43e9d192 | 924 | |
43e9d192 | 925 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ |
76b0cbf8 | 926 | (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) |
43e9d192 IB |
927 | |
928 | #define PAD_VARARGS_DOWN 0 | |
929 | ||
930 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
931 | aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) | |
932 | ||
933 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
934 | aarch64_function_arg_regno_p(REGNO) | |
935 | \f | |
936 | ||
937 | /* ISA Features. */ | |
938 | ||
939 | /* Addressing modes, etc. */ | |
940 | #define HAVE_POST_INCREMENT 1 | |
941 | #define HAVE_PRE_INCREMENT 1 | |
942 | #define HAVE_POST_DECREMENT 1 | |
943 | #define HAVE_PRE_DECREMENT 1 | |
944 | #define HAVE_POST_MODIFY_DISP 1 | |
945 | #define HAVE_PRE_MODIFY_DISP 1 | |
946 | ||
947 | #define MAX_REGS_PER_ADDRESS 2 | |
948 | ||
949 | #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) | |
950 | ||
43e9d192 IB |
951 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
952 | aarch64_regno_ok_for_base_p (REGNO, true) | |
953 | ||
954 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
955 | aarch64_regno_ok_for_index_p (REGNO, true) | |
956 | ||
957 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
958 | aarch64_legitimate_pic_operand_p (X) | |
959 | ||
960 | #define CASE_VECTOR_MODE Pmode | |
961 | ||
962 | #define DEFAULT_SIGNED_CHAR 0 | |
963 | ||
964 | /* An integer expression for the size in bits of the largest integer machine | |
965 | mode that should actually be used. We allow pairs of registers. */ | |
966 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
967 | ||
968 | /* Maximum bytes moved by a single instruction (load/store pair). */ | |
969 | #define MOVE_MAX (UNITS_PER_WORD * 2) | |
970 | ||
971 | /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ | |
972 | #define AARCH64_CALL_RATIO 8 | |
973 | ||
e2c75eea JG |
974 | /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. |
975 | move_by_pieces will continually copy the largest safe chunks. So a | |
976 | 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient | |
76715c32 | 977 | for both size and speed of copy, so we will instead use the "cpymem" |
e2c75eea | 978 | standard name to implement the copy. This logic does not apply when |
0caf592d KT |
979 | targeting -mstrict-align or TARGET_MOPS, so keep a sensible default in |
980 | that case. */ | |
43e9d192 | 981 | #define MOVE_RATIO(speed) \ |
0caf592d | 982 | ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) |
43e9d192 | 983 | |
54bbde55 SD |
984 | /* Like MOVE_RATIO, without -mstrict-align, make decisions in "setmem" when |
985 | we would use more than 3 scalar instructions. | |
986 | Otherwise follow a sensible default: when optimizing for size, give a better | |
987 | estimate of the length of a memset call, but use the default otherwise. */ | |
43e9d192 | 988 | #define CLEAR_RATIO(speed) \ |
d3bd985e | 989 | (!STRICT_ALIGNMENT ? (TARGET_MOPS ? 0 : 4) : (speed) ? 15 : AARCH64_CALL_RATIO) |
43e9d192 | 990 | |
54bbde55 SD |
991 | /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant. Without |
992 | -mstrict-align, make decisions in "setmem". Otherwise follow a sensible | |
993 | default: when optimizing for size adjust the ratio to account for the | |
994 | overhead of loading the constant. */ | |
43e9d192 | 995 | #define SET_RATIO(speed) \ |
d3bd985e | 996 | ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2) |
43e9d192 | 997 | |
43e9d192 IB |
998 | /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is |
999 | rarely a good idea in straight-line code since it adds an extra address | |
1000 | dependency between each instruction. Better to use incrementing offsets. */ | |
1001 | #define USE_LOAD_POST_INCREMENT(MODE) 0 | |
1002 | #define USE_LOAD_POST_DECREMENT(MODE) 0 | |
1003 | #define USE_LOAD_PRE_INCREMENT(MODE) 0 | |
1004 | #define USE_LOAD_PRE_DECREMENT(MODE) 0 | |
1005 | #define USE_STORE_POST_INCREMENT(MODE) 0 | |
1006 | #define USE_STORE_POST_DECREMENT(MODE) 0 | |
1007 | #define USE_STORE_PRE_INCREMENT(MODE) 0 | |
1008 | #define USE_STORE_PRE_DECREMENT(MODE) 0 | |
1009 | ||
56c9ef5f KT |
1010 | /* WORD_REGISTER_OPERATIONS does not hold for AArch64. |
1011 | The assigned word_mode is DImode but operations narrower than SImode | |
1012 | behave as 32-bit operations if using the W-form of the registers rather | |
1013 | than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS | |
1014 | expects. */ | |
1015 | #define WORD_REGISTER_OPERATIONS 0 | |
43e9d192 IB |
1016 | |
1017 | /* Define if loading from memory in MODE, an integral mode narrower than | |
1018 | BITS_PER_WORD will either zero-extend or sign-extend. The value of this | |
1019 | macro should be the code that says which one of the two operations is | |
1020 | implicitly done, or UNKNOWN if none. */ | |
1021 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1022 | ||
1023 | /* Define this macro to be non-zero if instructions will fail to work | |
1024 | if given data not on the nominal alignment. */ | |
1025 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN | |
1026 | ||
35e58efb WD |
1027 | /* Enable wide bitfield accesses for more efficient bitfield code. */ |
1028 | #define SLOW_BYTE_ACCESS 1 | |
43e9d192 | 1029 | |
43e9d192 IB |
1030 | #define NO_FUNCTION_CSE 1 |
1031 | ||
17a819cb YZ |
1032 | /* Specify the machine mode that the hardware addresses have. |
1033 | After generation of rtl, the compiler makes no further distinction | |
1034 | between pointers and any other objects of this machine mode. */ | |
43e9d192 | 1035 | #define Pmode DImode |
17a819cb YZ |
1036 | |
1037 | /* A C expression whose value is zero if pointers that need to be extended | |
1038 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
1039 | greater then zero if they are zero-extended and less then zero if the | |
1040 | ptr_extend instruction should be used. */ | |
1041 | #define POINTERS_EXTEND_UNSIGNED 1 | |
1042 | ||
1043 | /* Mode of a function address in a call instruction (for indexing purposes). */ | |
43e9d192 IB |
1044 | #define FUNCTION_MODE Pmode |
1045 | ||
1046 | #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) | |
1047 | ||
865257c4 RS |
1048 | /* Having an integer comparison mode guarantees that we can use |
1049 | reverse_condition, but the usual restrictions apply to floating-point | |
1050 | comparisons. */ | |
1051 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPmode && (MODE) != CCFPEmode) | |
43e9d192 IB |
1052 | |
1053 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
952e7819 | 1054 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
43e9d192 | 1055 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
952e7819 | 1056 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
43e9d192 IB |
1057 | |
1058 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) | |
1059 | ||
1060 | #define RETURN_ADDR_RTX aarch64_return_addr | |
1061 | ||
be178ecd MM |
1062 | /* BTI c + 3 insns |
1063 | + sls barrier of DSB + ISB. | |
1064 | + 2 pointer-sized entries. */ | |
1065 | #define TRAMPOLINE_SIZE (24 + (TARGET_ILP32 ? 8 : 16)) | |
43e9d192 IB |
1066 | |
1067 | /* Trampolines contain dwords, so must be dword aligned. */ | |
1068 | #define TRAMPOLINE_ALIGNMENT 64 | |
1069 | ||
1070 | /* Put trampolines in the text section so that mapping symbols work | |
1071 | correctly. */ | |
1072 | #define TRAMPOLINE_SECTION text_section | |
43e9d192 IB |
1073 | |
1074 | /* To start with. */ | |
b9066f5a MW |
1075 | #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ |
1076 | (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) | |
43e9d192 IB |
1077 | \f |
1078 | ||
1079 | /* Assembly output. */ | |
1080 | ||
1081 | /* For now we'll make all jump tables pc-relative. */ | |
1082 | #define CASE_VECTOR_PC_RELATIVE 1 | |
1083 | ||
1084 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
1085 | ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ | |
1086 | : (min < -0x1f0 || max > 0x1f0) ? HImode \ | |
1087 | : QImode) | |
1088 | ||
1089 | /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ | |
1090 | #define ADDR_VEC_ALIGN(JUMPTABLE) 0 | |
1091 | ||
92d649c4 VK |
1092 | #define MCOUNT_NAME "_mcount" |
1093 | ||
1094 | #define NO_PROFILE_COUNTERS 1 | |
1095 | ||
1096 | /* Emit rtl for profiling. Output assembler code to FILE | |
1097 | to call "_mcount" for profiling a function entry. */ | |
3294102b MS |
1098 | #define PROFILE_HOOK(LABEL) \ |
1099 | { \ | |
1100 | rtx fun, lr; \ | |
463a54e5 | 1101 | lr = aarch64_return_addr_rtx (); \ |
3294102b | 1102 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ |
db69559b | 1103 | emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \ |
3294102b | 1104 | } |
92d649c4 VK |
1105 | |
1106 | /* All the work done in PROFILE_HOOK, but still required. */ | |
1107 | #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) | |
43e9d192 IB |
1108 | |
1109 | /* For some reason, the Linux headers think they know how to define | |
1110 | these macros. They don't!!! */ | |
1111 | #undef ASM_APP_ON | |
1112 | #undef ASM_APP_OFF | |
1113 | #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" | |
1114 | #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" | |
1115 | ||
43e9d192 IB |
1116 | #define CONSTANT_POOL_BEFORE_FUNCTION 0 |
1117 | ||
1118 | /* This definition should be relocated to aarch64-elf-raw.h. This macro | |
1119 | should be undefined in aarch64-linux.h and a clear_cache pattern | |
1120 | implmented to emit either the call to __aarch64_sync_cache_range() | |
1121 | directly or preferably the appropriate sycall or cache clear | |
1122 | instructions inline. */ | |
1123 | #define CLEAR_INSN_CACHE(beg, end) \ | |
1124 | extern void __aarch64_sync_cache_range (void *, void *); \ | |
1125 | __aarch64_sync_cache_range (beg, end) | |
1126 | ||
e6bd9fb9 | 1127 | #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) |
43e9d192 | 1128 | |
73d9ac6a IB |
1129 | /* Choose appropriate mode for caller saves, so we do the minimum |
1130 | required size of load/store. */ | |
1131 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
1132 | aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) | |
1133 | ||
d78006d9 KT |
1134 | #undef SWITCHABLE_TARGET |
1135 | #define SWITCHABLE_TARGET 1 | |
1136 | ||
43e9d192 IB |
1137 | /* Check TLS Descriptors mechanism is selected. */ |
1138 | #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) | |
1139 | ||
1140 | extern enum aarch64_code_model aarch64_cmodel; | |
1141 | ||
1142 | /* When using the tiny addressing model conditional and unconditional branches | |
1143 | can span the whole of the available address space (1MB). */ | |
1144 | #define HAS_LONG_COND_BRANCH \ | |
1145 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
1146 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
1147 | ||
1148 | #define HAS_LONG_UNCOND_BRANCH \ | |
1149 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
1150 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
1151 | ||
2ca5b430 KT |
1152 | #define TARGET_SUPPORTS_WIDE_INT 1 |
1153 | ||
635e66fe AL |
1154 | /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ |
1155 | #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ | |
1156 | ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ | |
1157 | || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ | |
abbe1ed2 | 1158 | || (MODE) == DFmode || (MODE) == V4BFmode) |
635e66fe | 1159 | |
43e9d192 IB |
1160 | /* Modes valid for AdvSIMD Q registers. */ |
1161 | #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ | |
1162 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
71a11456 | 1163 | || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ |
abbe1ed2 | 1164 | || (MODE) == V2DFmode || (MODE) == V8BFmode) |
43e9d192 | 1165 | |
7ac29c0f RS |
1166 | #define ENDIAN_LANE_N(NUNITS, N) \ |
1167 | (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) | |
e58bf20a | 1168 | |
dd9e5f4d KT |
1169 | /* Extra specs when building a native AArch64-hosted compiler. |
1170 | Option rewriting rules based on host system. */ | |
1171 | #if defined(__aarch64__) | |
1172 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
1173 | #define HAVE_LOCAL_CPU_DETECT | |
1174 | # define EXTRA_SPEC_FUNCTIONS \ | |
1175 | { "local_cpu_detect", host_detect_local_cpu }, \ | |
1176 | MCPU_TO_MARCH_SPEC_FUNCTIONS | |
1177 | ||
1178 | /* Rewrite -m{arch,cpu,tune}=native based on the host system information. | |
1179 | When rewriting -march=native convert it into an -mcpu option if no other | |
1180 | -mcpu or -mtune was given. */ | |
1181 | # define MCPU_MTUNE_NATIVE_SPECS \ | |
1182 | " %{march=native:%<march=native %:local_cpu_detect(%{mcpu=*|mtune=*:arch;:cpu})}" \ | |
1183 | " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ | |
1184 | " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
1185 | /* This will be used in OPTION_DEFAULT_SPECS below. | |
1186 | When GCC is configured with --with-tune we don't want to materialize an | |
1187 | implicit -mtune would prevent the rewriting of -march=native into | |
1188 | -mcpu=native as per the above rules. */ | |
1189 | #define CONFIG_TUNE_SPEC \ | |
1190 | { "tune", "%{!mcpu=*:%{!mtune=*:%{!march=native:-mtune=%(VALUE)}}}" }, | |
1191 | #else | |
1192 | # define MCPU_MTUNE_NATIVE_SPECS "" | |
1193 | # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS | |
1194 | # define CONFIG_TUNE_SPEC \ | |
1195 | {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"}, | |
1196 | #endif | |
1197 | ||
4dc486b6 WD |
1198 | /* Support for configure-time --with-arch, --with-cpu and --with-tune. |
1199 | --with-arch and --with-cpu are ignored if either -mcpu or -march is used. | |
1200 | --with-tune is ignored if either -mtune or -mcpu is used (but is not | |
dd9e5f4d KT |
1201 | affected by -march, except in the -march=native case as per the |
1202 | CONFIG_TUNE_SPEC above). */ | |
9815fafa RE |
1203 | #define OPTION_DEFAULT_SPECS \ |
1204 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
4dc486b6 | 1205 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ |
dd9e5f4d | 1206 | CONFIG_TUNE_SPEC |
9815fafa | 1207 | |
054b4005 JG |
1208 | #define MCPU_TO_MARCH_SPEC \ |
1209 | " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" | |
682287fb JG |
1210 | |
1211 | extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); | |
054b4005 | 1212 | #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ |
682287fb JG |
1213 | { "rewrite_mcpu", aarch64_rewrite_mcpu }, |
1214 | ||
1215 | #define ASM_CPU_SPEC \ | |
054b4005 | 1216 | MCPU_TO_MARCH_SPEC |
682287fb | 1217 | |
682287fb JG |
1218 | #define EXTRA_SPECS \ |
1219 | { "asm_cpu_spec", ASM_CPU_SPEC } | |
1220 | ||
5fca7b66 RH |
1221 | #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue |
1222 | ||
1b62ed4f | 1223 | /* This type is the user-visible __fp16, and a pointer to that type. We |
e53b6e56 | 1224 | need it in many places in the backend. Defined in aarch64-builtins.cc. */ |
98f1dd02 AP |
1225 | extern GTY(()) tree aarch64_fp16_type_node; |
1226 | extern GTY(()) tree aarch64_fp16_ptr_type_node; | |
1b62ed4f | 1227 | |
abbe1ed2 | 1228 | /* This type is the user-visible __bf16, and a pointer to that type. Defined |
e53b6e56 | 1229 | in aarch64-builtins.cc. */ |
98f1dd02 AP |
1230 | extern GTY(()) tree aarch64_bf16_type_node; |
1231 | extern GTY(()) tree aarch64_bf16_ptr_type_node; | |
abbe1ed2 | 1232 | |
817221cc WD |
1233 | /* The generic unwind code in libgcc does not initialize the frame pointer. |
1234 | So in order to unwind a function using a frame pointer, the very first | |
1235 | function that is unwound must save the frame pointer. That way the frame | |
1236 | pointer is restored and its value is now valid - otherwise _Unwind_GetGR | |
1237 | crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ | |
1238 | #define LIBGCC2_UNWIND_ATTRIBUTE \ | |
1239 | __attribute__((optimize ("no-omit-frame-pointer"))) | |
1240 | ||
43cacb12 RS |
1241 | #ifndef USED_FOR_TARGET |
1242 | extern poly_uint16 aarch64_sve_vg; | |
1243 | ||
1244 | /* The number of bits and bytes in an SVE vector. */ | |
1245 | #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64)) | |
1246 | #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8)) | |
1247 | ||
c600df9a RS |
1248 | /* The number of bits and bytes in an SVE predicate. */ |
1249 | #define BITS_PER_SVE_PRED BYTES_PER_SVE_VECTOR | |
43cacb12 RS |
1250 | #define BYTES_PER_SVE_PRED aarch64_sve_vg |
1251 | ||
1252 | /* The SVE mode for a vector of bytes. */ | |
1253 | #define SVE_BYTE_MODE VNx16QImode | |
1254 | ||
1255 | /* The maximum number of bytes in a fixed-size vector. This is 256 bytes | |
1256 | (for -msve-vector-bits=2048) multiplied by the maximum number of | |
1257 | vectors in a structure mode (4). | |
1258 | ||
1259 | This limit must not be used for variable-size vectors, since | |
1260 | VL-agnostic code must work with arbitary vector lengths. */ | |
1261 | #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4) | |
1262 | #endif | |
1263 | ||
1264 | #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE) | |
1265 | ||
8c6e3b23 TC |
1266 | /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the |
1267 | outgoing arguments if stack clash protection is enabled. This is essential | |
1268 | as the extra arg space allows us to skip a check in alloca. */ | |
1269 | #undef STACK_DYNAMIC_OFFSET | |
1270 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
1271 | ((flag_stack_clash_protection \ | |
1272 | && cfun->calls_alloca \ | |
1273 | && known_lt (crtl->outgoing_args_size, \ | |
1274 | STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \ | |
1275 | ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \ | |
1276 | STACK_BOUNDARY / BITS_PER_UNIT) \ | |
1277 | : (crtl->outgoing_args_size + STACK_POINTER_OFFSET)) | |
1278 | ||
43e9d192 | 1279 | #endif /* GCC_AARCH64_H */ |