]>
Commit | Line | Data |
---|---|---|
43e9d192 | 1 | /* Machine description for AArch64 architecture. |
a5544970 | 2 | Copyright (C) 2009-2019 Free Software Foundation, Inc. |
43e9d192 IB |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but | |
13 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | #ifndef GCC_AARCH64_H | |
23 | #define GCC_AARCH64_H | |
24 | ||
25 | /* Target CPU builtins. */ | |
e4ea20c8 KT |
26 | #define TARGET_CPU_CPP_BUILTINS() \ |
27 | aarch64_cpu_cpp_builtins (pfile) | |
43e9d192 | 28 | |
b4c522fa IB |
29 | /* Target CPU versions for D. */ |
30 | #define TARGET_D_CPU_VERSIONS aarch64_d_target_versions | |
31 | ||
43e9d192 IB |
32 | \f |
33 | ||
e4ea20c8 KT |
34 | #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () |
35 | ||
43e9d192 IB |
36 | /* Target machine storage layout. */ |
37 | ||
38 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
39 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
40 | && GET_MODE_SIZE (MODE) < 4) \ | |
41 | { \ | |
42 | if (MODE == QImode || MODE == HImode) \ | |
43 | { \ | |
44 | MODE = SImode; \ | |
45 | } \ | |
46 | } | |
47 | ||
48 | /* Bits are always numbered from the LSBit. */ | |
49 | #define BITS_BIG_ENDIAN 0 | |
50 | ||
51 | /* Big/little-endian flavour. */ | |
52 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) | |
53 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
54 | ||
55 | /* AdvSIMD is supported in the default configuration, unless disabled by | |
683e3333 KT |
56 | -mgeneral-regs-only or by the +nosimd extension. */ |
57 | #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) | |
58 | #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) | |
43e9d192 IB |
59 | |
60 | #define UNITS_PER_WORD 8 | |
61 | ||
62 | #define UNITS_PER_VREG 16 | |
63 | ||
64 | #define PARM_BOUNDARY 64 | |
65 | ||
66 | #define STACK_BOUNDARY 128 | |
67 | ||
68 | #define FUNCTION_BOUNDARY 32 | |
69 | ||
70 | #define EMPTY_FIELD_BOUNDARY 32 | |
71 | ||
72 | #define BIGGEST_ALIGNMENT 128 | |
73 | ||
74 | #define SHORT_TYPE_SIZE 16 | |
75 | ||
76 | #define INT_TYPE_SIZE 32 | |
77 | ||
17a819cb YZ |
78 | #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) |
79 | ||
80 | #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) | |
43e9d192 IB |
81 | |
82 | #define LONG_LONG_TYPE_SIZE 64 | |
83 | ||
84 | #define FLOAT_TYPE_SIZE 32 | |
85 | ||
86 | #define DOUBLE_TYPE_SIZE 64 | |
87 | ||
88 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
89 | ||
cd1bef27 JL |
90 | /* This value is the amount of bytes a caller is allowed to drop the stack |
91 | before probing has to be done for stack clash protection. */ | |
92 | #define STACK_CLASH_CALLER_GUARD 1024 | |
93 | ||
8c6e3b23 TC |
94 | /* This value represents the minimum amount of bytes we expect the function's |
95 | outgoing arguments to be when stack-clash is enabled. */ | |
96 | #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8 | |
97 | ||
cd1bef27 JL |
98 | /* This value controls how many pages we manually unroll the loop for when |
99 | generating stack clash probes. */ | |
100 | #define STACK_CLASH_MAX_UNROLL_PAGES 4 | |
101 | ||
43e9d192 IB |
102 | /* The architecture reserves all bits of the address for hardware use, |
103 | so the vbit must go into the delta field of pointers to member | |
104 | functions. This is the same config as that in the AArch32 | |
105 | port. */ | |
106 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
107 | ||
98503487 RR |
108 | /* Align definitions of arrays, unions and structures so that |
109 | initializations and copies can be made more efficient. This is not | |
110 | ABI-changing, so it only affects places where we can see the | |
111 | definition. Increasing the alignment tends to introduce padding, | |
112 | so don't do this when optimizing for size/conserving stack space. */ | |
113 | #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ | |
114 | (((COND) && ((ALIGN) < BITS_PER_WORD) \ | |
115 | && (TREE_CODE (EXP) == ARRAY_TYPE \ | |
116 | || TREE_CODE (EXP) == UNION_TYPE \ | |
117 | || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
118 | ||
119 | /* Align global data. */ | |
120 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
121 | AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN) | |
122 | ||
123 | /* Similarly, make sure that objects on the stack are sensibly aligned. */ | |
124 | #define LOCAL_ALIGNMENT(EXP, ALIGN) \ | |
125 | AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN) | |
43e9d192 IB |
126 | |
127 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
128 | ||
e10dbae3 WD |
129 | /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY). */ |
130 | #define MALLOC_ABI_ALIGNMENT 128 | |
131 | ||
43e9d192 IB |
132 | /* Defined by the ABI */ |
133 | #define WCHAR_TYPE "unsigned int" | |
134 | #define WCHAR_TYPE_SIZE 32 | |
135 | ||
136 | /* Using long long breaks -ansi and -std=c90, so these will need to be | |
137 | made conditional for an LLP64 ABI. */ | |
138 | ||
139 | #define SIZE_TYPE "long unsigned int" | |
140 | ||
141 | #define PTRDIFF_TYPE "long int" | |
142 | ||
143 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
144 | ||
0c6caaf8 RL |
145 | /* Major revision number of the ARM Architecture implemented by the target. */ |
146 | extern unsigned aarch64_architecture_version; | |
43e9d192 IB |
147 | |
148 | /* Instruction tuning/selection flags. */ | |
149 | ||
150 | /* Bit values used to identify processor capabilities. */ | |
151 | #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ | |
152 | #define AARCH64_FL_FP (1 << 1) /* Has FP. */ | |
153 | #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ | |
95f99170 | 154 | #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ |
74bb9de4 | 155 | /* ARMv8.1-A architecture extensions. */ |
dfba575f | 156 | #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ |
1ddc47c0 TC |
157 | #define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */ |
158 | #define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */ | |
c61465bd | 159 | /* ARMv8.2-A architecture extensions. */ |
1ddc47c0 | 160 | #define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ |
c61465bd | 161 | #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ |
43cacb12 | 162 | #define AARCH64_FL_SVE (1 << 10) /* Has Scalable Vector Extensions. */ |
d766c52b | 163 | /* ARMv8.3-A architecture extensions. */ |
43cacb12 RS |
164 | #define AARCH64_FL_V8_3 (1 << 11) /* Has ARMv8.3-A features. */ |
165 | #define AARCH64_FL_RCPC (1 << 12) /* Has support for RCpc model. */ | |
166 | #define AARCH64_FL_DOTPROD (1 << 13) /* Has ARMv8.2-A Dot Product ins. */ | |
27086ea3 | 167 | /* New flags to split crypto into aes and sha2. */ |
43cacb12 RS |
168 | #define AARCH64_FL_AES (1 << 14) /* Has Crypto AES. */ |
169 | #define AARCH64_FL_SHA2 (1 << 15) /* Has Crypto SHA2. */ | |
27086ea3 | 170 | /* ARMv8.4-A architecture extensions. */ |
43cacb12 RS |
171 | #define AARCH64_FL_V8_4 (1 << 16) /* Has ARMv8.4-A features. */ |
172 | #define AARCH64_FL_SM4 (1 << 17) /* Has ARMv8.4-A SM3 and SM4. */ | |
173 | #define AARCH64_FL_SHA3 (1 << 18) /* Has ARMv8.4-a SHA3 and SHA512. */ | |
174 | #define AARCH64_FL_F16FML (1 << 19) /* Has ARMv8.4-a FP16 extensions. */ | |
3c5af608 | 175 | #define AARCH64_FL_RCPC8_4 (1 << 20) /* Has ARMv8.4-a RCPC extensions. */ |
43e9d192 | 176 | |
5170e47e | 177 | /* Statistical Profiling extensions. */ |
3c5af608 | 178 | #define AARCH64_FL_PROFILE (1 << 21) |
5170e47e | 179 | |
59beeb62 SD |
180 | /* ARMv8.5-A architecture extensions. */ |
181 | #define AARCH64_FL_V8_5 (1 << 22) /* Has ARMv8.5-A features. */ | |
9b4247de SD |
182 | #define AARCH64_FL_RNG (1 << 23) /* ARMv8.5-A Random Number Insns. */ |
183 | #define AARCH64_FL_MEMTAG (1 << 24) /* ARMv8.5-A Memory Tagging | |
184 | Extensions. */ | |
185 | ||
186 | /* Speculation Barrier instruction supported. */ | |
187 | #define AARCH64_FL_SB (1 << 25) | |
188 | ||
189 | /* Speculative Store Bypass Safe instruction supported. */ | |
190 | #define AARCH64_FL_SSBS (1 << 26) | |
191 | ||
192 | /* Execution and Data Prediction Restriction instructions supported. */ | |
193 | #define AARCH64_FL_PREDRES (1 << 27) | |
59beeb62 | 194 | |
28108a53 MM |
195 | /* SVE2 instruction supported. */ |
196 | #define AARCH64_FL_SVE2 (1 << 28) | |
197 | #define AARCH64_FL_SVE2_AES (1 << 29) | |
198 | #define AARCH64_FL_SVE2_SM4 (1 << 30) | |
199 | #define AARCH64_FL_SVE2_SHA3 (1ULL << 31) | |
200 | #define AARCH64_FL_SVE2_BITPERM (1ULL << 32) | |
201 | ||
89626179 SD |
202 | /* Transactional Memory Extension. */ |
203 | #define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */ | |
204 | ||
43e9d192 IB |
205 | /* Has FP and SIMD. */ |
206 | #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) | |
207 | ||
208 | /* Has FP without SIMD. */ | |
209 | #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) | |
210 | ||
211 | /* Architecture flags that effect instruction selection. */ | |
212 | #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) | |
ff09c88d | 213 | #define AARCH64_FL_FOR_ARCH8_1 \ |
43f84f6c JW |
214 | (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \ |
215 | | AARCH64_FL_RDMA | AARCH64_FL_V8_1) | |
c61465bd MW |
216 | #define AARCH64_FL_FOR_ARCH8_2 \ |
217 | (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) | |
d766c52b JW |
218 | #define AARCH64_FL_FOR_ARCH8_3 \ |
219 | (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3) | |
27086ea3 | 220 | #define AARCH64_FL_FOR_ARCH8_4 \ |
ec538483 | 221 | (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \ |
3c5af608 | 222 | | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4) |
59beeb62 | 223 | #define AARCH64_FL_FOR_ARCH8_5 \ |
9b4247de SD |
224 | (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \ |
225 | | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) | |
43e9d192 IB |
226 | |
227 | /* Macros to test ISA flags. */ | |
361fb3ee | 228 | |
5922847b | 229 | #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) |
43e9d192 IB |
230 | #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) |
231 | #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) | |
232 | #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) | |
045c2d32 | 233 | #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) |
43f84f6c | 234 | #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) |
c61465bd MW |
235 | #define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) |
236 | #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) | |
43cacb12 | 237 | #define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE) |
0617e23c | 238 | #define AARCH64_ISA_SVE2 (aarch64_isa_flags & AARCH64_FL_SVE2) |
d766c52b | 239 | #define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3) |
1ddc47c0 | 240 | #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) |
27086ea3 MC |
241 | #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) |
242 | #define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2) | |
243 | #define AARCH64_ISA_V8_4 (aarch64_isa_flags & AARCH64_FL_V8_4) | |
244 | #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) | |
245 | #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) | |
246 | #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) | |
3c5af608 | 247 | #define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_RCPC8_4) |
c5dc215d | 248 | #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) |
59beeb62 | 249 | #define AARCH64_ISA_V8_5 (aarch64_isa_flags & AARCH64_FL_V8_5) |
89626179 | 250 | #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME) |
43e9d192 | 251 | |
683e3333 KT |
252 | /* Crypto is an optional extension to AdvSIMD. */ |
253 | #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) | |
43e9d192 | 254 | |
27086ea3 MC |
255 | /* SHA2 is an optional extension to AdvSIMD. */ |
256 | #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO) | |
257 | ||
258 | /* SHA3 is an optional extension to AdvSIMD. */ | |
259 | #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3) | |
260 | ||
261 | /* AES is an optional extension to AdvSIMD. */ | |
262 | #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO) | |
263 | ||
264 | /* SM is an optional extension to AdvSIMD. */ | |
265 | #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4) | |
266 | ||
267 | /* FP16FML is an optional extension to AdvSIMD. */ | |
268 | #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST) | |
269 | ||
5d357f26 KT |
270 | /* CRC instructions that can be enabled through +crc arch extension. */ |
271 | #define TARGET_CRC32 (AARCH64_ISA_CRC) | |
272 | ||
045c2d32 MW |
273 | /* Atomic instructions that can be enabled through the +lse extension. */ |
274 | #define TARGET_LSE (AARCH64_ISA_LSE) | |
275 | ||
c61465bd MW |
276 | /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ |
277 | #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) | |
278 | #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) | |
279 | ||
1ddc47c0 TC |
280 | /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ |
281 | #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD) | |
282 | ||
43cacb12 RS |
283 | /* SVE instructions, enabled through +sve. */ |
284 | #define TARGET_SVE (AARCH64_ISA_SVE) | |
285 | ||
0617e23c AM |
286 | /* SVE2 instructions, enabled through +sve2. */ |
287 | #define TARGET_SVE2 (AARCH64_ISA_SVE2) | |
288 | ||
d766c52b JW |
289 | /* ARMv8.3-A features. */ |
290 | #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) | |
291 | ||
e1d5d19e KT |
292 | /* Javascript conversion instruction from Armv8.3-a. */ |
293 | #define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3) | |
294 | ||
9d63f43b TC |
295 | /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ |
296 | #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) | |
297 | ||
10bd1d96 KT |
298 | /* Floating-point rounding instructions from Armv8.5-a. */ |
299 | #define TARGET_FRINT (AARCH64_ISA_V8_5 && TARGET_FLOAT) | |
300 | ||
89626179 SD |
301 | /* TME instructions are enabled. */ |
302 | #define TARGET_TME (AARCH64_ISA_TME) | |
303 | ||
c5dc215d KT |
304 | /* Random number instructions from Armv8.5-a. */ |
305 | #define TARGET_RNG (AARCH64_ISA_RNG) | |
306 | ||
b32c1043 KT |
307 | /* Make sure this is always defined so we don't have to check for ifdefs |
308 | but rather use normal ifs. */ | |
309 | #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT | |
310 | #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 | |
311 | #else | |
312 | #undef TARGET_FIX_ERR_A53_835769_DEFAULT | |
313 | #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 | |
314 | #endif | |
315 | ||
316 | /* Apply the workaround for Cortex-A53 erratum 835769. */ | |
317 | #define TARGET_FIX_ERR_A53_835769 \ | |
318 | ((aarch64_fix_a53_err835769 == 2) \ | |
319 | ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) | |
320 | ||
48bb1a55 CL |
321 | /* Make sure this is always defined so we don't have to check for ifdefs |
322 | but rather use normal ifs. */ | |
323 | #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT | |
324 | #define TARGET_FIX_ERR_A53_843419_DEFAULT 0 | |
325 | #else | |
326 | #undef TARGET_FIX_ERR_A53_843419_DEFAULT | |
327 | #define TARGET_FIX_ERR_A53_843419_DEFAULT 1 | |
328 | #endif | |
329 | ||
330 | /* Apply the workaround for Cortex-A53 erratum 843419. */ | |
331 | #define TARGET_FIX_ERR_A53_843419 \ | |
332 | ((aarch64_fix_a53_err843419 == 2) \ | |
333 | ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) | |
334 | ||
74bb9de4 | 335 | /* ARMv8.1-A Adv.SIMD support. */ |
a3735e01 MW |
336 | #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) |
337 | ||
43e9d192 IB |
338 | /* Standard register usage. */ |
339 | ||
340 | /* 31 64-bit general purpose registers R0-R30: | |
341 | R30 LR (link register) | |
342 | R29 FP (frame pointer) | |
343 | R19-R28 Callee-saved registers | |
344 | R18 The platform register; use as temporary register. | |
345 | R17 IP1 The second intra-procedure-call temporary register | |
346 | (can be used by call veneers and PLT code); otherwise use | |
347 | as a temporary register | |
348 | R16 IP0 The first intra-procedure-call temporary register (can | |
349 | be used by call veneers and PLT code); otherwise use as a | |
350 | temporary register | |
351 | R9-R15 Temporary registers | |
352 | R8 Structure value parameter / temporary register | |
353 | R0-R7 Parameter/result registers | |
354 | ||
355 | SP stack pointer, encoded as X/R31 where permitted. | |
356 | ZR zero register, encoded as X/R31 elsewhere | |
357 | ||
358 | 32 x 128-bit floating-point/vector registers | |
359 | V16-V31 Caller-saved (temporary) registers | |
360 | V8-V15 Callee-saved registers | |
361 | V0-V7 Parameter/result registers | |
362 | ||
363 | The vector register V0 holds scalar B0, H0, S0 and D0 in its least | |
43cacb12 RS |
364 | significant bits. Unlike AArch32 S1 is not packed into D0, etc. |
365 | ||
366 | P0-P7 Predicate low registers: valid in all predicate contexts | |
367 | P8-P15 Predicate high registers: used as scratch space | |
368 | ||
369 | VG Pseudo "vector granules" register | |
370 | ||
371 | VG is the number of 64-bit elements in an SVE vector. We define | |
372 | it as a hard register so that we can easily map it to the DWARF VG | |
373 | register. GCC internally uses the poly_int variable aarch64_sve_vg | |
374 | instead. */ | |
43e9d192 | 375 | |
43e9d192 IB |
376 | #define FIXED_REGISTERS \ |
377 | { \ | |
378 | 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ | |
379 | 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ | |
380 | 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
381 | 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ | |
382 | 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ | |
383 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
384 | 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ | |
385 | 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ | |
43cacb12 RS |
386 | 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ |
387 | 0, 0, 0, 0, 0, 0, 0, 0, /* P0 - P7 */ \ | |
388 | 0, 0, 0, 0, 0, 0, 0, 0, /* P8 - P15 */ \ | |
43e9d192 IB |
389 | } |
390 | ||
643ef957 SP |
391 | /* X30 is marked as caller-saved which is in line with regular function call |
392 | behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does | |
393 | that for regular function calls and avoids it for sibcalls. X30 is | |
394 | considered live for sibcalls; EPILOGUE_USES helps achieve that by returning | |
395 | true but not until function epilogues have been generated. This ensures | |
396 | that X30 is available for use in leaf functions if needed. */ | |
397 | ||
43e9d192 IB |
398 | #define CALL_USED_REGISTERS \ |
399 | { \ | |
400 | 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ | |
401 | 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ | |
402 | 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
1c923b60 | 403 | 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ |
43e9d192 IB |
404 | 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ |
405 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
406 | 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ | |
407 | 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ | |
43cacb12 RS |
408 | 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ |
409 | 1, 1, 1, 1, 1, 1, 1, 1, /* P0 - P7 */ \ | |
410 | 1, 1, 1, 1, 1, 1, 1, 1, /* P8 - P15 */ \ | |
43e9d192 IB |
411 | } |
412 | ||
413 | #define REGISTER_NAMES \ | |
414 | { \ | |
415 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ | |
416 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ | |
417 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ | |
418 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ | |
419 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ | |
420 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ | |
421 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ | |
422 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ | |
43cacb12 RS |
423 | "sfp", "ap", "cc", "vg", \ |
424 | "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", \ | |
425 | "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", \ | |
43e9d192 IB |
426 | } |
427 | ||
428 | /* Generate the register aliases for core register N */ | |
429 | #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ | |
430 | {"w" # N, R0_REGNUM + (N)} | |
431 | ||
432 | #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ | |
433 | {"d" # N, V0_REGNUM + (N)}, \ | |
434 | {"s" # N, V0_REGNUM + (N)}, \ | |
435 | {"h" # N, V0_REGNUM + (N)}, \ | |
43cacb12 RS |
436 | {"b" # N, V0_REGNUM + (N)}, \ |
437 | {"z" # N, V0_REGNUM + (N)} | |
43e9d192 IB |
438 | |
439 | /* Provide aliases for all of the ISA defined register name forms. | |
440 | These aliases are convenient for use in the clobber lists of inline | |
441 | asm statements. */ | |
442 | ||
443 | #define ADDITIONAL_REGISTER_NAMES \ | |
444 | { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ | |
445 | R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ | |
446 | R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ | |
447 | R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ | |
448 | R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ | |
449 | R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ | |
450 | R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ | |
9259db42 | 451 | R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ |
43e9d192 IB |
452 | V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ |
453 | V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ | |
454 | V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ | |
455 | V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ | |
456 | V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ | |
457 | V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ | |
458 | V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ | |
459 | V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ | |
460 | } | |
461 | ||
a0d0b980 | 462 | #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO)) |
43e9d192 IB |
463 | |
464 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
204d2c03 WD |
465 | the stack pointer does not matter. This is only true if the function |
466 | uses alloca. */ | |
467 | #define EXIT_IGNORE_STACK (cfun->calls_alloca) | |
43e9d192 IB |
468 | |
469 | #define STATIC_CHAIN_REGNUM R18_REGNUM | |
470 | #define HARD_FRAME_POINTER_REGNUM R29_REGNUM | |
471 | #define FRAME_POINTER_REGNUM SFP_REGNUM | |
472 | #define STACK_POINTER_REGNUM SP_REGNUM | |
473 | #define ARG_POINTER_REGNUM AP_REGNUM | |
43cacb12 | 474 | #define FIRST_PSEUDO_REGISTER (P15_REGNUM + 1) |
43e9d192 IB |
475 | |
476 | /* The number of (integer) argument register available. */ | |
477 | #define NUM_ARG_REGS 8 | |
478 | #define NUM_FP_ARG_REGS 8 | |
479 | ||
480 | /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most | |
481 | four members. */ | |
482 | #define HA_MAX_NUM_FLDS 4 | |
483 | ||
484 | /* External dwarf register number scheme. These number are used to | |
485 | identify registers in dwarf debug information, the values are | |
486 | defined by the AArch64 ABI. The numbering scheme is independent of | |
487 | GCC's internal register numbering scheme. */ | |
488 | ||
489 | #define AARCH64_DWARF_R0 0 | |
490 | ||
491 | /* The number of R registers, note 31! not 32. */ | |
492 | #define AARCH64_DWARF_NUMBER_R 31 | |
493 | ||
494 | #define AARCH64_DWARF_SP 31 | |
43cacb12 RS |
495 | #define AARCH64_DWARF_VG 46 |
496 | #define AARCH64_DWARF_P0 48 | |
43e9d192 IB |
497 | #define AARCH64_DWARF_V0 64 |
498 | ||
499 | /* The number of V registers. */ | |
500 | #define AARCH64_DWARF_NUMBER_V 32 | |
501 | ||
502 | /* For signal frames we need to use an alternative return column. This | |
503 | value must not correspond to a hard register and must be out of the | |
504 | range of DWARF_FRAME_REGNUM(). */ | |
505 | #define DWARF_ALT_FRAME_RETURN_COLUMN \ | |
506 | (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) | |
507 | ||
508 | /* We add 1 extra frame register for use as the | |
509 | DWARF_ALT_FRAME_RETURN_COLUMN. */ | |
510 | #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) | |
511 | ||
512 | ||
513 | #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) | |
514 | /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders | |
515 | can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same | |
516 | as the default definition in dwarf2out.c. */ | |
517 | #undef DWARF_FRAME_REGNUM | |
518 | #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) | |
519 | ||
520 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
521 | ||
43e9d192 IB |
522 | #define DWARF2_UNWIND_INFO 1 |
523 | ||
524 | /* Use R0 through R3 to pass exception handling information. */ | |
525 | #define EH_RETURN_DATA_REGNO(N) \ | |
526 | ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) | |
527 | ||
528 | /* Select a format to encode pointers in exception handling data. */ | |
529 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
530 | aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) | |
531 | ||
361fb3ee KT |
532 | /* Output the assembly strings we want to add to a function definition. */ |
533 | #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ | |
534 | aarch64_declare_function_name (STR, NAME, DECL) | |
535 | ||
b07fc91c SN |
536 | /* Output assembly strings for alias definition. */ |
537 | #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ | |
538 | aarch64_asm_output_alias (STR, DECL, TARGET) | |
539 | ||
540 | /* Output assembly strings for undefined extern symbols. */ | |
541 | #undef ASM_OUTPUT_EXTERNAL | |
542 | #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ | |
543 | aarch64_asm_output_external (STR, DECL, NAME) | |
544 | ||
8fc16d72 ST |
545 | /* Output assembly strings after .cfi_startproc is emitted. */ |
546 | #define ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc | |
547 | ||
8144a493 WD |
548 | /* For EH returns X4 contains the stack adjustment. */ |
549 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) | |
550 | #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () | |
43e9d192 IB |
551 | |
552 | /* Don't use __builtin_setjmp until we've defined it. */ | |
553 | #undef DONT_USE_BUILTIN_SETJMP | |
554 | #define DONT_USE_BUILTIN_SETJMP 1 | |
555 | ||
0795f659 VL |
556 | #undef TARGET_COMPUTE_FRAME_LAYOUT |
557 | #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame | |
558 | ||
43e9d192 IB |
559 | /* Register in which the structure value is to be returned. */ |
560 | #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM | |
561 | ||
562 | /* Non-zero if REGNO is part of the Core register set. | |
563 | ||
564 | The rather unusual way of expressing this check is to avoid | |
565 | warnings when building the compiler when R0_REGNUM is 0 and REGNO | |
566 | is unsigned. */ | |
567 | #define GP_REGNUM_P(REGNO) \ | |
568 | (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) | |
569 | ||
570 | #define FP_REGNUM_P(REGNO) \ | |
571 | (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) | |
572 | ||
573 | #define FP_LO_REGNUM_P(REGNO) \ | |
574 | (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) | |
575 | ||
163b1f6a RS |
576 | #define FP_LO8_REGNUM_P(REGNO) \ |
577 | (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM)) | |
578 | ||
43cacb12 RS |
579 | #define PR_REGNUM_P(REGNO)\ |
580 | (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) | |
581 | ||
582 | #define PR_LO_REGNUM_P(REGNO)\ | |
583 | (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM)) | |
584 | ||
a0d0b980 SE |
585 | #define FP_SIMD_SAVED_REGNUM_P(REGNO) \ |
586 | (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM)) | |
43e9d192 IB |
587 | \f |
588 | /* Register and constant classes. */ | |
589 | ||
590 | enum reg_class | |
591 | { | |
592 | NO_REGS, | |
d677263e | 593 | TAILCALL_ADDR_REGS, |
43e9d192 IB |
594 | GENERAL_REGS, |
595 | STACK_REG, | |
596 | POINTER_REGS, | |
163b1f6a | 597 | FP_LO8_REGS, |
43e9d192 IB |
598 | FP_LO_REGS, |
599 | FP_REGS, | |
f25a140b | 600 | POINTER_AND_FP_REGS, |
43cacb12 RS |
601 | PR_LO_REGS, |
602 | PR_HI_REGS, | |
603 | PR_REGS, | |
43e9d192 IB |
604 | ALL_REGS, |
605 | LIM_REG_CLASSES /* Last */ | |
606 | }; | |
607 | ||
608 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
609 | ||
610 | #define REG_CLASS_NAMES \ | |
611 | { \ | |
612 | "NO_REGS", \ | |
d677263e | 613 | "TAILCALL_ADDR_REGS", \ |
43e9d192 IB |
614 | "GENERAL_REGS", \ |
615 | "STACK_REG", \ | |
616 | "POINTER_REGS", \ | |
163b1f6a | 617 | "FP_LO8_REGS", \ |
43e9d192 IB |
618 | "FP_LO_REGS", \ |
619 | "FP_REGS", \ | |
f25a140b | 620 | "POINTER_AND_FP_REGS", \ |
43cacb12 RS |
621 | "PR_LO_REGS", \ |
622 | "PR_HI_REGS", \ | |
623 | "PR_REGS", \ | |
43e9d192 IB |
624 | "ALL_REGS" \ |
625 | } | |
626 | ||
627 | #define REG_CLASS_CONTENTS \ | |
628 | { \ | |
629 | { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
901e66e0 | 630 | { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ |
43e9d192 IB |
631 | { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ |
632 | { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
633 | { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ | |
163b1f6a | 634 | { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ |
43e9d192 IB |
635 | { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ |
636 | { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ | |
f25a140b | 637 | { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ |
43cacb12 RS |
638 | { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \ |
639 | { 0x00000000, 0x00000000, 0x000ff000 }, /* PR_HI_REGS */ \ | |
640 | { 0x00000000, 0x00000000, 0x000ffff0 }, /* PR_REGS */ \ | |
641 | { 0xffffffff, 0xffffffff, 0x000fffff } /* ALL_REGS */ \ | |
43e9d192 IB |
642 | } |
643 | ||
644 | #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) | |
645 | ||
a4a182c6 | 646 | #define INDEX_REG_CLASS GENERAL_REGS |
43e9d192 IB |
647 | #define BASE_REG_CLASS POINTER_REGS |
648 | ||
6991c977 | 649 | /* Register pairs used to eliminate unneeded registers that point into |
43e9d192 IB |
650 | the stack frame. */ |
651 | #define ELIMINABLE_REGS \ | |
652 | { \ | |
653 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
654 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
655 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
656 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
657 | } | |
658 | ||
659 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
660 | (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) | |
661 | ||
662 | /* CPU/ARCH option handling. */ | |
663 | #include "config/aarch64/aarch64-opts.h" | |
664 | ||
665 | enum target_cpus | |
666 | { | |
e8fcc9fa | 667 | #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ |
192ed1dd | 668 | TARGET_CPU_##INTERNAL_IDENT, |
43e9d192 | 669 | #include "aarch64-cores.def" |
43e9d192 IB |
670 | TARGET_CPU_generic |
671 | }; | |
672 | ||
a3cd0246 | 673 | /* If there is no CPU defined at configure, use generic as default. */ |
43e9d192 IB |
674 | #ifndef TARGET_CPU_DEFAULT |
675 | #define TARGET_CPU_DEFAULT \ | |
a3cd0246 | 676 | (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) |
43e9d192 IB |
677 | #endif |
678 | ||
75cf1494 KT |
679 | /* If inserting NOP before a mult-accumulate insn remember to adjust the |
680 | length so that conditional branching code is updated appropriately. */ | |
681 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
8baff86e KT |
682 | do \ |
683 | { \ | |
684 | if (aarch64_madd_needs_nop (insn)) \ | |
685 | length += 4; \ | |
686 | } while (0) | |
75cf1494 KT |
687 | |
688 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
689 | aarch64_final_prescan_insn (INSN); \ | |
690 | ||
43e9d192 IB |
691 | /* The processor for which instructions should be scheduled. */ |
692 | extern enum aarch64_processor aarch64_tune; | |
693 | ||
694 | /* RTL generation support. */ | |
695 | #define INIT_EXPANDERS aarch64_init_expanders () | |
696 | \f | |
697 | ||
698 | /* Stack layout; function entry, exit and calling. */ | |
699 | #define STACK_GROWS_DOWNWARD 1 | |
700 | ||
6991c977 | 701 | #define FRAME_GROWS_DOWNWARD 1 |
43e9d192 | 702 | |
43e9d192 IB |
703 | #define ACCUMULATE_OUTGOING_ARGS 1 |
704 | ||
705 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
706 | ||
707 | /* Fix for VFP */ | |
708 | #define LIBCALL_VALUE(MODE) \ | |
709 | gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) | |
710 | ||
711 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
712 | ||
6a70badb | 713 | #ifdef HAVE_POLY_INT_H |
43e9d192 IB |
714 | struct GTY (()) aarch64_frame |
715 | { | |
716 | HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; | |
8799637a MS |
717 | |
718 | /* The number of extra stack bytes taken up by register varargs. | |
719 | This area is allocated by the callee at the very top of the | |
720 | frame. This value is rounded up to a multiple of | |
721 | STACK_BOUNDARY. */ | |
722 | HOST_WIDE_INT saved_varargs_size; | |
723 | ||
71bfb77a WD |
724 | /* The size of the saved callee-save int/FP registers. */ |
725 | ||
43e9d192 | 726 | HOST_WIDE_INT saved_regs_size; |
71bfb77a WD |
727 | |
728 | /* Offset from the base of the frame (incomming SP) to the | |
729 | top of the locals area. This value is always a multiple of | |
730 | STACK_BOUNDARY. */ | |
6a70badb | 731 | poly_int64 locals_offset; |
43e9d192 | 732 | |
1c960e02 MS |
733 | /* Offset from the base of the frame (incomming SP) to the |
734 | hard_frame_pointer. This value is always a multiple of | |
735 | STACK_BOUNDARY. */ | |
6a70badb | 736 | poly_int64 hard_fp_offset; |
1c960e02 MS |
737 | |
738 | /* The size of the frame. This value is the offset from base of the | |
6a70badb RS |
739 | frame (incomming SP) to the stack_pointer. This value is always |
740 | a multiple of STACK_BOUNDARY. */ | |
741 | poly_int64 frame_size; | |
71bfb77a WD |
742 | |
743 | /* The size of the initial stack adjustment before saving callee-saves. */ | |
6a70badb | 744 | poly_int64 initial_adjust; |
71bfb77a WD |
745 | |
746 | /* The writeback value when pushing callee-save registers. | |
747 | It is zero when no push is used. */ | |
748 | HOST_WIDE_INT callee_adjust; | |
749 | ||
750 | /* The offset from SP to the callee-save registers after initial_adjust. | |
751 | It may be non-zero if no push is used (ie. callee_adjust == 0). */ | |
6a70badb | 752 | poly_int64 callee_offset; |
71bfb77a WD |
753 | |
754 | /* The size of the stack adjustment after saving callee-saves. */ | |
6a70badb | 755 | poly_int64 final_adjust; |
1c960e02 | 756 | |
204d2c03 WD |
757 | /* Store FP,LR and setup a frame pointer. */ |
758 | bool emit_frame_chain; | |
759 | ||
363ffa50 JW |
760 | unsigned wb_candidate1; |
761 | unsigned wb_candidate2; | |
762 | ||
43e9d192 IB |
763 | bool laid_out; |
764 | }; | |
765 | ||
766 | typedef struct GTY (()) machine_function | |
767 | { | |
768 | struct aarch64_frame frame; | |
827ab47a KT |
769 | /* One entry for each hard register. */ |
770 | bool reg_is_wrapped_separately[LAST_SAVED_REGNUM]; | |
43e9d192 IB |
771 | } machine_function; |
772 | #endif | |
773 | ||
17a819cb YZ |
774 | /* Which ABI to use. */ |
775 | enum aarch64_abi_type | |
776 | { | |
777 | AARCH64_ABI_LP64 = 0, | |
778 | AARCH64_ABI_ILP32 = 1 | |
779 | }; | |
780 | ||
781 | #ifndef AARCH64_ABI_DEFAULT | |
782 | #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 | |
783 | #endif | |
784 | ||
785 | #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) | |
43e9d192 | 786 | |
43e9d192 IB |
787 | enum arm_pcs |
788 | { | |
789 | ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ | |
002ffd3c | 790 | ARM_PCS_SIMD, /* For aarch64_vector_pcs functions. */ |
bb6ce448 | 791 | ARM_PCS_TLSDESC, /* For targets of tlsdesc calls. */ |
43e9d192 IB |
792 | ARM_PCS_UNKNOWN |
793 | }; | |
794 | ||
795 | ||
43e9d192 | 796 | |
43e9d192 | 797 | |
ef4bddc2 | 798 | /* We can't use machine_mode inside a generator file because it |
43e9d192 IB |
799 | hasn't been created yet; we shouldn't be using any code that |
800 | needs the real definition though, so this ought to be safe. */ | |
801 | #ifdef GENERATOR_FILE | |
802 | #define MACHMODE int | |
803 | #else | |
804 | #include "insn-modes.h" | |
febd3244 | 805 | #define MACHMODE machine_mode |
43e9d192 IB |
806 | #endif |
807 | ||
febd3244 | 808 | #ifndef USED_FOR_TARGET |
43e9d192 IB |
809 | /* AAPCS related state tracking. */ |
810 | typedef struct | |
811 | { | |
812 | enum arm_pcs pcs_variant; | |
813 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
814 | int aapcs_ncrn; /* Next Core register number. */ | |
815 | int aapcs_nextncrn; /* Next next core register number. */ | |
816 | int aapcs_nvrn; /* Next Vector register number. */ | |
817 | int aapcs_nextnvrn; /* Next Next Vector register number. */ | |
818 | rtx aapcs_reg; /* Register assigned to this argument. This | |
819 | is NULL_RTX if this parameter goes on | |
820 | the stack. */ | |
821 | MACHMODE aapcs_vfp_rmode; | |
822 | int aapcs_stack_words; /* If the argument is passed on the stack, this | |
823 | is the number of words needed, after rounding | |
824 | up. Only meaningful when | |
825 | aapcs_reg == NULL_RTX. */ | |
826 | int aapcs_stack_size; /* The total size (in words, per 8 byte) of the | |
827 | stack arg area so far. */ | |
828 | } CUMULATIVE_ARGS; | |
febd3244 | 829 | #endif |
43e9d192 | 830 | |
43e9d192 | 831 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ |
76b0cbf8 | 832 | (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) |
43e9d192 IB |
833 | |
834 | #define PAD_VARARGS_DOWN 0 | |
835 | ||
836 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
837 | aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) | |
838 | ||
839 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
840 | aarch64_function_arg_regno_p(REGNO) | |
841 | \f | |
842 | ||
843 | /* ISA Features. */ | |
844 | ||
845 | /* Addressing modes, etc. */ | |
846 | #define HAVE_POST_INCREMENT 1 | |
847 | #define HAVE_PRE_INCREMENT 1 | |
848 | #define HAVE_POST_DECREMENT 1 | |
849 | #define HAVE_PRE_DECREMENT 1 | |
850 | #define HAVE_POST_MODIFY_DISP 1 | |
851 | #define HAVE_PRE_MODIFY_DISP 1 | |
852 | ||
853 | #define MAX_REGS_PER_ADDRESS 2 | |
854 | ||
855 | #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) | |
856 | ||
43e9d192 IB |
857 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
858 | aarch64_regno_ok_for_base_p (REGNO, true) | |
859 | ||
860 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
861 | aarch64_regno_ok_for_index_p (REGNO, true) | |
862 | ||
863 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
864 | aarch64_legitimate_pic_operand_p (X) | |
865 | ||
866 | #define CASE_VECTOR_MODE Pmode | |
867 | ||
868 | #define DEFAULT_SIGNED_CHAR 0 | |
869 | ||
870 | /* An integer expression for the size in bits of the largest integer machine | |
871 | mode that should actually be used. We allow pairs of registers. */ | |
872 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
873 | ||
874 | /* Maximum bytes moved by a single instruction (load/store pair). */ | |
875 | #define MOVE_MAX (UNITS_PER_WORD * 2) | |
876 | ||
877 | /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ | |
878 | #define AARCH64_CALL_RATIO 8 | |
879 | ||
e2c75eea JG |
880 | /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. |
881 | move_by_pieces will continually copy the largest safe chunks. So a | |
882 | 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient | |
76715c32 | 883 | for both size and speed of copy, so we will instead use the "cpymem" |
e2c75eea JG |
884 | standard name to implement the copy. This logic does not apply when |
885 | targeting -mstrict-align, so keep a sensible default in that case. */ | |
43e9d192 | 886 | #define MOVE_RATIO(speed) \ |
e2c75eea | 887 | (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) |
43e9d192 IB |
888 | |
889 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate | |
890 | of the length of a memset call, but use the default otherwise. */ | |
891 | #define CLEAR_RATIO(speed) \ | |
892 | ((speed) ? 15 : AARCH64_CALL_RATIO) | |
893 | ||
894 | /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
895 | optimizing for size adjust the ratio to account for the overhead of loading | |
896 | the constant. */ | |
897 | #define SET_RATIO(speed) \ | |
898 | ((speed) ? 15 : AARCH64_CALL_RATIO - 2) | |
899 | ||
43e9d192 IB |
900 | /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is |
901 | rarely a good idea in straight-line code since it adds an extra address | |
902 | dependency between each instruction. Better to use incrementing offsets. */ | |
903 | #define USE_LOAD_POST_INCREMENT(MODE) 0 | |
904 | #define USE_LOAD_POST_DECREMENT(MODE) 0 | |
905 | #define USE_LOAD_PRE_INCREMENT(MODE) 0 | |
906 | #define USE_LOAD_PRE_DECREMENT(MODE) 0 | |
907 | #define USE_STORE_POST_INCREMENT(MODE) 0 | |
908 | #define USE_STORE_POST_DECREMENT(MODE) 0 | |
909 | #define USE_STORE_PRE_INCREMENT(MODE) 0 | |
910 | #define USE_STORE_PRE_DECREMENT(MODE) 0 | |
911 | ||
56c9ef5f KT |
912 | /* WORD_REGISTER_OPERATIONS does not hold for AArch64. |
913 | The assigned word_mode is DImode but operations narrower than SImode | |
914 | behave as 32-bit operations if using the W-form of the registers rather | |
915 | than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS | |
916 | expects. */ | |
917 | #define WORD_REGISTER_OPERATIONS 0 | |
43e9d192 IB |
918 | |
919 | /* Define if loading from memory in MODE, an integral mode narrower than | |
920 | BITS_PER_WORD will either zero-extend or sign-extend. The value of this | |
921 | macro should be the code that says which one of the two operations is | |
922 | implicitly done, or UNKNOWN if none. */ | |
923 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
924 | ||
925 | /* Define this macro to be non-zero if instructions will fail to work | |
926 | if given data not on the nominal alignment. */ | |
927 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN | |
928 | ||
929 | /* Define this macro to be non-zero if accessing less than a word of | |
930 | memory is no faster than accessing a word of memory, i.e., if such | |
931 | accesses require more than one instruction or if there is no | |
932 | difference in cost. | |
933 | Although there's no difference in instruction count or cycles, | |
934 | in AArch64 we don't want to expand to a sub-word to a 64-bit access | |
935 | if we don't have to, for power-saving reasons. */ | |
936 | #define SLOW_BYTE_ACCESS 0 | |
937 | ||
43e9d192 IB |
938 | #define NO_FUNCTION_CSE 1 |
939 | ||
17a819cb YZ |
940 | /* Specify the machine mode that the hardware addresses have. |
941 | After generation of rtl, the compiler makes no further distinction | |
942 | between pointers and any other objects of this machine mode. */ | |
43e9d192 | 943 | #define Pmode DImode |
17a819cb YZ |
944 | |
945 | /* A C expression whose value is zero if pointers that need to be extended | |
946 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
947 | greater then zero if they are zero-extended and less then zero if the | |
948 | ptr_extend instruction should be used. */ | |
949 | #define POINTERS_EXTEND_UNSIGNED 1 | |
950 | ||
951 | /* Mode of a function address in a call instruction (for indexing purposes). */ | |
43e9d192 IB |
952 | #define FUNCTION_MODE Pmode |
953 | ||
954 | #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) | |
955 | ||
f8bf91ab N |
956 | #define REVERSIBLE_CC_MODE(MODE) 1 |
957 | ||
43e9d192 IB |
958 | #define REVERSE_CONDITION(CODE, MODE) \ |
959 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
960 | ? reverse_condition_maybe_unordered (CODE) \ | |
961 | : reverse_condition (CODE)) | |
962 | ||
963 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
952e7819 | 964 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
43e9d192 | 965 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
952e7819 | 966 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
43e9d192 IB |
967 | |
968 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) | |
969 | ||
970 | #define RETURN_ADDR_RTX aarch64_return_addr | |
971 | ||
b5f794b4 | 972 | /* BTI c + 3 insns + 2 pointer-sized entries. */ |
28514dda | 973 | #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) |
43e9d192 IB |
974 | |
975 | /* Trampolines contain dwords, so must be dword aligned. */ | |
976 | #define TRAMPOLINE_ALIGNMENT 64 | |
977 | ||
978 | /* Put trampolines in the text section so that mapping symbols work | |
979 | correctly. */ | |
980 | #define TRAMPOLINE_SECTION text_section | |
43e9d192 IB |
981 | |
982 | /* To start with. */ | |
b9066f5a MW |
983 | #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ |
984 | (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) | |
43e9d192 IB |
985 | \f |
986 | ||
987 | /* Assembly output. */ | |
988 | ||
989 | /* For now we'll make all jump tables pc-relative. */ | |
990 | #define CASE_VECTOR_PC_RELATIVE 1 | |
991 | ||
992 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
993 | ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ | |
994 | : (min < -0x1f0 || max > 0x1f0) ? HImode \ | |
995 | : QImode) | |
996 | ||
997 | /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ | |
998 | #define ADDR_VEC_ALIGN(JUMPTABLE) 0 | |
999 | ||
92d649c4 VK |
1000 | #define MCOUNT_NAME "_mcount" |
1001 | ||
1002 | #define NO_PROFILE_COUNTERS 1 | |
1003 | ||
1004 | /* Emit rtl for profiling. Output assembler code to FILE | |
1005 | to call "_mcount" for profiling a function entry. */ | |
3294102b MS |
1006 | #define PROFILE_HOOK(LABEL) \ |
1007 | { \ | |
1008 | rtx fun, lr; \ | |
1009 | lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ | |
1010 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ | |
db69559b | 1011 | emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \ |
3294102b | 1012 | } |
92d649c4 VK |
1013 | |
1014 | /* All the work done in PROFILE_HOOK, but still required. */ | |
1015 | #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) | |
43e9d192 IB |
1016 | |
1017 | /* For some reason, the Linux headers think they know how to define | |
1018 | these macros. They don't!!! */ | |
1019 | #undef ASM_APP_ON | |
1020 | #undef ASM_APP_OFF | |
1021 | #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" | |
1022 | #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" | |
1023 | ||
43e9d192 IB |
1024 | #define CONSTANT_POOL_BEFORE_FUNCTION 0 |
1025 | ||
1026 | /* This definition should be relocated to aarch64-elf-raw.h. This macro | |
1027 | should be undefined in aarch64-linux.h and a clear_cache pattern | |
1028 | implmented to emit either the call to __aarch64_sync_cache_range() | |
1029 | directly or preferably the appropriate sycall or cache clear | |
1030 | instructions inline. */ | |
1031 | #define CLEAR_INSN_CACHE(beg, end) \ | |
1032 | extern void __aarch64_sync_cache_range (void *, void *); \ | |
1033 | __aarch64_sync_cache_range (beg, end) | |
1034 | ||
e6bd9fb9 | 1035 | #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) |
43e9d192 | 1036 | |
73d9ac6a IB |
1037 | /* Choose appropriate mode for caller saves, so we do the minimum |
1038 | required size of load/store. */ | |
1039 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
1040 | aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) | |
1041 | ||
d78006d9 KT |
1042 | #undef SWITCHABLE_TARGET |
1043 | #define SWITCHABLE_TARGET 1 | |
1044 | ||
43e9d192 IB |
1045 | /* Check TLS Descriptors mechanism is selected. */ |
1046 | #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) | |
1047 | ||
1048 | extern enum aarch64_code_model aarch64_cmodel; | |
1049 | ||
1050 | /* When using the tiny addressing model conditional and unconditional branches | |
1051 | can span the whole of the available address space (1MB). */ | |
1052 | #define HAS_LONG_COND_BRANCH \ | |
1053 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
1054 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
1055 | ||
1056 | #define HAS_LONG_UNCOND_BRANCH \ | |
1057 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
1058 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
1059 | ||
2ca5b430 KT |
1060 | #define TARGET_SUPPORTS_WIDE_INT 1 |
1061 | ||
635e66fe AL |
1062 | /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ |
1063 | #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ | |
1064 | ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ | |
1065 | || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ | |
1066 | || (MODE) == DFmode) | |
1067 | ||
43e9d192 IB |
1068 | /* Modes valid for AdvSIMD Q registers. */ |
1069 | #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ | |
1070 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
71a11456 AL |
1071 | || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ |
1072 | || (MODE) == V2DFmode) | |
43e9d192 | 1073 | |
7ac29c0f RS |
1074 | #define ENDIAN_LANE_N(NUNITS, N) \ |
1075 | (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) | |
e58bf20a | 1076 | |
9815fafa RE |
1077 | /* Support for a configure-time default CPU, etc. We currently support |
1078 | --with-arch and --with-cpu. Both are ignored if either is specified | |
1079 | explicitly on the command line at run time. */ | |
1080 | #define OPTION_DEFAULT_SPECS \ | |
1081 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
1082 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, | |
1083 | ||
054b4005 JG |
1084 | #define MCPU_TO_MARCH_SPEC \ |
1085 | " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" | |
682287fb JG |
1086 | |
1087 | extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); | |
054b4005 | 1088 | #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ |
682287fb JG |
1089 | { "rewrite_mcpu", aarch64_rewrite_mcpu }, |
1090 | ||
7e1bcce3 KT |
1091 | #if defined(__aarch64__) |
1092 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
a08b5429 | 1093 | #define HAVE_LOCAL_CPU_DETECT |
7e1bcce3 KT |
1094 | # define EXTRA_SPEC_FUNCTIONS \ |
1095 | { "local_cpu_detect", host_detect_local_cpu }, \ | |
054b4005 | 1096 | MCPU_TO_MARCH_SPEC_FUNCTIONS |
7e1bcce3 KT |
1097 | |
1098 | # define MCPU_MTUNE_NATIVE_SPECS \ | |
1099 | " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ | |
1100 | " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ | |
1101 | " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
1102 | #else | |
1103 | # define MCPU_MTUNE_NATIVE_SPECS "" | |
054b4005 | 1104 | # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS |
7e1bcce3 KT |
1105 | #endif |
1106 | ||
682287fb | 1107 | #define ASM_CPU_SPEC \ |
054b4005 | 1108 | MCPU_TO_MARCH_SPEC |
682287fb | 1109 | |
682287fb JG |
1110 | #define EXTRA_SPECS \ |
1111 | { "asm_cpu_spec", ASM_CPU_SPEC } | |
1112 | ||
5fca7b66 RH |
1113 | #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue |
1114 | ||
1b62ed4f JG |
1115 | /* This type is the user-visible __fp16, and a pointer to that type. We |
1116 | need it in many places in the backend. Defined in aarch64-builtins.c. */ | |
1117 | extern tree aarch64_fp16_type_node; | |
1118 | extern tree aarch64_fp16_ptr_type_node; | |
1119 | ||
817221cc WD |
1120 | /* The generic unwind code in libgcc does not initialize the frame pointer. |
1121 | So in order to unwind a function using a frame pointer, the very first | |
1122 | function that is unwound must save the frame pointer. That way the frame | |
1123 | pointer is restored and its value is now valid - otherwise _Unwind_GetGR | |
1124 | crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ | |
1125 | #define LIBGCC2_UNWIND_ATTRIBUTE \ | |
1126 | __attribute__((optimize ("no-omit-frame-pointer"))) | |
1127 | ||
43cacb12 RS |
1128 | #ifndef USED_FOR_TARGET |
1129 | extern poly_uint16 aarch64_sve_vg; | |
1130 | ||
1131 | /* The number of bits and bytes in an SVE vector. */ | |
1132 | #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64)) | |
1133 | #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8)) | |
1134 | ||
1135 | /* The number of bytes in an SVE predicate. */ | |
1136 | #define BYTES_PER_SVE_PRED aarch64_sve_vg | |
1137 | ||
1138 | /* The SVE mode for a vector of bytes. */ | |
1139 | #define SVE_BYTE_MODE VNx16QImode | |
1140 | ||
1141 | /* The maximum number of bytes in a fixed-size vector. This is 256 bytes | |
1142 | (for -msve-vector-bits=2048) multiplied by the maximum number of | |
1143 | vectors in a structure mode (4). | |
1144 | ||
1145 | This limit must not be used for variable-size vectors, since | |
1146 | VL-agnostic code must work with arbitary vector lengths. */ | |
1147 | #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4) | |
1148 | #endif | |
1149 | ||
1150 | #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE) | |
1151 | ||
8c6e3b23 TC |
1152 | /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the |
1153 | outgoing arguments if stack clash protection is enabled. This is essential | |
1154 | as the extra arg space allows us to skip a check in alloca. */ | |
1155 | #undef STACK_DYNAMIC_OFFSET | |
1156 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
1157 | ((flag_stack_clash_protection \ | |
1158 | && cfun->calls_alloca \ | |
1159 | && known_lt (crtl->outgoing_args_size, \ | |
1160 | STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \ | |
1161 | ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \ | |
1162 | STACK_BOUNDARY / BITS_PER_UNIT) \ | |
1163 | : (crtl->outgoing_args_size + STACK_POINTER_OFFSET)) | |
1164 | ||
43e9d192 | 1165 | #endif /* GCC_AARCH64_H */ |