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43e9d192 | 1 | /* Machine description for AArch64 architecture. |
5624e564 | 2 | Copyright (C) 2009-2015 Free Software Foundation, Inc. |
43e9d192 IB |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but | |
13 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | #ifndef GCC_AARCH64_H | |
23 | #define GCC_AARCH64_H | |
24 | ||
25 | /* Target CPU builtins. */ | |
e4ea20c8 KT |
26 | #define TARGET_CPU_CPP_BUILTINS() \ |
27 | aarch64_cpu_cpp_builtins (pfile) | |
43e9d192 IB |
28 | |
29 | \f | |
30 | ||
e4ea20c8 KT |
31 | #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () |
32 | ||
43e9d192 IB |
33 | /* Target machine storage layout. */ |
34 | ||
35 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
36 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
37 | && GET_MODE_SIZE (MODE) < 4) \ | |
38 | { \ | |
39 | if (MODE == QImode || MODE == HImode) \ | |
40 | { \ | |
41 | MODE = SImode; \ | |
42 | } \ | |
43 | } | |
44 | ||
45 | /* Bits are always numbered from the LSBit. */ | |
46 | #define BITS_BIG_ENDIAN 0 | |
47 | ||
48 | /* Big/little-endian flavour. */ | |
49 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) | |
50 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
51 | ||
52 | /* AdvSIMD is supported in the default configuration, unless disabled by | |
683e3333 KT |
53 | -mgeneral-regs-only or by the +nosimd extension. */ |
54 | #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) | |
55 | #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) | |
43e9d192 IB |
56 | |
57 | #define UNITS_PER_WORD 8 | |
58 | ||
59 | #define UNITS_PER_VREG 16 | |
60 | ||
61 | #define PARM_BOUNDARY 64 | |
62 | ||
63 | #define STACK_BOUNDARY 128 | |
64 | ||
65 | #define FUNCTION_BOUNDARY 32 | |
66 | ||
67 | #define EMPTY_FIELD_BOUNDARY 32 | |
68 | ||
69 | #define BIGGEST_ALIGNMENT 128 | |
70 | ||
71 | #define SHORT_TYPE_SIZE 16 | |
72 | ||
73 | #define INT_TYPE_SIZE 32 | |
74 | ||
17a819cb YZ |
75 | #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) |
76 | ||
77 | #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) | |
43e9d192 IB |
78 | |
79 | #define LONG_LONG_TYPE_SIZE 64 | |
80 | ||
81 | #define FLOAT_TYPE_SIZE 32 | |
82 | ||
83 | #define DOUBLE_TYPE_SIZE 64 | |
84 | ||
85 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
86 | ||
87 | /* The architecture reserves all bits of the address for hardware use, | |
88 | so the vbit must go into the delta field of pointers to member | |
89 | functions. This is the same config as that in the AArch32 | |
90 | port. */ | |
91 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
92 | ||
93 | /* Make strings word-aligned so that strcpy from constants will be | |
94 | faster. */ | |
95 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
96 | ((TREE_CODE (EXP) == STRING_CST \ | |
97 | && !optimize_size \ | |
98 | && (ALIGN) < BITS_PER_WORD) \ | |
99 | ? BITS_PER_WORD : ALIGN) | |
100 | ||
101 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
102 | ((((ALIGN) < BITS_PER_WORD) \ | |
103 | && (TREE_CODE (EXP) == ARRAY_TYPE \ | |
104 | || TREE_CODE (EXP) == UNION_TYPE \ | |
105 | || TREE_CODE (EXP) == RECORD_TYPE)) \ | |
106 | ? BITS_PER_WORD : (ALIGN)) | |
107 | ||
108 | #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) | |
109 | ||
110 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
111 | ||
112 | /* Defined by the ABI */ | |
113 | #define WCHAR_TYPE "unsigned int" | |
114 | #define WCHAR_TYPE_SIZE 32 | |
115 | ||
116 | /* Using long long breaks -ansi and -std=c90, so these will need to be | |
117 | made conditional for an LLP64 ABI. */ | |
118 | ||
119 | #define SIZE_TYPE "long unsigned int" | |
120 | ||
121 | #define PTRDIFF_TYPE "long int" | |
122 | ||
123 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
124 | ||
0c6caaf8 RL |
125 | /* Major revision number of the ARM Architecture implemented by the target. */ |
126 | extern unsigned aarch64_architecture_version; | |
43e9d192 IB |
127 | |
128 | /* Instruction tuning/selection flags. */ | |
129 | ||
130 | /* Bit values used to identify processor capabilities. */ | |
131 | #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ | |
132 | #define AARCH64_FL_FP (1 << 1) /* Has FP. */ | |
133 | #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ | |
95f99170 | 134 | #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ |
ff09c88d | 135 | /* ARMv8.1 architecture extensions. */ |
dfba575f JG |
136 | #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ |
137 | #define AARCH64_FL_PAN (1 << 5) /* Has Privileged Access Never. */ | |
138 | #define AARCH64_FL_LOR (1 << 6) /* Has Limited Ordering regions. */ | |
139 | #define AARCH64_FL_RDMA (1 << 7) /* Has ARMv8.1 Adv.SIMD. */ | |
43e9d192 IB |
140 | |
141 | /* Has FP and SIMD. */ | |
142 | #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) | |
143 | ||
144 | /* Has FP without SIMD. */ | |
145 | #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) | |
146 | ||
147 | /* Architecture flags that effect instruction selection. */ | |
148 | #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) | |
ff09c88d MW |
149 | #define AARCH64_FL_FOR_ARCH8_1 \ |
150 | (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_PAN \ | |
151 | | AARCH64_FL_LOR | AARCH64_FL_RDMA) | |
43e9d192 IB |
152 | |
153 | /* Macros to test ISA flags. */ | |
361fb3ee | 154 | |
5922847b | 155 | #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) |
43e9d192 IB |
156 | #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) |
157 | #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) | |
158 | #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) | |
045c2d32 | 159 | #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) |
43e9d192 | 160 | |
683e3333 KT |
161 | /* Crypto is an optional extension to AdvSIMD. */ |
162 | #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) | |
43e9d192 | 163 | |
5d357f26 KT |
164 | /* CRC instructions that can be enabled through +crc arch extension. */ |
165 | #define TARGET_CRC32 (AARCH64_ISA_CRC) | |
166 | ||
045c2d32 MW |
167 | /* Atomic instructions that can be enabled through the +lse extension. */ |
168 | #define TARGET_LSE (AARCH64_ISA_LSE) | |
169 | ||
b32c1043 KT |
170 | /* Make sure this is always defined so we don't have to check for ifdefs |
171 | but rather use normal ifs. */ | |
172 | #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT | |
173 | #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 | |
174 | #else | |
175 | #undef TARGET_FIX_ERR_A53_835769_DEFAULT | |
176 | #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 | |
177 | #endif | |
178 | ||
179 | /* Apply the workaround for Cortex-A53 erratum 835769. */ | |
180 | #define TARGET_FIX_ERR_A53_835769 \ | |
181 | ((aarch64_fix_a53_err835769 == 2) \ | |
182 | ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) | |
183 | ||
43e9d192 IB |
184 | /* Standard register usage. */ |
185 | ||
186 | /* 31 64-bit general purpose registers R0-R30: | |
187 | R30 LR (link register) | |
188 | R29 FP (frame pointer) | |
189 | R19-R28 Callee-saved registers | |
190 | R18 The platform register; use as temporary register. | |
191 | R17 IP1 The second intra-procedure-call temporary register | |
192 | (can be used by call veneers and PLT code); otherwise use | |
193 | as a temporary register | |
194 | R16 IP0 The first intra-procedure-call temporary register (can | |
195 | be used by call veneers and PLT code); otherwise use as a | |
196 | temporary register | |
197 | R9-R15 Temporary registers | |
198 | R8 Structure value parameter / temporary register | |
199 | R0-R7 Parameter/result registers | |
200 | ||
201 | SP stack pointer, encoded as X/R31 where permitted. | |
202 | ZR zero register, encoded as X/R31 elsewhere | |
203 | ||
204 | 32 x 128-bit floating-point/vector registers | |
205 | V16-V31 Caller-saved (temporary) registers | |
206 | V8-V15 Callee-saved registers | |
207 | V0-V7 Parameter/result registers | |
208 | ||
209 | The vector register V0 holds scalar B0, H0, S0 and D0 in its least | |
210 | significant bits. Unlike AArch32 S1 is not packed into D0, | |
211 | etc. */ | |
212 | ||
213 | /* Note that we don't mark X30 as a call-clobbered register. The idea is | |
214 | that it's really the call instructions themselves which clobber X30. | |
215 | We don't care what the called function does with it afterwards. | |
216 | ||
217 | This approach makes it easier to implement sibcalls. Unlike normal | |
218 | calls, sibcalls don't clobber X30, so the register reaches the | |
219 | called function intact. EPILOGUE_USES says that X30 is useful | |
220 | to the called function. */ | |
221 | ||
222 | #define FIXED_REGISTERS \ | |
223 | { \ | |
224 | 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ | |
225 | 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ | |
226 | 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
227 | 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ | |
228 | 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ | |
229 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
230 | 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ | |
231 | 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ | |
232 | 1, 1, 1, /* SFP, AP, CC */ \ | |
233 | } | |
234 | ||
235 | #define CALL_USED_REGISTERS \ | |
236 | { \ | |
237 | 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ | |
238 | 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ | |
239 | 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
1c923b60 | 240 | 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ |
43e9d192 IB |
241 | 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ |
242 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
243 | 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ | |
244 | 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ | |
245 | 1, 1, 1, /* SFP, AP, CC */ \ | |
246 | } | |
247 | ||
248 | #define REGISTER_NAMES \ | |
249 | { \ | |
250 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ | |
251 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ | |
252 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ | |
253 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ | |
254 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ | |
255 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ | |
256 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ | |
257 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ | |
258 | "sfp", "ap", "cc", \ | |
259 | } | |
260 | ||
261 | /* Generate the register aliases for core register N */ | |
262 | #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ | |
263 | {"w" # N, R0_REGNUM + (N)} | |
264 | ||
265 | #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ | |
266 | {"d" # N, V0_REGNUM + (N)}, \ | |
267 | {"s" # N, V0_REGNUM + (N)}, \ | |
268 | {"h" # N, V0_REGNUM + (N)}, \ | |
269 | {"b" # N, V0_REGNUM + (N)} | |
270 | ||
271 | /* Provide aliases for all of the ISA defined register name forms. | |
272 | These aliases are convenient for use in the clobber lists of inline | |
273 | asm statements. */ | |
274 | ||
275 | #define ADDITIONAL_REGISTER_NAMES \ | |
276 | { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ | |
277 | R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ | |
278 | R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ | |
279 | R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ | |
280 | R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ | |
281 | R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ | |
282 | R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ | |
9259db42 | 283 | R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ |
43e9d192 IB |
284 | V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ |
285 | V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ | |
286 | V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ | |
287 | V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ | |
288 | V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ | |
289 | V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ | |
290 | V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ | |
291 | V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ | |
292 | } | |
293 | ||
294 | /* Say that the epilogue uses the return address register. Note that | |
295 | in the case of sibcalls, the values "used by the epilogue" are | |
296 | considered live at the start of the called function. */ | |
297 | ||
298 | #define EPILOGUE_USES(REGNO) \ | |
1c923b60 | 299 | (epilogue_completed && (REGNO) == LR_REGNUM) |
43e9d192 IB |
300 | |
301 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
302 | the stack pointer does not matter. The value is tested only in | |
303 | functions that have frame pointers. */ | |
304 | #define EXIT_IGNORE_STACK 1 | |
305 | ||
306 | #define STATIC_CHAIN_REGNUM R18_REGNUM | |
307 | #define HARD_FRAME_POINTER_REGNUM R29_REGNUM | |
308 | #define FRAME_POINTER_REGNUM SFP_REGNUM | |
309 | #define STACK_POINTER_REGNUM SP_REGNUM | |
310 | #define ARG_POINTER_REGNUM AP_REGNUM | |
311 | #define FIRST_PSEUDO_REGISTER 67 | |
312 | ||
313 | /* The number of (integer) argument register available. */ | |
314 | #define NUM_ARG_REGS 8 | |
315 | #define NUM_FP_ARG_REGS 8 | |
316 | ||
317 | /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most | |
318 | four members. */ | |
319 | #define HA_MAX_NUM_FLDS 4 | |
320 | ||
321 | /* External dwarf register number scheme. These number are used to | |
322 | identify registers in dwarf debug information, the values are | |
323 | defined by the AArch64 ABI. The numbering scheme is independent of | |
324 | GCC's internal register numbering scheme. */ | |
325 | ||
326 | #define AARCH64_DWARF_R0 0 | |
327 | ||
328 | /* The number of R registers, note 31! not 32. */ | |
329 | #define AARCH64_DWARF_NUMBER_R 31 | |
330 | ||
331 | #define AARCH64_DWARF_SP 31 | |
332 | #define AARCH64_DWARF_V0 64 | |
333 | ||
334 | /* The number of V registers. */ | |
335 | #define AARCH64_DWARF_NUMBER_V 32 | |
336 | ||
337 | /* For signal frames we need to use an alternative return column. This | |
338 | value must not correspond to a hard register and must be out of the | |
339 | range of DWARF_FRAME_REGNUM(). */ | |
340 | #define DWARF_ALT_FRAME_RETURN_COLUMN \ | |
341 | (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) | |
342 | ||
343 | /* We add 1 extra frame register for use as the | |
344 | DWARF_ALT_FRAME_RETURN_COLUMN. */ | |
345 | #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) | |
346 | ||
347 | ||
348 | #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) | |
349 | /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders | |
350 | can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same | |
351 | as the default definition in dwarf2out.c. */ | |
352 | #undef DWARF_FRAME_REGNUM | |
353 | #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) | |
354 | ||
355 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
356 | ||
357 | #define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE) | |
358 | ||
359 | #define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE) | |
360 | ||
97e1ad78 | 361 | #define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2) |
43e9d192 IB |
362 | |
363 | #define DWARF2_UNWIND_INFO 1 | |
364 | ||
365 | /* Use R0 through R3 to pass exception handling information. */ | |
366 | #define EH_RETURN_DATA_REGNO(N) \ | |
367 | ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) | |
368 | ||
369 | /* Select a format to encode pointers in exception handling data. */ | |
370 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
371 | aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) | |
372 | ||
361fb3ee KT |
373 | /* Output the assembly strings we want to add to a function definition. */ |
374 | #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ | |
375 | aarch64_declare_function_name (STR, NAME, DECL) | |
376 | ||
43e9d192 IB |
377 | /* The register that holds the return address in exception handlers. */ |
378 | #define AARCH64_EH_STACKADJ_REGNUM (R0_REGNUM + 4) | |
379 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM) | |
380 | ||
381 | /* Don't use __builtin_setjmp until we've defined it. */ | |
382 | #undef DONT_USE_BUILTIN_SETJMP | |
383 | #define DONT_USE_BUILTIN_SETJMP 1 | |
384 | ||
385 | /* Register in which the structure value is to be returned. */ | |
386 | #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM | |
387 | ||
388 | /* Non-zero if REGNO is part of the Core register set. | |
389 | ||
390 | The rather unusual way of expressing this check is to avoid | |
391 | warnings when building the compiler when R0_REGNUM is 0 and REGNO | |
392 | is unsigned. */ | |
393 | #define GP_REGNUM_P(REGNO) \ | |
394 | (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) | |
395 | ||
396 | #define FP_REGNUM_P(REGNO) \ | |
397 | (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) | |
398 | ||
399 | #define FP_LO_REGNUM_P(REGNO) \ | |
400 | (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) | |
401 | ||
402 | \f | |
403 | /* Register and constant classes. */ | |
404 | ||
405 | enum reg_class | |
406 | { | |
407 | NO_REGS, | |
43e06d03 | 408 | FIXED_REG0, |
fee9ba42 | 409 | CALLER_SAVE_REGS, |
43e9d192 IB |
410 | GENERAL_REGS, |
411 | STACK_REG, | |
412 | POINTER_REGS, | |
413 | FP_LO_REGS, | |
414 | FP_REGS, | |
415 | ALL_REGS, | |
416 | LIM_REG_CLASSES /* Last */ | |
417 | }; | |
418 | ||
419 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
420 | ||
421 | #define REG_CLASS_NAMES \ | |
422 | { \ | |
423 | "NO_REGS", \ | |
739a838e | 424 | "FIXED_REG0", \ |
fee9ba42 | 425 | "CALLER_SAVE_REGS", \ |
43e9d192 IB |
426 | "GENERAL_REGS", \ |
427 | "STACK_REG", \ | |
428 | "POINTER_REGS", \ | |
429 | "FP_LO_REGS", \ | |
430 | "FP_REGS", \ | |
431 | "ALL_REGS" \ | |
432 | } | |
433 | ||
434 | #define REG_CLASS_CONTENTS \ | |
435 | { \ | |
436 | { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
43e06d03 | 437 | { 0x00000001, 0x00000000, 0x00000000 }, /* FIXED_REG0 */ \ |
fee9ba42 | 438 | { 0x0007ffff, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ |
43e9d192 IB |
439 | { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ |
440 | { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
441 | { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ | |
442 | { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ | |
443 | { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ | |
444 | { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ | |
445 | } | |
446 | ||
447 | #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) | |
448 | ||
a4a182c6 | 449 | #define INDEX_REG_CLASS GENERAL_REGS |
43e9d192 IB |
450 | #define BASE_REG_CLASS POINTER_REGS |
451 | ||
6991c977 | 452 | /* Register pairs used to eliminate unneeded registers that point into |
43e9d192 IB |
453 | the stack frame. */ |
454 | #define ELIMINABLE_REGS \ | |
455 | { \ | |
456 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
457 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
458 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
459 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
460 | } | |
461 | ||
462 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
463 | (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) | |
464 | ||
465 | /* CPU/ARCH option handling. */ | |
466 | #include "config/aarch64/aarch64-opts.h" | |
467 | ||
468 | enum target_cpus | |
469 | { | |
7e1bcce3 | 470 | #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \ |
192ed1dd | 471 | TARGET_CPU_##INTERNAL_IDENT, |
43e9d192 IB |
472 | #include "aarch64-cores.def" |
473 | #undef AARCH64_CORE | |
474 | TARGET_CPU_generic | |
475 | }; | |
476 | ||
a3cd0246 | 477 | /* If there is no CPU defined at configure, use generic as default. */ |
43e9d192 IB |
478 | #ifndef TARGET_CPU_DEFAULT |
479 | #define TARGET_CPU_DEFAULT \ | |
a3cd0246 | 480 | (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) |
43e9d192 IB |
481 | #endif |
482 | ||
75cf1494 KT |
483 | /* If inserting NOP before a mult-accumulate insn remember to adjust the |
484 | length so that conditional branching code is updated appropriately. */ | |
485 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
8baff86e KT |
486 | do \ |
487 | { \ | |
488 | if (aarch64_madd_needs_nop (insn)) \ | |
489 | length += 4; \ | |
490 | } while (0) | |
75cf1494 KT |
491 | |
492 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
493 | aarch64_final_prescan_insn (INSN); \ | |
494 | ||
43e9d192 IB |
495 | /* The processor for which instructions should be scheduled. */ |
496 | extern enum aarch64_processor aarch64_tune; | |
497 | ||
498 | /* RTL generation support. */ | |
499 | #define INIT_EXPANDERS aarch64_init_expanders () | |
500 | \f | |
501 | ||
502 | /* Stack layout; function entry, exit and calling. */ | |
503 | #define STACK_GROWS_DOWNWARD 1 | |
504 | ||
6991c977 | 505 | #define FRAME_GROWS_DOWNWARD 1 |
43e9d192 IB |
506 | |
507 | #define STARTING_FRAME_OFFSET 0 | |
508 | ||
509 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
510 | ||
511 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
512 | ||
513 | /* Fix for VFP */ | |
514 | #define LIBCALL_VALUE(MODE) \ | |
515 | gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) | |
516 | ||
517 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
518 | ||
519 | #define AARCH64_ROUND_UP(X, ALIGNMENT) \ | |
520 | (((X) + ((ALIGNMENT) - 1)) & ~((ALIGNMENT) - 1)) | |
521 | ||
522 | #define AARCH64_ROUND_DOWN(X, ALIGNMENT) \ | |
523 | ((X) & ~((ALIGNMENT) - 1)) | |
524 | ||
525 | #ifdef HOST_WIDE_INT | |
526 | struct GTY (()) aarch64_frame | |
527 | { | |
528 | HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; | |
8799637a MS |
529 | |
530 | /* The number of extra stack bytes taken up by register varargs. | |
531 | This area is allocated by the callee at the very top of the | |
532 | frame. This value is rounded up to a multiple of | |
533 | STACK_BOUNDARY. */ | |
534 | HOST_WIDE_INT saved_varargs_size; | |
535 | ||
43e9d192 IB |
536 | HOST_WIDE_INT saved_regs_size; |
537 | /* Padding if needed after the all the callee save registers have | |
538 | been saved. */ | |
539 | HOST_WIDE_INT padding0; | |
540 | HOST_WIDE_INT hardfp_offset; /* HARD_FRAME_POINTER_REGNUM */ | |
43e9d192 | 541 | |
1c960e02 MS |
542 | /* Offset from the base of the frame (incomming SP) to the |
543 | hard_frame_pointer. This value is always a multiple of | |
544 | STACK_BOUNDARY. */ | |
545 | HOST_WIDE_INT hard_fp_offset; | |
546 | ||
547 | /* The size of the frame. This value is the offset from base of the | |
548 | * frame (incomming SP) to the stack_pointer. This value is always | |
549 | * a multiple of STACK_BOUNDARY. */ | |
550 | ||
363ffa50 JW |
551 | unsigned wb_candidate1; |
552 | unsigned wb_candidate2; | |
553 | ||
1c960e02 MS |
554 | HOST_WIDE_INT frame_size; |
555 | ||
43e9d192 IB |
556 | bool laid_out; |
557 | }; | |
558 | ||
559 | typedef struct GTY (()) machine_function | |
560 | { | |
561 | struct aarch64_frame frame; | |
43e9d192 IB |
562 | } machine_function; |
563 | #endif | |
564 | ||
17a819cb YZ |
565 | /* Which ABI to use. */ |
566 | enum aarch64_abi_type | |
567 | { | |
568 | AARCH64_ABI_LP64 = 0, | |
569 | AARCH64_ABI_ILP32 = 1 | |
570 | }; | |
571 | ||
572 | #ifndef AARCH64_ABI_DEFAULT | |
573 | #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 | |
574 | #endif | |
575 | ||
576 | #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) | |
43e9d192 | 577 | |
43e9d192 IB |
578 | enum arm_pcs |
579 | { | |
580 | ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ | |
581 | ARM_PCS_UNKNOWN | |
582 | }; | |
583 | ||
584 | ||
43e9d192 | 585 | |
43e9d192 | 586 | |
ef4bddc2 | 587 | /* We can't use machine_mode inside a generator file because it |
43e9d192 IB |
588 | hasn't been created yet; we shouldn't be using any code that |
589 | needs the real definition though, so this ought to be safe. */ | |
590 | #ifdef GENERATOR_FILE | |
591 | #define MACHMODE int | |
592 | #else | |
593 | #include "insn-modes.h" | |
febd3244 | 594 | #define MACHMODE machine_mode |
43e9d192 IB |
595 | #endif |
596 | ||
febd3244 | 597 | #ifndef USED_FOR_TARGET |
43e9d192 IB |
598 | /* AAPCS related state tracking. */ |
599 | typedef struct | |
600 | { | |
601 | enum arm_pcs pcs_variant; | |
602 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
603 | int aapcs_ncrn; /* Next Core register number. */ | |
604 | int aapcs_nextncrn; /* Next next core register number. */ | |
605 | int aapcs_nvrn; /* Next Vector register number. */ | |
606 | int aapcs_nextnvrn; /* Next Next Vector register number. */ | |
607 | rtx aapcs_reg; /* Register assigned to this argument. This | |
608 | is NULL_RTX if this parameter goes on | |
609 | the stack. */ | |
610 | MACHMODE aapcs_vfp_rmode; | |
611 | int aapcs_stack_words; /* If the argument is passed on the stack, this | |
612 | is the number of words needed, after rounding | |
613 | up. Only meaningful when | |
614 | aapcs_reg == NULL_RTX. */ | |
615 | int aapcs_stack_size; /* The total size (in words, per 8 byte) of the | |
616 | stack arg area so far. */ | |
617 | } CUMULATIVE_ARGS; | |
febd3244 | 618 | #endif |
43e9d192 IB |
619 | |
620 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
621 | (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward) | |
622 | ||
623 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ | |
624 | (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) | |
625 | ||
626 | #define PAD_VARARGS_DOWN 0 | |
627 | ||
628 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
629 | aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) | |
630 | ||
631 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
632 | aarch64_function_arg_regno_p(REGNO) | |
633 | \f | |
634 | ||
635 | /* ISA Features. */ | |
636 | ||
637 | /* Addressing modes, etc. */ | |
638 | #define HAVE_POST_INCREMENT 1 | |
639 | #define HAVE_PRE_INCREMENT 1 | |
640 | #define HAVE_POST_DECREMENT 1 | |
641 | #define HAVE_PRE_DECREMENT 1 | |
642 | #define HAVE_POST_MODIFY_DISP 1 | |
643 | #define HAVE_PRE_MODIFY_DISP 1 | |
644 | ||
645 | #define MAX_REGS_PER_ADDRESS 2 | |
646 | ||
647 | #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) | |
648 | ||
649 | /* Try a machine-dependent way of reloading an illegitimate address | |
650 | operand. If we find one, push the reload and jump to WIN. This | |
651 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
652 | ||
653 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ | |
654 | do { \ | |
655 | rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \ | |
656 | IND_L); \ | |
657 | if (new_x) \ | |
658 | { \ | |
659 | X = new_x; \ | |
660 | goto WIN; \ | |
661 | } \ | |
662 | } while (0) | |
663 | ||
664 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
665 | aarch64_regno_ok_for_base_p (REGNO, true) | |
666 | ||
667 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
668 | aarch64_regno_ok_for_index_p (REGNO, true) | |
669 | ||
670 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
671 | aarch64_legitimate_pic_operand_p (X) | |
672 | ||
673 | #define CASE_VECTOR_MODE Pmode | |
674 | ||
675 | #define DEFAULT_SIGNED_CHAR 0 | |
676 | ||
677 | /* An integer expression for the size in bits of the largest integer machine | |
678 | mode that should actually be used. We allow pairs of registers. */ | |
679 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
680 | ||
681 | /* Maximum bytes moved by a single instruction (load/store pair). */ | |
682 | #define MOVE_MAX (UNITS_PER_WORD * 2) | |
683 | ||
684 | /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ | |
685 | #define AARCH64_CALL_RATIO 8 | |
686 | ||
e2c75eea JG |
687 | /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. |
688 | move_by_pieces will continually copy the largest safe chunks. So a | |
689 | 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient | |
690 | for both size and speed of copy, so we will instead use the "movmem" | |
691 | standard name to implement the copy. This logic does not apply when | |
692 | targeting -mstrict-align, so keep a sensible default in that case. */ | |
43e9d192 | 693 | #define MOVE_RATIO(speed) \ |
e2c75eea | 694 | (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) |
43e9d192 IB |
695 | |
696 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate | |
697 | of the length of a memset call, but use the default otherwise. */ | |
698 | #define CLEAR_RATIO(speed) \ | |
699 | ((speed) ? 15 : AARCH64_CALL_RATIO) | |
700 | ||
701 | /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
702 | optimizing for size adjust the ratio to account for the overhead of loading | |
703 | the constant. */ | |
704 | #define SET_RATIO(speed) \ | |
705 | ((speed) ? 15 : AARCH64_CALL_RATIO - 2) | |
706 | ||
43e9d192 IB |
707 | /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is |
708 | rarely a good idea in straight-line code since it adds an extra address | |
709 | dependency between each instruction. Better to use incrementing offsets. */ | |
710 | #define USE_LOAD_POST_INCREMENT(MODE) 0 | |
711 | #define USE_LOAD_POST_DECREMENT(MODE) 0 | |
712 | #define USE_LOAD_PRE_INCREMENT(MODE) 0 | |
713 | #define USE_LOAD_PRE_DECREMENT(MODE) 0 | |
714 | #define USE_STORE_POST_INCREMENT(MODE) 0 | |
715 | #define USE_STORE_POST_DECREMENT(MODE) 0 | |
716 | #define USE_STORE_PRE_INCREMENT(MODE) 0 | |
717 | #define USE_STORE_PRE_DECREMENT(MODE) 0 | |
718 | ||
719 | /* ?? #define WORD_REGISTER_OPERATIONS */ | |
720 | ||
721 | /* Define if loading from memory in MODE, an integral mode narrower than | |
722 | BITS_PER_WORD will either zero-extend or sign-extend. The value of this | |
723 | macro should be the code that says which one of the two operations is | |
724 | implicitly done, or UNKNOWN if none. */ | |
725 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
726 | ||
727 | /* Define this macro to be non-zero if instructions will fail to work | |
728 | if given data not on the nominal alignment. */ | |
729 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN | |
730 | ||
731 | /* Define this macro to be non-zero if accessing less than a word of | |
732 | memory is no faster than accessing a word of memory, i.e., if such | |
733 | accesses require more than one instruction or if there is no | |
734 | difference in cost. | |
735 | Although there's no difference in instruction count or cycles, | |
736 | in AArch64 we don't want to expand to a sub-word to a 64-bit access | |
737 | if we don't have to, for power-saving reasons. */ | |
738 | #define SLOW_BYTE_ACCESS 0 | |
739 | ||
740 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
741 | ||
742 | #define NO_FUNCTION_CSE 1 | |
743 | ||
17a819cb YZ |
744 | /* Specify the machine mode that the hardware addresses have. |
745 | After generation of rtl, the compiler makes no further distinction | |
746 | between pointers and any other objects of this machine mode. */ | |
43e9d192 | 747 | #define Pmode DImode |
17a819cb YZ |
748 | |
749 | /* A C expression whose value is zero if pointers that need to be extended | |
750 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
751 | greater then zero if they are zero-extended and less then zero if the | |
752 | ptr_extend instruction should be used. */ | |
753 | #define POINTERS_EXTEND_UNSIGNED 1 | |
754 | ||
755 | /* Mode of a function address in a call instruction (for indexing purposes). */ | |
43e9d192 IB |
756 | #define FUNCTION_MODE Pmode |
757 | ||
758 | #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) | |
759 | ||
f8bf91ab N |
760 | #define REVERSIBLE_CC_MODE(MODE) 1 |
761 | ||
43e9d192 IB |
762 | #define REVERSE_CONDITION(CODE, MODE) \ |
763 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
764 | ? reverse_condition_maybe_unordered (CODE) \ | |
765 | : reverse_condition (CODE)) | |
766 | ||
767 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
952e7819 | 768 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
43e9d192 | 769 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
952e7819 | 770 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
43e9d192 IB |
771 | |
772 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) | |
773 | ||
774 | #define RETURN_ADDR_RTX aarch64_return_addr | |
775 | ||
28514dda YZ |
776 | /* 3 insns + padding + 2 pointer-sized entries. */ |
777 | #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) | |
43e9d192 IB |
778 | |
779 | /* Trampolines contain dwords, so must be dword aligned. */ | |
780 | #define TRAMPOLINE_ALIGNMENT 64 | |
781 | ||
782 | /* Put trampolines in the text section so that mapping symbols work | |
783 | correctly. */ | |
784 | #define TRAMPOLINE_SECTION text_section | |
43e9d192 IB |
785 | |
786 | /* To start with. */ | |
b9066f5a MW |
787 | #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ |
788 | (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) | |
43e9d192 IB |
789 | \f |
790 | ||
791 | /* Assembly output. */ | |
792 | ||
793 | /* For now we'll make all jump tables pc-relative. */ | |
794 | #define CASE_VECTOR_PC_RELATIVE 1 | |
795 | ||
796 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
797 | ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ | |
798 | : (min < -0x1f0 || max > 0x1f0) ? HImode \ | |
799 | : QImode) | |
800 | ||
801 | /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ | |
802 | #define ADDR_VEC_ALIGN(JUMPTABLE) 0 | |
803 | ||
804 | #define PRINT_OPERAND(STREAM, X, CODE) aarch64_print_operand (STREAM, X, CODE) | |
805 | ||
806 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
807 | aarch64_print_operand_address (STREAM, X) | |
808 | ||
92d649c4 VK |
809 | #define MCOUNT_NAME "_mcount" |
810 | ||
811 | #define NO_PROFILE_COUNTERS 1 | |
812 | ||
813 | /* Emit rtl for profiling. Output assembler code to FILE | |
814 | to call "_mcount" for profiling a function entry. */ | |
3294102b MS |
815 | #define PROFILE_HOOK(LABEL) \ |
816 | { \ | |
817 | rtx fun, lr; \ | |
818 | lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ | |
819 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ | |
820 | emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ | |
821 | } | |
92d649c4 VK |
822 | |
823 | /* All the work done in PROFILE_HOOK, but still required. */ | |
824 | #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) | |
43e9d192 IB |
825 | |
826 | /* For some reason, the Linux headers think they know how to define | |
827 | these macros. They don't!!! */ | |
828 | #undef ASM_APP_ON | |
829 | #undef ASM_APP_OFF | |
830 | #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" | |
831 | #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" | |
832 | ||
43e9d192 IB |
833 | #define CONSTANT_POOL_BEFORE_FUNCTION 0 |
834 | ||
835 | /* This definition should be relocated to aarch64-elf-raw.h. This macro | |
836 | should be undefined in aarch64-linux.h and a clear_cache pattern | |
837 | implmented to emit either the call to __aarch64_sync_cache_range() | |
838 | directly or preferably the appropriate sycall or cache clear | |
839 | instructions inline. */ | |
840 | #define CLEAR_INSN_CACHE(beg, end) \ | |
841 | extern void __aarch64_sync_cache_range (void *, void *); \ | |
842 | __aarch64_sync_cache_range (beg, end) | |
843 | ||
43e9d192 IB |
844 | #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD |
845 | ||
73d9ac6a IB |
846 | /* Choose appropriate mode for caller saves, so we do the minimum |
847 | required size of load/store. */ | |
848 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
849 | aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) | |
850 | ||
43e9d192 IB |
851 | /* Callee only saves lower 64-bits of a 128-bit register. Tell the |
852 | compiler the callee clobbers the top 64-bits when restoring the | |
853 | bottom 64-bits. */ | |
854 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
855 | (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8) | |
856 | ||
d78006d9 KT |
857 | #undef SWITCHABLE_TARGET |
858 | #define SWITCHABLE_TARGET 1 | |
859 | ||
43e9d192 IB |
860 | /* Check TLS Descriptors mechanism is selected. */ |
861 | #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) | |
862 | ||
863 | extern enum aarch64_code_model aarch64_cmodel; | |
864 | ||
865 | /* When using the tiny addressing model conditional and unconditional branches | |
866 | can span the whole of the available address space (1MB). */ | |
867 | #define HAS_LONG_COND_BRANCH \ | |
868 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
869 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
870 | ||
871 | #define HAS_LONG_UNCOND_BRANCH \ | |
872 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
873 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
874 | ||
875 | /* Modes valid for AdvSIMD Q registers. */ | |
876 | #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ | |
877 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
71a11456 AL |
878 | || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ |
879 | || (MODE) == V2DFmode) | |
43e9d192 | 880 | |
e58bf20a TB |
881 | #define ENDIAN_LANE_N(mode, n) \ |
882 | (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) | |
883 | ||
9815fafa RE |
884 | /* Support for a configure-time default CPU, etc. We currently support |
885 | --with-arch and --with-cpu. Both are ignored if either is specified | |
886 | explicitly on the command line at run time. */ | |
887 | #define OPTION_DEFAULT_SPECS \ | |
888 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
889 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, | |
890 | ||
054b4005 JG |
891 | #define MCPU_TO_MARCH_SPEC \ |
892 | " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" | |
682287fb JG |
893 | |
894 | extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); | |
054b4005 | 895 | #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ |
682287fb JG |
896 | { "rewrite_mcpu", aarch64_rewrite_mcpu }, |
897 | ||
7e1bcce3 KT |
898 | #if defined(__aarch64__) |
899 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
900 | # define EXTRA_SPEC_FUNCTIONS \ | |
901 | { "local_cpu_detect", host_detect_local_cpu }, \ | |
054b4005 | 902 | MCPU_TO_MARCH_SPEC_FUNCTIONS |
7e1bcce3 KT |
903 | |
904 | # define MCPU_MTUNE_NATIVE_SPECS \ | |
905 | " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ | |
906 | " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ | |
907 | " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
908 | #else | |
909 | # define MCPU_MTUNE_NATIVE_SPECS "" | |
054b4005 | 910 | # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS |
7e1bcce3 KT |
911 | #endif |
912 | ||
682287fb | 913 | #define ASM_CPU_SPEC \ |
054b4005 | 914 | MCPU_TO_MARCH_SPEC |
682287fb | 915 | |
682287fb JG |
916 | #define EXTRA_SPECS \ |
917 | { "asm_cpu_spec", ASM_CPU_SPEC } | |
918 | ||
43e9d192 | 919 | #endif /* GCC_AARCH64_H */ |