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43e9d192 | 1 | /* Machine description for AArch64 architecture. |
d1e082c2 | 2 | Copyright (C) 2009-2013 Free Software Foundation, Inc. |
43e9d192 IB |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but | |
13 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | #ifndef GCC_AARCH64_H | |
23 | #define GCC_AARCH64_H | |
24 | ||
25 | /* Target CPU builtins. */ | |
26 | #define TARGET_CPU_CPP_BUILTINS() \ | |
27 | do \ | |
28 | { \ | |
29 | builtin_define ("__aarch64__"); \ | |
30 | if (TARGET_BIG_END) \ | |
31 | builtin_define ("__AARCH64EB__"); \ | |
32 | else \ | |
33 | builtin_define ("__AARCH64EL__"); \ | |
34 | \ | |
35 | switch (aarch64_cmodel) \ | |
36 | { \ | |
37 | case AARCH64_CMODEL_TINY: \ | |
38 | case AARCH64_CMODEL_TINY_PIC: \ | |
39 | builtin_define ("__AARCH64_CMODEL_TINY__"); \ | |
40 | break; \ | |
41 | case AARCH64_CMODEL_SMALL: \ | |
42 | case AARCH64_CMODEL_SMALL_PIC: \ | |
43 | builtin_define ("__AARCH64_CMODEL_SMALL__");\ | |
44 | break; \ | |
45 | case AARCH64_CMODEL_LARGE: \ | |
46 | builtin_define ("__AARCH64_CMODEL_LARGE__"); \ | |
47 | break; \ | |
48 | default: \ | |
49 | break; \ | |
50 | } \ | |
51 | \ | |
43be9a95 YZ |
52 | if (TARGET_ILP32) \ |
53 | { \ | |
54 | cpp_define (parse_in, "_ILP32"); \ | |
55 | cpp_define (parse_in, "__ILP32__"); \ | |
56 | } \ | |
43e9d192 IB |
57 | } while (0) |
58 | ||
59 | \f | |
60 | ||
61 | /* Target machine storage layout. */ | |
62 | ||
63 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
64 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
65 | && GET_MODE_SIZE (MODE) < 4) \ | |
66 | { \ | |
67 | if (MODE == QImode || MODE == HImode) \ | |
68 | { \ | |
69 | MODE = SImode; \ | |
70 | } \ | |
71 | } | |
72 | ||
73 | /* Bits are always numbered from the LSBit. */ | |
74 | #define BITS_BIG_ENDIAN 0 | |
75 | ||
76 | /* Big/little-endian flavour. */ | |
77 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) | |
78 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
79 | ||
80 | /* AdvSIMD is supported in the default configuration, unless disabled by | |
81 | -mgeneral-regs-only. */ | |
82 | #define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY | |
83 | #define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY | |
84 | ||
85 | #define UNITS_PER_WORD 8 | |
86 | ||
87 | #define UNITS_PER_VREG 16 | |
88 | ||
89 | #define PARM_BOUNDARY 64 | |
90 | ||
91 | #define STACK_BOUNDARY 128 | |
92 | ||
93 | #define FUNCTION_BOUNDARY 32 | |
94 | ||
95 | #define EMPTY_FIELD_BOUNDARY 32 | |
96 | ||
97 | #define BIGGEST_ALIGNMENT 128 | |
98 | ||
99 | #define SHORT_TYPE_SIZE 16 | |
100 | ||
101 | #define INT_TYPE_SIZE 32 | |
102 | ||
17a819cb YZ |
103 | #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) |
104 | ||
105 | #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) | |
43e9d192 IB |
106 | |
107 | #define LONG_LONG_TYPE_SIZE 64 | |
108 | ||
109 | #define FLOAT_TYPE_SIZE 32 | |
110 | ||
111 | #define DOUBLE_TYPE_SIZE 64 | |
112 | ||
113 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
114 | ||
115 | /* The architecture reserves all bits of the address for hardware use, | |
116 | so the vbit must go into the delta field of pointers to member | |
117 | functions. This is the same config as that in the AArch32 | |
118 | port. */ | |
119 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
120 | ||
121 | /* Make strings word-aligned so that strcpy from constants will be | |
122 | faster. */ | |
123 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
124 | ((TREE_CODE (EXP) == STRING_CST \ | |
125 | && !optimize_size \ | |
126 | && (ALIGN) < BITS_PER_WORD) \ | |
127 | ? BITS_PER_WORD : ALIGN) | |
128 | ||
129 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
130 | ((((ALIGN) < BITS_PER_WORD) \ | |
131 | && (TREE_CODE (EXP) == ARRAY_TYPE \ | |
132 | || TREE_CODE (EXP) == UNION_TYPE \ | |
133 | || TREE_CODE (EXP) == RECORD_TYPE)) \ | |
134 | ? BITS_PER_WORD : (ALIGN)) | |
135 | ||
136 | #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) | |
137 | ||
138 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
139 | ||
140 | /* Defined by the ABI */ | |
141 | #define WCHAR_TYPE "unsigned int" | |
142 | #define WCHAR_TYPE_SIZE 32 | |
143 | ||
144 | /* Using long long breaks -ansi and -std=c90, so these will need to be | |
145 | made conditional for an LLP64 ABI. */ | |
146 | ||
147 | #define SIZE_TYPE "long unsigned int" | |
148 | ||
149 | #define PTRDIFF_TYPE "long int" | |
150 | ||
151 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
152 | ||
153 | ||
154 | /* Instruction tuning/selection flags. */ | |
155 | ||
156 | /* Bit values used to identify processor capabilities. */ | |
157 | #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ | |
158 | #define AARCH64_FL_FP (1 << 1) /* Has FP. */ | |
159 | #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ | |
160 | #define AARCH64_FL_SLOWMUL (1 << 3) /* A slow multiply core. */ | |
5922847b | 161 | #define AARCH64_FL_CRC (1 << 4) /* Has CRC. */ |
43e9d192 IB |
162 | |
163 | /* Has FP and SIMD. */ | |
164 | #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) | |
165 | ||
166 | /* Has FP without SIMD. */ | |
167 | #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) | |
168 | ||
169 | /* Architecture flags that effect instruction selection. */ | |
170 | #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) | |
171 | ||
172 | /* Macros to test ISA flags. */ | |
173 | extern unsigned long aarch64_isa_flags; | |
5922847b | 174 | #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) |
43e9d192 IB |
175 | #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) |
176 | #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) | |
177 | #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) | |
178 | ||
179 | /* Macros to test tuning flags. */ | |
180 | extern unsigned long aarch64_tune_flags; | |
181 | #define AARCH64_TUNE_SLOWMUL (aarch64_tune_flags & AARCH64_FL_SLOWMUL) | |
182 | ||
183 | ||
184 | /* Standard register usage. */ | |
185 | ||
186 | /* 31 64-bit general purpose registers R0-R30: | |
187 | R30 LR (link register) | |
188 | R29 FP (frame pointer) | |
189 | R19-R28 Callee-saved registers | |
190 | R18 The platform register; use as temporary register. | |
191 | R17 IP1 The second intra-procedure-call temporary register | |
192 | (can be used by call veneers and PLT code); otherwise use | |
193 | as a temporary register | |
194 | R16 IP0 The first intra-procedure-call temporary register (can | |
195 | be used by call veneers and PLT code); otherwise use as a | |
196 | temporary register | |
197 | R9-R15 Temporary registers | |
198 | R8 Structure value parameter / temporary register | |
199 | R0-R7 Parameter/result registers | |
200 | ||
201 | SP stack pointer, encoded as X/R31 where permitted. | |
202 | ZR zero register, encoded as X/R31 elsewhere | |
203 | ||
204 | 32 x 128-bit floating-point/vector registers | |
205 | V16-V31 Caller-saved (temporary) registers | |
206 | V8-V15 Callee-saved registers | |
207 | V0-V7 Parameter/result registers | |
208 | ||
209 | The vector register V0 holds scalar B0, H0, S0 and D0 in its least | |
210 | significant bits. Unlike AArch32 S1 is not packed into D0, | |
211 | etc. */ | |
212 | ||
213 | /* Note that we don't mark X30 as a call-clobbered register. The idea is | |
214 | that it's really the call instructions themselves which clobber X30. | |
215 | We don't care what the called function does with it afterwards. | |
216 | ||
217 | This approach makes it easier to implement sibcalls. Unlike normal | |
218 | calls, sibcalls don't clobber X30, so the register reaches the | |
219 | called function intact. EPILOGUE_USES says that X30 is useful | |
220 | to the called function. */ | |
221 | ||
222 | #define FIXED_REGISTERS \ | |
223 | { \ | |
224 | 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ | |
225 | 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ | |
226 | 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
227 | 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ | |
228 | 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ | |
229 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
230 | 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ | |
231 | 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ | |
232 | 1, 1, 1, /* SFP, AP, CC */ \ | |
233 | } | |
234 | ||
235 | #define CALL_USED_REGISTERS \ | |
236 | { \ | |
237 | 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ | |
238 | 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ | |
239 | 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
240 | 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ | |
241 | 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ | |
242 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
243 | 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ | |
244 | 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ | |
245 | 1, 1, 1, /* SFP, AP, CC */ \ | |
246 | } | |
247 | ||
248 | #define REGISTER_NAMES \ | |
249 | { \ | |
250 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ | |
251 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ | |
252 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ | |
253 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ | |
254 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ | |
255 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ | |
256 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ | |
257 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ | |
258 | "sfp", "ap", "cc", \ | |
259 | } | |
260 | ||
261 | /* Generate the register aliases for core register N */ | |
262 | #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ | |
263 | {"w" # N, R0_REGNUM + (N)} | |
264 | ||
265 | #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ | |
266 | {"d" # N, V0_REGNUM + (N)}, \ | |
267 | {"s" # N, V0_REGNUM + (N)}, \ | |
268 | {"h" # N, V0_REGNUM + (N)}, \ | |
269 | {"b" # N, V0_REGNUM + (N)} | |
270 | ||
271 | /* Provide aliases for all of the ISA defined register name forms. | |
272 | These aliases are convenient for use in the clobber lists of inline | |
273 | asm statements. */ | |
274 | ||
275 | #define ADDITIONAL_REGISTER_NAMES \ | |
276 | { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ | |
277 | R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ | |
278 | R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ | |
279 | R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ | |
280 | R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ | |
281 | R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ | |
282 | R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ | |
9259db42 | 283 | R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ |
43e9d192 IB |
284 | V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ |
285 | V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ | |
286 | V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ | |
287 | V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ | |
288 | V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ | |
289 | V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ | |
290 | V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ | |
291 | V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ | |
292 | } | |
293 | ||
294 | /* Say that the epilogue uses the return address register. Note that | |
295 | in the case of sibcalls, the values "used by the epilogue" are | |
296 | considered live at the start of the called function. */ | |
297 | ||
298 | #define EPILOGUE_USES(REGNO) \ | |
299 | ((REGNO) == LR_REGNUM) | |
300 | ||
301 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
302 | the stack pointer does not matter. The value is tested only in | |
303 | functions that have frame pointers. */ | |
304 | #define EXIT_IGNORE_STACK 1 | |
305 | ||
306 | #define STATIC_CHAIN_REGNUM R18_REGNUM | |
307 | #define HARD_FRAME_POINTER_REGNUM R29_REGNUM | |
308 | #define FRAME_POINTER_REGNUM SFP_REGNUM | |
309 | #define STACK_POINTER_REGNUM SP_REGNUM | |
310 | #define ARG_POINTER_REGNUM AP_REGNUM | |
311 | #define FIRST_PSEUDO_REGISTER 67 | |
312 | ||
313 | /* The number of (integer) argument register available. */ | |
314 | #define NUM_ARG_REGS 8 | |
315 | #define NUM_FP_ARG_REGS 8 | |
316 | ||
317 | /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most | |
318 | four members. */ | |
319 | #define HA_MAX_NUM_FLDS 4 | |
320 | ||
321 | /* External dwarf register number scheme. These number are used to | |
322 | identify registers in dwarf debug information, the values are | |
323 | defined by the AArch64 ABI. The numbering scheme is independent of | |
324 | GCC's internal register numbering scheme. */ | |
325 | ||
326 | #define AARCH64_DWARF_R0 0 | |
327 | ||
328 | /* The number of R registers, note 31! not 32. */ | |
329 | #define AARCH64_DWARF_NUMBER_R 31 | |
330 | ||
331 | #define AARCH64_DWARF_SP 31 | |
332 | #define AARCH64_DWARF_V0 64 | |
333 | ||
334 | /* The number of V registers. */ | |
335 | #define AARCH64_DWARF_NUMBER_V 32 | |
336 | ||
337 | /* For signal frames we need to use an alternative return column. This | |
338 | value must not correspond to a hard register and must be out of the | |
339 | range of DWARF_FRAME_REGNUM(). */ | |
340 | #define DWARF_ALT_FRAME_RETURN_COLUMN \ | |
341 | (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) | |
342 | ||
343 | /* We add 1 extra frame register for use as the | |
344 | DWARF_ALT_FRAME_RETURN_COLUMN. */ | |
345 | #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) | |
346 | ||
347 | ||
348 | #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) | |
349 | /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders | |
350 | can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same | |
351 | as the default definition in dwarf2out.c. */ | |
352 | #undef DWARF_FRAME_REGNUM | |
353 | #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) | |
354 | ||
355 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
356 | ||
357 | #define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE) | |
358 | ||
359 | #define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE) | |
360 | ||
361 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
362 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
363 | ||
364 | #define DWARF2_UNWIND_INFO 1 | |
365 | ||
366 | /* Use R0 through R3 to pass exception handling information. */ | |
367 | #define EH_RETURN_DATA_REGNO(N) \ | |
368 | ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) | |
369 | ||
370 | /* Select a format to encode pointers in exception handling data. */ | |
371 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
372 | aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) | |
373 | ||
374 | /* The register that holds the return address in exception handlers. */ | |
375 | #define AARCH64_EH_STACKADJ_REGNUM (R0_REGNUM + 4) | |
376 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM) | |
377 | ||
378 | /* Don't use __builtin_setjmp until we've defined it. */ | |
379 | #undef DONT_USE_BUILTIN_SETJMP | |
380 | #define DONT_USE_BUILTIN_SETJMP 1 | |
381 | ||
382 | /* Register in which the structure value is to be returned. */ | |
383 | #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM | |
384 | ||
385 | /* Non-zero if REGNO is part of the Core register set. | |
386 | ||
387 | The rather unusual way of expressing this check is to avoid | |
388 | warnings when building the compiler when R0_REGNUM is 0 and REGNO | |
389 | is unsigned. */ | |
390 | #define GP_REGNUM_P(REGNO) \ | |
391 | (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) | |
392 | ||
393 | #define FP_REGNUM_P(REGNO) \ | |
394 | (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) | |
395 | ||
396 | #define FP_LO_REGNUM_P(REGNO) \ | |
397 | (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) | |
398 | ||
399 | \f | |
400 | /* Register and constant classes. */ | |
401 | ||
402 | enum reg_class | |
403 | { | |
404 | NO_REGS, | |
405 | CORE_REGS, | |
406 | GENERAL_REGS, | |
407 | STACK_REG, | |
408 | POINTER_REGS, | |
409 | FP_LO_REGS, | |
410 | FP_REGS, | |
411 | ALL_REGS, | |
412 | LIM_REG_CLASSES /* Last */ | |
413 | }; | |
414 | ||
415 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
416 | ||
417 | #define REG_CLASS_NAMES \ | |
418 | { \ | |
419 | "NO_REGS", \ | |
420 | "CORE_REGS", \ | |
421 | "GENERAL_REGS", \ | |
422 | "STACK_REG", \ | |
423 | "POINTER_REGS", \ | |
424 | "FP_LO_REGS", \ | |
425 | "FP_REGS", \ | |
426 | "ALL_REGS" \ | |
427 | } | |
428 | ||
429 | #define REG_CLASS_CONTENTS \ | |
430 | { \ | |
431 | { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
432 | { 0x7fffffff, 0x00000000, 0x00000003 }, /* CORE_REGS */ \ | |
433 | { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ | |
434 | { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
435 | { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ | |
436 | { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ | |
437 | { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ | |
438 | { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ | |
439 | } | |
440 | ||
441 | #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) | |
442 | ||
443 | #define INDEX_REG_CLASS CORE_REGS | |
444 | #define BASE_REG_CLASS POINTER_REGS | |
445 | ||
446 | /* Register pairs used to eliminate unneeded registers that point intoi | |
447 | the stack frame. */ | |
448 | #define ELIMINABLE_REGS \ | |
449 | { \ | |
450 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
451 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
452 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
453 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
454 | } | |
455 | ||
456 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
457 | (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) | |
458 | ||
459 | /* CPU/ARCH option handling. */ | |
460 | #include "config/aarch64/aarch64-opts.h" | |
461 | ||
462 | enum target_cpus | |
463 | { | |
464 | #define AARCH64_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ | |
465 | TARGET_CPU_##IDENT, | |
466 | #include "aarch64-cores.def" | |
467 | #undef AARCH64_CORE | |
468 | TARGET_CPU_generic | |
469 | }; | |
470 | ||
471 | /* If there is no CPU defined at configure, use "generic" as default. */ | |
472 | #ifndef TARGET_CPU_DEFAULT | |
473 | #define TARGET_CPU_DEFAULT \ | |
474 | (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) | |
475 | #endif | |
476 | ||
477 | /* The processor for which instructions should be scheduled. */ | |
478 | extern enum aarch64_processor aarch64_tune; | |
479 | ||
480 | /* RTL generation support. */ | |
481 | #define INIT_EXPANDERS aarch64_init_expanders () | |
482 | \f | |
483 | ||
484 | /* Stack layout; function entry, exit and calling. */ | |
485 | #define STACK_GROWS_DOWNWARD 1 | |
486 | ||
487 | #define FRAME_GROWS_DOWNWARD 0 | |
488 | ||
489 | #define STARTING_FRAME_OFFSET 0 | |
490 | ||
491 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
492 | ||
493 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
494 | ||
495 | /* Fix for VFP */ | |
496 | #define LIBCALL_VALUE(MODE) \ | |
497 | gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) | |
498 | ||
499 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
500 | ||
501 | #define AARCH64_ROUND_UP(X, ALIGNMENT) \ | |
502 | (((X) + ((ALIGNMENT) - 1)) & ~((ALIGNMENT) - 1)) | |
503 | ||
504 | #define AARCH64_ROUND_DOWN(X, ALIGNMENT) \ | |
505 | ((X) & ~((ALIGNMENT) - 1)) | |
506 | ||
507 | #ifdef HOST_WIDE_INT | |
508 | struct GTY (()) aarch64_frame | |
509 | { | |
510 | HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; | |
511 | HOST_WIDE_INT saved_regs_size; | |
512 | /* Padding if needed after the all the callee save registers have | |
513 | been saved. */ | |
514 | HOST_WIDE_INT padding0; | |
515 | HOST_WIDE_INT hardfp_offset; /* HARD_FRAME_POINTER_REGNUM */ | |
516 | HOST_WIDE_INT fp_lr_offset; /* Space needed for saving fp and/or lr */ | |
517 | ||
518 | bool laid_out; | |
519 | }; | |
520 | ||
521 | typedef struct GTY (()) machine_function | |
522 | { | |
523 | struct aarch64_frame frame; | |
524 | ||
525 | /* The number of extra stack bytes taken up by register varargs. | |
526 | This area is allocated by the callee at the very top of the frame. */ | |
527 | HOST_WIDE_INT saved_varargs_size; | |
528 | ||
529 | } machine_function; | |
530 | #endif | |
531 | ||
17a819cb YZ |
532 | /* Which ABI to use. */ |
533 | enum aarch64_abi_type | |
534 | { | |
535 | AARCH64_ABI_LP64 = 0, | |
536 | AARCH64_ABI_ILP32 = 1 | |
537 | }; | |
538 | ||
539 | #ifndef AARCH64_ABI_DEFAULT | |
540 | #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 | |
541 | #endif | |
542 | ||
543 | #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) | |
43e9d192 | 544 | |
43e9d192 IB |
545 | enum arm_pcs |
546 | { | |
547 | ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ | |
548 | ARM_PCS_UNKNOWN | |
549 | }; | |
550 | ||
551 | ||
43e9d192 | 552 | extern enum arm_pcs arm_pcs_variant; |
43e9d192 IB |
553 | |
554 | #ifndef ARM_DEFAULT_PCS | |
555 | #define ARM_DEFAULT_PCS ARM_PCS_AAPCS64 | |
556 | #endif | |
557 | ||
558 | /* We can't use enum machine_mode inside a generator file because it | |
559 | hasn't been created yet; we shouldn't be using any code that | |
560 | needs the real definition though, so this ought to be safe. */ | |
561 | #ifdef GENERATOR_FILE | |
562 | #define MACHMODE int | |
563 | #else | |
564 | #include "insn-modes.h" | |
565 | #define MACHMODE enum machine_mode | |
566 | #endif | |
567 | ||
568 | ||
569 | /* AAPCS related state tracking. */ | |
570 | typedef struct | |
571 | { | |
572 | enum arm_pcs pcs_variant; | |
573 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
574 | int aapcs_ncrn; /* Next Core register number. */ | |
575 | int aapcs_nextncrn; /* Next next core register number. */ | |
576 | int aapcs_nvrn; /* Next Vector register number. */ | |
577 | int aapcs_nextnvrn; /* Next Next Vector register number. */ | |
578 | rtx aapcs_reg; /* Register assigned to this argument. This | |
579 | is NULL_RTX if this parameter goes on | |
580 | the stack. */ | |
581 | MACHMODE aapcs_vfp_rmode; | |
582 | int aapcs_stack_words; /* If the argument is passed on the stack, this | |
583 | is the number of words needed, after rounding | |
584 | up. Only meaningful when | |
585 | aapcs_reg == NULL_RTX. */ | |
586 | int aapcs_stack_size; /* The total size (in words, per 8 byte) of the | |
587 | stack arg area so far. */ | |
588 | } CUMULATIVE_ARGS; | |
589 | ||
590 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
591 | (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward) | |
592 | ||
593 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ | |
594 | (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) | |
595 | ||
596 | #define PAD_VARARGS_DOWN 0 | |
597 | ||
598 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
599 | aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) | |
600 | ||
601 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
602 | aarch64_function_arg_regno_p(REGNO) | |
603 | \f | |
604 | ||
605 | /* ISA Features. */ | |
606 | ||
607 | /* Addressing modes, etc. */ | |
608 | #define HAVE_POST_INCREMENT 1 | |
609 | #define HAVE_PRE_INCREMENT 1 | |
610 | #define HAVE_POST_DECREMENT 1 | |
611 | #define HAVE_PRE_DECREMENT 1 | |
612 | #define HAVE_POST_MODIFY_DISP 1 | |
613 | #define HAVE_PRE_MODIFY_DISP 1 | |
614 | ||
615 | #define MAX_REGS_PER_ADDRESS 2 | |
616 | ||
617 | #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) | |
618 | ||
619 | /* Try a machine-dependent way of reloading an illegitimate address | |
620 | operand. If we find one, push the reload and jump to WIN. This | |
621 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
622 | ||
623 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ | |
624 | do { \ | |
625 | rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \ | |
626 | IND_L); \ | |
627 | if (new_x) \ | |
628 | { \ | |
629 | X = new_x; \ | |
630 | goto WIN; \ | |
631 | } \ | |
632 | } while (0) | |
633 | ||
634 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
635 | aarch64_regno_ok_for_base_p (REGNO, true) | |
636 | ||
637 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
638 | aarch64_regno_ok_for_index_p (REGNO, true) | |
639 | ||
640 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
641 | aarch64_legitimate_pic_operand_p (X) | |
642 | ||
643 | #define CASE_VECTOR_MODE Pmode | |
644 | ||
645 | #define DEFAULT_SIGNED_CHAR 0 | |
646 | ||
647 | /* An integer expression for the size in bits of the largest integer machine | |
648 | mode that should actually be used. We allow pairs of registers. */ | |
649 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
650 | ||
651 | /* Maximum bytes moved by a single instruction (load/store pair). */ | |
652 | #define MOVE_MAX (UNITS_PER_WORD * 2) | |
653 | ||
654 | /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ | |
655 | #define AARCH64_CALL_RATIO 8 | |
656 | ||
657 | /* When optimizing for size, give a better estimate of the length of a memcpy | |
658 | call, but use the default otherwise. But move_by_pieces_ninsns() counts | |
659 | memory-to-memory moves, and we'll have to generate a load & store for each, | |
660 | so halve the value to take that into account. */ | |
661 | #define MOVE_RATIO(speed) \ | |
662 | (((speed) ? 15 : AARCH64_CALL_RATIO) / 2) | |
663 | ||
664 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate | |
665 | of the length of a memset call, but use the default otherwise. */ | |
666 | #define CLEAR_RATIO(speed) \ | |
667 | ((speed) ? 15 : AARCH64_CALL_RATIO) | |
668 | ||
669 | /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
670 | optimizing for size adjust the ratio to account for the overhead of loading | |
671 | the constant. */ | |
672 | #define SET_RATIO(speed) \ | |
673 | ((speed) ? 15 : AARCH64_CALL_RATIO - 2) | |
674 | ||
675 | /* STORE_BY_PIECES_P can be used when copying a constant string, but | |
676 | in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR). | |
677 | For now we always fail this and let the move_by_pieces code copy | |
678 | the string from read-only memory. */ | |
679 | #define STORE_BY_PIECES_P(SIZE, ALIGN) 0 | |
680 | ||
681 | /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is | |
682 | rarely a good idea in straight-line code since it adds an extra address | |
683 | dependency between each instruction. Better to use incrementing offsets. */ | |
684 | #define USE_LOAD_POST_INCREMENT(MODE) 0 | |
685 | #define USE_LOAD_POST_DECREMENT(MODE) 0 | |
686 | #define USE_LOAD_PRE_INCREMENT(MODE) 0 | |
687 | #define USE_LOAD_PRE_DECREMENT(MODE) 0 | |
688 | #define USE_STORE_POST_INCREMENT(MODE) 0 | |
689 | #define USE_STORE_POST_DECREMENT(MODE) 0 | |
690 | #define USE_STORE_PRE_INCREMENT(MODE) 0 | |
691 | #define USE_STORE_PRE_DECREMENT(MODE) 0 | |
692 | ||
693 | /* ?? #define WORD_REGISTER_OPERATIONS */ | |
694 | ||
695 | /* Define if loading from memory in MODE, an integral mode narrower than | |
696 | BITS_PER_WORD will either zero-extend or sign-extend. The value of this | |
697 | macro should be the code that says which one of the two operations is | |
698 | implicitly done, or UNKNOWN if none. */ | |
699 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
700 | ||
701 | /* Define this macro to be non-zero if instructions will fail to work | |
702 | if given data not on the nominal alignment. */ | |
703 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN | |
704 | ||
705 | /* Define this macro to be non-zero if accessing less than a word of | |
706 | memory is no faster than accessing a word of memory, i.e., if such | |
707 | accesses require more than one instruction or if there is no | |
708 | difference in cost. | |
709 | Although there's no difference in instruction count or cycles, | |
710 | in AArch64 we don't want to expand to a sub-word to a 64-bit access | |
711 | if we don't have to, for power-saving reasons. */ | |
712 | #define SLOW_BYTE_ACCESS 0 | |
713 | ||
714 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
715 | ||
716 | #define NO_FUNCTION_CSE 1 | |
717 | ||
17a819cb YZ |
718 | /* Specify the machine mode that the hardware addresses have. |
719 | After generation of rtl, the compiler makes no further distinction | |
720 | between pointers and any other objects of this machine mode. */ | |
43e9d192 | 721 | #define Pmode DImode |
17a819cb YZ |
722 | |
723 | /* A C expression whose value is zero if pointers that need to be extended | |
724 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
725 | greater then zero if they are zero-extended and less then zero if the | |
726 | ptr_extend instruction should be used. */ | |
727 | #define POINTERS_EXTEND_UNSIGNED 1 | |
728 | ||
729 | /* Mode of a function address in a call instruction (for indexing purposes). */ | |
43e9d192 IB |
730 | #define FUNCTION_MODE Pmode |
731 | ||
732 | #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) | |
733 | ||
f8bf91ab N |
734 | #define REVERSIBLE_CC_MODE(MODE) 1 |
735 | ||
43e9d192 IB |
736 | #define REVERSE_CONDITION(CODE, MODE) \ |
737 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
738 | ? reverse_condition_maybe_unordered (CODE) \ | |
739 | : reverse_condition (CODE)) | |
740 | ||
741 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
742 | ((VALUE) = ((MODE) == SImode ? 32 : 64), 2) | |
743 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
744 | ((VALUE) = ((MODE) == SImode ? 32 : 64), 2) | |
745 | ||
746 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) | |
747 | ||
748 | #define RETURN_ADDR_RTX aarch64_return_addr | |
749 | ||
28514dda YZ |
750 | /* 3 insns + padding + 2 pointer-sized entries. */ |
751 | #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) | |
43e9d192 IB |
752 | |
753 | /* Trampolines contain dwords, so must be dword aligned. */ | |
754 | #define TRAMPOLINE_ALIGNMENT 64 | |
755 | ||
756 | /* Put trampolines in the text section so that mapping symbols work | |
757 | correctly. */ | |
758 | #define TRAMPOLINE_SECTION text_section | |
759 | \f | |
760 | /* Costs, etc. */ | |
761 | #define MEMORY_MOVE_COST(M, CLASS, IN) \ | |
762 | (GET_MODE_SIZE (M) < 8 ? 8 : GET_MODE_SIZE (M)) | |
763 | ||
764 | /* To start with. */ | |
765 | #define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2 | |
766 | \f | |
767 | ||
768 | /* Assembly output. */ | |
769 | ||
770 | /* For now we'll make all jump tables pc-relative. */ | |
771 | #define CASE_VECTOR_PC_RELATIVE 1 | |
772 | ||
773 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
774 | ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ | |
775 | : (min < -0x1f0 || max > 0x1f0) ? HImode \ | |
776 | : QImode) | |
777 | ||
778 | /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ | |
779 | #define ADDR_VEC_ALIGN(JUMPTABLE) 0 | |
780 | ||
781 | #define PRINT_OPERAND(STREAM, X, CODE) aarch64_print_operand (STREAM, X, CODE) | |
782 | ||
783 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
784 | aarch64_print_operand_address (STREAM, X) | |
785 | ||
786 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
787 | aarch64_function_profiler (STREAM, LABELNO) | |
788 | ||
789 | /* For some reason, the Linux headers think they know how to define | |
790 | these macros. They don't!!! */ | |
791 | #undef ASM_APP_ON | |
792 | #undef ASM_APP_OFF | |
793 | #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" | |
794 | #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" | |
795 | ||
43e9d192 IB |
796 | #define CONSTANT_POOL_BEFORE_FUNCTION 0 |
797 | ||
798 | /* This definition should be relocated to aarch64-elf-raw.h. This macro | |
799 | should be undefined in aarch64-linux.h and a clear_cache pattern | |
800 | implmented to emit either the call to __aarch64_sync_cache_range() | |
801 | directly or preferably the appropriate sycall or cache clear | |
802 | instructions inline. */ | |
803 | #define CLEAR_INSN_CACHE(beg, end) \ | |
804 | extern void __aarch64_sync_cache_range (void *, void *); \ | |
805 | __aarch64_sync_cache_range (beg, end) | |
806 | ||
43e9d192 IB |
807 | /* VFP registers may only be accessed in the mode they |
808 | were set. */ | |
809 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
810 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
811 | ? reg_classes_intersect_p (FP_REGS, (CLASS)) \ | |
812 | : 0) | |
813 | ||
814 | ||
815 | #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD | |
816 | ||
817 | /* Callee only saves lower 64-bits of a 128-bit register. Tell the | |
818 | compiler the callee clobbers the top 64-bits when restoring the | |
819 | bottom 64-bits. */ | |
820 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
821 | (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8) | |
822 | ||
823 | /* Check TLS Descriptors mechanism is selected. */ | |
824 | #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) | |
825 | ||
826 | extern enum aarch64_code_model aarch64_cmodel; | |
827 | ||
828 | /* When using the tiny addressing model conditional and unconditional branches | |
829 | can span the whole of the available address space (1MB). */ | |
830 | #define HAS_LONG_COND_BRANCH \ | |
831 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
832 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
833 | ||
834 | #define HAS_LONG_UNCOND_BRANCH \ | |
835 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
836 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
837 | ||
838 | /* Modes valid for AdvSIMD Q registers. */ | |
839 | #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ | |
840 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
841 | || (MODE) == V4SFmode || (MODE) == V2DImode || mode == V2DFmode) | |
842 | ||
843 | #endif /* GCC_AARCH64_H */ |