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43e9d192 | 1 | /* Machine description for AArch64 architecture. |
5624e564 | 2 | Copyright (C) 2009-2015 Free Software Foundation, Inc. |
43e9d192 IB |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but | |
13 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | #ifndef GCC_AARCH64_H | |
23 | #define GCC_AARCH64_H | |
24 | ||
25 | /* Target CPU builtins. */ | |
26 | #define TARGET_CPU_CPP_BUILTINS() \ | |
27 | do \ | |
28 | { \ | |
9e98c8c3 RL |
29 | builtin_define ("__aarch64__"); \ |
30 | builtin_define ("__ARM_64BIT_STATE"); \ | |
0c6caaf8 RL |
31 | builtin_define_with_int_value \ |
32 | ("__ARM_ARCH", aarch64_architecture_version); \ | |
33 | cpp_define_formatted \ | |
34 | (parse_in, "__ARM_ARCH_%dA", aarch64_architecture_version); \ | |
9e98c8c3 | 35 | builtin_define ("__ARM_ARCH_ISA_A64"); \ |
0c6caaf8 RL |
36 | builtin_define_with_int_value \ |
37 | ("__ARM_ARCH_PROFILE", 'A'); \ | |
9e98c8c3 RL |
38 | builtin_define ("__ARM_FEATURE_CLZ"); \ |
39 | builtin_define ("__ARM_FEATURE_IDIV"); \ | |
40 | builtin_define ("__ARM_FEATURE_UNALIGNED"); \ | |
45b70a73 RL |
41 | if (flag_unsafe_math_optimizations) \ |
42 | builtin_define ("__ARM_FP_FAST"); \ | |
9e98c8c3 RL |
43 | builtin_define ("__ARM_PCS_AAPCS64"); \ |
44 | builtin_define_with_int_value \ | |
45 | ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8); \ | |
46 | builtin_define_with_int_value \ | |
47 | ("__ARM_SIZEOF_MINIMAL_ENUM", \ | |
48 | flag_short_enums? 1 : 4); \ | |
43e9d192 | 49 | if (TARGET_BIG_END) \ |
9e98c8c3 RL |
50 | { \ |
51 | builtin_define ("__AARCH64EB__"); \ | |
52 | builtin_define ("__ARM_BIG_ENDIAN"); \ | |
53 | } \ | |
43e9d192 IB |
54 | else \ |
55 | builtin_define ("__AARCH64EL__"); \ | |
56 | \ | |
45b70a73 RL |
57 | if (TARGET_FLOAT) \ |
58 | { \ | |
59 | builtin_define ("__ARM_FEATURE_FMA"); \ | |
60 | builtin_define_with_int_value ("__ARM_FP", 0x0C); \ | |
61 | } \ | |
62 | if (TARGET_SIMD) \ | |
63 | { \ | |
64 | builtin_define ("__ARM_FEATURE_NUMERIC_MAXMIN"); \ | |
65 | builtin_define ("__ARM_NEON"); \ | |
66 | builtin_define_with_int_value ("__ARM_NEON_FP", 0x0C);\ | |
67 | } \ | |
68 | \ | |
69 | if (TARGET_CRC32) \ | |
5d357f26 KT |
70 | builtin_define ("__ARM_FEATURE_CRC32"); \ |
71 | \ | |
43e9d192 IB |
72 | switch (aarch64_cmodel) \ |
73 | { \ | |
74 | case AARCH64_CMODEL_TINY: \ | |
75 | case AARCH64_CMODEL_TINY_PIC: \ | |
76 | builtin_define ("__AARCH64_CMODEL_TINY__"); \ | |
77 | break; \ | |
78 | case AARCH64_CMODEL_SMALL: \ | |
79 | case AARCH64_CMODEL_SMALL_PIC: \ | |
80 | builtin_define ("__AARCH64_CMODEL_SMALL__");\ | |
81 | break; \ | |
82 | case AARCH64_CMODEL_LARGE: \ | |
83 | builtin_define ("__AARCH64_CMODEL_LARGE__"); \ | |
84 | break; \ | |
85 | default: \ | |
86 | break; \ | |
87 | } \ | |
88 | \ | |
43be9a95 YZ |
89 | if (TARGET_ILP32) \ |
90 | { \ | |
91 | cpp_define (parse_in, "_ILP32"); \ | |
92 | cpp_define (parse_in, "__ILP32__"); \ | |
93 | } \ | |
afb582f1 TB |
94 | if (TARGET_CRYPTO) \ |
95 | builtin_define ("__ARM_FEATURE_CRYPTO"); \ | |
43e9d192 IB |
96 | } while (0) |
97 | ||
98 | \f | |
99 | ||
100 | /* Target machine storage layout. */ | |
101 | ||
102 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
103 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
104 | && GET_MODE_SIZE (MODE) < 4) \ | |
105 | { \ | |
106 | if (MODE == QImode || MODE == HImode) \ | |
107 | { \ | |
108 | MODE = SImode; \ | |
109 | } \ | |
110 | } | |
111 | ||
112 | /* Bits are always numbered from the LSBit. */ | |
113 | #define BITS_BIG_ENDIAN 0 | |
114 | ||
115 | /* Big/little-endian flavour. */ | |
116 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) | |
117 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
118 | ||
119 | /* AdvSIMD is supported in the default configuration, unless disabled by | |
683e3333 KT |
120 | -mgeneral-regs-only or by the +nosimd extension. */ |
121 | #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) | |
122 | #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) | |
43e9d192 IB |
123 | |
124 | #define UNITS_PER_WORD 8 | |
125 | ||
126 | #define UNITS_PER_VREG 16 | |
127 | ||
128 | #define PARM_BOUNDARY 64 | |
129 | ||
130 | #define STACK_BOUNDARY 128 | |
131 | ||
132 | #define FUNCTION_BOUNDARY 32 | |
133 | ||
134 | #define EMPTY_FIELD_BOUNDARY 32 | |
135 | ||
136 | #define BIGGEST_ALIGNMENT 128 | |
137 | ||
138 | #define SHORT_TYPE_SIZE 16 | |
139 | ||
140 | #define INT_TYPE_SIZE 32 | |
141 | ||
17a819cb YZ |
142 | #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) |
143 | ||
144 | #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) | |
43e9d192 IB |
145 | |
146 | #define LONG_LONG_TYPE_SIZE 64 | |
147 | ||
148 | #define FLOAT_TYPE_SIZE 32 | |
149 | ||
150 | #define DOUBLE_TYPE_SIZE 64 | |
151 | ||
152 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
153 | ||
154 | /* The architecture reserves all bits of the address for hardware use, | |
155 | so the vbit must go into the delta field of pointers to member | |
156 | functions. This is the same config as that in the AArch32 | |
157 | port. */ | |
158 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
159 | ||
160 | /* Make strings word-aligned so that strcpy from constants will be | |
161 | faster. */ | |
162 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
163 | ((TREE_CODE (EXP) == STRING_CST \ | |
164 | && !optimize_size \ | |
165 | && (ALIGN) < BITS_PER_WORD) \ | |
166 | ? BITS_PER_WORD : ALIGN) | |
167 | ||
168 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
169 | ((((ALIGN) < BITS_PER_WORD) \ | |
170 | && (TREE_CODE (EXP) == ARRAY_TYPE \ | |
171 | || TREE_CODE (EXP) == UNION_TYPE \ | |
172 | || TREE_CODE (EXP) == RECORD_TYPE)) \ | |
173 | ? BITS_PER_WORD : (ALIGN)) | |
174 | ||
175 | #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) | |
176 | ||
177 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
178 | ||
179 | /* Defined by the ABI */ | |
180 | #define WCHAR_TYPE "unsigned int" | |
181 | #define WCHAR_TYPE_SIZE 32 | |
182 | ||
183 | /* Using long long breaks -ansi and -std=c90, so these will need to be | |
184 | made conditional for an LLP64 ABI. */ | |
185 | ||
186 | #define SIZE_TYPE "long unsigned int" | |
187 | ||
188 | #define PTRDIFF_TYPE "long int" | |
189 | ||
190 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
191 | ||
0c6caaf8 RL |
192 | /* Major revision number of the ARM Architecture implemented by the target. */ |
193 | extern unsigned aarch64_architecture_version; | |
43e9d192 IB |
194 | |
195 | /* Instruction tuning/selection flags. */ | |
196 | ||
197 | /* Bit values used to identify processor capabilities. */ | |
198 | #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ | |
199 | #define AARCH64_FL_FP (1 << 1) /* Has FP. */ | |
200 | #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ | |
201 | #define AARCH64_FL_SLOWMUL (1 << 3) /* A slow multiply core. */ | |
5922847b | 202 | #define AARCH64_FL_CRC (1 << 4) /* Has CRC. */ |
43e9d192 IB |
203 | |
204 | /* Has FP and SIMD. */ | |
205 | #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) | |
206 | ||
207 | /* Has FP without SIMD. */ | |
208 | #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) | |
209 | ||
210 | /* Architecture flags that effect instruction selection. */ | |
211 | #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) | |
212 | ||
213 | /* Macros to test ISA flags. */ | |
214 | extern unsigned long aarch64_isa_flags; | |
5922847b | 215 | #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) |
43e9d192 IB |
216 | #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) |
217 | #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) | |
218 | #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) | |
219 | ||
220 | /* Macros to test tuning flags. */ | |
221 | extern unsigned long aarch64_tune_flags; | |
222 | #define AARCH64_TUNE_SLOWMUL (aarch64_tune_flags & AARCH64_FL_SLOWMUL) | |
223 | ||
683e3333 KT |
224 | /* Crypto is an optional extension to AdvSIMD. */ |
225 | #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) | |
43e9d192 | 226 | |
5d357f26 KT |
227 | /* CRC instructions that can be enabled through +crc arch extension. */ |
228 | #define TARGET_CRC32 (AARCH64_ISA_CRC) | |
229 | ||
43e9d192 IB |
230 | /* Standard register usage. */ |
231 | ||
232 | /* 31 64-bit general purpose registers R0-R30: | |
233 | R30 LR (link register) | |
234 | R29 FP (frame pointer) | |
235 | R19-R28 Callee-saved registers | |
236 | R18 The platform register; use as temporary register. | |
237 | R17 IP1 The second intra-procedure-call temporary register | |
238 | (can be used by call veneers and PLT code); otherwise use | |
239 | as a temporary register | |
240 | R16 IP0 The first intra-procedure-call temporary register (can | |
241 | be used by call veneers and PLT code); otherwise use as a | |
242 | temporary register | |
243 | R9-R15 Temporary registers | |
244 | R8 Structure value parameter / temporary register | |
245 | R0-R7 Parameter/result registers | |
246 | ||
247 | SP stack pointer, encoded as X/R31 where permitted. | |
248 | ZR zero register, encoded as X/R31 elsewhere | |
249 | ||
250 | 32 x 128-bit floating-point/vector registers | |
251 | V16-V31 Caller-saved (temporary) registers | |
252 | V8-V15 Callee-saved registers | |
253 | V0-V7 Parameter/result registers | |
254 | ||
255 | The vector register V0 holds scalar B0, H0, S0 and D0 in its least | |
256 | significant bits. Unlike AArch32 S1 is not packed into D0, | |
257 | etc. */ | |
258 | ||
259 | /* Note that we don't mark X30 as a call-clobbered register. The idea is | |
260 | that it's really the call instructions themselves which clobber X30. | |
261 | We don't care what the called function does with it afterwards. | |
262 | ||
263 | This approach makes it easier to implement sibcalls. Unlike normal | |
264 | calls, sibcalls don't clobber X30, so the register reaches the | |
265 | called function intact. EPILOGUE_USES says that X30 is useful | |
266 | to the called function. */ | |
267 | ||
268 | #define FIXED_REGISTERS \ | |
269 | { \ | |
270 | 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ | |
271 | 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ | |
272 | 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
273 | 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ | |
274 | 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ | |
275 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
276 | 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ | |
277 | 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ | |
278 | 1, 1, 1, /* SFP, AP, CC */ \ | |
279 | } | |
280 | ||
281 | #define CALL_USED_REGISTERS \ | |
282 | { \ | |
283 | 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ | |
284 | 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ | |
285 | 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ | |
1c923b60 | 286 | 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ |
43e9d192 IB |
287 | 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ |
288 | 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ | |
289 | 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ | |
290 | 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ | |
291 | 1, 1, 1, /* SFP, AP, CC */ \ | |
292 | } | |
293 | ||
294 | #define REGISTER_NAMES \ | |
295 | { \ | |
296 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ | |
297 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ | |
298 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ | |
299 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ | |
300 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ | |
301 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ | |
302 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ | |
303 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ | |
304 | "sfp", "ap", "cc", \ | |
305 | } | |
306 | ||
307 | /* Generate the register aliases for core register N */ | |
308 | #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ | |
309 | {"w" # N, R0_REGNUM + (N)} | |
310 | ||
311 | #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ | |
312 | {"d" # N, V0_REGNUM + (N)}, \ | |
313 | {"s" # N, V0_REGNUM + (N)}, \ | |
314 | {"h" # N, V0_REGNUM + (N)}, \ | |
315 | {"b" # N, V0_REGNUM + (N)} | |
316 | ||
317 | /* Provide aliases for all of the ISA defined register name forms. | |
318 | These aliases are convenient for use in the clobber lists of inline | |
319 | asm statements. */ | |
320 | ||
321 | #define ADDITIONAL_REGISTER_NAMES \ | |
322 | { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ | |
323 | R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ | |
324 | R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ | |
325 | R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ | |
326 | R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ | |
327 | R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ | |
328 | R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ | |
9259db42 | 329 | R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ |
43e9d192 IB |
330 | V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ |
331 | V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ | |
332 | V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ | |
333 | V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ | |
334 | V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ | |
335 | V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ | |
336 | V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ | |
337 | V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ | |
338 | } | |
339 | ||
340 | /* Say that the epilogue uses the return address register. Note that | |
341 | in the case of sibcalls, the values "used by the epilogue" are | |
342 | considered live at the start of the called function. */ | |
343 | ||
344 | #define EPILOGUE_USES(REGNO) \ | |
1c923b60 | 345 | (epilogue_completed && (REGNO) == LR_REGNUM) |
43e9d192 IB |
346 | |
347 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
348 | the stack pointer does not matter. The value is tested only in | |
349 | functions that have frame pointers. */ | |
350 | #define EXIT_IGNORE_STACK 1 | |
351 | ||
352 | #define STATIC_CHAIN_REGNUM R18_REGNUM | |
353 | #define HARD_FRAME_POINTER_REGNUM R29_REGNUM | |
354 | #define FRAME_POINTER_REGNUM SFP_REGNUM | |
355 | #define STACK_POINTER_REGNUM SP_REGNUM | |
356 | #define ARG_POINTER_REGNUM AP_REGNUM | |
357 | #define FIRST_PSEUDO_REGISTER 67 | |
358 | ||
359 | /* The number of (integer) argument register available. */ | |
360 | #define NUM_ARG_REGS 8 | |
361 | #define NUM_FP_ARG_REGS 8 | |
362 | ||
363 | /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most | |
364 | four members. */ | |
365 | #define HA_MAX_NUM_FLDS 4 | |
366 | ||
367 | /* External dwarf register number scheme. These number are used to | |
368 | identify registers in dwarf debug information, the values are | |
369 | defined by the AArch64 ABI. The numbering scheme is independent of | |
370 | GCC's internal register numbering scheme. */ | |
371 | ||
372 | #define AARCH64_DWARF_R0 0 | |
373 | ||
374 | /* The number of R registers, note 31! not 32. */ | |
375 | #define AARCH64_DWARF_NUMBER_R 31 | |
376 | ||
377 | #define AARCH64_DWARF_SP 31 | |
378 | #define AARCH64_DWARF_V0 64 | |
379 | ||
380 | /* The number of V registers. */ | |
381 | #define AARCH64_DWARF_NUMBER_V 32 | |
382 | ||
383 | /* For signal frames we need to use an alternative return column. This | |
384 | value must not correspond to a hard register and must be out of the | |
385 | range of DWARF_FRAME_REGNUM(). */ | |
386 | #define DWARF_ALT_FRAME_RETURN_COLUMN \ | |
387 | (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) | |
388 | ||
389 | /* We add 1 extra frame register for use as the | |
390 | DWARF_ALT_FRAME_RETURN_COLUMN. */ | |
391 | #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) | |
392 | ||
393 | ||
394 | #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) | |
395 | /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders | |
396 | can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same | |
397 | as the default definition in dwarf2out.c. */ | |
398 | #undef DWARF_FRAME_REGNUM | |
399 | #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) | |
400 | ||
401 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
402 | ||
403 | #define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE) | |
404 | ||
405 | #define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE) | |
406 | ||
97e1ad78 | 407 | #define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2) |
43e9d192 IB |
408 | |
409 | #define DWARF2_UNWIND_INFO 1 | |
410 | ||
411 | /* Use R0 through R3 to pass exception handling information. */ | |
412 | #define EH_RETURN_DATA_REGNO(N) \ | |
413 | ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) | |
414 | ||
415 | /* Select a format to encode pointers in exception handling data. */ | |
416 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
417 | aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) | |
418 | ||
419 | /* The register that holds the return address in exception handlers. */ | |
420 | #define AARCH64_EH_STACKADJ_REGNUM (R0_REGNUM + 4) | |
421 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM) | |
422 | ||
423 | /* Don't use __builtin_setjmp until we've defined it. */ | |
424 | #undef DONT_USE_BUILTIN_SETJMP | |
425 | #define DONT_USE_BUILTIN_SETJMP 1 | |
426 | ||
427 | /* Register in which the structure value is to be returned. */ | |
428 | #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM | |
429 | ||
430 | /* Non-zero if REGNO is part of the Core register set. | |
431 | ||
432 | The rather unusual way of expressing this check is to avoid | |
433 | warnings when building the compiler when R0_REGNUM is 0 and REGNO | |
434 | is unsigned. */ | |
435 | #define GP_REGNUM_P(REGNO) \ | |
436 | (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) | |
437 | ||
438 | #define FP_REGNUM_P(REGNO) \ | |
439 | (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) | |
440 | ||
441 | #define FP_LO_REGNUM_P(REGNO) \ | |
442 | (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) | |
443 | ||
444 | \f | |
445 | /* Register and constant classes. */ | |
446 | ||
447 | enum reg_class | |
448 | { | |
449 | NO_REGS, | |
fee9ba42 | 450 | CALLER_SAVE_REGS, |
43e9d192 IB |
451 | GENERAL_REGS, |
452 | STACK_REG, | |
453 | POINTER_REGS, | |
454 | FP_LO_REGS, | |
455 | FP_REGS, | |
456 | ALL_REGS, | |
457 | LIM_REG_CLASSES /* Last */ | |
458 | }; | |
459 | ||
460 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
461 | ||
462 | #define REG_CLASS_NAMES \ | |
463 | { \ | |
464 | "NO_REGS", \ | |
fee9ba42 | 465 | "CALLER_SAVE_REGS", \ |
43e9d192 IB |
466 | "GENERAL_REGS", \ |
467 | "STACK_REG", \ | |
468 | "POINTER_REGS", \ | |
469 | "FP_LO_REGS", \ | |
470 | "FP_REGS", \ | |
471 | "ALL_REGS" \ | |
472 | } | |
473 | ||
474 | #define REG_CLASS_CONTENTS \ | |
475 | { \ | |
476 | { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
fee9ba42 | 477 | { 0x0007ffff, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ |
43e9d192 IB |
478 | { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ |
479 | { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
480 | { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ | |
481 | { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ | |
482 | { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ | |
483 | { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ | |
484 | } | |
485 | ||
486 | #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) | |
487 | ||
a4a182c6 | 488 | #define INDEX_REG_CLASS GENERAL_REGS |
43e9d192 IB |
489 | #define BASE_REG_CLASS POINTER_REGS |
490 | ||
6991c977 | 491 | /* Register pairs used to eliminate unneeded registers that point into |
43e9d192 IB |
492 | the stack frame. */ |
493 | #define ELIMINABLE_REGS \ | |
494 | { \ | |
495 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
496 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
497 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
498 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
499 | } | |
500 | ||
501 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
502 | (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) | |
503 | ||
504 | /* CPU/ARCH option handling. */ | |
505 | #include "config/aarch64/aarch64-opts.h" | |
506 | ||
507 | enum target_cpus | |
508 | { | |
d86cb6d5 | 509 | #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS) \ |
192ed1dd | 510 | TARGET_CPU_##INTERNAL_IDENT, |
43e9d192 IB |
511 | #include "aarch64-cores.def" |
512 | #undef AARCH64_CORE | |
513 | TARGET_CPU_generic | |
514 | }; | |
515 | ||
a3cd0246 | 516 | /* If there is no CPU defined at configure, use generic as default. */ |
43e9d192 IB |
517 | #ifndef TARGET_CPU_DEFAULT |
518 | #define TARGET_CPU_DEFAULT \ | |
a3cd0246 | 519 | (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) |
43e9d192 IB |
520 | #endif |
521 | ||
75cf1494 KT |
522 | /* If inserting NOP before a mult-accumulate insn remember to adjust the |
523 | length so that conditional branching code is updated appropriately. */ | |
524 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
8baff86e KT |
525 | do \ |
526 | { \ | |
527 | if (aarch64_madd_needs_nop (insn)) \ | |
528 | length += 4; \ | |
529 | } while (0) | |
75cf1494 KT |
530 | |
531 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
532 | aarch64_final_prescan_insn (INSN); \ | |
533 | ||
43e9d192 IB |
534 | /* The processor for which instructions should be scheduled. */ |
535 | extern enum aarch64_processor aarch64_tune; | |
536 | ||
537 | /* RTL generation support. */ | |
538 | #define INIT_EXPANDERS aarch64_init_expanders () | |
539 | \f | |
540 | ||
541 | /* Stack layout; function entry, exit and calling. */ | |
542 | #define STACK_GROWS_DOWNWARD 1 | |
543 | ||
6991c977 | 544 | #define FRAME_GROWS_DOWNWARD 1 |
43e9d192 IB |
545 | |
546 | #define STARTING_FRAME_OFFSET 0 | |
547 | ||
548 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
549 | ||
550 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
551 | ||
552 | /* Fix for VFP */ | |
553 | #define LIBCALL_VALUE(MODE) \ | |
554 | gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) | |
555 | ||
556 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
557 | ||
558 | #define AARCH64_ROUND_UP(X, ALIGNMENT) \ | |
559 | (((X) + ((ALIGNMENT) - 1)) & ~((ALIGNMENT) - 1)) | |
560 | ||
561 | #define AARCH64_ROUND_DOWN(X, ALIGNMENT) \ | |
562 | ((X) & ~((ALIGNMENT) - 1)) | |
563 | ||
564 | #ifdef HOST_WIDE_INT | |
565 | struct GTY (()) aarch64_frame | |
566 | { | |
567 | HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; | |
8799637a MS |
568 | |
569 | /* The number of extra stack bytes taken up by register varargs. | |
570 | This area is allocated by the callee at the very top of the | |
571 | frame. This value is rounded up to a multiple of | |
572 | STACK_BOUNDARY. */ | |
573 | HOST_WIDE_INT saved_varargs_size; | |
574 | ||
43e9d192 IB |
575 | HOST_WIDE_INT saved_regs_size; |
576 | /* Padding if needed after the all the callee save registers have | |
577 | been saved. */ | |
578 | HOST_WIDE_INT padding0; | |
579 | HOST_WIDE_INT hardfp_offset; /* HARD_FRAME_POINTER_REGNUM */ | |
43e9d192 | 580 | |
1c960e02 MS |
581 | /* Offset from the base of the frame (incomming SP) to the |
582 | hard_frame_pointer. This value is always a multiple of | |
583 | STACK_BOUNDARY. */ | |
584 | HOST_WIDE_INT hard_fp_offset; | |
585 | ||
586 | /* The size of the frame. This value is the offset from base of the | |
587 | * frame (incomming SP) to the stack_pointer. This value is always | |
588 | * a multiple of STACK_BOUNDARY. */ | |
589 | ||
363ffa50 JW |
590 | unsigned wb_candidate1; |
591 | unsigned wb_candidate2; | |
592 | ||
1c960e02 MS |
593 | HOST_WIDE_INT frame_size; |
594 | ||
43e9d192 IB |
595 | bool laid_out; |
596 | }; | |
597 | ||
598 | typedef struct GTY (()) machine_function | |
599 | { | |
600 | struct aarch64_frame frame; | |
43e9d192 IB |
601 | } machine_function; |
602 | #endif | |
603 | ||
17a819cb YZ |
604 | /* Which ABI to use. */ |
605 | enum aarch64_abi_type | |
606 | { | |
607 | AARCH64_ABI_LP64 = 0, | |
608 | AARCH64_ABI_ILP32 = 1 | |
609 | }; | |
610 | ||
611 | #ifndef AARCH64_ABI_DEFAULT | |
612 | #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 | |
613 | #endif | |
614 | ||
615 | #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) | |
43e9d192 | 616 | |
43e9d192 IB |
617 | enum arm_pcs |
618 | { | |
619 | ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ | |
620 | ARM_PCS_UNKNOWN | |
621 | }; | |
622 | ||
623 | ||
43e9d192 | 624 | |
43e9d192 | 625 | |
ef4bddc2 | 626 | /* We can't use machine_mode inside a generator file because it |
43e9d192 IB |
627 | hasn't been created yet; we shouldn't be using any code that |
628 | needs the real definition though, so this ought to be safe. */ | |
629 | #ifdef GENERATOR_FILE | |
630 | #define MACHMODE int | |
631 | #else | |
632 | #include "insn-modes.h" | |
febd3244 | 633 | #define MACHMODE machine_mode |
43e9d192 IB |
634 | #endif |
635 | ||
febd3244 | 636 | #ifndef USED_FOR_TARGET |
43e9d192 IB |
637 | /* AAPCS related state tracking. */ |
638 | typedef struct | |
639 | { | |
640 | enum arm_pcs pcs_variant; | |
641 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
642 | int aapcs_ncrn; /* Next Core register number. */ | |
643 | int aapcs_nextncrn; /* Next next core register number. */ | |
644 | int aapcs_nvrn; /* Next Vector register number. */ | |
645 | int aapcs_nextnvrn; /* Next Next Vector register number. */ | |
646 | rtx aapcs_reg; /* Register assigned to this argument. This | |
647 | is NULL_RTX if this parameter goes on | |
648 | the stack. */ | |
649 | MACHMODE aapcs_vfp_rmode; | |
650 | int aapcs_stack_words; /* If the argument is passed on the stack, this | |
651 | is the number of words needed, after rounding | |
652 | up. Only meaningful when | |
653 | aapcs_reg == NULL_RTX. */ | |
654 | int aapcs_stack_size; /* The total size (in words, per 8 byte) of the | |
655 | stack arg area so far. */ | |
656 | } CUMULATIVE_ARGS; | |
febd3244 | 657 | #endif |
43e9d192 IB |
658 | |
659 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
660 | (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward) | |
661 | ||
662 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ | |
663 | (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) | |
664 | ||
665 | #define PAD_VARARGS_DOWN 0 | |
666 | ||
667 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
668 | aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) | |
669 | ||
670 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
671 | aarch64_function_arg_regno_p(REGNO) | |
672 | \f | |
673 | ||
674 | /* ISA Features. */ | |
675 | ||
676 | /* Addressing modes, etc. */ | |
677 | #define HAVE_POST_INCREMENT 1 | |
678 | #define HAVE_PRE_INCREMENT 1 | |
679 | #define HAVE_POST_DECREMENT 1 | |
680 | #define HAVE_PRE_DECREMENT 1 | |
681 | #define HAVE_POST_MODIFY_DISP 1 | |
682 | #define HAVE_PRE_MODIFY_DISP 1 | |
683 | ||
684 | #define MAX_REGS_PER_ADDRESS 2 | |
685 | ||
686 | #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) | |
687 | ||
688 | /* Try a machine-dependent way of reloading an illegitimate address | |
689 | operand. If we find one, push the reload and jump to WIN. This | |
690 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
691 | ||
692 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ | |
693 | do { \ | |
694 | rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \ | |
695 | IND_L); \ | |
696 | if (new_x) \ | |
697 | { \ | |
698 | X = new_x; \ | |
699 | goto WIN; \ | |
700 | } \ | |
701 | } while (0) | |
702 | ||
703 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
704 | aarch64_regno_ok_for_base_p (REGNO, true) | |
705 | ||
706 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
707 | aarch64_regno_ok_for_index_p (REGNO, true) | |
708 | ||
709 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
710 | aarch64_legitimate_pic_operand_p (X) | |
711 | ||
712 | #define CASE_VECTOR_MODE Pmode | |
713 | ||
714 | #define DEFAULT_SIGNED_CHAR 0 | |
715 | ||
716 | /* An integer expression for the size in bits of the largest integer machine | |
717 | mode that should actually be used. We allow pairs of registers. */ | |
718 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
719 | ||
720 | /* Maximum bytes moved by a single instruction (load/store pair). */ | |
721 | #define MOVE_MAX (UNITS_PER_WORD * 2) | |
722 | ||
723 | /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ | |
724 | #define AARCH64_CALL_RATIO 8 | |
725 | ||
e2c75eea JG |
726 | /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. |
727 | move_by_pieces will continually copy the largest safe chunks. So a | |
728 | 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient | |
729 | for both size and speed of copy, so we will instead use the "movmem" | |
730 | standard name to implement the copy. This logic does not apply when | |
731 | targeting -mstrict-align, so keep a sensible default in that case. */ | |
43e9d192 | 732 | #define MOVE_RATIO(speed) \ |
e2c75eea | 733 | (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) |
43e9d192 IB |
734 | |
735 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate | |
736 | of the length of a memset call, but use the default otherwise. */ | |
737 | #define CLEAR_RATIO(speed) \ | |
738 | ((speed) ? 15 : AARCH64_CALL_RATIO) | |
739 | ||
740 | /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
741 | optimizing for size adjust the ratio to account for the overhead of loading | |
742 | the constant. */ | |
743 | #define SET_RATIO(speed) \ | |
744 | ((speed) ? 15 : AARCH64_CALL_RATIO - 2) | |
745 | ||
43e9d192 IB |
746 | /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is |
747 | rarely a good idea in straight-line code since it adds an extra address | |
748 | dependency between each instruction. Better to use incrementing offsets. */ | |
749 | #define USE_LOAD_POST_INCREMENT(MODE) 0 | |
750 | #define USE_LOAD_POST_DECREMENT(MODE) 0 | |
751 | #define USE_LOAD_PRE_INCREMENT(MODE) 0 | |
752 | #define USE_LOAD_PRE_DECREMENT(MODE) 0 | |
753 | #define USE_STORE_POST_INCREMENT(MODE) 0 | |
754 | #define USE_STORE_POST_DECREMENT(MODE) 0 | |
755 | #define USE_STORE_PRE_INCREMENT(MODE) 0 | |
756 | #define USE_STORE_PRE_DECREMENT(MODE) 0 | |
757 | ||
758 | /* ?? #define WORD_REGISTER_OPERATIONS */ | |
759 | ||
760 | /* Define if loading from memory in MODE, an integral mode narrower than | |
761 | BITS_PER_WORD will either zero-extend or sign-extend. The value of this | |
762 | macro should be the code that says which one of the two operations is | |
763 | implicitly done, or UNKNOWN if none. */ | |
764 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
765 | ||
766 | /* Define this macro to be non-zero if instructions will fail to work | |
767 | if given data not on the nominal alignment. */ | |
768 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN | |
769 | ||
770 | /* Define this macro to be non-zero if accessing less than a word of | |
771 | memory is no faster than accessing a word of memory, i.e., if such | |
772 | accesses require more than one instruction or if there is no | |
773 | difference in cost. | |
774 | Although there's no difference in instruction count or cycles, | |
775 | in AArch64 we don't want to expand to a sub-word to a 64-bit access | |
776 | if we don't have to, for power-saving reasons. */ | |
777 | #define SLOW_BYTE_ACCESS 0 | |
778 | ||
779 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
780 | ||
781 | #define NO_FUNCTION_CSE 1 | |
782 | ||
17a819cb YZ |
783 | /* Specify the machine mode that the hardware addresses have. |
784 | After generation of rtl, the compiler makes no further distinction | |
785 | between pointers and any other objects of this machine mode. */ | |
43e9d192 | 786 | #define Pmode DImode |
17a819cb YZ |
787 | |
788 | /* A C expression whose value is zero if pointers that need to be extended | |
789 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
790 | greater then zero if they are zero-extended and less then zero if the | |
791 | ptr_extend instruction should be used. */ | |
792 | #define POINTERS_EXTEND_UNSIGNED 1 | |
793 | ||
794 | /* Mode of a function address in a call instruction (for indexing purposes). */ | |
43e9d192 IB |
795 | #define FUNCTION_MODE Pmode |
796 | ||
797 | #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) | |
798 | ||
f8bf91ab N |
799 | #define REVERSIBLE_CC_MODE(MODE) 1 |
800 | ||
43e9d192 IB |
801 | #define REVERSE_CONDITION(CODE, MODE) \ |
802 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
803 | ? reverse_condition_maybe_unordered (CODE) \ | |
804 | : reverse_condition (CODE)) | |
805 | ||
806 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
952e7819 | 807 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
43e9d192 | 808 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
952e7819 | 809 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
43e9d192 IB |
810 | |
811 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) | |
812 | ||
813 | #define RETURN_ADDR_RTX aarch64_return_addr | |
814 | ||
28514dda YZ |
815 | /* 3 insns + padding + 2 pointer-sized entries. */ |
816 | #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) | |
43e9d192 IB |
817 | |
818 | /* Trampolines contain dwords, so must be dword aligned. */ | |
819 | #define TRAMPOLINE_ALIGNMENT 64 | |
820 | ||
821 | /* Put trampolines in the text section so that mapping symbols work | |
822 | correctly. */ | |
823 | #define TRAMPOLINE_SECTION text_section | |
43e9d192 IB |
824 | |
825 | /* To start with. */ | |
826 | #define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2 | |
827 | \f | |
828 | ||
829 | /* Assembly output. */ | |
830 | ||
831 | /* For now we'll make all jump tables pc-relative. */ | |
832 | #define CASE_VECTOR_PC_RELATIVE 1 | |
833 | ||
834 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
835 | ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ | |
836 | : (min < -0x1f0 || max > 0x1f0) ? HImode \ | |
837 | : QImode) | |
838 | ||
839 | /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ | |
840 | #define ADDR_VEC_ALIGN(JUMPTABLE) 0 | |
841 | ||
842 | #define PRINT_OPERAND(STREAM, X, CODE) aarch64_print_operand (STREAM, X, CODE) | |
843 | ||
844 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
845 | aarch64_print_operand_address (STREAM, X) | |
846 | ||
92d649c4 VK |
847 | #define MCOUNT_NAME "_mcount" |
848 | ||
849 | #define NO_PROFILE_COUNTERS 1 | |
850 | ||
851 | /* Emit rtl for profiling. Output assembler code to FILE | |
852 | to call "_mcount" for profiling a function entry. */ | |
3294102b MS |
853 | #define PROFILE_HOOK(LABEL) \ |
854 | { \ | |
855 | rtx fun, lr; \ | |
856 | lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ | |
857 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ | |
858 | emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ | |
859 | } | |
92d649c4 VK |
860 | |
861 | /* All the work done in PROFILE_HOOK, but still required. */ | |
862 | #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) | |
43e9d192 IB |
863 | |
864 | /* For some reason, the Linux headers think they know how to define | |
865 | these macros. They don't!!! */ | |
866 | #undef ASM_APP_ON | |
867 | #undef ASM_APP_OFF | |
868 | #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" | |
869 | #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" | |
870 | ||
43e9d192 IB |
871 | #define CONSTANT_POOL_BEFORE_FUNCTION 0 |
872 | ||
873 | /* This definition should be relocated to aarch64-elf-raw.h. This macro | |
874 | should be undefined in aarch64-linux.h and a clear_cache pattern | |
875 | implmented to emit either the call to __aarch64_sync_cache_range() | |
876 | directly or preferably the appropriate sycall or cache clear | |
877 | instructions inline. */ | |
878 | #define CLEAR_INSN_CACHE(beg, end) \ | |
879 | extern void __aarch64_sync_cache_range (void *, void *); \ | |
880 | __aarch64_sync_cache_range (beg, end) | |
881 | ||
43e9d192 IB |
882 | #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD |
883 | ||
73d9ac6a IB |
884 | /* Choose appropriate mode for caller saves, so we do the minimum |
885 | required size of load/store. */ | |
886 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
887 | aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) | |
888 | ||
43e9d192 IB |
889 | /* Callee only saves lower 64-bits of a 128-bit register. Tell the |
890 | compiler the callee clobbers the top 64-bits when restoring the | |
891 | bottom 64-bits. */ | |
892 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
893 | (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8) | |
894 | ||
895 | /* Check TLS Descriptors mechanism is selected. */ | |
896 | #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) | |
897 | ||
898 | extern enum aarch64_code_model aarch64_cmodel; | |
899 | ||
900 | /* When using the tiny addressing model conditional and unconditional branches | |
901 | can span the whole of the available address space (1MB). */ | |
902 | #define HAS_LONG_COND_BRANCH \ | |
903 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
904 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
905 | ||
906 | #define HAS_LONG_UNCOND_BRANCH \ | |
907 | (aarch64_cmodel == AARCH64_CMODEL_TINY \ | |
908 | || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) | |
909 | ||
910 | /* Modes valid for AdvSIMD Q registers. */ | |
911 | #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ | |
912 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
913 | || (MODE) == V4SFmode || (MODE) == V2DImode || mode == V2DFmode) | |
914 | ||
e58bf20a TB |
915 | #define ENDIAN_LANE_N(mode, n) \ |
916 | (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) | |
917 | ||
9815fafa RE |
918 | /* Support for a configure-time default CPU, etc. We currently support |
919 | --with-arch and --with-cpu. Both are ignored if either is specified | |
920 | explicitly on the command line at run time. */ | |
921 | #define OPTION_DEFAULT_SPECS \ | |
922 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
923 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, | |
924 | ||
682287fb | 925 | #define BIG_LITTLE_SPEC \ |
1c05df59 | 926 | " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" |
682287fb JG |
927 | |
928 | extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); | |
929 | #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ | |
930 | { "rewrite_mcpu", aarch64_rewrite_mcpu }, | |
931 | ||
932 | #define ASM_CPU_SPEC \ | |
933 | BIG_LITTLE_SPEC | |
934 | ||
935 | #define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS | |
936 | ||
937 | #define EXTRA_SPECS \ | |
938 | { "asm_cpu_spec", ASM_CPU_SPEC } | |
939 | ||
43e9d192 | 940 | #endif /* GCC_AARCH64_H */ |