[thirdparty/gcc.git] / gcc / config / aarch64 / aarch64.opt

; Machine description for AArch64 architecture.
; Copyright (C) 2009-2020 Free Software Foundation, Inc.
; Contributed by ARM Ltd.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3, or (at your option)
; any later version.
;
; GCC is distributed in the hope that it will be useful, but
; WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
; General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

HeaderInclude
config/aarch64/aarch64-opts.h

TargetVariable
enum aarch64_processor explicit_tune_core = aarch64_none

TargetVariable
enum aarch64_arch explicit_arch = aarch64_no_arch

TargetSave
const char *x_aarch64_override_tune_string

TargetVariable
uint64_t aarch64_isa_flags = 0

TargetVariable
unsigned aarch64_enable_bti = 2

; The TLS dialect names to use with -mtls-dialect.

Enum
Name(tls_type) Type(enum aarch64_tls_type)
The possible TLS dialects:

EnumValue
Enum(tls_type) String(trad) Value(TLS_TRADITIONAL)

EnumValue
Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS)

; The code model option names for -mcmodel.

Enum
Name(cmodel) Type(enum aarch64_code_model)
The code model option names for -mcmodel:

EnumValue
Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY)

EnumValue
Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL)

EnumValue
Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE)

mbig-endian
Target Report RejectNegative Mask(BIG_END)
Assume target CPU is configured as big endian.

mgeneral-regs-only
Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save
Generate code which uses only the general registers.

mfix-cortex-a53-835769
Target Report Var(aarch64_fix_a53_err835769) Init(2) Save
Workaround for ARM Cortex-A53 Erratum number 835769.

mfix-cortex-a53-843419
Target Report Var(aarch64_fix_a53_err843419) Init(2) Save
Workaround for ARM Cortex-A53 Erratum number 843419.

mlittle-endian
Target Report RejectNegative InverseMask(BIG_END)
Assume target CPU is configured as little endian.

mcmodel=
Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save
Specify the code model.

mstrict-align
Target Report Mask(STRICT_ALIGN) Save
Don't assume that unaligned accesses are handled by the system.

momit-leaf-frame-pointer
Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save
Omit the frame pointer in leaf functions.

mtls-dialect=
Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save
Specify TLS dialect.

mtls-size=
Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size)
Specifies bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48.

Enum
Name(aarch64_tls_size) Type(int)

EnumValue
Enum(aarch64_tls_size) String(12) Value(12)

EnumValue
Enum(aarch64_tls_size) String(24) Value(24)

EnumValue
Enum(aarch64_tls_size) String(32) Value(32)

EnumValue
Enum(aarch64_tls_size) String(48) Value(48)

march=
Target RejectNegative Negative(march=) ToLower Joined Var(aarch64_arch_string)
Use features of architecture ARCH.

mcpu=
Target RejectNegative Negative(mcpu=) ToLower Joined Var(aarch64_cpu_string)
Use features of and optimize for CPU.

mtune=
Target RejectNegative Negative(mtune=) ToLower Joined Var(aarch64_tune_string)
Optimize for CPU.

mabi=
Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT)
Generate code that conforms to the specified ABI.

moverride=
Target RejectNegative ToLower Joined Var(aarch64_override_tune_string)
-moverride=<string>	Power users only! Override CPU optimization parameters.

Enum
Name(aarch64_abi) Type(int)
Known AArch64 ABIs (for use with the -mabi= option):

EnumValue
Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32)

EnumValue
Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)

mpc-relative-literal-loads
Target Report Save Var(pcrelative_literal_loads) Init(2) Save
PC relative literal loads.

mbranch-protection=
Target RejectNegative Joined Var(aarch64_branch_protection_string) Save
Use branch-protection features.

msign-return-address=
Target WarnRemoved RejectNegative Joined Enum(aarch64_ra_sign_scope_t) Var(aarch64_ra_sign_scope) Init(AARCH64_FUNCTION_NONE) Save
Select return address signing scope.

Enum
Name(aarch64_ra_sign_scope_t) Type(enum aarch64_function_type)
Supported AArch64 return address signing scope (for use with -msign-return-address= option):

EnumValue
Enum(aarch64_ra_sign_scope_t) String(none) Value(AARCH64_FUNCTION_NONE)

EnumValue
Enum(aarch64_ra_sign_scope_t) String(non-leaf) Value(AARCH64_FUNCTION_NON_LEAF)

EnumValue
Enum(aarch64_ra_sign_scope_t) String(all) Value(AARCH64_FUNCTION_ALL)

mlow-precision-recip-sqrt
Target Var(flag_mrecip_low_precision_sqrt) Optimization
Enable the reciprocal square root approximation.  Enabling this reduces
precision of reciprocal square root results to about 16 bits for
single precision and to 32 bits for double precision.

mlow-precision-sqrt
Target Var(flag_mlow_precision_sqrt) Optimization
Enable the square root approximation.  Enabling this reduces
precision of square root results to about 16 bits for
single precision and to 32 bits for double precision.
If enabled, it implies -mlow-precision-recip-sqrt.

mlow-precision-div
Target Var(flag_mlow_precision_div) Optimization
Enable the division approximation.  Enabling this reduces
precision of division results to about 16 bits for
single precision and to 32 bits for double precision.

Enum
Name(sve_vector_bits) Type(enum aarch64_sve_vector_bits_enum)
The possible SVE vector lengths:

EnumValue
Enum(sve_vector_bits) String(scalable) Value(SVE_SCALABLE)

EnumValue
Enum(sve_vector_bits) String(128) Value(SVE_128)

EnumValue
Enum(sve_vector_bits) String(256) Value(SVE_256)

EnumValue
Enum(sve_vector_bits) String(512) Value(SVE_512)

EnumValue
Enum(sve_vector_bits) String(1024) Value(SVE_1024)

EnumValue
Enum(sve_vector_bits) String(2048) Value(SVE_2048)

msve-vector-bits=
Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) Init(SVE_SCALABLE)
-msve-vector-bits=<number>	Set the number of bits in an SVE vector register.

mverbose-cost-dump
Target Undocumented Var(flag_aarch64_verbose_cost)
Enables verbose cost model dumping in the debug dump files.

mtrack-speculation
Target Var(aarch64_track_speculation)
Generate code to track when the CPU might be speculating incorrectly.

mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(aarch64_stack_protector_guard) Init(SSP_GLOBAL)
Use given stack-protector guard.

Enum
Name(stack_protector_guard) Type(enum stack_protector_guard)
Valid arguments to -mstack-protector-guard=:

EnumValue
Enum(stack_protector_guard) String(sysreg) Value(SSP_SYSREG)

EnumValue
Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)

mstack-protector-guard-reg=
Target Joined RejectNegative String Var(aarch64_stack_protector_guard_reg_str)
Use the system register specified on the command line as the stack protector
guard register. This option is for use with fstack-protector-strong and
not for use in user-land code.

mstack-protector-guard-offset=
Target Joined RejectNegative String Var(aarch64_stack_protector_guard_offset_str)
Use an immediate to offset from the stack protector guard register, sp_el0.
This option is for use with fstack-protector-strong and not for use in
user-land code.

TargetVariable
long aarch64_stack_protector_guard_offset = 0

moutline-atomics
Target Report Mask(OUTLINE_ATOMICS) Save
Generate local calls to out-of-line atomic operations.

-param=aarch64-sve-compare-costs=
Target Joined UInteger Var(aarch64_sve_compare_costs) Init(1) IntegerRange(0, 1) Param
When vectorizing for SVE, consider using unpacked vectors for smaller elements and use the cost model to pick the cheapest approach.  Also use the cost model to choose between SVE and Advanced SIMD vectorization.
Commit	Line	Data
43e9d192	1	; Machine description for AArch64 architecture.
8d9254fc	2	; Copyright (C) 2009-2020 Free Software Foundation, Inc.
43e9d192 IB	3	; Contributed by ARM Ltd.
	4	;
	5	; This file is part of GCC.
	6	;
	7	; GCC is free software; you can redistribute it and/or modify it
	8	; under the terms of the GNU General Public License as published by
	9	; the Free Software Foundation; either version 3, or (at your option)
	10	; any later version.
	11	;
	12	; GCC is distributed in the hope that it will be useful, but
	13	; WITHOUT ANY WARRANTY; without even the implied warranty of
	14	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	; General Public License for more details.
	16	;
	17	; You should have received a copy of the GNU General Public License
	18	; along with GCC; see the file COPYING3. If not see
	19	; <http://www.gnu.org/licenses/>.
	20
	21	HeaderInclude
	22	config/aarch64/aarch64-opts.h
	23
361fb3ee KT	24	TargetVariable
	25	enum aarch64_processor explicit_tune_core = aarch64_none
	26
	27	TargetVariable
	28	enum aarch64_arch explicit_arch = aarch64_no_arch
	29
	30	TargetSave
	31	const char *x_aarch64_override_tune_string
	32
	33	TargetVariable
28108a53	34	uint64_t aarch64_isa_flags = 0
361fb3ee	35
30afdf34 SD	36	TargetVariable
	37	unsigned aarch64_enable_bti = 2
	38
43e9d192 IB	39	; The TLS dialect names to use with -mtls-dialect.
	40
	41	Enum
	42	Name(tls_type) Type(enum aarch64_tls_type)
	43	The possible TLS dialects:
	44
	45	EnumValue
	46	Enum(tls_type) String(trad) Value(TLS_TRADITIONAL)
	47
	48	EnumValue
	49	Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS)
	50
	51	; The code model option names for -mcmodel.
	52
	53	Enum
	54	Name(cmodel) Type(enum aarch64_code_model)
	55	The code model option names for -mcmodel:
	56
	57	EnumValue
	58	Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY)
	59
	60	EnumValue
	61	Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL)
	62
	63	EnumValue
	64	Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE)
	65
43e9d192 IB	66	mbig-endian
43e9d192 IB	67	Target Report RejectNegative Mask(BIG_END)
a7b2e184	68	Assume target CPU is configured as big endian.
43e9d192 IB	69
43e9d192 IB	70	mgeneral-regs-only
361fb3ee	71	Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save
a7b2e184	72	Generate code which uses only the general registers.
43e9d192	73
75cf1494	74	mfix-cortex-a53-835769
361fb3ee	75	Target Report Var(aarch64_fix_a53_err835769) Init(2) Save
a7b2e184	76	Workaround for ARM Cortex-A53 Erratum number 835769.
75cf1494	77
bf05ef76	78	mfix-cortex-a53-843419
48bb1a55	79	Target Report Var(aarch64_fix_a53_err843419) Init(2) Save
a7b2e184	80	Workaround for ARM Cortex-A53 Erratum number 843419.
bf05ef76	81
43e9d192 IB	82	mlittle-endian
43e9d192 IB	83	Target Report RejectNegative InverseMask(BIG_END)
a7b2e184	84	Assume target CPU is configured as little endian.
43e9d192 IB	85
43e9d192 IB	86	mcmodel=
361fb3ee	87	Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save
a7b2e184	88	Specify the code model.
43e9d192 IB	89
43e9d192 IB	90	mstrict-align
675d044c	91	Target Report Mask(STRICT_ALIGN) Save
a7b2e184	92	Don't assume that unaligned accesses are handled by the system.
43e9d192 IB	93
43e9d192 IB	94	momit-leaf-frame-pointer
361fb3ee	95	Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save
a7b2e184	96	Omit the frame pointer in leaf functions.
43e9d192 IB	97
43e9d192 IB	98	mtls-dialect=
361fb3ee	99	Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save
a7b2e184	100	Specify TLS dialect.
43e9d192	101
5eee3c34 JW	102	mtls-size=
	103	Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size)
	104	Specifies bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48.
	105
	106	Enum
	107	Name(aarch64_tls_size) Type(int)
	108
	109	EnumValue
	110	Enum(aarch64_tls_size) String(12) Value(12)
	111
	112	EnumValue
	113	Enum(aarch64_tls_size) String(24) Value(24)
	114
	115	EnumValue
	116	Enum(aarch64_tls_size) String(32) Value(32)
	117
	118	EnumValue
	119	Enum(aarch64_tls_size) String(48) Value(48)
	120
43e9d192	121	march=
6fdbe419	122	Target RejectNegative Negative(march=) ToLower Joined Var(aarch64_arch_string)
266c2b54	123	Use features of architecture ARCH.
43e9d192 IB	124
43e9d192 IB	125	mcpu=
6fdbe419	126	Target RejectNegative Negative(mcpu=) ToLower Joined Var(aarch64_cpu_string)
266c2b54	127	Use features of and optimize for CPU.
43e9d192 IB	128
43e9d192 IB	129	mtune=
6fdbe419	130	Target RejectNegative Negative(mtune=) ToLower Joined Var(aarch64_tune_string)
266c2b54	131	Optimize for CPU.
17a819cb YZ	132
	133	mabi=
	134	Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT)
266c2b54	135	Generate code that conforms to the specified ABI.
17a819cb	136
8dec06f2 JG	137	moverride=
8dec06f2 JG	138	Target RejectNegative ToLower Joined Var(aarch64_override_tune_string)
266c2b54	139	-moverride=<string> Power users only! Override CPU optimization parameters.
8dec06f2	140
17a819cb YZ	141	Enum
	142	Name(aarch64_abi) Type(int)
	143	Known AArch64 ABIs (for use with the -mabi= option):
	144
	145	EnumValue
	146	Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32)
	147
	148	EnumValue
	149	Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
b4f50fd4 RR	150
b4f50fd4 RR	151	mpc-relative-literal-loads
9ee6540a	152	Target Report Save Var(pcrelative_literal_loads) Init(2) Save
b4f50fd4	153	PC relative literal loads.
a6fc00da	154
efac62a3 ST	155	mbranch-protection=
	156	Target RejectNegative Joined Var(aarch64_branch_protection_string) Save
	157	Use branch-protection features.
	158
db58fd89	159	msign-return-address=
68a57628	160	Target WarnRemoved RejectNegative Joined Enum(aarch64_ra_sign_scope_t) Var(aarch64_ra_sign_scope) Init(AARCH64_FUNCTION_NONE) Save
db58fd89 JW	161	Select return address signing scope.
	162
	163	Enum
	164	Name(aarch64_ra_sign_scope_t) Type(enum aarch64_function_type)
	165	Supported AArch64 return address signing scope (for use with -msign-return-address= option):
	166
	167	EnumValue
	168	Enum(aarch64_ra_sign_scope_t) String(none) Value(AARCH64_FUNCTION_NONE)
	169
	170	EnumValue
	171	Enum(aarch64_ra_sign_scope_t) String(non-leaf) Value(AARCH64_FUNCTION_NON_LEAF)
	172
	173	EnumValue
	174	Enum(aarch64_ra_sign_scope_t) String(all) Value(AARCH64_FUNCTION_ALL)
	175
a6fc00da	176	mlow-precision-recip-sqrt
88e25f47	177	Target Var(flag_mrecip_low_precision_sqrt) Optimization
98daafa0 EM	178	Enable the reciprocal square root approximation. Enabling this reduces
	179	precision of reciprocal square root results to about 16 bits for
	180	single precision and to 32 bits for double precision.
	181
	182	mlow-precision-sqrt
88e25f47	183	Target Var(flag_mlow_precision_sqrt) Optimization
98daafa0 EM	184	Enable the square root approximation. Enabling this reduces
	185	precision of square root results to about 16 bits for
	186	single precision and to 32 bits for double precision.
	187	If enabled, it implies -mlow-precision-recip-sqrt.
79a2bc2d EM	188
79a2bc2d EM	189	mlow-precision-div
88e25f47	190	Target Var(flag_mlow_precision_div) Optimization
79a2bc2d EM	191	Enable the division approximation. Enabling this reduces
	192	precision of division results to about 16 bits for
	193	single precision and to 32 bits for double precision.
c10e3d7f	194
43cacb12 RS	195	Enum
	196	Name(sve_vector_bits) Type(enum aarch64_sve_vector_bits_enum)
	197	The possible SVE vector lengths:
	198
	199	EnumValue
	200	Enum(sve_vector_bits) String(scalable) Value(SVE_SCALABLE)
	201
	202	EnumValue
	203	Enum(sve_vector_bits) String(128) Value(SVE_128)
	204
	205	EnumValue
	206	Enum(sve_vector_bits) String(256) Value(SVE_256)
	207
	208	EnumValue
	209	Enum(sve_vector_bits) String(512) Value(SVE_512)
	210
	211	EnumValue
	212	Enum(sve_vector_bits) String(1024) Value(SVE_1024)
	213
	214	EnumValue
	215	Enum(sve_vector_bits) String(2048) Value(SVE_2048)
	216
	217	msve-vector-bits=
	218	Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) Init(SVE_SCALABLE)
f499726a	219	-msve-vector-bits=<number> Set the number of bits in an SVE vector register.
43cacb12	220
c10e3d7f	221	mverbose-cost-dump
88e25f47	222	Target Undocumented Var(flag_aarch64_verbose_cost)
d1132c1b	223	Enables verbose cost model dumping in the debug dump files.
3b0c2502 RE	224
	225	mtrack-speculation
	226	Target Var(aarch64_track_speculation)
	227	Generate code to track when the CPU might be speculating incorrectly.
cd0b2d36 RR	228
	229	mstack-protector-guard=
	230	Target RejectNegative Joined Enum(stack_protector_guard) Var(aarch64_stack_protector_guard) Init(SSP_GLOBAL)
	231	Use given stack-protector guard.
	232
	233	Enum
	234	Name(stack_protector_guard) Type(enum stack_protector_guard)
	235	Valid arguments to -mstack-protector-guard=:
	236
	237	EnumValue
	238	Enum(stack_protector_guard) String(sysreg) Value(SSP_SYSREG)
	239
	240	EnumValue
	241	Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
	242
	243	mstack-protector-guard-reg=
	244	Target Joined RejectNegative String Var(aarch64_stack_protector_guard_reg_str)
	245	Use the system register specified on the command line as the stack protector
	246	guard register. This option is for use with fstack-protector-strong and
	247	not for use in user-land code.
	248
	249	mstack-protector-guard-offset=
	250	Target Joined RejectNegative String Var(aarch64_stack_protector_guard_offset_str)
	251	Use an immediate to offset from the stack protector guard register, sp_el0.
	252	This option is for use with fstack-protector-strong and not for use in
	253	user-land code.
	254
	255	TargetVariable
	256	long aarch64_stack_protector_guard_offset = 0
	257
3950b229 RH	258	moutline-atomics
	259	Target Report Mask(OUTLINE_ATOMICS) Save
	260	Generate local calls to out-of-line atomic operations.
eb23241b RS	261
	262	-param=aarch64-sve-compare-costs=
	263	Target Joined UInteger Var(aarch64_sve_compare_costs) Init(1) IntegerRange(0, 1) Param
	264	When vectorizing for SVE, consider using unpacked vectors for smaller elements and use the cost model to pick the cheapest approach. Also use the cost model to choose between SVE and Advanced SIMD vectorization.